A TBC solar cell and its preparation method

Abstract

The present application relates to the technical field of solar cells, and specifically to a TBC solar cell and a preparation method thereof, which includes the following steps: S1, polishing; S2, primary deposition and doping; S3, primary laser treatment; S4, alkaline solution treatment; S5, secondary deposition and doping; S6, secondary laser treatment; S7, acid solution treatment; S8, alkaline solution treatment and texturing; S9, cleaning; S10, aluminum oxide deposition; S11, passivation layer deposition; S12, screen printing: the positive and negative electrode sub-grids are printed at one time using the same slurry, and the depth and density of the silver spikes of the negative electrode sub-grid in the groove penetrating the phosphorus-doped polysilicon layer are lower than the depth and density of the silver spikes of the positive electrode sub-grid outside the groove penetrating the boron-doped polysilicon layer. The present application has the effect of ensuring that the positive and negative electrode sub-grids are printed at one time using the same silver paste composition and under the same sintering conditions without causing under-sintering of the P region or over-sintering of the N region, thereby helping to reduce production costs.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a TBC solar cell and a preparation method thereof. Background Art

[0002] With the development of the photovoltaic industry, the conversion efficiency of crystalline silicon solar cells has continued to improve, gradually approaching its theoretical limit. To further increase the light-receiving area of ​​the cell, high-efficiency cells are undergoing a trend from double-sided contact to back-contact (BC). Removing the front electrode from obstruction can improve short-circuit current (Isc) by 2-3%. Based on surface passivation technology, BC cells can be further divided into Tunneling Oxide Passivated Contact (TOPCon) cells, Heterojunction Junction (HJT) cells, and HPBC cells using hybrid passivation technologies (such as Al-BSF, PERC, TOPCon, and HJT). Of these, TBC cells offer the highest cost-effectiveness and the greatest potential for industrialization.

[0003] In terms of metallization, the positive and negative electrodes of traditional bifacial TOPCon cells are located on the front and back of the cell, respectively, requiring separate printing. The main grid and secondary grid for each electrode are also typically printed separately, resulting in a total of four printing steps. Unlike bifacial TOPCon cells, the positive and negative electrodes of TBC cells are concentrated on the back of the cell, theoretically reducing the number of printing steps and lowering production costs.

[0004] Currently, TBC cells have essentially achieved the simultaneous printing of the positive and negative main grids, but the positive and negative secondary grids still need to be printed separately. For processes requiring a second printing pass, such as overprinting the silver seed layer and copper grid lines, more printing passes are required. The primary reason for the separate printing of the positive and negative secondary grids is the difference in doping concentrations within the polysilicon layer on the back of the TBC cell. Because the boron doping concentration in the polysilicon layer is 1-2 orders of magnitude lower than the phosphorus doping concentration in the polysilicon layer, the contact resistivity between the metal electrode in the N region and the phosphorus-doped polysilicon layer differs significantly from the contact resistivity between the metal electrode in the P region and the boron-doped polysilicon layer. Using the same negative electrode silver paste can easily result in poor contact in the P region or excessive contact in the N region. Therefore, the positive and negative secondary grids need to be printed separately (i.e., twice) using different secondary grid paste compositions to ensure good contact and passivation between the P and N regions, which results in higher production costs. Summary of the Invention

[0005] In order to ensure that printing the positive and negative electrode sub-grids at one time using silver paste of the same composition will not result in under-sintering of the P region or over-sintering of the N region, thereby reducing production costs, the present application provides a TBC solar cell and a preparation method thereof.

[0006] In a first aspect, the present application provides a method for preparing a TBC solar cell, which adopts the following technical solution:

[0007] A method for preparing a TBC solar cell comprises the following steps:

[0008] S1, polishing;

[0009] S2, primary deposition and diffusion: a tunneling oxide layer, a boron-doped polysilicon layer, and a borosilicate glass layer are sequentially formed on the back of the polished silicon wafer;

[0010] S3, primary laser processing: laser scanning is performed on the back of the silicon wafer, with the scanning areas arranged at intervals;

[0011] S4, alkali solution treatment: treating the laser-treated silicon wafer with alkali solution to form spaced grooves on the back of the silicon wafer, wherein the tower bases in the grooves are larger than the tower bases outside the grooves;

[0012] S5, secondary deposition and diffusion: a tunnel oxide layer, phosphorus-doped polysilicon, and phosphosilicate glass layer are sequentially formed on the back side of the silicon wafer;

[0013] S6. Secondary laser processing: Laser scanning is performed on the area on the back of the silicon wafer that has not been laser processed once, and laser scanning is performed on one side of the groove near the groove sidewall;

[0014] S7, acid treatment: performing acid treatment on the front side of the silicon wafer;

[0015] S8, alkali solution treatment and texturing: etching the silicon wafer in a mixed solution of alkali solution and a texturing additive to form a pyramid textured surface on the front side of the silicon wafer, while removing the phosphorus-doped polysilicon and phosphorus-silicate glass layer and the tunneling oxide layer in the secondary laser-treated area on the back side of the silicon wafer, thereby forming a channel region in the groove;

[0016] S9, cleaning;

[0017] S10, aluminum oxide deposition: depositing an aluminum oxide layer on the surface of the silicon wafer;

[0018] S11, passivation layer deposition: depositing a passivation anti-reflection layer on the surface of the silicon wafer under the same deposition conditions, wherein the thickness of the passivation anti-reflection layer in the groove is greater than the thickness of the passivation anti-reflection layer outside the groove;

[0019] S12. Screen printing: Screen printing is performed on the back of the silicon wafer, followed by sintering and light injection. The positive electrode sub-grid and the negative electrode sub-grid are printed at one time using the same slurry. After sintering, the depth and density of the silver spikes of the negative electrode sub-grid in the groove penetrating into the phosphorus-doped polysilicon layer are lower than the depth and density of the silver spikes of the positive electrode sub-grid outside the groove penetrating into the boron-doped polysilicon layer.

[0020] By adopting the above-mentioned technical solution, the precursor for printing positive and negative electrodes prepared by the preparation method of the present application can achieve the effect that the density and depth of the silver spikes of the negative electrode sub-gate penetrating into the phosphorus-doped polysilicon layer are lower than the density and depth of the silver spikes of the positive electrode sub-gate penetrating into the boron-doped polysilicon layer, that is, the density and depth of the silver spikes of the metal electrode in the N region are both smaller than the density and depth of the silver spikes in the P region, thereby overcoming the problems of poor contact in the P region and excessive contact in the N region caused by the difference in contact resistivity between the P region and the N region themselves, and thus achieving better contact and passivation levels on both the positive and negative electrodes when the same sub-gate slurry is used for printing in the P region and the N region.

[0021] Because boron doping requires higher temperatures than phosphorus doping, BC cells first fabricate the tunneling oxide and boron-doped polysilicon layers in the P region (i.e., the non-grooved area) before completing the tunneling oxide and phosphorus-doped polysilicon layers in the N region (i.e., the grooved area). Consequently, the silicon substrate in the N region undergoes an additional alkaline etch (i.e., S4, alkaline treatment) compared to the P region, resulting in a larger tower base and a more mirror-like surface morphology. The subsequent silicon nitride layer deposited is also thicker (i.e., S11, passivation layer deposition). Consequently, under the same printing paste and sintering conditions (i.e., S12, screen printing), the silver spike depth and density in the N region are lower than those in the P region. Due to the different solubility of boron and phosphorus in polysilicon, the doping concentration of the N region-doped polysilicon is much higher than that in the P region. Therefore, a good ohmic contact can be formed without excessive silver spike depth and density (which would otherwise result in recombination losses). Therefore, this application controls the size of the N-region and P-region tower bases by adjusting the polishing process parameters, thereby optimizing the performance of the N-region and P-region after screen printing and sintering (i.e., contact resistivity, dark saturation current density, etc.).

[0022] Optionally, in S1, polishing, the back side of the silicon wafer is polished, and the silicon wafer thickness is 100-130 μm, resulting in a silicon wafer with a tower base of 15-25 μm. Specifically, the tower base of the silicon wafer can be 15 μm, 18 μm, 20 μm, 22 μm, 24 μm, etc. The thickness of the silicon wafer can be 100 μm, 110 μm, 120 μm, 130 μm, etc.

[0023] Optionally, in the step S2, the single deposition and doping are performed by LPCVD deposition, with a certain range of edge expansion, a deposition temperature of 550-650°C, a deposition time of 60-120 min, and then boron diffusion, a boron diffusion temperature of 900-1000°C, a boron diffusion time of 60-120 min, and a boron doping concentration of 1E19-1E20 cm -3 The thickness of the prepared tunnel oxide layer is 1-2 nm, the thickness of the boron-doped polysilicon layer is 200-400 nm, and the thickness of the borosilicate glass (BSG) layer is 40-70 nm.

[0024] The deposition temperature can be 550°C, 560°C, 580°C, 600°C, 620°C, 650°C, etc., the deposition time can be 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, etc., the boron diffusion temperature can be 900°C, 920°C, 930°C, 950°C, 980°C, 1000°C, etc., and the boron diffusion time can be 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, etc.

[0025] The deposition thickness of the tunnel oxide layer can be 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, etc., the deposition thickness of the boron-doped polysilicon layer can be 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, etc., and the deposition thickness of the borosilicate glass layer can be 50 nm, 80 nm, 100 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.

[0026] Optionally, in the single laser treatment in step S3, the laser wavelength is 300-600 nm, the frequency is 100 kHz-10 MHz, the speed is 2-10 m / s, the distance between the laser scanning areas in the length direction of the silicon wafer is 0.5-1.5 mm, and the laser depth is 1-3 μm. The interval between the laser scanning areas can be 0.5 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.5 mm, etc. The laser depth can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.5 μm, 2.8 μm, etc.

[0027] Optionally, in the S4, alkaline solution treatment, the depth of the groove formed on the back of the silicon wafer is 2-5 μm, the bottom of the groove is a polished morphology, the base of the tower in the area outside the groove is 15-25 μm, and the base of the tower in the area inside the groove is 20-40 μm.

[0028] The depth of the formed groove can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, etc., the tower base outside the groove can be 15μm, 18μm, 20μm, 22μm, 24μm, etc., and the tower base inside the groove can be 20μm, 22μm, 25μm, 30μm, 35μm, 38μm, etc.

[0029] By adopting the above technical solution, the borosilicate glass layer on the back is modified through laser scanning, so that it loses its ability to resist alkali corrosion. Therefore, after the alkali solution treatment, the borosilicate glass layer, boron-doped polysilicon layer and tunneling oxide layer in the laser area are all removed to form spaced grooves. At the same time, the silicon substrate in the grooves is once again alkali-etched to form a polished morphology with a larger tower base size; the non-laser scanned area (i.e., the non-groove area) will not be etched by the alkali solution because it is not laser scanned, so that the tower base in the non-groove area is consistent in size with the tower base after the initial polishing.

[0030] Optionally, in the S5, secondary deposition and diffusion, LPCVD deposition is used, with a deposition temperature of 550-650°C and a deposition time of 30-60 minutes. The edges have a certain range of expansion, and deposition is formed on the bottom and sidewalls of the groove. Phosphorus diffusion is then performed, with a phosphorus diffusion temperature of 800-900°C, a diffusion time of 30-90 minutes, and a phosphorus doping concentration of 1E20-5E20cm -3 The thickness of the prepared tunnel oxide layer is 1-2 nm, the thickness of the phosphorus-doped polysilicon layer is 100-200 nm, and the thickness of the phosphorus-silicate glass layer is 30-50 nm.

[0031] The phosphorus diffusion temperature can be 800°C, 820°C, 850°C, 880°C, etc., the diffusion time can be 30 min, 50 min, 70 min and 90 min, etc., the thickness of the prepared tunneling oxide layer can be 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 2 nm, etc., the thickness of the phosphorus-doped polysilicon layer can be 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc., and the thickness of the phosphosilicate glass layer can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0032] Optionally, in S6, the secondary laser treatment, the laser scanning area is the area not scanned by the primary laser treatment, and the secondary laser scanning area overlaps with the primary laser scanning area to a certain extent, with the overlapping area being the channel region. The laser wavelength is 300-600 nm, the frequency is 100 kHz-10 MHz, and the speed is 5-10 m / s.

[0033] Optionally, in the acid treatment step S7, the silicon wafer is pickled using an acid solution having a concentration of 10-20% hydrofluoric acid, 30-50% nitric acid, and 10-15% sulfuric acid. The pickling time is 1-2 minutes, and the wrap film layer on the front and edge of the silicon wafer is completely removed. The crystalline silicon on the front of the silicon wafer is also etched away by 1-3 μm.

[0034] Optionally, in the alkali solution treatment and texturing in S8, a mixed solution of 1-2% alkali solution and 0.5-1% texturing additive is used to corrode the silicon wafer for 5-10 minutes.

[0035] By adopting the above technical solution, a pyramid velvet surface is formed on the front side of the silicon wafer in a mixed solution of alkali solution and texturing additives, the phosphosilicate glass layer in the secondary laser area on the back side loses its ability to resist alkali corrosion and is completely corroded, the phosphorus-doped polysilicon layer and the tunneling oxide layer in the channel area are also completely removed, and the borosilicate glass layer thereunder blocks further corrosion of the mixed solution, the phosphorus-doped polysilicon and the second tunneling oxide layer in the channel area are also completely removed, and the crystalline silicon thereunder is also partially corroded to form a pyramid velvet surface.

[0036] Optionally, in the cleaning step S9, hydrofluoric acid is used to remove the phosphosilicate glass layer and borosilicate glass layer remaining on the back of the silicon wafer.

[0037] Optionally, in the step S10, depositing aluminum oxide, an aluminum oxide layer is deposited by atomic layer deposition (ALD), and the thickness of the aluminum oxide layer is 4-7 nm. The thickness of the aluminum oxide layer can be 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, etc.

[0038] Optionally, in S11, in depositing the passivation layer, the deposited passivation anti-reflection layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide. The deposition temperature of the passivation anti-reflection layer is 400-600° C., the deposition time is 600-1200 s, the thickness of the passivation anti-reflection layer outside the groove is 60-90 nm, and the thickness ratio of the passivation anti-reflection layer inside the groove to that outside the groove is 1.05-1.15. The thickness of the passivation anti-reflection layer outside the groove can be 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, etc., and the thickness ratio of the passivation anti-reflection layer inside the groove to that outside the groove can be 1.05, 1.1, 1.15, etc.

[0039] By adopting the above technical solution, due to the different sizes of the tower base inside and outside the groove, the thickness of the passivation anti-reflection layer formed subsequently under the same passivation layer deposition conditions is different, that is, the thickness of the passivation anti-reflection layer in the area inside the groove is greater than the thickness of the passivation anti-reflection layer in the area outside the groove.

[0040] In the aforementioned S12, screen printing, the sintering temperature is 600-800°C. The depth of the silver spikes inside the groove (i.e., the N region) is 40-60 nm, and the depth of the silver spikes outside the groove (i.e., the P region) is 60-120 nm. The ratio of the silver spike density outside the groove to the silver spike density inside the groove is 2-10. The sintering temperature can be 600°C, 650°C, 700°C, 750°C, 800°C, etc. The depth of the silver spikes inside the groove (i.e., the N region) can be 40 nm, 42 nm, 44 nm, 46 nm, 48 nm, 50 nm, 52 nm, 54 nm, 56 nm, 58 nm, 60 nm, etc. The depth of the silver spikes outside the groove (i.e., the P region) can be 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, etc. The density ratio of the silver spikes outside the groove to the silver spikes inside the groove can be 2, 4, 6, 8, 10, etc.

[0041] By adopting the above technical solution, the same metal paste is used to print the positive and negative electrode sub-grids. Under the same sintering conditions, since the passivation anti-reflection layer in the N region is thicker than the passivation anti-reflection layer in the P region, after sintering, the depth and density of the silver spikes of the negative electrode sub-grid in the phosphorus-doped polysilicon layer are lower than the depth and density of the silver spikes of the positive electrode sub-grid in the boron-doped polysilicon layer outside the groove (i.e., the P region), thereby overcoming the problem that the use of the same composition of negative electrode silver paste easily causes poor contact in the P region or excessive contact in the N region due to the boron doping concentration in the polysilicon layer being 1-2 orders of magnitude lower than the phosphorus doping concentration in the polysilicon layer. This application achieves good contact and passivation levels on both the positive and negative electrodes by implementing differentiated doping of polysilicon and passivation anti-reflection films in the N and P regions when the same paste is used for printing in the two regions.

[0042] In summary, this application has the following beneficial effects:

[0043] This application proposes an electrode structure and fabrication method for a TBC battery. This approach aims to reduce production costs by printing the secondary grids of the positive and negative electrodes of the TBC battery in a single pass using the same slurry. By controlling the wet etching and anti-reflection passivation layer deposition processes, good contact and passivation levels can be achieved in both the N and P regions without adding additional steps.

[0044] 2. Because boron doping requires higher temperatures than phosphorus doping, BC cells first prepare the tunneling oxide and boron-doped polysilicon layers in the P region (i.e., the non-grooved area) before completing the tunneling oxide and phosphorus-doped polysilicon layers in the N region (i.e., the grooved area). Consequently, the silicon substrate in the N region undergoes an additional alkaline etch (i.e., S4, alkaline treatment) compared to the P region, resulting in a larger tower base and a more mirror-like surface morphology. The subsequently deposited silicon nitride layer is also thicker (i.e., S11, passivation layer deposition). Therefore, under the same printing paste and sintering conditions (i.e., S12, screen printing), the silver spike depth and density in the N region are lower than those in the P region. Due to the different solubility of boron and phosphorus in polysilicon, the doping concentration of the polysilicon in the N region is much higher than that in the P region. Therefore, a good ohmic contact can be formed without excessive silver spike depth and density (which would otherwise result in recombination losses). Therefore, this application controls the size of the N-region and P-region tower bases by adjusting the polishing process parameters, thereby optimizing the performance of the N-region and P-region after screen printing and sintering (i.e., contact resistivity, dark saturation current density, etc.). BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a process flow chart of the preparation method of the TBC solar cell of this application.

[0046] Figure 2 This is the negative electrode sub-gate structure (i.e., N-region structure) on the back of the silicon wafer after screen printing.

[0047] Figure 3 This is the positive electrode sub-gate structure (i.e., P region structure) on the back of the silicon wafer after screen printing.

[0048] Explanation of the accompanying symbols: 1. N-type substrate; 2. Tunneling oxide layer; 3. Phosphorus-doped polysilicon; 4. Boron-doped polysilicon; 5. Aluminum oxide layer; 6. Passivation anti-reflection layer; 7. Negative electrode sub-gate; 8. Positive electrode sub-gate. DETAILED DESCRIPTION

[0049] The tower base mentioned in this application refers to the size of the pyramid tower base of the silicon base velvet surface or plane structure corresponding to the back of the silicon wafer.

[0050] The experimental methods in the following examples of this application, where specific conditions are not specified, are generally carried out under conventional conditions or conditions recommended by the manufacturers. The various commonly used chemical reagents used in the examples are all commercially available products.

[0051] Example 1

[0052] Reference Figure 1-Figure 3A TBC solar cell includes an N-type substrate 1. The back side of the N-type substrate 1 includes an N region (i.e., a groove region) and a P region (i.e., a non-groove region) alternately arranged along the length direction, with a channel region between adjacent N and P regions. The N region includes a tunneling oxide layer 2, a phosphorus-doped polysilicon layer 3, an aluminum oxide layer 5, and a passivation anti-reflection layer 6 arranged in sequence from a side close to the N-type substrate 1 to a side away from the N-type substrate 1. The N region is also printed with a negative electrode sub-grid 7, which is embedded in the phosphorus-doped polysilicon layer 3 to form an ohmic contact. The P region includes a tunneling oxide layer 2, a boron-doped polysilicon layer 4, an aluminum oxide layer 5, and a passivation anti-reflection layer 6 arranged in sequence from a side close to the N-type substrate 1 to a side away from the N-type substrate 1. The P region is also printed with a positive electrode sub-grid 8, which is embedded in the boron-doped polysilicon layer 4 to form an ohmic contact. The depth and density of the silver spikes of the negative electrode auxiliary gate 7 in the N region penetrating into the phosphorus-doped polysilicon 3 layer are lower than the depth and density of the silver spikes of the positive electrode auxiliary gate 8 in the P region penetrating into the boron-doped polysilicon 4 layer.

[0053] Reference Figure 1 , a method for preparing a TBC solar cell, comprising the following steps:

[0054] S1. Polishing: Polish the N-type silicon wafer with a thickness of 110 μm. The tower base on the back of the silicon wafer after polishing is 20 μm.

[0055] S2. Primary deposition and diffusion: LPCVD is used to deposit boron on the back of the polished silicon wafer, with a certain range of diffusion around the edge. The deposition temperature is 600°C and the deposition time is 90 minutes. High-temperature diffusion is then performed, with the boron diffusion temperature at 940°C and the boron diffusion time at 80 minutes. The boron doping concentration (i.e., the doping concentration in the P region) is 1E19 cm -3 , a 1.5nm tunneling oxide layer, a 300nm boron-doped polysilicon layer, and a 55nm borosilicate glass layer were prepared;

[0056] S3. Primary laser treatment: The back of the silicon wafer is laser scanned, with the scanning areas spaced apart. The laser wavelength is 450nm, the frequency is 1000kHz, and the speed is 5m / s. The laser scanning areas are spaced 1mm apart along the length of the silicon wafer, and the laser depth is 2μm. This modifies the borosilicate glass layer in the scanned area, making it easier to remove it later.

[0057] S4, alkali solution treatment: The silicon wafer after laser treatment is corroded with 8% alkali solution for 3 minutes, so that the film layer in the laser scanned area is corroded and removed by the alkali solution, and grooves arranged at intervals are formed on the back of the silicon wafer; the depth of the grooves formed on the back of the silicon wafer is 3.5μm, and the bottom of the grooves is a polished morphology. At this time, the tower base in the area outside the groove is consistent with the tower base after S1 polishing, both of which are 20μm. The tower base in the area inside the groove is 30μm due to the alkali solution treatment, that is, the tower base size of the silicon base corresponding to the area inside the groove is larger than the tower base size of the silicon base corresponding to the area outside the groove.

[0058] S5. Secondary deposition and diffusion: LPCVD deposition is used at a temperature of 600°C for 50 minutes. There is a certain degree of expansion around the edges, and deposition also forms inside the grooves and on the sidewalls (not shown in the figure). High-temperature diffusion is then performed, with a phosphorus diffusion temperature of 850°C and a diffusion time of 40 minutes. The phosphorus doping concentration (i.e., the N-region doping concentration) is 2 E20 cm -3 A 1.5nm tunnel oxide layer, a 150nm phosphorus-doped polysilicon layer, and a 40nm phosphorus-silicon glass layer were prepared.

[0059] S6. Secondary laser treatment: The area on the back of the silicon wafer that has not been laser treated once is laser scanned. The laser scanned area is in an intermittent finger-like pattern. The laser wavelength is 450nm, the frequency is 1000kHz, and the speed is 8m / s. The laser scan is also performed on one side of the groove near the side wall, so that there is a certain overlap between the first laser treatment and the second laser treatment area. The overlapping area is the channel area. The secondary laser treatment modifies part of the phosphosilicate glass layer on the back of the silicon wafer to facilitate its subsequent removal.

[0060] S7. Acid treatment: Place the front side of the silicon wafer downward and perform acid treatment on the front side of the silicon wafer using an acid solution containing 15% hydrofluoric acid, 40% nitric acid, and 12% sulfuric acid on a chain wet process equipment; the wrap-around film layer on the front side and edge is completely removed, and the silicon substrate on the front side of the silicon wafer is also etched away by 2μm.

[0061] S8, Alkali Treatment and Texturing: The silicon wafer is etched with a mixture of 1.5% alkali solution and 0.8% texturing additive for 8 minutes, forming a pyramid texture on the front of the wafer. Simultaneously, the phosphorus-doped polysilicon, phosphosilicate glass, and tunneling oxide layers in the secondary laser-treated area on the back of the wafer are removed, forming a channel region within the groove. Because the phosphosilicate glass layer in the secondary laser-scanned area on the back of the wafer loses its alkali corrosion resistance and is completely removed, the phosphorus-doped polysilicon and tunneling oxide layers outside the channel region are completely removed, leaving the underlying borosilicate glass layer to continue to block corrosion. The phosphorus-doped polysilicon and tunneling oxide layers inside the channel region are completely removed, leaving the underlying borosilicate glass layer partially etched, forming a pyramid texture.

[0062] S9, cleaning, using hydrofluoric acid to remove the residual phosphosilicate glass layer and borosilicate glass layer on the back of the silicon wafer;

[0063] S10, aluminum oxide deposition: ALD (atomic layer deposition) is used to deposit an aluminum oxide layer on the surface of the silicon wafer. The thickness of the aluminum oxide layer is 5 nm.

[0064] S11. Depositing a passivation layer: depositing a passivation anti-reflection layer on the surface of the silicon wafer at a deposition temperature of 500° C. for 1000 s. The deposited passivation anti-reflection layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the passivation anti-reflection layer outside the groove is 75 nm. The thickness ratio of the passivation anti-reflection layer inside the groove to that outside the groove is 1.1, that is, the thickness of the passivation anti-reflection layer inside the groove is 82.5 nm.

[0065] S12, screen printing: screen printing is performed on the back of the silicon wafer. First, the main grid is printed with metal paste, and then the positive electrode sub-grid and negative electrode sub-grid are printed simultaneously with the same metal paste. The positive electrode sub-grid and the negative electrode sub-grid are printed in the groove inner area and the groove outer area (i.e., the P area and the N area) respectively. Then sintering and light injection are performed, and the sintering temperature is 700℃. Figure 2 and Figure 3 As shown in the figure, after sintering, the depth and density of the silver spikes of the negative electrode auxiliary gate penetrating into the phosphorus-doped polysilicon layer in the groove are lower than the depth and density of the silver spikes of the positive electrode auxiliary gate penetrating into the boron-doped polysilicon layer outside the groove, that is, the depth of the silver spikes outside the groove (P region) is 100nm, and the depth of the silver spikes inside the groove (N region) is 50nm, and the ratio of the silver spike density outside the groove (P region) to the silver spike density inside the groove (N region) is 6.

[0066] Example 2

[0067] A method for preparing a TBC solar cell comprises the following steps:

[0068] S1. Polishing: Polish the N-type silicon wafer with a thickness of 100 μm. The tower base on the back of the silicon wafer after polishing is 15 μm.

[0069] S2. Primary deposition and diffusion: LPCVD is used to deposit boron on the back of the polished silicon wafer, with a certain range of diffusion around the edge. The deposition temperature is 550°C and the deposition time is 120 minutes. High-temperature diffusion is then performed, with the boron diffusion temperature at 900°C and the boron diffusion time at 120 minutes. The boron doping concentration is 1e19 cm -3 , a tunneling oxide layer of 1nm, a boron-doped polysilicon layer of 200nm and a borosilicate glass layer of 40nm were prepared.

[0070] S3. Primary laser treatment: Laser scanning is performed on the back of the silicon wafer. The scanning areas are arranged at intervals. The laser wavelength is 300nm, the frequency is 100kHz, and the speed is 0.5m / s. The laser scanning areas are spaced 1mm apart along the length of the silicon wafer, and the laser depth is 1μm. This modifies the borosilicate glass layer in the scanned area, making it easier to remove it later.

[0071] S4. Alkali solution treatment: The silicon wafer after laser treatment is corroded with 8% alkaline solution for 3 minutes, so that the film layer in the laser scanned area is corroded and removed by the alkaline solution, and grooves arranged at intervals are formed on the back of the silicon wafer; the depth of the grooves formed on the back of the silicon wafer is 2μm, the bottom of the groove is a polished morphology, the tower base outside the groove is 15μm, and the tower base inside the groove is 20μm, that is, the tower base size of the silicon base corresponding to the area inside the groove is larger than the tower base size of the silicon base corresponding to the area outside the groove.

[0072] S5. Secondary deposition and diffusion: LPCVD deposition was used, with a deposition temperature of 550°C and a deposition time of 30 minutes. There was a certain degree of expansion around the edges, and deposition also formed inside the grooves and on the sidewalls (not shown in the figure). High-temperature diffusion was then performed, with a phosphorus diffusion temperature of 800°C and a diffusion time of 90 minutes. The phosphorus doping concentration was 1 E20 cm -3 On the back of the silicon wafer, a 1nm tunneling oxide layer, a 100nm phosphorus-doped polysilicon layer, and a 30nm phosphorus-silicon glass layer are sequentially prepared.

[0073] S6. Secondary laser treatment: The area on the back of the silicon wafer that has not been laser treated once is laser scanned. The laser scanned area is in an intermittent finger-like pattern. The laser wavelength is 300nm, the frequency is 100kHz, and the speed is 5m / s. The laser scan is also performed on one side of the groove near the side wall, so that there is a certain overlap between the first laser treatment and the second laser treatment area. The overlapping area is the channel area. The secondary laser treatment modifies part of the phosphosilicate glass layer on the back of the silicon wafer to facilitate its subsequent removal.

[0074] S7. Acid treatment: Place the front side of the silicon wafer downward and perform acid treatment on the front side of the silicon wafer using an acid solution containing 10% hydrofluoric acid, 30% nitric acid and 10% sulfuric acid on a chain wet process equipment. The pickling time is 1 minute; the wrap-around film layer on the front side and edge is completely removed, and the silicon substrate on the front side of the silicon wafer is also etched away by 2μm.

[0075] S8, Alkali Treatment and Texturing: A mixed solution of 1% alkali solution and 0.5% texturing additive is used to etch the silicon wafer for 5 minutes, forming a pyramid texture on the front of the wafer. Simultaneously, the phosphorus-doped polysilicon, phosphosilicate glass, and tunneling oxide layers in the secondary laser-treated area on the back of the wafer are removed, forming a channel region within the groove. Because the phosphosilicate glass layer in the secondary laser-scanned area on the back of the wafer loses its alkali corrosion resistance and is completely removed, the phosphorus-doped polysilicon and tunneling oxide layers outside the channel region are completely removed, leaving the underlying borosilicate glass layer to continue to block corrosion. The phosphorus-doped polysilicon and tunneling oxide layers inside the channel region are completely removed, leaving the underlying borosilicate glass layer partially corroded, forming a pyramid texture.

[0076] S9, cleaning: using hydrofluoric acid to remove the residual phosphosilicate glass layer and borosilicate glass layer on the back of the silicon wafer;

[0077] S10, aluminum oxide deposition: ALD (atomic layer deposition) is used to deposit an aluminum oxide layer on the surface of the silicon wafer. The thickness of the aluminum oxide layer is 4 nm.

[0078] S11. Deposition of a passivation layer: depositing a passivation anti-reflection layer on the surface of the silicon wafer at a deposition temperature of 400° C. for 1200 seconds. The deposited passivation anti-reflection layer is a silicon nitride layer. The thickness of the passivation anti-reflection layer outside the groove is 60 nm. The thickness ratio of the passivation anti-reflection layer inside the groove to that outside the groove is 1.05, i.e., the thickness of the passivation anti-reflection layer inside the groove is 63 nm.

[0079] S12, screen printing: screen printing is performed on the back of the silicon wafer. First, the main grid is printed with metal paste, and then the positive electrode sub-grid and the negative electrode sub-grid are printed simultaneously with the same metal paste. The positive electrode sub-grid and the negative electrode sub-grid are printed in the groove inner area and the groove outer area (i.e., the P area and the N area) respectively; then sintering and light injection are performed, and the sintering temperature is 600℃. Figure 2 and Figure 3 As shown in the figure, the depth and density of the silver spikes of the negative electrode auxiliary gate penetrating into the phosphorus-doped polysilicon layer in the groove are lower than the depth and density of the silver spikes of the positive electrode auxiliary gate penetrating into the boron-doped polysilicon layer outside the groove, that is, the depth of the silver spikes outside the groove (P region) is 60nm, and the depth of the silver spikes inside the groove (N region) is 40nm. The ratio of the silver spike density outside the groove (P region) to the silver spike density inside the groove (N region) is 2.

[0080] Example 3

[0081] A method for preparing a TBC battery comprises the following steps:

[0082] S1. Polishing: Polish the N-type silicon wafer with a thickness of 130 μm. The tower base on the back of the silicon wafer after polishing is 25 μm.

[0083] S2. Primary deposition and diffusion: LPCVD is used to deposit boron on the back of the polished silicon wafer, with a certain range of diffusion around the edge. The deposition temperature is 650°C and the deposition time is 60 minutes. High-temperature diffusion is then performed, with the boron diffusion temperature being 1000°C and the boron diffusion time being 60 minutes. The boron doping concentration is 1E20 cm -3 On the back of the silicon wafer, a 2nm tunneling oxide layer, a 400nm boron-doped polysilicon layer, and a 70nm borosilicate glass layer are sequentially prepared.

[0084] S3. Primary laser treatment: The back of the silicon wafer is laser scanned, with the scanning areas spaced apart. The laser wavelength is 600nm, the frequency is 2000kHz, and the speed is 5m / s. The laser scanning areas are spaced 1.5mm apart along the length of the silicon wafer, and the laser depth is 3μm. This modifies the borosilicate glass layer in the scanned area, making it easier to remove it later.

[0085] S4. Alkali solution treatment: The silicon wafer after laser treatment is corroded with 10% alkaline solution for 5 minutes, so that the film layer in the laser scanned area is corroded and removed by the alkaline solution, and grooves arranged at intervals are formed on the back of the silicon wafer; the depth of the groove formed on the back of the silicon wafer is 5μm, the bottom of the groove is a polished morphology, and the tower base in the area inside the groove is 40μm. At this time, the tower base in the area outside the groove is 25μm because it is not etched by the alkaline solution, that is, the tower base size of the silicon base corresponding to the area inside the groove is larger than the tower base size of the silicon base corresponding to the area outside the groove.

[0086] S5. Secondary deposition and diffusion: LPCVD deposition was used at a temperature of 650°C for 30 minutes. There was a certain degree of expansion around the edges, and deposition also formed inside the grooves and on the sidewalls (not shown in the figure). High-temperature diffusion was then performed, with a phosphorus diffusion temperature of 900°C for 30 minutes and a phosphorus doping concentration of 5E20 cm -3 On the back of the silicon wafer, a 1.5nm tunneling oxide layer, a 150nm phosphorus-doped polysilicon layer, and a 40nm phosphorus-silicon glass layer are sequentially formed.

[0087] S6. Secondary laser treatment: The area on the back of the silicon wafer that has not been laser treated once is laser scanned. The laser scanned area is in an intermittent finger-like pattern. The laser wavelength is 600nm, the frequency is 2000kHz, and the speed is 10m / s. The laser scan is also performed on one side of the groove near the side wall, so that there is a certain overlap between the first laser treatment and the second laser treatment area. The overlapping area is the channel area. The secondary laser treatment modifies part of the phosphosilicate glass layer on the back of the silicon wafer to facilitate its subsequent removal.

[0088] S7. Acid treatment: Place the front side of the silicon wafer downward and perform acid treatment on the front side of the silicon wafer using an acid solution containing 20% ​​hydrofluoric acid, 50% nitric acid, and 15% sulfuric acid on a chain wet process equipment. Pickling takes 2 minutes. The wrap-around film layer on the front side and edge is completely removed, and the silicon substrate on the front side of the silicon wafer is also etched away by 3μm.

[0089] S8. Alkali treatment and texturing: The silicon wafer is etched with a mixture of 2% alkali solution and 1% texturing additive for 10 minutes, forming a pyramid texture on the front of the wafer. Simultaneously, the phosphorus-doped polysilicon, phosphosilicate glass, and tunneling oxide layers in the secondary laser-treated area on the back of the wafer are removed, forming a channel region within the groove. Because the phosphosilicate glass layer in the secondary laser-scanned area on the back of the wafer loses its alkali corrosion resistance and is completely removed, the phosphorus-doped polysilicon and tunneling oxide layers outside the channel region are completely removed, leaving the underlying borosilicate glass layer to continue to block corrosion. The phosphorus-doped polysilicon and tunneling oxide layers inside the channel region are completely removed, leaving the underlying borosilicate glass layer partially etched, forming a pyramid texture.

[0090] S9, cleaning, using hydrofluoric acid to remove the residual phosphosilicate glass layer and borosilicate glass layer on the back of the silicon wafer;

[0091] S10, aluminum oxide deposition: ALD (atomic layer deposition) is used to deposit an aluminum oxide layer on the surface of the silicon wafer. The thickness of the aluminum oxide layer is 7 nm.

[0092] S11. Depositing a passivation layer: depositing a passivation anti-reflection layer on the surface of the silicon wafer at a deposition temperature of 600° C. for 600 seconds. The deposited passivation anti-reflection layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the passivation anti-reflection layer outside the groove is 90 nm. The thickness ratio of the passivation anti-reflection layer inside the groove to that outside the groove is 1.15, that is, the thickness of the passivation anti-reflection layer inside the groove is 103.5 nm.

[0093] S12, screen printing: screen printing is performed on the back of the silicon wafer. First, the main grid is printed with metal paste, and then the positive electrode sub-grid and negative electrode sub-grid are printed simultaneously with the same metal paste. The positive electrode sub-grid and the negative electrode sub-grid are printed in the area inside the groove and the area outside the groove (i.e., the P area and the N area). Then sintering and light injection are performed. The sintering temperature is 800℃. Figure 2 and Figure 3 As shown in the figure, after sintering, the depth and density of the silver spikes of the negative electrode auxiliary gate penetrating into the phosphorus-doped polysilicon layer in the groove are lower than the depth and density of the silver spikes of the positive electrode auxiliary gate penetrating into the boron-doped polysilicon layer outside the groove, that is, the depth of the silver spikes outside the groove (P region) is 120nm, and the depth of the silver spikes inside the groove (N region) is 60nm, and the ratio of the silver spike density outside the groove (P region) to the silver spike density inside the groove (N region) is 10.

[0094] Comparative Example

[0095] Comparative Example 1

[0096] A method for preparing a TBC solar cell differs from that of Example 1 in that:

[0097] The tower base of the groove area (i.e., N area) obtained after treatment with S4 and alkali solution is 50μm, and the tower base of the non-groove area (i.e., P area) is 20μm.

[0098] After S11 and passivation layer deposition, the thickness of the passivation layer in the groove area is 120 nm, and the thickness of the passivation layer deposited in the non-groove area is 75 nm.

[0099] S12. Screen printing: Use the same slurry to print the positive electrode sub-grid and the negative electrode sub-grid in the groove area and the non-groove area at one time respectively. After sintering at 700°C, the depth and density of the silver spikes of the negative electrode sub-grid in the groove penetrating into the phosphorus-doped polysilicon layer are lower than the depth and density of the silver spikes of the positive electrode sub-grid outside the groove penetrating into the boron-doped polysilicon layer, that is, the depth of the silver spikes outside the groove (P area) is 100nm, the depth of the silver spikes inside the groove (N area) is 40nm, and the ratio of the silver spike density outside the groove (P area) to the silver spike density inside the groove (N area) is 20.

[0100] The remaining steps are the same.

[0101] Comparative Example 2

[0102] A method for preparing a TBC solar cell, which is different from Example 2 in that:

[0103] Without S4, alkali solution treatment, that is, S3, one-time laser treatment, the tower base of the groove area (ie, N area) obtained is 15μm, and the tower base of the non-groove area (ie, P area) is 15μm.

[0104] S11, passivation layer deposition: The thickness of the passivation layer deposited in the groove area and the non-groove area is 60 nm.

[0105] S12. Screen printing: Use the same slurry to print the positive electrode sub-grid and the negative electrode sub-grid in the groove area and the non-groove area at one time. After sintering at 700°C, the depth and density of the silver spikes of the negative electrode sub-grid in the groove penetrating into the phosphorus-doped polysilicon layer are equal to the depth and density of the silver spikes of the positive electrode sub-grid outside the groove penetrating into the boron-doped polysilicon layer.

[0106] The remaining steps are the same.

[0107] Comparative Example 3

[0108] A method for preparing a TBC solar cell, which is different from that of Example 1 in that:

[0109] After S1 polishing, the tower base on the back of the silicon wafer is 10 μm;

[0110] The tower base of the groove area (i.e., N area) obtained after treatment with S4 and alkali solution is 50μm, and the tower base of the non-groove area (i.e., P area) is 10μm.

[0111] After S11 and passivation layer deposition, the thickness of the passivation layer in the groove area is 120 nm, and the thickness of the passivation layer deposited in the non-groove area is 50 nm.

[0112] S12. Screen printing: Use the same slurry to print the positive electrode sub-grid and the negative electrode sub-grid at one time in the groove area and the non-groove area respectively. After sintering at 700°C, the depth and density of the silver spikes of the negative electrode sub-grid in the groove penetrating into the phosphorus-doped polysilicon layer are smaller than the depth and density of the silver spikes of the positive electrode sub-grid outside the groove penetrating into the boron-doped polysilicon layer, that is, the depth of the silver spikes outside the groove (P area) is 180nm, the depth of the silver spikes inside the groove (N area) is 40nm, and the ratio of the silver spike density outside the groove (P area) to the silver spike density inside the groove (N area) is 30.

[0113] The remaining steps are the same.

[0114] Comparative Example 4

[0115] A method for preparing a TBC solar cell, which is different from that of Example 1 in that:

[0116] After S1 polishing, the tower base on the back of the silicon wafer is 30 μm;

[0117] The tower base of the groove area (i.e., N area) obtained after treatment with S4 and alkali solution is 50μm, and the tower base of the non-groove area (i.e., P area) is 30μm.

[0118] After S11 and the passivation layer deposition, the thickness of the passivation layer in the groove area is 100 nm, and the thickness of the passivation layer deposited in the non-groove area is 80 nm.

[0119] S12. Screen printing: Use the same slurry to print the positive electrode sub-grid and the negative electrode sub-grid in the groove area and the non-groove area at one time. After sintering at 700°C, the depth and density of the silver spikes of the negative electrode sub-grid in the groove penetrating the phosphorus-doped polysilicon layer are smaller than the depth and density of the silver spikes of the positive electrode sub-grid outside the groove penetrating the boron-doped polysilicon layer, that is, the depth of the silver spikes outside the groove (P area) is 120nm, and the depth of the silver spikes inside the groove (N area) is 80nm. The ratio of the silver spike density outside the groove (P area) to the silver spike density inside the groove (N area) is 15.

[0120] The remaining steps are the same.

[0121] Performance testing experiment

[0122] 1. Contact and passivation level test of positive and negative electrodes

[0123] Contact resistivity: Using the TLM method, the resistance between electrodes with different spacing is measured as the y-axis, and the spacing is the x-axis. After forming a linear function, the y-axis intercept is the contact resistance, and the contact resistance multiplied by the electrode area is the contact resistivity. The smaller the contact resistivity, the better the contact performance.

[0124] Dark Saturation Current Density: Measure the dark saturation current density of electrode patterns with varying aperture ratios, using the y-axis as the y-axis and the electrode pattern aperture ratio as the x-axis. A linear function is formed, with the slope being the difference between the dark saturation current density of the electrode and passivation regions. The corresponding value for the electrode region is then calculated. A higher dark saturation current density indicates a poorer passivation level.

[0125] Table 1 Test results of Examples 1-3 and Comparative Examples 1-4

[0126]

[0127] Combining Examples 1-3 and Comparative Examples 1-4 with Table 1, it can be seen that the positive and negative electrodes of the battery cells of Examples 1-3 have good contact and passivation levels. The reason for this may be that by controlling the size of the tower base in the N region to be larger than the tower base in the P region (i.e., the tower base in the area inside the groove is 20-40 μm, and the tower base in the area outside the groove is 15-25 μm), the passivation layer formed in the N region is thicker than the passivation layer formed in the P region (i.e., the thickness of the passivation anti-reflection layer outside the groove is 60-90 nm, and the thickness ratio of the passivation anti-reflection layer inside the groove to that outside the groove is 1.05-1.15). After printing the positive and negative electrode grid lines using the same slurry, under the same sintering conditions, due to the difference in solid solubility of boron and phosphorus in polysilicon, the doping concentration of the doped polysilicon in the N region is much higher than that in the P region. Therefore, the N region does not require an excessively high silver spike depth and density to form a good ohmic contact. Without adding additional steps, good contact and passivation levels can be achieved in both the N region and the P region.

[0128] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing a TBC solar cell, characterized in that: The following steps are involved: S1, polishing; S2, primary deposition and diffusion: a tunneling oxide layer, a boron-doped polysilicon layer, and a borosilicate glass layer are sequentially formed on the back of the polished silicon wafer; S3, primary laser processing: laser scanning is performed on the back of the silicon wafer, with the scanning areas arranged at intervals; S4, alkali solution treatment: treating the laser-treated silicon wafer with alkali solution to form spaced grooves on the back of the silicon wafer, wherein the tower bases in the grooves are larger than the tower bases outside the grooves; S5, secondary deposition and diffusion: a tunnel oxide layer, phosphorus-doped polysilicon, and phosphosilicate glass layer are sequentially formed on the back side of the silicon wafer; S6. Secondary laser processing: Laser scanning is performed on the area on the back of the silicon wafer that has not been laser processed once, and laser scanning is performed on one side of the groove near the groove sidewall; S7, acid treatment: performing acid treatment on the front side of the silicon wafer; S8, alkali solution treatment and texturing: etching the silicon wafer in a mixed solution of alkali solution and a texturing additive to form a pyramid textured surface on the front side of the silicon wafer, while removing the phosphorus-doped polysilicon and phosphorus-silicate glass layer and the tunneling oxide layer in the secondary laser-treated area on the back side of the silicon wafer, thereby forming a channel region in the groove; S9, cleaning; S10, aluminum oxide deposition: depositing an aluminum oxide layer on the surface of the silicon wafer; S11, passivation layer deposition: depositing a passivation anti-reflection layer on the surface of the silicon wafer, wherein the thickness of the passivation anti-reflection layer in the area inside the groove is greater than the thickness of the passivation anti-reflection layer in the area outside the groove; S12, screen printing: Screen printing is performed on the back side of the silicon wafer, followed by sintering and light injection. The positive electrode sub-grid and the negative electrode sub-grid are printed at the same time using the same slurry. After sintering, the depth and density of the silver spikes of the negative electrode sub-grid in the groove penetrating the phosphorus-doped polysilicon layer are lower than the depth and density of the silver spikes of the positive electrode sub-grid in the boron-doped polysilicon layer outside the groove. In the S12, screen printing, the sintering temperature is 600-800° C., the depth of the silver spikes in the groove is 40-60 nm, the depth of the silver spikes outside the groove is 60-120 nm, and the density ratio of the silver spikes outside the groove to the silver spikes inside the groove is 2-10.

2. The method for preparing a TBC solar cell according to claim 1, wherein: In the polishing step S1, the back side of the silicon wafer is polished to obtain a silicon wafer with a tower base of 15-25 μm.

3. The method for preparing a TBC solar cell according to claim 1, wherein: In the S2, one-time deposition and doping, the LPCVD deposition method is adopted, the deposition temperature is 550-650℃, the time is 60-120min, and then boron diffusion is carried out, the boron diffusion temperature is 900-1000℃, and the boron diffusion time is 60-120min. The thickness of the prepared tunneling oxide layer is 1-2nm, the thickness of the boron-doped polysilicon layer is 200-400nm, and the thickness of the borosilicate glass layer is 40-70nm.

4. The method for preparing a TBC solar cell according to claim 1, wherein: In the S3, one laser treatment, the laser wavelength is 300-600 nm, the frequency is 100 kHz-10 MHz, the speed is 2-10 m / s, the distance between the laser scanning areas in the length direction of the silicon wafer is 0.5-1.5 mm, and the laser depth is 1-3 μm.

5. The method for preparing a TBC solar cell according to claim 1, wherein: In the S4, alkaline solution treatment, the depth of the groove formed on the back of the silicon wafer is 2-5 μm, the bottom of the groove is a polished morphology, the tower base in the area outside the groove is 15-25 μm, and the tower base in the area inside the groove is 20-40 μm.

6. The method for preparing a TBC solar cell according to claim 1, wherein: In the S5, secondary deposition and diffusion, the LPCVD deposition method is adopted, the deposition temperature is 550-650°C, the deposition time is 30-60min, and then phosphorus diffusion is carried out, the phosphorus diffusion temperature is 800-900°C, the diffusion time is 30-90min, and the thickness of the prepared tunneling oxide layer is 1-2nm, the thickness of the phosphorus-doped polysilicon layer is 100-200nm, and the thickness of the phosphosilicate glass layer is 30-50nm.

7. The method for preparing a TBC solar cell according to claim 1, wherein: In the acid solution treatment S7, the silicon wafer is pickled with an acid solution having a concentration of 10-20% hydrofluoric acid, 30-50% nitric acid and 10-15% sulfuric acid, and the pickling time is 1-2 minutes.

8. The method for preparing a TBC solar cell according to claim 1, wherein: In the cleaning step S9, hydrofluoric acid is used to remove all the remaining borosilicate glass layer and phosphosilicate glass layer on the back of the silicon wafer.

9. The method for preparing a TBC solar cell according to claim 1, wherein: In the S11, passivation layer deposition, the passivation anti-reflection layer includes one or more of silicon nitride, silicon oxynitride and silicon oxide, the thickness of the passivation anti-reflection layer outside the groove is 60-90nm, and the thickness ratio of the passivation anti-reflection layer inside the groove to that outside the groove is 1.05-1.

15.

10. A TBC solar cell, characterized in that: The TBC solar cell is prepared by the preparation method according to any one of claims 1 to 9.

Images