Semiconductor device

Abstract

A semiconductor device (1) includes: a semiconductor layer (40) divided into three regions of a first region (A1), a second region (A2), and a third region (A3) that do not overlap each other in plan view; a first vertical MOS transistor (10) formed in the first region (A1); a second vertical MOS transistor (20) formed in the second region (A2); and a third vertical MOS transistor (30) formed in the third region (A3). A first gate wire (118) of the first vertical MOS transistor (10) and a third gate wire (138) of the third vertical MOS transistor (30) are electrically connected in series via a first diode (113) that is forward in this order, and a second gate wire (128) of the second vertical MOS transistor (20) and the third gate wire (138) are electrically connected in series via a second diode (123) that is forward in this order.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device of a chip size package type. BACKGROUND

[0002] A vertical MOS transistor is sometimes used in a circuit in which two systems having different specification current values are combined into one system.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent No. 7253674 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] Miniaturization of a circuit in which a vertical MOS transistor is used is required.

[0008] MEANS FOR SOLVING THE PROBLEMS

[0009] To solve the above problems, a semiconductor device of one embodiment of the present disclosure is a chip size packaged semiconductor device which can be mounted face down, and includes: a semiconductor layer including a semiconductor substrate on the back surface side, the semiconductor layer being divided into three regions, i.e., a first region, a second region, and a third region, which do not overlap each other and are each not dispersed when the semiconductor device is observed in plan view; a first vertical MOS transistor formed in the first region of the semiconductor layer; a second vertical MOS transistor formed in the second region of the semiconductor layer; a third vertical MOS transistor formed in the third region of the semiconductor layer; and a metal layer formed in contact with the back surface side of the semiconductor layer; the semiconductor substrate is a common drain region of the first vertical MOS transistor, the second vertical MOS transistor, and the third vertical MOS transistor; a first source pad and a first gate pad of the first vertical MOS transistor and a first gate wiring connected to the first gate pad are formed at a position included in the first region when the semiconductor device is observed in plan view; a second source pad and a second gate pad of the second vertical MOS transistor and a second gate wiring connected to the second gate pad are formed at a position included in the second region when the semiconductor device is observed in plan view; a third source pad and a third gate wiring of the third vertical MOS transistor are formed at a position included in the third region when the semiconductor device is observed in plan view; the first gate wiring and the third gate wiring are electrically connected in series through a first diode whose direction from the first gate wiring toward the third gate wiring is a forward direction; and the second gate wiring and the third gate wiring are electrically connected in series through a second diode whose direction from the second gate wiring toward the third gate wiring is a forward direction.

[0010] Effects of Invention

[0011] By using the vertical MOS transistor of the triple structure described above in a circuit in which two conduction paths having different specification current values are combined into one, for example, the area required for the circuit can be reduced compared to the related art.

[0012] Thus, according to the semiconductor device described above, miniaturization of a circuit using a vertical MOS transistor can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a cross-sectional schematic view of an example of the structure of a semiconductor device of an embodiment.

[0014] Figure 2A is a planar schematic view of an example of the structure of a semiconductor device of an embodiment.

[0015] Figure 2Bis a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0016] Figure 3A is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0017] Figure 3B is a cross-sectional view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0018] Figure 3C is a cross-sectional view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0019] Figure 4A is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0020] Figure 4B is a cross-sectional view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0021] Figure 4C is a cross-sectional view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0022] Figure 5A is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0023] Figure 5B is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0024] Figure 6 is a circuit diagram showing an example of use of a semiconductor device of an embodiment.

[0025] Figure 7 is a circuit diagram showing an example of use of a semiconductor device of an embodiment.

[0026] Figure 8A is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0027] Figure 8B is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0028] Figure 9A is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0029] Figure 9B is a plan view schematically showing a part of a structure of a semiconductor device of an embodiment.

[0030] Figure 10Ais a plan view schematically showing a modification of the configuration of the semiconductor device of the embodiment.

[0031] Figure 10B is a plan view schematically showing a modification of the configuration of the semiconductor device of the embodiment.

[0032] Figure 11 is a graph depicting the relationship between the area of a transistor in a plan view and ESD resistance. DETAILED DESCRIPTION

[0033] The embodiments described below each represent one specific example of the present disclosure. The numerical values, shapes, materials, configurations, arrangement positions, and connection modes, and the like shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0034] In the present disclosure, "A is electrically connected to B" includes the case where A and B are directly connected via a wiring, the case where A and B are directly connected without a wiring, and the case where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0035] (Embodiment)

[0036] [1. Configuration of Semiconductor Device]

[0037] Hereinafter, the configuration of the semiconductor device of the embodiment will be described. The semiconductor device of the embodiment is a chip size package (CSP) type semiconductor device capable of face-down mounting, in which three longitudinal MOS (Metal Oxide Semiconductor) transistors of a triple structure are formed in a semiconductor substrate. The three longitudinal MOS transistors are power transistors, and are so-called trench MOS type FETs (Field Effect Transistors).

[0038] Figure 1 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device 1 of the embodiment. Figure 2A , Figure 2B is a plan view schematically showing an example of the configuration of the semiconductor device 1 of the embodiment. In Figure 2A , Figure 2B , the size and shape of the semiconductor device 1 are an example. In addition, the size, shape, and arrangement of the pads and electrodes are also an example.

[0039] Further, Figure 2BThis diagram illustrates the state immediately following the formation of the first source electrode 11 (part 13), first gate electrode 19, first gate wiring 118, second source electrode 21 (part 23), second gate electrode 29, second gate wiring 128, third source electrode 31 (part 33), and third gate wiring 138 on the surface side of semiconductor layer 40. Pads that should not be visible at this point are indicated by dashed lines. The various components will be described later.

[0040] Figure 1 It is along Figure 2A II is the cut surface when semiconductor device 1 is cut.

[0041] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor substrate 42, a metal layer 41, and a low-concentration impurity layer 43 formed on the semiconductor substrate 42. In this disclosure, the semiconductor substrate 42 and the low-concentration impurity layer 43 are collectively referred to as the semiconductor layer 40.

[0042] A semiconductor substrate 42 is disposed on the back side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities of a first concentration. The semiconductor layer 40 has a low-concentration impurity layer 43 of the first conductivity type, formed in contact with the semiconductor substrate 42, containing impurities of a second concentration lower than the first concentration. The low-concentration impurity layer 43 is formed on the semiconductor substrate 42, for example, by epitaxial growth.

[0043] like Figure 1 and Figure 2A As shown, the semiconductor device 1 includes: a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10"), which is formed entirely in a first region A1 of the semiconductor layer 40; a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20"), which is formed entirely in a second region A2 of the semiconductor layer 40; and a third vertical MOS transistor 30 (hereinafter also referred to as "transistor 30"), which is formed entirely in a third region A3 of the semiconductor layer 40.

[0044] The term "transistor 10, which is entirely formed within the first region A1" means that, when viewed in a planar manner, all elements constituting transistor 10 are contained within the first region A1 and not within any region other than the first region A1. Similarly, the term "transistor 20, which is entirely formed within the second region A2" means that, when viewed in a planar manner, all elements constituting transistor 20 are contained within the second region A2 and not within any region other than the second region A2. Likewise, the term "transistor 30, which is entirely formed within the third region A3" means that, when viewed in a planar manner, all elements constituting transistor 30 are contained within the third region A3 and not within any region other than the third region A3.

[0045] like Figure 2AAs shown, when viewed in a planar manner, the surface of the semiconductor layer 40 is divided into a first region A1, a second region A2, and a third region A3, which are non-overlapping and separately arranged. Here, "the first region A1, the second region A2, and the third region A3 are separately arranged" means that each of these regions does not have an adjacent enclave. Figure 2A In the diagram, dashed lines represent the imaginary boundary lines 90 that divide the first region A1, the second region A2, and the third region A3. For ease of understanding, the dashed lines representing the boundary lines 90 are shown as extending to the outside of the semiconductor layer 40, but the actual boundary lines 90 terminate at the outer periphery of the semiconductor layer 40 when viewed in a plane (in...). Figure 2A , Figure 2B For convenience, the termination points of boundary line 90 are designated as P1, P2, P3, and P4, respectively. Boundary line 90 will be discussed later.

[0046] In addition, Figure 2A In the diagram, for ease of understanding, the dashed lines representing the first region A1, the second region A2, and the third region A3 are not strictly aligned with the outer perimeter and boundary line 90 of the semiconductor layer 40. Instead, they are shown on the inside with some blank areas. However, in reality, the outer perimeters of the first region A1, the second region A2, and the third region A3 are aligned with the outer perimeter and boundary line 90 of the semiconductor layer 40. When viewed in a plane, the semiconductor device 1 of this embodiment does not contain any region that is neither the first region A1, the second region A2, nor the third region A3.

[0047] The metal layer 41 is formed in contact with the back side of the semiconductor layer 40, and as a non-limiting example, it can be made of silver (Ag) or copper (Cu). In addition, the metal layer 41 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material.

[0048] like Figure 1 As shown, in the first region A1 of the low-concentration impurity layer 43, a first body region 18 of a second conductivity type different from the first conductivity type is formed. A first source region 14 of the first conductivity type is formed in the first body region 18.

[0049] Furthermore, a plurality of first gate trenches 17 are formed in the first region A1. These first gate trenches 17 are formed to a depth extending from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a portion of the low-concentration impurity layer 43. A first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trenches 17. The first gate conductor 15 is a buried gate electrode embedded inside the semiconductor layer 40. The first gate conductor 15 is electrically connected to the first gate electrode 19 via the first gate wiring 118 (see reference). Figure 2B ).

[0050] The first source electrode 11 includes a portion 12 and a portion 13, wherein the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13.

[0051] Part 12 of the first source electrode 11 is a layer that bonds with solder during reflow when mounted face down. As a non-limiting example, it may be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of part 12.

[0052] The portion 13 of the first source electrode 11 is a layer that connects the portion 12 to the semiconductor layer 40. As a non-limiting example, it may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0053] The first gate electrode 19 may be formed simultaneously with the first source electrode 11, and may be formed with the same structure and / or the same material as the first source electrode 11.

[0054] like Figure 2B As shown, the first gate wiring 118 is configured to surround portion 13 of the first source electrode 11 and the first gate electrode 19 when viewed in a planar manner. The first gate wiring 118 is connected in series with the first gate electrode 19 via a first gate resistor element 117. Figure 3B This is a cross-sectional schematic diagram showing the first gate resistor element 117. Figure 3B It is along Figure 3A II-II is the cut surface when semiconductor device 1 is cut. Figure 3A It will be Figure 2B The enlarged planar diagram of region A11, enclosed by the dashed line.

[0055] like Figure 2B As shown, when viewed in a plane, a first Zener diode 115 is disposed between a portion 13 of the first source electrode 11 and the first gate electrode 19. Figure 3C This is a cross-sectional schematic diagram including the first Zener diode 115. Figure 3C It is along Figure 3A The cut surface when semiconductor device 1 is cut off (III-III). A portion 13 of the first gate electrode 19 and the first source electrode 11 is electrically connected via the first Zener diode 115.

[0056] The gate resistance element and the Zener diode are provided for the purpose of preventing the transistor from being destroyed when an excess voltage is applied to the gate electrode, that is, for the purpose of improving the ESD (Electro Static Discharge) resistance. The first gate resistance element 117 and the first Zener diode 115 can be formed by, for example, implanting impurities into polysilicon. By controlling the kind, the amount of implantation, and the position of implantation of the impurities, respectively, it is possible to control the resistivity of the first gate resistance element 117, the position, the number, and the electric direction of the PN junction in the first Zener diode 115.

[0057] For example, as shown in FIG. 1, the first Zener diode 115 can be alternately formed with a portion which is implanted with impurities of the first conductivity type and becomes the first conductivity type and a portion which is implanted with impurities of the second conductivity type and becomes the second conductivity type. In the example shown in FIG. 1, between the first gate electrode 19 and the portion 13 of the first source electrode 11, two PN junctions are formed bidirectionally by the first Zener diode 115. Figure 3C Figure 3C In the example shown in FIG. 1, between the first gate electrode 19 and the portion 13 of the first source electrode 11, two PN junctions are formed bidirectionally by the first Zener diode 115.

[0058] On the outer periphery of the first region Al, a first EQR (Equi potential Ring) 116 which is electrically connected to the semiconductor substrate 42 can be provided when viewed in plan. The first EQR 116 is provided for the purpose of preventing a leakage current from flowing between the outside and the first body region 18 for the transistor 10. The first EQR 116 can be composed of a metal material including any one or more of aluminum, copper, gold, and silver, for example, as a non-limiting example.

[0059] Furthermore, in the semiconductor device 1 of the embodiment, it is not necessary to necessarily provide a gate resistance element, a Zener diode, and an EQR.

[0060] In the second region A2 of the low-concentration impurity layer 43, a second body region 28 of the second conductivity type is formed. In the second body region 28, a second source region 24 of the first conductivity type is formed.

[0061] Furthermore, in the second region A2, a plurality of second gate trenches 27 are formed which are formed to a depth reaching a portion of the low-concentration impurity layer 43 from the upper surface of the semiconductor layer 40, and further, a second gate conductor 25 is formed on a second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode which is buried inside the semiconductor layer 40. The second gate conductor 25 is electrically connected to a second gate electrode 29 via a second gate wiring 128 (see FIG. 2). Figure 2B

[0062] ​​The second source electrode 21 includes a portion 22 and a portion 23, with portion 22 connected to the second source region 24 and the second body region 28 via portion 23.

[0063] The portion 22 of the second source electrode 21 is a layer that bonds with the solder during reflow when mounted face down. As a non-limiting example, it can be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. A plating layer such as gold can be applied to the surface of the portion 22.

[0064] The portion 23 of the second source electrode 21 is a layer that connects the portion 22 to the semiconductor layer 40. As a non-limiting example, it may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0065] The second gate electrode 29 may be formed simultaneously with the second source electrode 21, and may be formed with the same structure and / or the same material as the second source electrode 21.

[0066] like Figure 2B As shown, the second gate wiring 128 is configured to surround a portion 23 of the second source electrode 21 and the second gate electrode 29 when viewed in a planar manner. The second gate wiring 128 is connected in series with the second gate electrode 29 via a second gate resistor element 127.

[0067] like Figure 2B As shown, when viewed in a planar view, a second Zener diode 125 is disposed between a portion 23 of the second source electrode 21 and the second gate electrode 29. The second gate electrode 29 and the portion 23 of the second source electrode 21 are electrically connected via the second Zener diode 125.

[0068] The second gate resistor element 127 and the second Zener diode 125 can both be formed, for example, by implanting impurities into polysilicon. By controlling the type, amount, and location of the impurities, the resistivity of the second gate resistor element 127 and the location, number, and electrical direction of the PN junctions in the second Zener diode 125 can be controlled.

[0069] The second Zener diode 125 can be, for example, with... Figure 3C It has the same construction as the first Zener diode 115 shown.

[0070] When viewed in planar view, a second EQR126 electrically connected to the semiconductor substrate 42 may be disposed on the outer periphery of the second region A2. For the transistor 20, the second EQR126 is provided to prevent leakage current from flowing between the external region and the second body region 28. As a non-limiting example, the second EQR126 may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0071] A third body region 38 of a second conductivity type is formed in the third region A3 of the low-concentration impurity layer 43. A third source region 34 of a first conductivity type is formed in the third body region 38. Furthermore, a plurality of third gate trenches 37 are formed in the third region A3, the trenches extending from the upper surface of the semiconductor layer 40 through the third source region 34 and the third body region 38 to a portion of the low-concentration impurity layer 43. A third gate conductor 35 is formed on the third gate insulating film 36 inside the third gate trenches 37. The third gate conductor 35 is a buried gate electrode embedded inside the semiconductor layer 40. The third gate conductor 35 is electrically connected to the third gate wiring 138 (see reference). Figure 2B ).

[0072] The third source electrode 31 includes a portion 32 and a portion 33, with portion 32 connected to the third source region 34 and the third body region 38 via portion 33.

[0073] The portion 32 of the third source electrode 31 is a layer that bonds with the solder during reflow when mounted face down. As a non-limiting example, it may be made of any one or more metallic materials including nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of the portion 32.

[0074] The portion 33 of the third source electrode 31 is a layer that connects the portion 32 to the semiconductor layer 40. As a non-limiting example, it may be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0075] When viewed in planar view, a third EQR 136 electrically connected to the semiconductor substrate 42 can be disposed on the outer periphery of the third region A3. For the transistor 30, the third EQR 136 is provided to prevent leakage current from flowing between the external region and the third body region 38. As a non-limiting example, the third EQR 136 can be made of any one or more metallic materials including aluminum, copper, gold, and silver.

[0076] like Figure 2B As shown, the third gate wiring 138 is configured to surround a portion 33 of the third source electrode 31 when viewed in planar view. However, in this disclosure, there is no gate electrode or gate pad connected to the third gate wiring 138 at the location included in the third region A3. Furthermore, the gate resistor element and Zener diode that could be disposed in the first region A1 or the second region A2 are not formed.

[0077] The third gate wiring 138 is connected in series with the first gate wiring 118 via the first diode 113. The first diode 113 is formed in such a way that it is electrically positive from the first gate wiring 118 toward the third gate wiring 138. Figure 4Bis a cross-sectional view showing the first diode 113. Figure 4B is a cross-sectional view showing the first resistance element 114. Figure 4A is a cross-sectional view showing the semiconductor device 1 when it is cut along Figure 4A is a plan view showing the region A12 surrounded by the broken line in Figure 2B is a plan view showing the region A12 surrounded by the broken line in

[0078] The third gate wiring 138 is connected in series with the first gate wiring 118 via the first resistance element 114. Therefore, the first diode 113 and the first resistance element 114 are in a parallel connection relationship between the first gate wiring 118 and the third gate wiring 138. Figure 4C is a cross-sectional view showing the first resistance element 114. Figure 4C is a cross-sectional view showing the semiconductor device 1 when it is cut along Figure 4A is a cross-sectional view showing the semiconductor device 1 when it is cut along

[0079] The first resistance element 114 and the first diode 113 can each be formed by, for example, implanting impurities into polysilicon. By controlling the kind of impurities, the amount of implantation, and the position of implantation, respectively, the resistivity of the first resistance element 114, the position, the number, and the electric direction of the PN junction in the first diode 113 can be controlled.

[0080] For example, as shown in Figure 4B , the first diode 113 can each be formed with a portion that is implanted with impurities of the first conductivity type to become the first conductivity type and a portion that is implanted with impurities of the second conductivity type to become the second conductivity type. In the example shown in Figure 4B , only a PN junction that becomes forward in the direction from the first gate wiring 118 toward the third gate wiring 138 is formed.

[0081] The third gate wiring 138 is connected in series with the second gate wiring 128 via the second diode 123. The second diode 123 is formed in a manner that the direction from the second gate wiring 128 toward the third gate wiring 138 is forward in electricity. In addition, the third gate wiring 138 is connected in series with the second gate wiring 128 via the second resistance element 124. Therefore, the second diode 123 and the second resistance element 124 are in a parallel connection relationship between the second gate wiring 128 and the third gate wiring 138.

[0082] The second resistance element 124 and the second diode 123 can each be formed by, for example, implanting impurities into polysilicon. By controlling the kind of impurities, the amount of implantation, and the position of implantation, respectively, the resistivity of the second resistance element 124, the position, the number, and the electric direction of the PN junction in the second diode 123 can be controlled.

[0083] The second diode 123 is, for example, a diode that is the same as Figure 4BThe first diode 113 is similarly configured, except that a PN junction that is electrically positive in the direction from the second gate wiring 128 toward the third gate wiring 138 is formed.

[0084] As Figure 1 shown, the first body region 18 and the first source region 14 are covered with the interlayer insulating layer 44 having an opening, and a portion 13 of the first source electrode 11 is provided so as to be connected to the first source region 14 through the opening of the interlayer insulating layer 44. The interlayer insulating layer 44 and the portion 13 of the first source electrode 11 are covered with the passivation layer 45 having an opening, and a portion 12 is provided so as to be connected to the portion 13 of the first source electrode 11 through the opening of the passivation layer 45.

[0085] Similarly, the second body region 28 and the second source region 24 are covered with the interlayer insulating layer 44 having an opening, and a portion 23 of the second source electrode 21 is provided so as to be connected to the second source region 24 through the opening of the interlayer insulating layer 44. The interlayer insulating layer 44 and the portion 23 of the second source electrode 21 are covered with the passivation layer 45 having an opening, and a portion 22 is provided so as to be connected to the portion 23 of the second source electrode 21 through the opening of the passivation layer 45.

[0086] Similarly, the third body region 38 and the third source region 34 are covered with the interlayer insulating layer 44 having an opening, and a portion 33 of the third source electrode 31 is provided so as to be connected to the third source region 34 through the opening of the interlayer insulating layer 44. The interlayer insulating layer 44 and the portion 33 of the third source electrode 31 are covered with the passivation layer 45 having an opening, and a portion 32 is provided so as to be connected to the portion 33 of the third source electrode 31 through the opening of the passivation layer 45.

[0087] Therefore, as will be described later, the first source pad 111, the second source pad 121, and the third source pad 131 each refer to a portion of the first source electrode 11, the second source electrode 21, and the third source electrode 31, respectively, which is partially exposed on the surface of the semiconductor device 1, i.e., a terminal. Similarly, the first gate pad 119 and the second gate pad 129 each refer to a portion of the first gate electrode 19 and the second gate electrode 29, respectively, which is partially exposed on the surface of the semiconductor device 1, i.e., a terminal. Figure 2B As will also be described later, the first source pad 111, the second source pad 121, and the third source pad 131 each refer to a portion of the first source electrode 11, the second source electrode 21, and the third source electrode 31, respectively, which is partially exposed on the surface of the semiconductor device 1, i.e., a terminal. Similarly, the first gate pad 119 and the second gate pad 129 each refer to a portion of the first gate electrode 19 and the second gate electrode 29, respectively, which is partially exposed on the surface of the semiconductor device 1, i.e., a terminal.

[0088] The number of the first source pad 111, the second source pad 121, and the third source pad 131 is not necessarily limited to Figure 2A the number illustrated. In addition, the shape of the first source pad 111, the second source pad 121, and the third source pad 131 is not necessarily limited to Figure 2AThe exemplified oblong shape can also be, for example, rectangular or circular. Furthermore, the configuration of the first source pad 111, the second source pad 121, and the third source pad 131 is not limited to... Figure 2A The illustrated configuration.

[0089] The number of the first gate pad 119 and the second gate pad 129 is not necessarily limited to [number missing]. Figure 2A The number shown can also be two or more. Furthermore, the shapes of the first gate pad 119 and the second gate pad 129 need not be separately limited to... Figure 2A The circular shape shown can also be rectangular or oblong.

[0090] With the above-described structure of transistors 10, 20, and 30, the area directly above the semiconductor substrate 42 in the semiconductor substrate 42 and the low-concentration impurity layer 43 is a common drain region that combines the first drain region of transistor 10, the second drain region of transistor 20, and the third drain region of transistor 30.

[0091] Metal layer 41 is a common drain electrode that makes the first drain electrode of transistor 10, the second drain electrode of transistor 20, and the third drain electrode of transistor 30 common.

[0092] Furthermore, in this disclosure, the center of the shape is defined as follows when viewed in a plane. For example... Figure 2A For a circular shape like the first gate pad 119, it refers to its center. For a rectangular shape like the first region A1, it refers to the intersection of its diagonals. For an oblong region like the first source pad 111, it refers to the intersection of the axis of symmetry of the line extending in its length direction and the axis of symmetry of the line extending in its width direction.

[0093] In addition, such as Figure 2A As shown, the first region A1 and the second region A2 are configured to sandwich the third region A3. In this disclosure, "the first region A1 and the second region A2 sandwiching the third region A3" means that the first region A1 and the third region A3 are adjacent to each other without any other regions sandwiching them, and the second region A2 and the third region A3 are adjacent to each other without any other regions sandwiching them. Therefore, when viewed in a planar view of the semiconductor layer 40, the third region A3 is adjacent to both the first region A1 and the second region A2.

[0094] The phrase "adjacent to another region in planar observation" has the same meaning as "opposite," referring to the fact that their outer perimeters are consistent at a 90° boundary line between them. Hereinafter, the length of the 90° boundary line is sometimes referred to as the "opposite length."

[0095] like Figure 2BAs shown, the boundary line 90 between the first region A1 and the third region A3 can be understood as an imaginary line along the central position of the interval between the portion 13 of the first source electrode 11 and the portion 33 of the third source electrode 31. Furthermore, the boundary line 90 has a finite width, but can also be understood as the interval itself. Even this interval can be identified as a line to the naked eye or at low magnification. The boundary line 90 between the first region A1 and the third region A3... Figure 2A , Figure 2B The example shown is a dashed line from P1 to P2.

[0096] Furthermore, when viewed in a planar manner, if the first EQR116 is located on the outer periphery of the first region A1 and the third EQR136 is located on the outer periphery of the third region A3, the first EQR116 and the third EQR136 can be common to a single unit at the point where the outer periphery of the first region A1 coincides with the outer periphery of the third region A3. In this case, the location where the common EQR is located can be understood in a planar view as the boundary line 90 between the first region A1 and the third region A3.

[0097] In short, such as Figure 2B As shown, in the semiconductor device 1 of the embodiment, the first diode 113 is disposed across the boundary line 90 between the first region A1 and the third region A3 when viewed in a planar manner. That is, when viewed in a planar manner, one end of the first diode 113 is located in the first region A1, and the other end is located in the third region A3.

[0098] like Figure 2B As shown, in the semiconductor device 1 of the embodiment, the first resistive element 114 is provided across the boundary line 90 between the first region A1 and the third region A3 when viewed in a plane. That is, when viewed in a plane, one end of the first resistive element 114 is located in the first region A1, and the other end is located in the third region A3.

[0099] The boundary line 90 between the second region A2 and the third region A3 can be understood as an imaginary line along the central position of the interval between the portion 23 of the second source electrode 21 and the portion 33 of the third source electrode 31. Alternatively, although it has a finite width, it can also be understood as the interval itself. Figure 2A , Figure 2B In the example shown, the boundary line 90 between the second region A2 and the third region A3 is a dashed line from P3 through P5 to P4.

[0100] Further, in a case where the second EQR 126 is provided at the outer periphery of the second region A2 and the third EQR 136 is provided at the outer periphery of the third region A3, the second EQR 126 and the third EQR 136 can be commonized to be one at a position where the outer periphery of the second region A2 coincides with the outer periphery of the third region A3 in planar view. The position where the commonized EQR is provided can be understood as the boundary line 90 between the second region A2 and the third region A3 in planar view.

[0101] In summary, as Figure 2B indicated, in the semiconductor device 1 of the embodiment, the second diode 123 is provided across the boundary line 90 between the second region A2 and the third region A3 in planar view. That is, one of the end portions of the second diode 123 is positioned in the second region A2 and the other is positioned in the third region A3 in planar view.

[0102] As Figure 2B indicated, in the semiconductor device 1 of the embodiment, the second resistance element 124 is provided across the boundary line 90 between the second region A2 and the third region A3 in planar view. That is, one of the end portions of the second resistance element 124 is positioned in the second region A2 and the other is positioned in the third region A3 in planar view.

[0103] In addition, although not shown in Figure 2A , Figure 2B , a case where the first region A1 and the second region A2 are contiguous can also be considered (see the modification example shown in Figure 10A , Figure 10B ). The boundary line between the first region A1 and the second region A2 can be understood as an imaginary line along the central position of the interval of the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. In addition, it can also be understood as the interval itself, although it is of limited width.

[0104] Further, in a case where the first EQR 116 is provided at the outer periphery of the first region A1 and the second EQR 126 is provided at the outer periphery of the second region A2, the first EQR 116 and the second EQR 126 can be commonized to be one at a position where the outer periphery of the first region A1 coincides with the outer periphery of the second region A2 in planar view. The position where the commonized EQR is provided can be understood as the boundary line between the first region A1 and the second region A2 in planar view.

[0105] In the semiconductor device 1 of the embodiment, as Figure 2A , Figure 2BAs shown, the area al of the first region Al in plan view is larger than the area a3 of the third region A3 in plan view (al > a3). Further, the area a3 of the third region A3 in plan view is larger than the area a2 of the second region A2 in plan view (a3 > a2). Thus, the first region Al, the second region A2, and the third region A3 have a relationship of areas in plan view of al > a3 > a2.

[0106] On the other hand, in Figure 2B In the example shown, the area of the portion 13 of the first source electrode 11 formed in the first region Al in plan view is approximately equal to the area of the portion 33 of the third source electrode 31 formed in the third region A3 in plan view. This is because, as explained above, the area al of the first region Al in plan view is larger than the area a3 of the third region A3 in plan view (al > a3), but since the first gate electrode 19 is formed in the first region Al, the area al of the first region Al increases accordingly.

[0107] Figure 5A and Figure 5B are a plan view and a perspective view of a substantially unit structure of the transistors 10, 20, 30 repeatedly formed in the X direction and the Y direction of the semiconductor device 1 of the embodiment, respectively. In Figure 5A and Figure 5B In the drawings, the semiconductor substrate 42 and the metal layer 41, and the passivation layer 45 and the first source electrode 11, the second source electrode 21, the third source electrode 31, the interlayer insulating layer 44 are not illustrated for ease of understanding.

[0108] Further, the Y direction refers to a direction parallel to the surface of the semiconductor layer 40 and in which the first gate trench 17 extends. In addition, the X direction refers to a direction parallel to the surface of the semiconductor layer 40 and orthogonal to the Y direction. The Z direction refers to a direction orthogonal to both the X direction and the Y direction and indicating the height direction of the semiconductor device 1.

[0109] As shown in Figure 5A and Figure 5B The transistor 10 has a first connection portion 18a electrically connecting the first bulk region 18 and the first source electrode 11. The first connection portion 18a is a region of the first bulk region 18 in which the first source region 14 is not formed, and is the same second conductivity type as the first bulk region 18. The first source region 14 and the first connection portion 18a are alternately and periodically repeatedly arranged along the Y direction. The same applies to the transistor 20 and the transistor 30.

[0110] In the semiconductor device 1 of the present disclosure, the first conductivity type is set to N type, the second conductivity type is set to P type, the first source region 14, the second source region 24, the third source region 34, the semiconductor substrate 42, and the low-concentration impurity layer 43 are N-type semiconductors, and the first body region 18, the first connection portion 18a, the second body region 28, the second connection portion 28a, the third body region 38, and the third connection portion 38a are P-type semiconductors.

[0111] [2. Operation of semiconductor device]

[0112] In the semiconductor device 1 of the embodiment, it is assumed that a current flows with one of the first source pad 111 of the first region Al or the second source pad 121 of the second region A2 as an inflow port, via the common drain region and the back surface drain electrode 41, with the third source pad 131 of the third region A3 as an outflow port. That is, in the embodiment, conduction in which a drive is conducted in a path from the first source pad 111 to the second source pad 121 or a reverse path thereof is not assumed.

[0113] In the semiconductor device 1, a conduction path in which a current flows with the first source pad 111 of the first region Al as an inflow port and with the third source pad 131 of the third region A3 as an outflow port is referred to as a first conduction path. A conduction path in which a current flows with the second source pad 121 of the second region A2 as an inflow port and with the third source pad 131 of the third region A3 as an outflow port is referred to as a second conduction path.

[0114] In the first conduction path, a current flows as follows. First, in the semiconductor device 1, a high voltage is applied to the first source electrode 11, a low voltage is applied to the third source electrode 31, and a voltage equal to or greater than a threshold value and large enough is applied to the first gate electrode 19 (the first gate conductor 15) with the first source electrode 11 as a reference (ON control). Thus, a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18.

[0115] Further, the voltage applied to the first gate electrode 19 is transmitted to the third gate conductor 35 via the first gate wiring 118, the first diode 113, and the third gate wiring 138. If the voltage is equal to or greater than a threshold value (ON control), a conduction channel is formed in the vicinity of the third gate insulating film 36 in the third body region 38. At this time, a current flows in a path of the first source electrode 11 - the first source region 14 - the conduction channel formed in the first body region 18 - the low-concentration impurity layer 43 - the semiconductor substrate 42 - the metal layer 41 - the semiconductor substrate 42 - the low-concentration impurity layer 43 - the conduction channel formed in the third body region 38 - the third source region 34 - the third source electrode 31, and the semiconductor device 1 becomes in an ON state.

[0116] The above-described path is a first conduction path. The semiconductor device 1 of the embodiment is a configuration in which the transistor 30 is naturally controlled to be on in a case where the transistor 10 is controlled to be on.

[0117] Note that, in the case where the first conduction path is made to be on, the PN junction at the contact surface between the second body region 28 in the transistor 20 and the low-concentration impurity layer 43 functions as a body diode. Therefore, conduction from the first source pad 111 to the second source pad 121 does not occur. In the case where the first conduction path is used in the semiconductor device 1, it is preferable that a voltage above the threshold value is not applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20 (OFF control).

[0118] In addition, the first diode 113 has a certain voltage drop. The voltage applied to the first gate electrode 19 in order to make the first conduction path to be on needs to be adjusted to increase the voltage drop of the first diode 113 by an amount compared with the threshold value of the transistor 30.

[0119] In addition, the third gate wiring 138 is connected to the second gate wiring 128 via the second diode 123, but the second diode 123 is formed in a manner that the direction from the third gate wiring 138 to the second gate wiring 128 is reversed in terms of electricity. Therefore, the voltage applied to the first gate electrode 19 is not transmitted to the second gate wiring 128 (second gate conductor 25).

[0120] In addition, the third gate wiring 138 is connected to the second gate wiring 128 via the second resistance element 124, but the resistance value of the second resistance element 124 is adjusted to be a size at which the voltage from the third gate wiring 138 is sufficiently reduced. Therefore, the voltage applied to the first gate electrode 19 is not transmitted to the second gate wiring 128 (second gate conductor 25) at least in a size above the threshold value.

[0121] In the second conduction path, current flows as follows. First, in the semiconductor device 1, a high voltage is applied to the second source electrode 21, a low voltage is applied to the third source electrode 31, and a voltage above the threshold value and large enough is applied to the second gate electrode 29 (second gate conductor 25) with the second source electrode 21 as a reference (on control). Then, an on channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28.

[0122] Further, the voltage applied to the second gate electrode 29 is transmitted to the third gate conductor 35 via the second gate wiring 128 and the second diode 123 and the third gate wiring 138. If this voltage is above the threshold value (on control), an on channel is formed in the vicinity of the third gate insulating film 36 in the third body region 38. At this time, current flows in the path of the second source electrode 21 - the second source region 24 - the on channel formed in the second body region 28 - the low-concentration impurity layer 43 - the semiconductor substrate 42 - the metal layer 41 - the semiconductor substrate 42 - the low-concentration impurity layer 43 - the on channel formed in the third body region 38 - the third source region 34 - the third source electrode 31, and the semiconductor device 1 becomes in an on state.

[0123] The above-described path is a second on path. The semiconductor device 1 of the embodiment is a configuration in which the transistor 30 is naturally on-controlled in the case where the transistor 20 is on-controlled.

[0124] Note that, at the time of turning on the second on path, the PN junction at the contact surface of the first body region 18 and the low-concentration impurity layer 43 in the transistor 10 functions as a body diode. Therefore, conduction from the second source pad 121 to the first source pad 111 does not occur. In the case where the second on path is used in the semiconductor device 1, it is preferable that, for the first gate electrode 19 (the first gate conductor 15) of the transistor 10, no voltage above the threshold value is applied (off control).

[0125] Further, the second diode 123 has a certain voltage drop. The voltage applied to the second gate electrode 29 in order to turn on the second on path needs to be adjusted to increase the voltage drop of the second diode 123 by an amount compared to the threshold value of the transistor 30.

[0126] Further, the third gate wiring 138 is connected to the first gate wiring 118 via the first diode 113, but the first diode 113 is formed in a manner that the direction from the third gate wiring 138 toward the first gate wiring 118 becomes reverse in terms of electricity. Therefore, the voltage applied to the second gate electrode 29 is not transmitted to the first gate wiring 118 (the first gate conductor 15).

[0127] Further, the third gate wiring 138 is connected to the first gate wiring 118 via the first resistance element 114, but the resistance value of the first resistance element 114 is adjusted to be a size at which the voltage from the third gate wiring 138 is sufficiently reduced. Therefore, the voltage applied to the second gate electrode 29 is not transmitted at least in a size above the threshold value to the first gate wiring 118 (the first gate conductor 15).

[0128] As explained above, it is preferable that the first diode 113 is configured to have only one PN junction so as to cause as little unnecessary drop as possible before the voltage applied to the first gate pad 119 is transferred to the third gate wiring 138. In addition, it is required that the first resistance element 114 has a resistance value large enough to cause the voltage applied to the first gate pad 119 to drop to a voltage below the threshold value before being transferred to the second gate wiring 128.

[0129] Likewise, it is preferable that the second diode 123 is configured to have only one PN junction so as to cause as little unnecessary drop as possible before the voltage applied to the second gate pad 129 is transferred to the third gate wiring 138. In addition, it is required that the second resistance element 124 has a resistance value large enough to cause the voltage applied to the second gate pad 129 to drop to a voltage below the threshold value before being transferred to the first gate wiring 118.

[0130] In addition, in either the first conduction path or the second conduction path, the current flowing inside the semiconductor device 1 in the horizontal direction almost always passes through the metal layer 41 having a low resistivity, but a part of the current also flows through the semiconductor substrate 42.

[0131] [3. Usage example of semiconductor device]

[0132] Figure 6 is a circuit diagram showing a part of a power supply circuit through which a current flows from the first power supply 51 and the second power supply 52, which can be separately attached and detached, to the load 6 via the semiconductor device 1 of the embodiment. Here, the potential of the first power supply 51 is higher than the potential of the second power supply 52, with the potential of the load 6 as a reference.

[0133] The semiconductor device 1 of the embodiment is configured to realize a function of merging two systems of power supply from the first power supply 51 of a high potential and power supply from the second power supply 52 of a low potential lower than the first power supply 51, and collecting them as one system toward the load 6 of a low potential downstream.

[0134] The maximum value of the current flowing by the power supply from the first power supply 51 of a high potential is set to I1 [A], and the maximum value of the current flowing by the power supply from the second power supply 52 of a low potential lower than the first power supply 51 is set to I2 [A]. I1 and I2 can each be understood as a specification maximum current value of the first conduction path and the second conduction path described in a product data sheet of the semiconductor device 1 of the embodiment.

[0135] Based on the potential relationship between the first power supply 51 and the second power supply 52, there exists a relationship of I1 > I2. The side of the first power supply 51, which is energized by a relatively large current I1, is connected to the first source pad 111 of the transistor 10, which has a large area when viewed from the planar perspective in the semiconductor device 1. The side of the second power supply 52, which is energized by a relatively small current I2, is connected to the second source pad 121 of the transistor 20, which has a small area when viewed from the planar perspective in the semiconductor device 1.

[0136] Furthermore, a switching element 8 (e.g., a single-weight vertical MOS transistor) is connected between the semiconductor device 1 and the second power supply 52. ​​A control IC 4 is connected to the switching element 8 and the semiconductor device 1, and the switching element 8, transistor 10 and transistor 20 are independently controlled to be on / off.

[0137] First, let's explain the state where only the first power supply 51 is connected and the second power supply 52 is not connected. Figure 6 (In the state where the second power supply 52 is not present). At this time, the control IC4 controls the conduction of transistor 10 and the cutoff of transistor 20. Since transistor 10 is controlled to conduct, transistor 30 is naturally also controlled to conduct. Thus, power is supplied from the first power supply 51 to the load 6 via the first conduction path within the semiconductor device 1.

[0138] The first conduction path is an internal conduction path of the semiconductor device 1. As previously explained, it is a conduction path through which current flows, with the first source pad 111 of transistor 10 as the inlet and the third source pad 131 of transistor 30 as the outlet. When the first conduction path is turned on, transistor 20 is turned off. Because transistor 20 is turned off, it is possible to prevent current flowing through the power supply from the first power supply 51 from flowing to the second power supply 52 side.

[0139] Next, the state where only the second power supply 52 is connected and the first power supply 51 is not connected will be explained. Figure 6 (In the state where the first power supply 51 is not present). At this time, the control IC4 controls the conduction of transistor 20 and the cutoff of transistor 10. Since transistor 20 is controlled to conduct, transistor 30 is also naturally controlled to conduct. Thus, power is supplied from the second power supply 52 to the load 6 via the second conduction path within the semiconductor device 1.

[0140] The second conduction path is an internal conduction path of semiconductor device 1. As previously explained, it is a conduction path through which current flows, with the second source pad 121 of transistor 20 as the inlet and the third source pad 131 of transistor 30 as the outlet. When the second conduction path is turned on, transistor 10 is turned off. Because transistor 10 is turned off, it is possible to prevent current flowing through the power supply from the second power supply 52 from flowing to the first power supply 51 side.

[0141] When the first power supply 51 and the second power supply 52 are connected simultaneously ( Figure 6 In the first state (of power supply 51), the switching element 8 is first turned off by the control IC4, thus enabling power supply only from the first power supply 51. This is because the first power supply 51 has a higher potential, giving it an advantage in power supply. Then, by turning on transistor 10 and turning off transistor 20, transistor 30 is also turned on, supplying power from the first power supply 51 to the load 6 via the first conduction path.

[0142] [4. Effects of Semiconductor Devices]

[0143] exist Figure 7 The text shows that in Figure 6 The power supply circuit shown is a comparative example in which the semiconductor device 1 of the embodiment is not used. Hereinafter, the effects of using the semiconductor device 1 of the embodiment will be explained by comparison with the comparative example.

[0144] exist Figure 7 In the comparative examples shown, instead of the semiconductor device 1 in the embodiment, for example, it is used in... Figure 8A and Figure 8B The schematic diagram shows an example of a single-structure vertical MOS transistor 10B (hereinafter referred to as transistor 10B), and in... Figure 9A and Figure 9B The schematic diagram shows an example of a single-structure vertical MOS transistor 20B (hereinafter referred to as transistor 20B). Furthermore, immediately in front of the load 6, connected to... Figure 8A , Figure 8B The schematic diagram shows an example of a single-structure vertical MOS transistor 30B (hereinafter referred to as transistor 30B).

[0145] In transistors 10B, 20B, and 30B, for components that are the same as those in the semiconductor device 1 of the embodiment, the reference numeral B is added to the corresponding component's reference numerals.

[0146] When viewed in a planar manner, transistor 10B has a drain pad 151B in addition to two source pads 111B and a gate pad 119B. The drain pad 151B of transistor 10B is connected to the surface drain electrode, for example, serving as an outlet for current flowing into the source pads 111B of transistor 10B.

[0147] When viewed in a planar manner, transistor 20B has a drain pad 152B in addition to two source pads 121B and a gate pad 129B. The drain pad 152B of transistor 20B is connected to the surface drain electrode, for example, serving as an outlet for current flowing into the source pads 121B of transistor 20B.

[0148] When viewed in a planar manner, transistor 30B has a drain pad 153B in addition to two source pads 131B and a gate pad 139B. The drain pad 153B of transistor 30B is connected to the surface drain electrode, for example, serving as an inlet for current flowing out to the source pads 131B of transistor 30B.

[0149] exist Figure 8B , Figure 9B In the middle, a plan view of the semiconductor device 1 of this embodiment is shown ( Figure 2B The same situation is shown below, illustrating the case after the surface drain electrode is connected to the source electrode portion 13B (23B, 33B), gate electrode 19B (29B, 39B), gate wiring 118B (128B, 138B), and drain pad 151B (152B, 153B) that has just been formed on the surface side of semiconductor layer 40. Figure 8B , Figure 9B In the diagram, pads that should not be visible at this point in time are shown with dashed lines for ease of understanding.

[0150] The area of ​​the source electrode portion 13B of transistor 10B when viewed in a planar view is the same as the area of ​​the first source electrode portion 13 of transistor 10 in the semiconductor device 1 of the embodiment when viewed in a planar view. Furthermore, the area of ​​the source electrode portion 33B of transistor 30B when viewed in a planar view is the same as the area of ​​the third source electrode portion 31 of transistor 30 in the semiconductor device 1 of the embodiment when viewed in a planar view. Therefore, in Figure 7 The on-resistance of the path from the first power supply 51 through transistors 10B and 30B to the load 6 can be understood as being related to... Figure 6 The on-resistance of the first conduction path of the semiconductor device 1 in the embodiment is the same.

[0151] In addition, the area of the portion 23B of the source electrode of the transistor 20B in plan view is the same as the area of the portion 23 of the second source electrode 21 of the transistor 20 included in the semiconductor device 1 of the embodiment in plan view. Thus, in Figure 7 the on-resistance of the path from the second power supply 52 to the load 6 via the transistor 20B and the transistor 30B in the embodiment of Figure 6 can be understood to be equivalent to the on-resistance of the second on-path of the semiconductor device 1 in the embodiment of

[0152] In the power supply circuit shown in Figure 7 , in the case where only the first power supply 51 is connected (the second power supply 52 is not present in Figure 7 ), the transistor 20B is controlled to be off by the control IC 4, and the current flowing by power supply from the first power supply 51 is prevented from flowing to the second power supply 52 side. Further, the gate pad 119B of the transistor 10B is applied with a voltage above the threshold value and is controlled to be on, and further, the gate pad 139B of the transistor 30B is also applied with a voltage above the threshold value and is controlled to be on.

[0153] Thus, the current flowing by power supply from the first power supply 51 flows in from the source pad 111B of the transistor 10B, flows out from the drain pad 151B, and thereafter, flows in from the drain pad 153B of the transistor 30B, and flows out from the source pad 131B. As shown in Figure 8A , Figure 8B , the area of the transistor 10B in plan view (the area of the portion 13B of the source electrode) is relatively large because the current flowing by power supply from the first power supply 51 is relatively large.

[0154] In the power supply circuit shown in Figure 7 , in the case where only the second power supply 52 is connected (the first power supply 51 is not present in Figure 7 ), the transistor 10B is controlled to be off by the control IC 4, and the current flowing by power supply from the second power supply 52 is prevented from flowing to the first power supply 51 side. Further, the gate pad 129B of the transistor 20B is applied with a voltage above the threshold value and is controlled to be on, and further, the gate pad 139B of the transistor 30B is also applied with a voltage above the threshold value and is controlled to be on.

[0155] Thus, the current flowing by power supply from the second power supply 52 flows in from the source pad 121B of the transistor 20B, flows out from the drain pad 152B, and thereafter, flows in from the drain pad 153B of the transistor 30B, and flows out from the source pad 131B. As shown in Figure 9A , Figure 9BAs shown, the area of the transistor 20B in plan view (the area of the portion 23B of the source electrode) is relatively small because the current flowing by the power supply from the second power supply 52 is relatively small.

[0156] As described above, in the power supply circuit of the comparative example, Figure 7 As shown, the transistors 10B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 10 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit. Figure 6 As shown, the transistors 20B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 20 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit. Figure 7 As shown, the transistors 20B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 20 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit. Figure 6 As shown, the transistors 20B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 20 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit.

[0157] However, in the circuit board mounting the power supply circuit of the comparative example, Figure 7 As shown, the transistors 20B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 20 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit.

[0158] On the other hand, in the circuit board mounting the power supply circuit as shown, Figure 6 As shown, the transistors 20B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 20 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit.

[0159] Further, in the semiconductor device 1 of the embodiment, the drain pads (151B, 152B, 153B) each possessed by the transistors 10B, 20B, and 30B in the comparative example can be deleted. Further, in the semiconductor device 1 of the embodiment, since the third transistor 30 does not have a gate pad, the gate pad 139B formed in the transistor 30B in the comparative example as shown can also be deleted. Figure 7 Figure 8B As shown, the transistors 20B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 20 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit.

[0160] As described above, if the semiconductor device 1 of the embodiment is used, the area required for the circuit board can be greatly reduced. In the circuit board mounting the power supply circuit as shown, Figure 6 As shown, the transistors 20B and 30B in the power supply circuit of the comparative example function in the same manner as the transistors 20 and 30 provided in the semiconductor device 1 of the embodiment of the power supply circuit. ​

[0161] Thus, the semiconductor device 1 of the embodiment is a chip size package type semiconductor device 1 capable of face-down mounting, and includes: a semiconductor layer 40 having a semiconductor substrate 42 on a back surface side, and being divided into three regions, i.e., a first region Al, a second region A2, and a third region A3, which do not overlap each other and are each not dispersed when the semiconductor device 1 is viewed in plan; a first vertical MOS transistor 10 formed entirely in the first region Al of the semiconductor layer 40; a second vertical MOS transistor 20 formed entirely in the second region A2 of the semiconductor layer 40; a third vertical MOS transistor 30 formed entirely in the third region A3 of the semiconductor layer 40; and a metal layer 41 formed in contact with the back surface side of the semiconductor layer 40; the semiconductor substrate 42 is a common drain region of the first vertical MOS transistor 10, the second vertical MOS transistor 20, and the third vertical MOS transistor 30, and, when viewed in plan, a first source pad 111 and a first gate pad 119 of the first vertical MOS transistor 10 and a first gate wire 118 connected to the first gate pad 119 are formed at a position included in the first region Al; when viewed in plan, a second source pad 121 and a second gate pad 129 of the second vertical MOS transistor 20 and a second gate wire 128 connected to the second gate pad 129 are formed at a position included in the second region A2; when viewed in plan, a third source pad 131 and a third gate wire 138 of the third vertical MOS transistor 30 are formed at a position included in the third region A3; the first gate wire 118 and the third gate wire 138 are electrically connected in series via a first diode 113 having a forward direction from the first gate wire 118 toward the third gate wire 138, and the second gate wire 128 and the third gate wire 138 are electrically connected in series via a second diode 123 having a forward direction from the second gate wire 128 toward the third gate wire 138.

[0162] The semiconductor device 1 of the embodiment is configured such that the first diode 113 is provided so that the transistor 30 is naturally controlled to be on when the transistor 10 is controlled to be on, and the first on path is on. At this time, the second diode 123 is formed in reverse in electrical terms from the third gate wire 138, and thus the transistor 20 is not controlled to be on.

[0163] Likewise, the second on path is on by virtue of the configuration in which the second diode 123 is provided so that the transistor 30 is naturally controlled to be on when the transistor 20 is controlled to be on. At this time, the first diode 113 is formed in reverse in electrical terms from the third gate wire 138, and thus the transistor 10 is not controlled to be on.

[0164] One end of the first diode 113 is connected to the first gate wiring 118, and the other end is connected to the third gate wiring 138. Similarly, one end of the second diode 123 is connected to the second gate wiring 128, and the other end is connected to the third gate wiring 138.

[0165] Therefore, in the semiconductor device 1 of the embodiment, the first diode 113 is formed such that, when viewed in a planar view, one end of the first diode 113 is located in a first region A1 and the other end of the first diode 113 is located in a third region A3, and when viewed in a planar view, the second diode 123 is formed such that one end of the second diode 123 is located in a second region A2 and the other end of the second diode 123 is located in a third region A3.

[0166] If the first diode 113 and the second diode 123 are formed as described above, it is also possible to prevent the conduction area of ​​the first conduction path or the second conduction path from being unnecessarily reduced.

[0167] like Figure 2B As shown, typically, the first diode 113 is positioned across the boundary line 90 (the dashed line from P1 to P2) between the first region A1 and the third region A3 when viewed in a planar manner. When the first EQR 116 is positioned in the first region A1 and the third EQR 136 is positioned in the third region A3, the common point between the first EQR 116 and the third EQR 136 when viewed in a planar manner becomes the boundary line 90 between the first region A1 and the third region A3. However, in order to position the first diode 113, there are cases where the common EQR portion must be partially truncated.

[0168] Therefore, in the semiconductor device 1 of the embodiment, a first EQR 116 may be formed in at least a portion of the outer periphery of the first region A1 when viewed in a planar view, and a third EQR 136 may be formed in at least a portion of the outer periphery of the third region A3 when viewed in a planar view. In the portion where the first region A1 and the third region A3 are opposite each other when viewed in a planar view, the first EQR 116 and the third EQR 136 are common. In the portion where the first EQR and the third EQR are not common when viewed in a planar view, the first diode 113 may be provided at the location where the common EQR is interrupted, forming the boundary line 90 between the first region A1 and the third region A3.

[0169] In addition, Figure 6In the power supply circuit shown, there is a case where no voltage is applied to both the first gate pad 119 and the second gate pad 129. At this time, with respect to the semiconductor device 1, depending on the use state immediately before, there is a case where a residual potential is present in either the first gate wire 118 and the third gate wire 138, or the second gate wire 128 and the third gate wire 138.

[0170] If the first gate wire 118 and the third gate wire 138 are connected via the first resistance element 114, even if the resistance value of the first resistance element 114 is high, a path is formed that releases the residual potentials of the first gate wire 118 and the third gate wire 138 to the first gate pad 119, and thus is preferable. Similarly, if the second gate wire 128 and the third gate wire 138 are connected via the second resistance element 124, even if the resistance value of the second resistance element 124 is high, a path is formed that releases the residual potentials of the second gate wire 128 and the third gate wire 138 to the second gate pad 129, and thus is preferable.

[0171] Therefore, in the semiconductor device 1 of the embodiment, it can also be that the first gate wire 118 and the third gate wire 138 are connected in series via the first resistance element 114, the first diode 113 and the first resistance element 114 are connected in parallel between the first gate wire 118 and the third gate wire 138, the second gate wire 128 and the third gate wire 138 are connected in series via the second resistance element 124, and the second diode 123 and the second resistance element 124 are connected in parallel between the second gate wire 128 and the third gate wire 138.

[0172] One end of the first resistance element 114 is connected to the first gate wire 118, and the other end is connected to the third gate wire 138. Similarly, one end of the second resistance element 124 is connected to the second gate wire 128, and the other end is connected to the third gate wire 138.

[0173] Therefore, in the semiconductor device 1 of the embodiment, it is preferable that, in plan view, the first resistance element 114 be formed such that one end of the first resistance element 114 is positioned in the first region Al and the other end of the first resistance element 114 is positioned in the third region A3, and, in plan view, the second resistance element 124 be formed such that one end of the second resistance element 124 is positioned in the second region A2 and the other end of the second resistance element 124 is positioned in the third region A3.

[0174] If the first resistance element 114 and the second resistance element 124 are formed as described above, an effect of preventing the conduction area of the first conduction path or the second conduction path from being unnecessarily reduced can also be obtained.

[0175] In the semiconductor device 1 of the embodiment, the first conduction path has the first source pad 111 of the first region Al as an inflow port and the third source pad 131 of the third region A3 as an outflow port. Therefore, if the first region Al and the third region A3 are adjacent when viewed in plan, the first conduction path is shortened and the conduction resistance can be reduced, which is preferable. Similarly, the second conduction path has the second source pad 121 of the second region A2 as an inflow port and the third source pad 131 of the third region A3 as an outflow port. Therefore, if the second region A2 and the third region A3 are adjacent when viewed in plan, the second conduction path is shortened and the conduction resistance can be reduced, which is preferable.

[0176] Therefore, it is preferable that the first region Al and the second region A2 are arranged to sandwich the third region A3 when viewed in plan, and the third region A3 is adjacent to the first region Al and the second region A2.

[0177] In the semiconductor device 1 of the embodiment, the conduction resistance of the first conduction path is reduced. Therefore, as shown in Figs. 1 and 2, it is preferable that the first region Al is arranged to be adjacent to the third region A3 when viewed in plan. Figure 2A or Figure 2B If the arrangement of the semiconductor device 1 when viewed in plan is as described above, the place where the current density is the highest in the first conduction path can be enlarged (the length of the opposing line is made longer), so the conduction resistance can be reduced.

[0178] In the semiconductor device 1 of the embodiment, it is preferable that the inflow port and the outflow port in the first conduction path through which a relatively large current flows have the same degree of area when viewed in plan. This is because if one of the inflow port and the outflow port is relatively small, the place becomes a bottleneck and the conduction resistance increases.

[0179] Therefore, in the semiconductor device 1 of the embodiment, it is preferable that the first source electrode of the first vertical MOS transistor 10 is formed at a position included in the first region Al when viewed in plan, the third source electrode of the third vertical MOS transistor 30 is formed at a position included in the third region A3 when viewed in plan, and the area of the first source electrode and the area of the third source electrode are substantially the same when viewed in plan. The first source electrode and the third source electrode herein refer to the portions 13 and 33 of the first source electrode 11 and the third source electrode 31 that directly contact the semiconductor layer 40.

[0180] In addition, in the semiconductor device 1 of the embodiment, the gate pad and the gate electrode are not present in the third region A3 in plan view, and thus even if the portion 13 of the first source electrode 11 and the portion 33 of the third source electrode 31 have the same area in plan view, the area a3 of the third region A3 can be made smaller than the area al of the first region A1.

[0181] In addition, the second conduction path has a small rated current, and thus the area of conduction can be reduced in consideration of this. At this time, it is not a problem that the area of the flow outlet (the portion 33 of the third source electrode 31) is larger than the area of the flow inlet (the portion 23 of the second source electrode 21) in plan view.

[0182] Thus, in the semiconductor device 1 of the embodiment, it is preferable that the area al of the first region A1 be larger than the area a3 of the third region A3 in plan view, and the area a3 of the third region A3 be larger than the area a2 of the second region A2 in plan view. In addition, the difference between the area al of the first region A1 in plan view and the area a3 of the third region A3 in plan view is approximately the amount of one first gate pad 119.

[0183] In Figure 10A , Figure 10B a plan view showing a modification of the configuration of the semiconductor device 1 of the embodiment is shown. Figure 10B With Figure 2B the same, a case is shown in which the portion 13 of the first source electrode 11, the first gate electrode 19, the first gate wiring 118, the portion 23 of the second source electrode 21, the second gate electrode 29, the second gate wiring 128, the portion 33 of the third source electrode 31, and the third gate wiring 138 have just been formed on the surface side of the semiconductor layer 40. The pads that should not be seen at this point in time are illustrated with dotted lines.

[0184] In Figure 10A , Figure 10B the modification shown, the third region A3 is not disposed sandwiched by the first region A1 and the second region A2 as compared with Figure 2A , Figure 2B , and there is a portion at which the first region A1 and the second region A2 are contiguous. In addition, in plan view, the first gate pad 119 is disposed in the first region A1 at a position close to the third region A3.

[0185] The first gate pad 119 being disposed in the first region A1 at a position close to the third region A3 means that, in the first region A1, between the first gate pad 119 and the third region A3 closest to the first gate pad 119, no portion of the first source pad 111 is disposed sandwiched therebetween.

[0186] According to such a configuration, the connection distance of the first gate pad 119 to the third gate wiring 138 can be shortened. Therefore, the voltage applied to the first gate pad 119 can be promptly transmitted to the third gate wiring 138, and thus the response speed of the semiconductor device 1 can be improved. This effect is the same for the configuration of the second gate pad 129 and the third region A3 when viewed in plan.

[0187] Therefore, it can also be that the first gate pad 119 is disposed at a position close to the third region A3 when viewed in plan, and the second gate pad 129 is disposed at a position close to the third region A3 when viewed in plan.

[0188] Further, in either of the examples shown in Figure 2B and Figure 10B it is preferable that, in a case where the first Zener diode 115 and / or the second Zener diode 125 are formed in the semiconductor device 1, the first diode 113 and / or the second diode 123 are also formed at the same time. By forming at the same time, the manufacturing of the semiconductor device 1 can be facilitated.

[0189] The first Zener diode 115 and / or the second Zener diode 125 are diodes as is the first diode 113 and / or the second diode 123, and the functions thereof can be realized only by appropriately controlling the formation position, number, or direction of the PN junction in the electric aspect. As Figure 2B indicated, the first Zener diode 115 and / or the second Zener diode 125 and the first diode 113 and / or the second diode 123 are only different in the in-plane disposition position when the semiconductor device 1 is viewed in plan. Therefore, they can be formed at the same time only by changing the impurity injection position in the plane accordingly.

[0190] At this time, when the regions having the same conductivity type possessed by the first diode 113 and the first Zener diode 115 are compared with each other when viewed in plan, the concentration of the impurity of the same conductivity type is the same. The same concentration of the impurity means that the concentration distribution of the impurity is substantially uniform when a certain region is compared with a certain region in the depth direction.

[0191] Therefore, it can also be that, when viewed in plan, the first source electrode 11 (of the portion 13) and the first gate electrode 19 of the first vertical MOS transistor 10 are formed at a position included in the first region Al, the first Zener diode 115 is formed between the first source electrode 11 (of the portion 13) and the first gate electrode 19 when viewed in plan, and the impurity of the same conductivity type in the regions of the same conductivity type included in the first diode 113 and the first Zener diode 115 is of the same concentration.

[0192] Also, it is preferable that, in a case where the first gate resistance element 117 and / or the second gate resistance element 127 is formed in the semiconductor device 1, the first resistance element 114 and / or the second resistance element 124 is also formed at the same time. By forming at the same time, it is possible to make the manufacturing of the semiconductor device 1 easy.

[0193] Therefore, it is also possible that, in the first region Al, the first gate electrode 19 of the first vertical MOS transistor 10 is formed, in plan view, the first gate resistance element 117 is formed between the first gate electrode 19 and the first gate wiring 118, in plan view, and the impurities of the same conductivity type in the regions of the same conductivity type included in the first resistance element 114 and the first gate resistance element 117 are of the same concentration.

[0194] [5. Additional Considerations]

[0195] Returning to the semiconductor device 1 using the embodiments Figure 6 In the transistor in the on state, generally, the total gate width increases when the area of the transistor in plan view is large, and thus the on resistance becomes low. That is, the area of the transistor in plan view and the on resistance are in approximately inverse proportion.

[0196] In the semiconductor device 1, the area al in plan view of the transistor 10 forming the first conduction path is larger than the area a2 in plan view of the transistor 20 forming the second conduction path. Therefore, the on resistance of the first conduction path is low, and becomes a path suitable for flowing a relatively large current.

[0197] As for the on resistance Rl [Ω] of the first conduction path, it is determined by taking into account the maximum value Ii [A] of the current flowing by the power supply from the first power supply 51. Also, as for the on resistance R2 [Ω] of the second conduction path, it is determined by taking into account the maximum value I2 [A] of the current flowing by the power supply from the second power supply 52. Therefore, in the semiconductor device 1 of the embodiments, it is preferable that the areas of the transistor 10 and the transistor 20 are decided so as to realize the on resistances suitable for the first conduction path and the second conduction path, respectively.

[0198] However, if the area in plan view of each transistor is too small as calculated above, the ESD resistance can decrease. This is because, if the area in plan view of a transistor is small, the excess voltage applied to the gate electrode, the surge current does not sufficiently disperse in the cell (gate conductor) of the transistor.

[0199] Hereinafter, if the ESD guarantee value (electrostatic discharge protection value) of semiconductor device 1 is denoted as ESDt[V], then in the semiconductor device 1 of the embodiment, it is required to achieve ESDt or higher resistance in the transistor 20 with the smallest area. When using... Figure 6 In the case of a power supply circuit as shown, the ESDt required by semiconductor device 1 is typically around 1000 [V] to 2000 [V].

[0200] To achieve the desired ESDt, for transistor 20, a second Zener diode 125 and / or a second gate resistor element 127 are described. However, as Figure 6 As shown in the portion of transistor 20, setting the second Zener diode 125 results in setting a path that connects the second gate pad 129 (second gate electrode 29) to the second source pad 121 (part 23 of the second source electrode 21), thus creating the side effect of generating leakage current between the gate and source.

[0201] Figure 11 The area a [mm²] of the transistor when viewed in a planar shape, as confirmed by the inventors through experiments. 2 The relationship between this and the maximum voltage value ESDt [V] that confirms the transistor is not damaged when applied to the gate pad is shown. The horizontal axis is a, and the vertical axis is ESDt. Furthermore, regarding the area a of the transistor when viewed in planar view, in the example of semiconductor device 1 of the embodiment, it refers to the area a1 of the first region A1 and the area a2 of the second region A2 when viewed in planar view. That is, it also includes areas that do not contribute to conduction.

[0202] Data plotted using circles was created using transistors that have neither Zener diodes nor gate resistors. Data plotted using triangles was created using transistors that have only Zener diodes and no gate resistors. Data plotted using diamonds was created using transistors that have both Zener diodes and gate resistors.

[0203] according to Figure 11 It is known that, without a gate resistor, there is a tendency for a larger transistor area *a* to result in a higher ESDt. Furthermore, it is also known that even without increasing the transistor area *a*, adding a Zener diode increases ESDt. When a gate resistor is added in addition to the Zener diode, an almost constant ESDt is obtained regardless of the transistor area.

[0204] If it is desired to set the ESD protection value of the semiconductor device 1 in the embodiment to, for example, 2000 [V], it is sufficient to guarantee 2000 [V] for the transistor 20, which has the smallest area when viewed in a planar view. Figure 11, if the area a2 of the transistor 20 in plan view is less than about 2.0 [mm 2 ], it is preferable to provide the second Zener diode 125 and the second gate resistive element 127. On the other hand, according to the provision of the second Zener diode 125, in a case where it is intended to avoid an increase in the gate-source leakage current, it is preferable not to provide the second Zener diode 125. If the necessary ESD guarantee value is 2000 [V], the area a2 of the transistor 20 in plan view can be about 2.0 [mm 2 ] or more.

[0205] Therefore, according to Figure 11 the data of the circular mark, if the electrostatic resistance guarantee value described in the product data sheet of the semiconductor device 1 is set as ESDt [V] and the area of the second region A2 in plan view is set as a2 [mm 2 ], the relationship a2 > (ESDt - 93) / 990 is satisfied.

[0206] Further, at this time, it can also be that, at a position included in the second region A2 in plan view, the portion 23 of the second source electrode 21 and the second gate electrode 29 of the second vertical MOS transistor 20 are formed, a path electrically connecting the portion 23 of the second source electrode 21 and the second gate electrode 29 is not present, and the second gate electrode 29 is connected to the second gate wiring 128 without passing through a resistive body.

[0207] By being configured as described above, in the transistor 20, an increase in the gate-source leakage current can be avoided, and a desired ESD guarantee value (ESDt [V]) is obtained in the semiconductor device 1.

[0208] At this time, in the semiconductor device 1, a sufficient ESDt should have been achieved in the transistor 10 having a larger area in plan view. Therefore, it can be that, at a position included in the first region Al in plan view, the portion 13 of the first source electrode 11 and the first gate electrode 19 of the first vertical MOS transistor 10 are formed, a path electrically connecting the portion 13 of the first source electrode 11 and the first gate electrode 19 is not present, and the first gate electrode 19 is connected to the first gate wiring 118 without passing through a resistive body.

[0209] If this configuration is adopted, in the transistor 10, an unnecessary increase in the gate-source leakage current can be avoided.

[0210] In addition, with respect to the area a2 of the second region A2 in plan view, even if the relationship a2 < (ESDt - 93) / 990 is satisfied, there can be a case where a desired ESD guarantee value can be achieved by providing the second Zener diode 125 and the second gate resistive element 127.

[0211] Therefore, it can also be that, in a plan view, a position included in the first region Al, a portion 13 of the first source electrode 11 forming the first longitudinal MOS transistor 10, and the first gate electrode 19, a path electrically connecting between the portion 13 of the first source electrode 11 and the first gate electrode 19 is not present, the first gate electrode 19 is connected to the first gate wiring 118 without passing through a resistance element, a position included in the second region A2 in a plan view, a portion 23 of the second source electrode 21 forming the second longitudinal MOS transistor 20, and the second gate electrode 29, the portion 23 of the second source electrode 21 and the second gate electrode 29 are connected via the second Zener diode 125, and the second gate electrode 29 and the second gate wiring 128 are connected in series via the second gate resistance element 127.

[0212] By being configured as described above, in the transistor 10, a desired ESD guarantee value (ESDt [V]) of the semiconductor device 1 can be obtained while unnecessary increase in gate-source leakage current is avoided.

[0213] The above-described semiconductor device according to one embodiment of the present disclosure has been described based on the embodiments and modified examples, but the present disclosure is not limited to the embodiments. As long as the spirit of the present disclosure is not deviated from, a mode obtained by applying various modifications that can be thought of by those skilled in the art to these embodiments, a mode constructed by combining constituent elements in different embodiments and modified examples can also be included in the scope of one or more modes of the present disclosure.

[0214] Industrial Applicability

[0215] The semiconductor device having the longitudinal MOS transistor according to the present application can be widely used as a device that controls the on state of a current path.

[0216] Explanation of Reference Numerals

[0217] 1 Semiconductor device

[0218] 4 Control IC

[0219] 6 Load

[0220] 8 Switching element

[0221] 10 Transistor (first longitudinal MOS transistor)

[0222] 10B, 20B, 30B Transistor (longitudinal MOS transistor of single well structure)

[0223] 12, 13, 13B, 22, 23, 23B, 32, 33, 33B Portion

[0224] 14 First source region

[0225] 15 first gate conductor

[0226] 16 first gate insulating film

[0227] 17 first gate trench

[0228] 18 first body region

[0229] 18a first connection portion

[0230] 19 first gate electrode

[0231] 19B, 29B, 39B gate electrode

[0232] 20 transistor (second vertical MOS transistor)

[0233] 21 second source electrode

[0234] 24 second source region

[0235] 25 second gate conductor

[0236] 26 second gate insulating film

[0237] 27 second gate trench

[0238] 28 second body region

[0239] 28a second connection portion

[0240] 29 second gate electrode

[0241] 30 transistor (third vertical MOS transistor)

[0242] 31 third source electrode

[0243] 34 third source region

[0244] 35 third gate conductor

[0245] 36 third gate insulating film

[0246] 37 third gate trench

[0247] 38 third body region

[0248] 38a third connection portion

[0249] 40 semiconductor layer

[0250] 41 metal layer (back surface drain electrode)

[0251] 42 semiconductor substrate

[0252] 43 low-concentration impurity layer

[0253] 44 interlayer insulating layer

[0254] 45 passivation layer

[0255] 90 boundary line

[0256] 111 first source pad

[0257] 111B, 121B, 131B source pad

[0258] 113 first diode

[0259] 114 first resistance element

[0260] 115 first Zener diode

[0261] 116 first EQR

[0262] 117 first gate resistance element

[0263] 118 first gate wiring

[0264] 118B, 128B, 138B gate wiring

[0265] 119 first gate pad

[0266] 119B, 129B, 139B gate pad

[0267] 121 second source pad

[0268] 123 second diode

[0269] 124 second resistance element

[0270] 125 second Zener diode

[0271] 126 second EQR

[0272] 127 second gate resistance element

[0273] 128 second gate wiring

[0274] 129 second gate pad

[0275] 131 third source pad

[0276] 136 third EQR

[0277] 138 third gate wiring

[0278] 151B, 152B, 153B drain pad

[0279] A1 first region

[0280] A2 second region

[0281] A3 third region

Claims

1. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, characterized in that, have: The semiconductor layer has a semiconductor substrate on the back side and is divided into three regions, namely the first region, the second region, and the third region, which are not overlapping each other and are not dispersed when viewed in a planar view of the semiconductor device. The first vertical MOS transistor is integrally formed in the first region of the semiconductor layer; The second vertical MOS transistor is integrally formed in the second region of the semiconductor layer; The third vertical MOS transistor is integrally formed in the third region of the semiconductor layer; as well as A metal layer is formed in contact with the back side of the semiconductor layer. The semiconductor substrate is the common drain region of the first vertical MOS transistor, the second vertical MOS transistor, and the third vertical MOS transistor. When viewed in the planar view, a first source pad and a first gate pad, as well as a first gate wiring connected to the first gate pad, are formed at a location contained within the first region. When viewed in the planar view, a second source pad and a second gate pad, as well as a second gate wiring connected to the second gate pad, are formed at a location included within the second region. When viewed in the plane, the third source pad and the third gate wiring of the third vertical MOS transistor are formed at a location contained within the third region. The first gate wiring and the third gate wiring are electrically connected in series via a first diode oriented in a positive direction from the first gate wiring toward the third gate wiring. The second gate wiring and the third gate wiring are electrically connected in series via a second diode that is positively oriented from the second gate wiring toward the third gate wiring.

2. The semiconductor device according to claim 1, characterized in that, The first diode is formed such that one end of the first diode is located in the first region, and the other end of the first diode is located in the third region. The second diode is formed such that one end of the second diode is located in the second region, and the other end of the second diode is located in the third region.

3. The semiconductor device according to claim 1, characterized in that, The first gate wiring and the third gate wiring are also connected in series via a first resistive element. The first diode and the first resistive element are connected in parallel between the first gate wiring and the third gate wiring. The second gate wiring and the third gate wiring are also connected in series via a second resistive element. The second diode and the second resistor are connected in parallel between the second gate wiring and the third gate wiring.

4. The semiconductor device according to claim 3, characterized in that, The first resistive element is formed such that one end of the first resistive element is located in the first region, and the other end of the first resistive element is located in the third region. The second resistive element is formed such that one end of the second resistive element is located in the second region, and the other end of the second resistive element is located in the third region.

5. The semiconductor device according to claim 1, characterized in that, When viewed from the plane, the first region is adjacent to the third region, and the second region is adjacent to the third region.

6. The semiconductor device according to claim 1, characterized in that, When viewed from the plane, the area of ​​the first region is greater than the area of ​​the third region, and the area of ​​the third region is greater than the area of ​​the second region.

7. The semiconductor device according to claim 6, characterized in that, When viewed in the plane, the first source electrode of the first vertical MOS transistor is formed at a location contained within the first region. When viewed in the plane, the third source electrode of the third vertical MOS transistor is formed at a location contained within the third region. When viewed in the plane, the area of ​​the first source electrode is approximately the same as the area of ​​the third source electrode.

8. The semiconductor device according to claim 1, characterized in that, When viewed in the plane, a first equipotential ring is formed in at least a portion of the outer periphery of the first region. When viewed from the plane, a third equipotential ring is formed in at least a portion of the outer periphery of the third region. When viewed in the plane, in the portion where the first region and the third region are opposite each other, the first equipotential ring and the third equipotential ring are common. When viewed in the plane, the first diode is located in the portion of the first equipotential ring and the third equipotential ring that is not common.

9. The semiconductor device according to claim 1, characterized in that, When viewed from the plane, the first gate pad is positioned close to the third region. When viewed in the plane, the second gate pad is positioned close to the third region.

10. The semiconductor device according to claim 1, characterized in that, When viewed in the plane, the first source electrode and the first gate electrode of the first vertical MOS transistor are formed at a location contained within the first region. When viewed from the plane, a first Zener diode is formed between the first source electrode and the first gate electrode. The impurities of the same conductivity type in the regions containing the first diode and the first Zener diode have the same concentration.

11. The semiconductor device according to claim 3, characterized in that, When viewed in the plane, the first source electrode and the first gate electrode of the first vertical MOS transistor are formed at a location contained within the first region. When viewed in the planar view, a first gate resistor element is formed between the first gate electrode and the first gate wiring. The impurities of the same conductivity type in the regions containing the first resistive element and the first gate resistive element have the same concentration.

12. The semiconductor device according to claim 1, characterized in that, When viewed in the plane, no gate electrode or gate pad connected to the third gate wiring is formed in the location contained within the third region.

13. The semiconductor device according to claim 6, characterized in that, The electrostatic discharge (ESD) resistance guarantee value recorded in the product data sheet of the semiconductor device is set as ESDt in V. The area of ​​the second region during planar observation is set in mm. 2 a2 in units Then the relationship a2>(ESDt-93) / 990 holds true.

14. The semiconductor device according to claim 13, characterized in that, When viewed in the plane, the second source electrode and the second gate electrode of the second vertical MOS transistor are formed at a location contained within the second region. There is no electrical connection between the second source electrode and the second gate electrode. The second gate electrode is connected to the second gate wiring without a resistor.

15. The semiconductor device according to claim 14, characterized in that, When viewed in the plane, the first source electrode and the first gate electrode of the first vertical MOS transistor are formed at a location contained within the first region. There is no electrical connection between the first source electrode and the first gate electrode. The first gate electrode is connected to the first gate wiring without a resistor.

16. The semiconductor device according to claim 6, characterized in that, In the planar view, the first source electrode and the first gate electrode of the first vertical MOS transistor are formed at a location contained within the first region. There is no electrical connection between the first source electrode and the first gate electrode. The first gate electrode and the first gate wiring are connected without a resistor. In the planar view, the second source electrode and the second gate electrode of the second vertical MOS transistor are formed at a location contained within the second region. The second source electrode and the second gate electrode are connected via a second Zener diode. The second gate electrode and the second gate wiring are connected in series between them via a second gate resistor element.

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