Mask, deposition apparatus, and method of manufacturing mask

Abstract

A mask, a deposition apparatus, and a method of manufacturing a mask are provided, the mask including: a first layer defining a first opening; and a second layer disposed on the first layer, in which the second layer includes a deposition pattern having an inverted conical shape in a cross-sectional view. The deposition pattern defines a second opening overlapping the first opening in a plan view, and the second layer includes a first electrode having a lt; 100 gt; and silicon in crystal orientation.

Description

Technical Field

[0001] Embodiments relate to a mask, a deposition apparatus including the mask, and a method of manufacturing the mask. Background Art

[0002] Display devices are typically formed by stacking multiple layers, such as light-emitting layers and metal layers. A deposition process can be performed to form the multiple layers of a display device. The deposition process can be performed by placing a mask having the same pattern as the light-emitting layer, metal layer, etc., in close contact with a target substrate on which deposition is to be performed. In this case, evaporated material ejected from a deposition source can pass through the mask and be deposited on the target substrate. Summary of the Invention

[0003] Embodiments provide a mask with improved reliability.

[0004] An embodiment provides a deposition apparatus including the mask.

[0005] An embodiment provides a method for manufacturing the mask.

[0006] A mask according to a disclosed embodiment includes: a first layer defining a first opening; and a second layer disposed on the first layer, wherein the second layer includes a deposition pattern having an inverted conical shape in a cross-sectional view. In such an embodiment, the deposition pattern defines a second opening overlapping the first opening in a plan view, and the second layer includes a deposition pattern having an inverted conical shape. <100> Crystal orientation of silicon.

[0007] In an embodiment, an angle formed between a surface of the deposition pattern spaced apart from the first layer and a side surface of the deposition pattern may be greater than or equal to about 45° and less than or equal to about 75°.

[0008] In an embodiment, a width of each of the second openings may be greater than or equal to a thickness of the deposition pattern.

[0009] In an embodiment, the first layer may include silicon.

[0010] In an embodiment, the mask may further include an insulating layer disposed between the first layer and the second layer.

[0011] The deposition apparatus according to the disclosed embodiment includes: a deposition source accommodating a deposition material; a mask disposed on the deposition source, wherein the deposition material passes through the mask; and a stage disposed on the mask, wherein a target substrate on which the deposition material is deposited is fixed to the stage. In such an embodiment, the mask includes: a first layer defining a first opening; and a second layer disposed on the first layer, wherein the second layer includes a deposition pattern having an inverted conical shape in a cross-sectional view. In such an embodiment, the deposition pattern defines a second opening overlapping the first opening in a plan view, and the second layer includes a deposition pattern having a <100> Crystal orientation of silicon.

[0012] In an embodiment, an angle formed between a surface of the deposition pattern spaced apart from the first layer and a side surface of the deposition pattern may be greater than or equal to about 45° and less than or equal to about 75°.

[0013] In an embodiment, a width of each of the second openings may be greater than or equal to a thickness of the deposition pattern.

[0014] In an embodiment, the first layer may include silicon.

[0015] In an embodiment, the mask may further include an insulating layer disposed between the first layer and the second layer.

[0016] The method of manufacturing a mask according to the disclosed embodiment includes: forming a first layer defining a first opening by etching a preliminary first layer; and forming a second layer by etching a preliminary second layer disposed below the preliminary first layer, the second layer including a deposition pattern having an inverted tapered shape in a cross-sectional view, wherein the deposition pattern defines a second opening overlapping the first opening in a plan view, and the second layer including a <100> Crystal orientation of silicon.

[0017] In an embodiment, in forming the second layer, the deposition pattern may be formed such that a surface of the deposition pattern spaced apart from the first layer and a side surface of the deposition pattern form an angle of about 45° or more and about 75° or less.

[0018] In an embodiment, in the step of forming the second layer, a width of each of the second openings may be formed to be greater than or equal to a thickness of the deposition pattern.

[0019] In an embodiment, in the step of forming the second layer, the preliminary second layer may be etched using an etchant including potassium hydroxide (KOH).

[0020] In an embodiment, the concentration of potassium hydroxide may be greater than or equal to about 15 weight percent (wt %) and less than or equal to about 70 wt %.

[0021] In an embodiment, the temperature of the potassium hydroxide may be greater than or equal to about 50°C and less than or equal to about 100°C.

[0022] In an embodiment, the step of forming the first layer may include forming an auxiliary pattern defining the auxiliary opening by etching the preliminary first layer.

[0023] In an embodiment, the forming of the auxiliary pattern may include forming a first sub-opening by etching the preliminary first layer, and forming a second sub-opening connected to the first sub-opening by etching the preliminary first layer.

[0024] In an embodiment, in the step of forming the second layer, the auxiliary pattern of the preliminary first layer and the preliminary second layer may be simultaneously etched.

[0025] In an embodiment, the method may further include forming an insulating layer by etching a preliminary insulating layer disposed between the preliminary first layer and the preliminary second layer.

[0026] In a deposition apparatus according to a disclosed embodiment, the deposition apparatus may include a mask comprising silicon. In such an embodiment, the mask may include a deposition pattern defining an opening and having an inverted conical shape in a cross-sectional view. Therefore, the deposition material that passes through the opening of the mask and is deposited on the target substrate may not be deposited in areas other than the deposition area of ​​the target substrate. Therefore, in an embodiment of a display device manufactured using the mask, stains, color mixing, etc. on the display device that may occur when the deposition material is deposited in areas other than the deposition area of ​​the target substrate can be minimized.

[0027] In addition, in the method of manufacturing a mask according to the disclosed embodiment, the etching process of the wafer can be performed sequentially in one direction without any process of flipping the wafer during the etching process of the wafer, so that problems caused by foreign matter, etc. that may occur when flipping the wafer during the manufacturing process of the mask can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a cross-sectional view schematically illustrating a deposition apparatus according to a disclosed embodiment.

[0029] Figure 2 It is shown that the Figure 1 A cross-sectional view of a mask in a deposition apparatus.

[0030] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9 It shows the manufacturing Figure 2 A cross-sectional view of an embodiment of a mask method.

[0031] Figure 10 is a schematic diagram showing the use of Figure 1A cross-sectional view of an embodiment of a display device manufactured using a deposition apparatus. DETAILED DESCRIPTION

[0032] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals represent like elements throughout.

[0033] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0034] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, the "first element," "first component," "first region," "first layer," or "first part" discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0035] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "a," "an," "the," and "at least one" do not indicate a limitation of quantity and are intended to encompass both the singular and the plural. Thus, a reference in a claim to "an element" followed by "the element" includes both one and multiple elements. For example, unless the context clearly indicates otherwise, "element" and "at least one element" have the same meaning. "At least one" is not to be construed as limiting "a" or "an." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms "comprises" and / or its variations or "comprising" and / or its variations are used in this specification, they indicate the presence of the recited features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0036] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the figures is turned over, an element described as being on the "lower" side of the other elements would subsequently be positioned on the "upper" side of the other elements. Thus, depending on the specific orientation of the drawings, the term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in one of the figures is turned over, an element described as being "below" or "beneath" another element would subsequently be positioned "above" the other element. Thus, the terms "below" or "under" can include both "upper" and "lower" orientations.

[0037] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0039] The embodiments are described herein with reference to cross-sectional illustrations which are schematic illustrations of idealized embodiments. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown, but rather are to include deviations in shape due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0040] Hereinafter, the disclosed embodiments will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and any repeated detailed description of the same components will be omitted or simplified.

[0041] Figure 1 is a cross-sectional view schematically illustrating a deposition apparatus according to a disclosed embodiment.

[0042] Reference Figure 1 , an embodiment of a deposition apparatus 1000 may include a chamber CB, a mask 100 , a deposition source 200 , and a stage 300 .

[0043] The deposition apparatus 1000 can deposit a deposition material on a target substrate 10. The target substrate 10 can be a substrate used to manufacture a display device. For example, the target substrate 10 can refer to a display device being manufactured. The target substrate 10 can include a plastic substrate, a glass substrate, a silicon substrate, etc., and can include at least one layer included in the display device. In an embodiment, for example, the target substrate 10 can include at least one selected from an inorganic layer, an organic layer, and a metal layer.

[0044] That is, the deposition apparatus 1000 can be used in a manufacturing process of a display device. For example, the deposition apparatus 1000 can be used in a process of depositing a light-emitting layer on a target substrate 10 in a manufacturing process of a display device. However, the disclosure is not limited thereto, and the deposition apparatus 1000 can be used in various deposition processes in a manufacturing process of a display device.

[0045] In an embodiment, the display device may be a micro light emitting diode display device including micro light emitting diodes as light emitting elements. However, the disclosure is not limited thereto, and in another embodiment, the display device may be an organic light emitting diode display device including organic light emitting diodes as light emitting elements.

[0046] The chamber CB may provide an internal space in which a deposition process may be performed. In an embodiment, in the chamber CB, evaporation of a deposition material and deposition of the deposition material on the target substrate 10 may be performed as a deposition process. In such an embodiment, the internal space of the chamber CB may be maintained in a vacuum state.

[0047] Various components that may be used in a deposition process may be disposed inside the chamber CB. In an embodiment, for example, a mask 100, a deposition source 200, and a stage 300 may be disposed inside the chamber CB.

[0048] The mask 100 may be parallel to a plane defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The mask 100 may have a pattern, and the deposition material may be deposited on the target substrate 10 in a pattern corresponding to the pattern. In an embodiment, for example, the mask 100 may include a deposition film defining a plurality of openings, and the openings may respectively correspond to deposition regions of the target substrate 10.

[0049] In an embodiment, the mask 100 may include silicon. In an embodiment, for example, the mask 100 may include a silicon wafer (Si wafer), a silicon carbide wafer (SiC wafer), a single crystal silicon wafer (single crystal Si wafer), or the like.

[0050] although Figure 1 An embodiment in which the mask 100 is spaced apart from the target substrate 10 by a predetermined interval is shown, but the disclosure is not limited thereto. In another embodiment, for example, the mask 100 may be disposed in contact with the target substrate 10.

[0051] The deposition source 200 may be disposed to face the mask 100. In an embodiment, for example, the deposition source 200 may be disposed below the mask 100 and may be disposed to face the target substrate 10 with the mask 100 interposed therebetween.

[0052] The deposition source 200 can accommodate a deposition material. The deposition source 200 can provide the deposition material to the target substrate 10. In an embodiment, for example, the deposition source 200 can evaporate the deposition material and can provide the evaporated deposition material toward the target substrate 10. In an embodiment, for example, the deposition material can be provided in a third direction DR3 that intersects each of the first direction DR1 and the second direction DR2. For example, the third direction DR3 can be perpendicular to each of the first direction DR1 and the second direction DR2. In such an embodiment, the evaporated deposition material can pass through the mask 100 and be deposited on the target substrate 10. That is, the deposition material can pass through the opening of the mask 100 and be deposited in a deposition area on the target substrate 10. In an embodiment, for example, the deposition source 200 can provide an organic material that forms a light-emitting layer included in a display device, but the disclosure is not limited thereto.

[0053] The stage 300 may be disposed to face the mask 100 in a direction opposite to the deposition source 200. In an embodiment, for example, the stage 300 may be disposed on the mask 100 and may be disposed to face the deposition source 200, with the mask 100 interposed therebetween. The target substrate 10 may be fixed to the stage 300. The target substrate 10 may be fixed to the stage 300 and disposed between the stage 300 and the mask 100.

[0054] Figure 2 It is shown that the Figure 1 A cross-sectional view of a mask in a deposition apparatus. For example, Figure 2 FIG. 1 may be a cross-sectional view schematically illustrating a portion of the mask 100 .

[0055] Reference Figure 1 and Figure 2 , an embodiment of the mask 100 may include a first layer 110 , a second layer 120 , and an insulating layer 130 .

[0056] In an embodiment, the first layer 110 may include silicon. The first layer 110 may include silicon crystal. In an embodiment, for example, the first layer 110 may include single crystal silicon.

[0057] The first layer 110 may define a first opening OP1. The first opening OP1 may be defined to pass through the first layer 110 in the third direction DR3.

[0058] The second layer 120 may be disposed on the first layer 110. In an embodiment, the second layer 120 may include silicon. The second layer 120 may include silicon crystals. In an embodiment, for example, the second layer 120 may include single crystal silicon. In an embodiment, the second layer 120 may include silicon having <100> Crystalline Orientation of Silicon. In such an embodiment, the crystallographic orientation of the silicon included in the second layer 120 can be different from or the same as the crystallographic orientation of the silicon included in the first layer 110.

[0059] The second layer 120 may define a plurality of second openings OP2. The second layer 120 may include a deposition pattern DP defining the second openings OP2. Each of the second openings OP2 may be defined to pass through the second layer 120 in the third direction DR3. The second openings OP2 may be repeatedly arranged along the first direction DR1 or the second direction DR2 and may be spaced apart from each other. In an embodiment, for example, the second openings OP2 may be arranged in a matrix along the first direction DR1 and the second direction DR2. In another embodiment, for example, the second openings OP2 may be arranged along the first direction DR1 or the second direction DR2. The deposition pattern DP may be arranged between adjacent second openings OP2. In an embodiment, for example, the deposition pattern DP may have a mesh shape in a plan view. Here, the phrase "in a plan view" may mean when viewed in the third direction DR3.

[0060] The second opening OP2 may overlap the first opening OP1 in a plan view. The second opening OP2 may be connected to the first opening OP1. The first opening OP1 and the second opening OP2 may be defined to pass through the mask 100 in the third direction DR3.

[0061] In an embodiment, the deposition pattern DP may have an inverted tapered shape in a cross-sectional view. That is, the width of the deposition pattern DP may gradually increase in the third direction DR3, and the side surface SS of the deposition pattern DP may be inclined. Here, the width of the deposition pattern DP may be the length of the deposition pattern DP in the first direction DR1. The side surface SS of the deposition pattern DP may be inclined at a constant angle along the thickness direction of the deposition pattern DP (i.e., the third direction DR3 or a direction opposite to the third direction DR3). Therefore, the angle at which the deposition material provided toward the target substrate 10 in the third direction DR3 passes through the mask 100 may be limited.

[0062] In an embodiment, the angle θ formed between the surface SF of the deposition pattern DP spaced apart from the first layer 110 and the side surface SS of the deposition pattern DP may be greater than or equal to about 45° and less than or equal to about 75°. In an embodiment, for example, the angle θ may be greater than or equal to about 50° and less than or equal to about 60°. In an embodiment, for example, the angle θ may be greater than or equal to about 53° and less than or equal to about 57°. In such an embodiment, the angle θ may be adjusted in such a manner that the deposition material having passed through the mask 100 is not deposited in an area other than the deposition area of ​​the target substrate 10.

[0063] In an embodiment, the width WD of the second opening OP2 may be greater than or equal to the thickness TH of the deposition pattern DP. Here, the width WD of the second opening OP2 may be the length of the second opening OP2 in the first direction DR1, and the thickness TH of the deposition pattern DP may be the length of the deposition pattern DP in the third direction DR3. In other words, the spacing distance between the deposition pattern DP defining the second opening OP2 in the first direction DR1 in a cross-sectional view may be greater than or equal to the thickness TH of the deposition pattern DP. In an embodiment, for example, the width WD of the second opening OP2 may be greater than or equal to approximately 4 micrometers (μm) and less than or equal to approximately 5 μm, and the thickness TH of the deposition pattern DP may be greater than or equal to approximately 1 μm and less than or equal to approximately 4 μm, but the disclosure is not limited thereto.

[0064] If the thickness TH of the deposition pattern DP is greater than the width WD of the second opening OP2, a region where the deposition material is insufficiently deposited may exist in the deposition region on the target substrate 10. Therefore, since the width WD of the second opening OP2 is formed to be greater than or equal to the thickness TH of the deposition pattern DP, the region where the deposition material is insufficiently deposited in the deposition region on the target substrate 10 can be minimized.

[0065] The insulating layer 130 may be provided between the first layer 110 and the second layer 120. The insulating layer 130 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or the like. The insulating layer 130 may define an opening corresponding to the first opening OP1 of the first layer 110. The opening may be defined to pass through the insulating layer 130 in the third direction DR3, and thus, the opening, the first opening OP1, and the second opening OP2 may be defined to pass through the mask 100.

[0066] The deposition apparatus 1000 according to the disclosed embodiment may include a mask 100 including a first layer 110 and a second layer 120. The mask 100 may include silicon, and the second layer 120 may include a deposition pattern DP having an inverted tapered shape in a cross-sectional view. The angle at which the deposition material provided toward the target substrate 10 passes through the mask 100 may be limited by the cross-sectional shape of the deposition pattern DP. Therefore, the deposition material passing through the mask 100 and deposited on the target substrate 10 may not be deposited in areas other than the deposition area of ​​the target substrate 10. Therefore, stains, color mixing, etc. on the display device that may be caused by the deposition material being deposited in areas other than the deposition area of ​​the target substrate 10 can be effectively prevented, thereby improving the display quality of the display device manufactured using the mask 100.

[0067] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9 It shows the manufacturing Figure 2 A cross-sectional view of an embodiment of a mask method.

[0068] Reference Figure 3 and Figure 4 , in an embodiment of a method of manufacturing a mask, a preliminary second layer P_120 and a preliminary insulating layer P_130 may be formed on the preliminary first layer P_110.

[0069] In an embodiment, the preliminary first layer P_110 may include silicon. The preliminary first layer P_110 may include silicon crystal. In an embodiment, for example, the preliminary first layer P_110 may include single crystal silicon.

[0070] The preliminary second layer P_120 may be disposed on the preliminary first layer P_110. In an embodiment, the preliminary second layer P_120 may include silicon. The preliminary second layer P_120 may include silicon crystals. In an embodiment, for example, the preliminary second layer P_120 may include single crystal silicon. In an embodiment, the preliminary second layer P_120 may include silicon having <100> Crystal Orientation of Silicon. In such an embodiment, the crystal orientation of the silicon included in the preliminary second layer P_120 may be different from or the same as the crystal orientation of the silicon included in the preliminary first layer P_110.

[0071] The preliminary insulating layer P_130 may be disposed between the preliminary first layer P_110 and the preliminary second layer P_120. The preliminary insulating layer P_130 may include an inorganic material such as silicon oxide, silicon nitride, or the like.

[0072] Each of the preliminary first layer P_110, the preliminary second layer P_120, and the preliminary insulating layer P_130 may be a flat layer parallel to a plane defined by the first direction DR1 and the second direction DR2. The preliminary first layer P_110, the preliminary insulating layer P_130, and the preliminary second layer P_120 may be sequentially arranged along the third direction DR3. In an embodiment, for example, a wafer including the preliminary first layer P_110, the preliminary insulating layer P_130, and the preliminary second layer P_120 may be provided. In an embodiment, for example, the wafer may be a silicon-on-insulator (SOI) wafer.

[0073] Thereafter, the wafer including the preliminary first layer P_110, the preliminary insulating layer P_130, and the preliminary second layer P_120 may be flipped over. Figure 3 The wafer shown in can be Figure 4 . Thus, the preliminary second layer P_120, the preliminary insulating layer P_130, and the preliminary first layer P_110 may be sequentially arranged along the third direction DR3. However, the disclosure is not limited thereto, and the wafer including the preliminary first layer P_110, the preliminary insulating layer P_130, and the preliminary second layer P_120 may be arranged in the following manner: Figure 4 The inverted state shown in is prepared or provided.

[0074] Reference Figure 4 and Figure 5 , a portion of the preliminary first layer P_110 may be removed to form a first sub-opening SOP1. The first sub-opening SOP1 may be formed not completely through the preliminary first layer P_110.

[0075] The first sub-opening SOP1 may be formed by etching in a direction opposite to the third direction DR3 from a surface of the preliminary first layer P_110 spaced apart from the preliminary second layer P_120. In an embodiment, for example, the first sub-opening SOP1 may be formed by a wet etching process, but the disclosure is not limited thereto.

[0076] Reference Figure 5 and Figure 6 , a portion of the preliminary first layer P_110 may be further removed to form a plurality of second sub-openings SOP2. In addition, a portion of the preliminary first layer P_110 may be removed to form first auxiliary patterns AP1 that define the second sub-openings SOP2.

[0077] The second sub-openings SOP2 may be repeatedly arranged along the first direction DR1 or the second direction DR2 and may be spaced apart from each other. In an embodiment, for example, the second sub-openings SOP2 may be arranged in a matrix along the first direction DR1 and the second direction DR2. In another embodiment, for example, the second sub-openings SOP2 may be arranged along the first direction DR1 or the second direction DR2. The first auxiliary pattern AP1 may be provided between adjacent second sub-openings SOP2. In an embodiment, for example, the first auxiliary pattern AP1 may be formed in a mesh shape in a plan view.

[0078] The second sub-opening SOP2 may be formed by etching from the first sub-opening SOP1 of the preliminary first layer P_110 in a direction opposite to the third direction DR3. In an embodiment, for example, the second sub-opening SOP2 and the first auxiliary pattern AP1 may be formed by a dry etching process, but the disclosure is not limited thereto.

[0079] The second sub-opening SOP2 may be connected to the first sub-opening SOP1, and the first sub-opening SOP1 and the second sub-opening SOP2 may form a first auxiliary opening AOP1. The first auxiliary opening AOP1 may define a first auxiliary pattern AP1 and may be formed to pass through the preliminary first layer P_110 in the third direction DR3. That is, the first auxiliary opening AOP1 and the first auxiliary pattern AP1 may be formed in the preliminary first layer P_110 through an etching process.

[0080] Reference Figure 6 and Figure 7 , a portion of the preliminary insulating layer P_130 may be removed to form a plurality of second auxiliary openings AOP2. In addition, a portion of the preliminary insulating layer P_130 may be removed to form second auxiliary patterns AP2 defining the second auxiliary openings AOP2. Each of the second auxiliary openings AOP2 may be formed to pass through the preliminary insulating layer P_130 in the third direction DR3.

[0081] The second auxiliary openings AOP2 may be repeatedly arranged along the first direction DR1 or the second direction DR2 and may be spaced apart from each other. In an embodiment, for example, the second auxiliary openings AOP2 may be arranged in a matrix along the first direction DR1 and the second direction DR2. In another embodiment, for example, the second auxiliary openings AOP2 may be arranged along the first direction DR1 or the second direction DR2. The second auxiliary pattern AP2 may be provided between adjacent second auxiliary openings AOP2. In an embodiment, for example, the second auxiliary pattern AP2 may be formed in a mesh shape in a plan view.

[0082] Each of the second auxiliary openings AOP2 can be formed by etching from the first auxiliary opening AOP1 of the preliminary first layer P_110 in a direction opposite to the third direction DR3. The second auxiliary pattern AP2 can be formed by etching in a direction opposite to the third direction DR3 using the first auxiliary pattern AP1 of the preliminary first layer P_110 as a mask. Therefore, the second auxiliary opening AOP2 can be connected to the first auxiliary opening AOP1, and the second auxiliary pattern AP2 can overlap with the first auxiliary pattern AP1 in a plan view. In an embodiment, for example, the second auxiliary opening AOP2 and the second auxiliary pattern AP2 can be formed by a dry etching process, but the disclosure is not limited thereto.

[0083] Reference Figure 7 and Figure 8 The first auxiliary pattern AP1 of the preliminary first layer P_110 may be removed to form the first opening OP1, and a portion of the preliminary second layer P_120 may be removed to form the second opening OP2. In addition, a portion of the preliminary second layer P_120 may be removed to form a deposition pattern DP defining the second opening OP2.

[0084] Each of the second openings OP2 can be formed by etching from the second auxiliary openings AOP2 of the preliminary insulating layer P_130 in a direction opposite to the third direction DR3. The deposition pattern DP can be formed by etching in a direction opposite to the third direction DR3 using the second auxiliary pattern AP2 of the preliminary insulating layer P_130 as a mask. Therefore, the second openings OP2 can be connected to the second auxiliary openings AOP2, respectively, and the deposition pattern DP can overlap with the second auxiliary pattern AP2 in a plan view. In an embodiment, for example, the second openings OP2 and the deposition pattern DP can be formed by a wet etching process, but the disclosure is not limited thereto.

[0085] Thus, a first layer 110 defining a first opening OP1 and a second layer 120 including a deposition pattern DP defining a second opening OP2 may be formed. The first opening OP1 may be formed to pass through the first layer 110 in the third direction DR3, and each of the second openings OP2 may be formed to pass through the second layer 120 in the third direction DR3. The first opening OP1 and the second opening OP2 may be connected by a second auxiliary opening AOP2.

[0086] In an embodiment, a portion of the first auxiliary pattern AP1 of the preliminary first layer P_110 and the preliminary second layer P_120 may be removed by the same wet etching process. That is, the first layer 110 and the second layer 120 may be formed by the same wet etching process.

[0087] In an embodiment, the wet etching process may be performed using an etchant including potassium hydroxide (KOH). In an embodiment, for example, the etchant may include potassium hydroxide, water, and isopropyl alcohol.

[0088] In one embodiment, the concentration of potassium hydroxide may be greater than or equal to about 15 weight percent (wt%) and less than or equal to about 70 wt%. In one embodiment, for example, the concentration of potassium hydroxide may be greater than or equal to about 30 wt% and less than or equal to about 45 wt%. If the concentration of potassium hydroxide is less than about 30 wt%, the roughness of the deposition pattern DP of the second layer 120 may be relatively increased.

[0089] In an embodiment, the temperature of potassium hydroxide may be greater than or equal to about 50° C. and less than or equal to about 100° C. In an embodiment, for example, the temperature of potassium hydroxide may be greater than or equal to about 70° C. and less than or equal to about 90° C.

[0090] In such an embodiment, the time for performing the wet etching process may be appropriately changed or controlled according to the concentration of potassium hydroxide and the temperature of potassium hydroxide.

[0091] In an embodiment, the deposition pattern DP of the second layer 120 may be formed to have an inverted tapered (or tapered) shape in a cross-sectional view by a wet etching process. In such an embodiment, the side surface SS of the deposition pattern DP may be formed to be inclined at a constant angle along the thickness direction of the deposition pattern DP (i.e., the third direction DR3 or a direction opposite to the third direction DR3).

[0092] In an embodiment, the deposition pattern DP may be formed such that a surface SF of the deposition pattern DP spaced apart from the first layer 110 and a side surface SS of the deposition pattern DP form an angle θ of about 45° or more and about 75° or less. In an embodiment, for example, the angle θ may be formed to be about 50° or more and about 60° or less. In an embodiment, for example, the angle θ may be formed to be about 53° or more and about 57° or less.

[0093] In an embodiment, since the preliminary second layer P_120 may include <100> The silicon is crystal-oriented, so when the preliminary second layer P_120 is etched by an etchant including potassium hydroxide, a second layer 120 including a deposition pattern DP in which the surface SF and the side surface SS form an angle θ can be formed. In addition, in an embodiment, the width WD of the second opening OP2 can be formed to be greater than or equal to the thickness TH of the deposition pattern DP.

[0094] although Figure 8An embodiment is shown in which the first auxiliary pattern AP1 of the preliminary first layer P_110 is completely removed during the wet etching process for removing a portion of the preliminary first layer P_110 and a portion of the preliminary second layer P_120 to form the first layer 110 and the second layer 120, respectively, but the disclosure is not limited thereto. In an embodiment, for example, a portion of the first auxiliary pattern AP1 of the preliminary first layer P_110 may remain without being removed during the wet etching process, and in such an embodiment, an etching process may be further performed to remove the portion. In an embodiment, for example, the portion of the first auxiliary pattern AP1 that remains unremoved may be removed by a dry etching process.

[0095] Reference Figure 2 、 Figure 8 and Figure 9 , the second auxiliary pattern AP2 of the preliminary insulating layer P_130 may be removed to form the insulating layer 130. The second auxiliary pattern AP2 may be removed to form an opening corresponding to the first opening OP1, and the opening, the first opening OP1, and the second opening OP2 may penetrate the mask 100. In an embodiment, for example, the second auxiliary pattern AP2 may be removed by a dry etching process, but the disclosure is not limited thereto.

[0096] Thus, a mask 100 including a first layer 110 defining a first opening OP1, a second layer 120 including a deposition pattern DP defining a second opening OP2, and an insulating layer 130 disposed between the first layer 110 and the second layer 120 may be manufactured. For example, Figure 9 The mask shown in can be used as Figure 2 The inverted state shown in FIG is used for the deposition process.

[0097] In the method of manufacturing the mask 100 according to the disclosed embodiment, the etching process of the wafer can be sequentially performed in one direction (for example, a direction from the first layer 110 to the second layer 120), and any process of flipping the wafer during the etching process may not be performed, so that problems caused by foreign matter, etc. that may occur when flipping the wafer can be minimized, thereby improving the reliability of the process.

[0098] In such an embodiment, since the wafer includes a preliminary second layer P_120, the preliminary second layer P_120 includes <100> The preliminary second layer P_120 is etched by an etchant including potassium hydroxide, and thus the mask 100 including the deposition pattern DP having an inverted tapered shape in a cross-sectional view can be effectively formed.

[0099] Figure 10 is a schematic diagram showing the use of Figure 1 A cross-sectional view of an embodiment of a display device manufactured using a deposition apparatus. For example, Figure 10It may be a cross-sectional view schematically illustrating a portion of a display device DD manufactured using the deposition apparatus 1000. For example, the display device DD may be formed by cutting the target substrate 10 into a plurality of pieces after manufacturing the target substrate 10 into a plurality of display devices.

[0100] Reference Figure 1 and Figure 10 , an embodiment of the display device DD may include a base substrate SUB, a buffer layer BFR, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a light emitting element LE, a pixel defining layer PDL, and an encapsulation layer TFE.

[0101] In such an embodiment, the transistor TR may include an active pattern ACT, a gate electrode GE, a first electrode SD1 and a second electrode SD2, and the light emitting element LE may include a pixel electrode PE, a light emitting layer EL and a common electrode CE.

[0102] The base substrate SUB may include a transparent material or an opaque material. In an embodiment, for example, the base substrate SUB may include plastic, glass, quartz, silicon, etc. In an embodiment, for example, the base substrate SUB may include a silicon wafer, a silicon carbide wafer, a single crystal silicon wafer, etc. These may be used alone or in combination.

[0103] The buffer layer BFR may be provided on the base substrate SUB. The buffer layer BFR may prevent metal atoms, impurities, etc. from diffusing into the transistor TR. In addition, when the surface of the base substrate SUB is uneven, the buffer layer BFR may improve the flatness of the surface of the base substrate SUB. The buffer layer BFR may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0104] The active pattern ACT may be disposed on the buffer layer BFR. The active pattern ACT may include a source region, a drain region, and a channel region between the source and drain regions. The active pattern ACT may be made of a silicon semiconductor material or an oxide semiconductor material. Examples of silicon semiconductor materials include amorphous silicon and polycrystalline silicon. Examples of oxide semiconductor materials include indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). These materials may be used alone or in combination.

[0105] The gate insulating layer GI may be disposed on the active pattern ACT and may cover the active pattern ACT. The gate insulating layer GI may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0106] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the channel region of the active pattern ACT in a plan view or when viewed in the thickness direction of the base substrate SUB. The gate electrode GE may include a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination.

[0107] The interlayer insulating layer ILD may be provided on the gate electrode GE and may cover the gate electrode GE. The interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0108] The first electrode SD1 and the second electrode SD2 may be disposed on the interlayer insulating layer ILD. The first electrode SD1 may be connected to the source region of the active pattern ACT via a first contact hole defined in the gate insulating layer GI and the interlayer insulating layer ILD. Furthermore, the second electrode SD2 may be connected to the drain region of the active pattern ACT via a second contact hole defined in the gate insulating layer GI and the interlayer insulating layer ILD. In embodiments, each of the first electrode SD1 and the second electrode SD2 may include, for example, a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination.

[0109] Thus, the transistor TR including the active pattern ACT, the gate electrode GE, the first electrode SD1 and the second electrode SD2 may be disposed on the base substrate SUB.

[0110] The via insulating layer VIA may be disposed on the interlayer insulating layer ILD and may cover the first electrode SD1 and the second electrode SD2. The via insulating layer VIA may include an organic material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0111] The pixel electrode PE may be disposed on the via insulating layer VIA. The pixel electrode PE may be connected to the second electrode SD2 via a contact hole defined in the via insulating layer VIA. The pixel electrode PE may include a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. In an embodiment, for example, the pixel electrode PE may function as an anode.

[0112] The pixel defining layer PDL may be disposed on the via insulating layer VIA and may cover at least a portion of the pixel electrode PE. An opening exposing at least a portion of the upper surface of the pixel electrode PE may be defined in the pixel defining layer PDL. The pixel defining layer PDL may include an inorganic material or an organic material. In an embodiment, for example, the pixel defining layer PDL may include an organic material such as an epoxy resin, a silicone resin, or the like. In another embodiment, for example, the pixel defining layer PDL may include an inorganic material or an organic material, the inorganic material or the organic material including a light-shielding material having a black color.

[0113] The light emitting layer EL may be disposed on the pixel electrode PE. The light emitting layer EL may be disposed on the pixel electrode PE exposed by the pixel defining layer PDL. The light emitting layer EL may include an organic material that emits light of a predetermined color.

[0114] In an embodiment, the light emitting layer EL may be formed using the deposition apparatus 1000. In an embodiment, for example, the light emitting layer EL may be formed as the target substrate 10 having the pixel defining layer PDL formed thereon moves or passes through the deposition apparatus 1000. However, the disclosure is not limited thereto, and various thin films included in the display device DD may be formed using the deposition apparatus 1000.

[0115] The common electrode CE may be disposed on the light-emitting layer EL. In embodiments, the common electrode CE may be, for example, a plate-shaped electrode. The common electrode CE may include a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. For example, the common electrode CE may function as a cathode.

[0116] Thus, a light emitting element LE including a pixel electrode PE, a light emitting layer EL, and a common electrode CE may be disposed on the base substrate SUB. The light emitting element LE may be electrically connected to the transistor TR.

[0117] The encapsulation layer TFE may be provided on the common electrode CE. The encapsulation layer TFE may protect the light-emitting element LE from external oxygen, moisture, and the like. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. In an embodiment, for example, the encapsulation layer TFE may have a structure in which inorganic layers and organic layers are alternately stacked.

[0118] The disclosed embodiments may be applied to manufacturing processes of various display devices, such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, medical display devices, and the like.

[0119] The invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0120] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A mask, comprising: a first layer defining a first opening; as well as a second layer disposed on the first layer, wherein the second layer includes a deposition pattern having an inverted conical shape in a cross-sectional view, wherein the deposition pattern defines a second opening overlapping the first opening in plan view, and Wherein, the second layer comprises <100> Crystal orientation of silicon.

2. The mask according to claim 1, wherein An angle formed between a surface of the deposition pattern spaced apart from the first layer and a side surface of the deposition pattern is greater than or equal to 45° and less than or equal to 75°.

3. The mask according to claim 1, wherein A width of each of the second openings is greater than or equal to a thickness of the deposition pattern. The mask according to claim 1 , wherein: The first layer includes silicon.

5. The mask according to claim 1, further comprising: An insulating layer is provided between the first layer and the second layer.

6. A deposition device, comprising: a deposition source, containing deposition materials; a mask disposed on the deposition source, wherein the deposition material passes through the mask; and a stage provided on the mask, wherein a target substrate on which the deposition material is deposited is fixed to the stage, Wherein, the mask comprises: a first layer defining a first opening; and a second layer disposed on the first layer, wherein the second layer includes a deposition pattern having an inverted conical shape in a cross-sectional view, wherein the deposition pattern defines a second opening overlapping the first opening in plan view, and Wherein, the second layer comprises <100> Crystal orientation of silicon.

7. The deposition apparatus according to claim 6, wherein: An angle formed between a surface of the deposition pattern spaced apart from the first layer and a side surface of the deposition pattern is greater than or equal to 45° and less than or equal to 75°.

8. The deposition apparatus according to claim 6, wherein: A width of each of the second openings is greater than or equal to a thickness of the deposition pattern.

9. The deposition apparatus according to claim 6, wherein: The first layer includes silicon.

10. The deposition apparatus according to claim 6, wherein: The mask further includes an insulating layer disposed between the first layer and the second layer.

11. A method for manufacturing a mask, the method comprising the following steps: forming a first layer defining a first opening by etching the preliminary first layer; as well as forming a second layer by etching a preliminary second layer disposed below the preliminary first layer, the second layer including a deposition pattern having an inverted tapered shape in a cross-sectional view, wherein the deposition pattern defines a second opening overlapping the first opening in plan view, and Wherein, the second layer comprises <100> Crystal orientation of silicon.

12. The method according to claim 11, wherein In the step of forming the second layer, The deposition pattern is formed in such a manner that a surface of the deposition pattern spaced apart from the first layer and a side surface of the deposition pattern form an angle of greater than or equal to 45° and less than or equal to 75°.

13. The method according to claim 11, wherein In the step of forming the second layer, A width of each of the second openings is formed to be greater than or equal to a thickness of the deposition pattern.

14. The method according to claim 11, wherein In the step of forming the second layer, The preliminary second layer is etched using an etchant including potassium hydroxide.

15. The method according to claim 14, wherein The concentration of the potassium hydroxide is greater than or equal to 15 wt % and less than or equal to 70 wt %.

16. The method according to claim 14, wherein The temperature of the potassium hydroxide is greater than or equal to 50° C. and less than or equal to 100° C.

17. The method according to claim 11, wherein The steps of forming the first layer include: An auxiliary pattern defining an auxiliary opening is formed by etching the preliminary first layer.

18. The method according to claim 17, wherein The step of forming the auxiliary pattern includes: forming a first sub-opening by etching the preliminary first layer; and A second sub-opening connected to the first sub-opening is formed by etching the preliminary first layer.

19. The method according to claim 17, wherein In the step of forming the second layer, The auxiliary pattern of the preliminary first layer and the preliminary second layer are simultaneously etched.

20. The method according to claim 11, further comprising: An insulating layer is formed by etching a preliminary insulating layer disposed between the preliminary first layer and the preliminary second layer.

Images