High-speed train speed pulse acquisition device

Abstract

The invention discloses a high-speed train speed pulse acquisition device which comprises two speed pulse acquisition modules of a two-out-of-two redundant structure, and each speed pulse acquisition module comprises a speed pulse processing and line detection unit, a speed pulse generation circuit electrically connected to a speed pulse simulation platform, and a speed pulse processing and line detection unit electrically connected to the speed pulse generation circuit. The speed pulse processing and line detection unit receives the three-channel initial speed pulse signals output by the speed pulse generation circuit and then outputs three-channel intermediate speed pulse signals; the FPGA unit is used for calculating and obtaining parameter information of the intermediate speed pulse signals of the three channels according to the intermediate speed pulse signals of the three channels; and the main control unit calculates according to the parameter information to obtain train parameters corresponding to the initial speed pulse signal, the train parameters comprise the real-time speed of the train, and the main control unit outputs the real-time speed to the vehicle-mounted subsystem.

Description

Technical Field

[0001] The present invention belongs to the technical field of rail transportation, and in particular relates to a high-speed train speed pulse acquisition device. Background Art

[0002] With the rapid expansion of high-speed rail networks worldwide in recent years, the safety and efficiency of train operations have become a focus of widespread concern within and beyond the industry. As a crucial component of modern railway transportation systems, speed data collection technology is crucial for ensuring the safe and efficient operation of high-speed trains. The application of speed pulse acquisition technology is particularly important in core control systems such as Automatic Train Protection (ATP), Automatic Train Monitoring (ATS), and Automatic Train Operation (ATO).

[0003] Within the ATP system, real-time tracking of train speed fluctuations ensures that trains always remain within the set safe speed limits, effectively preventing safety issues that may arise from speeding. The ATS system utilizes precise speed information to comprehensively monitor train position and speed, optimizing scheduling and improving the transportation efficiency of the entire railway network. In the ATO system, precise speed control is the foundation for achieving smooth operation of trains from start to stop, directly impacting the passenger experience. Furthermore, meticulous speed management helps significantly reduce energy consumption during train operation, promoting the implementation of environmentally friendly travel concepts.

[0004] Traditionally, speed sensors used in high-speed railways are divided into two types: current-based and voltage-based. This requires the use of different acquisition circuits, increasing the need for hardware replacement and wasting resources. Furthermore, these traditional circuits only process circuit pulses and do not involve pulse calculation or phase determination.

[0005] Therefore, there is an urgent need to develop a high-speed train speed pulse acquisition device that overcomes the above-mentioned defects. Summary of the Invention

[0006] In response to the above problems, the present invention provides a high-speed train speed pulse acquisition device, which includes: two speed pulse acquisition modules with a 2-out-of-2 redundant structure, each of the speed pulse acquisition modules including:

[0007] A speed pulse processing and circuit detection unit is electrically connected to the speed pulse generation circuit of the speed pulse simulation platform, and the speed pulse processing and circuit detection unit receives the initial speed pulse signals of the three channels output by the speed pulse generation circuit and outputs intermediate speed pulse signals of the three channels;

[0008] An FPGA unit calculates and obtains parameter information of the intermediate speed pulse signals of the three channels according to the intermediate speed pulse signals of the three channels;

[0009] The main control unit calculates and obtains train parameters corresponding to the initial speed pulse signal based on the parameter information, wherein the train parameters include the instantaneous speed of the train, and the main control unit outputs the instantaneous speed to the on-board subsystem.

[0010] The above-mentioned high-speed train speed pulse acquisition device, wherein the speed pulse processing and line detection unit also outputs three-channel line detection signals according to the three-channel initial speed pulse signals, and the FPGA unit performs line detection based on the line detection signals.

[0011] The above-mentioned high-speed train speed pulse acquisition device, wherein the speed pulse processing and line detection unit includes:

[0012] The three-channel speed pulse processing circuit outputs the three-channel intermediate speed pulse signals according to the three-channel initial speed pulse signals.

[0013] The three-channel speed pulse disconnection detection circuit outputs three-channel line detection signals according to the initial speed pulse signals of the three channels.

[0014] In the above-mentioned high-speed train speed pulse acquisition device, each of the speed pulse processing circuits includes:

[0015] a first pulse receiving end and a first speed pulse loop end, wherein the first pulse receiving end and the first speed pulse loop end are electrically connected to the speed pulse generating circuit, receive the three-channel initial speed pulse signals output by the speed pulse generating circuit via the first pulse receiving end, and output a return signal via the first speed pulse loop end;

[0016] a hysteresis comparator, wherein the first pulse receiving terminal is electrically connected to a first input terminal of the hysteresis comparator through a filter resistor, a first voltage reference is electrically connected to a second input terminal of the hysteresis comparator, and the hysteresis comparator is also electrically connected to the speed pulse loop terminal;

[0017] a first optocoupler electrically connected to the output terminal of the hysteresis comparator;

[0018] a first power supply electrically connected to the first optical coupler via a first current limiting resistor;

[0019] A first RC filter plus inverter has one end electrically connected to the first optical coupler and the FPGA unit, and the other end grounded.

[0020] The above-mentioned high-speed train speed pulse acquisition device, wherein the speed pulse processing circuit further includes:

[0021] a first overvoltage protection device, one end of which is electrically connected to the first pulse receiving end, and the other end of which is electrically connected to the first speed pulse loop end;

[0022] a first voltage conversion resistor, one end of which is electrically connected to the connection path between the first overvoltage protection device and the filter resistor, and the other end of which is electrically connected to the first speed pulse loop end;

[0023] a first filter capacitor, one end of which is electrically connected to the connection path between the first voltage conversion resistor and the filter resistor, and the other end of which is electrically connected to the first speed pulse loop end;

[0024] A second filter capacitor has one end electrically connected to the connection path between the first input end and the filter resistor, and the other end electrically connected to the first speed pulse loop end.

[0025] The above-mentioned high-speed train speed pulse acquisition device, wherein the hysteresis comparator further includes:

[0026] a first circuit voltage-dividing resistor, one end of which is electrically connected to the first input end;

[0027] a first comparator, wherein the other end of the first loop voltage-dividing resistor is electrically connected to the first comparator, the reference voltage is electrically connected to the first comparator, and the first comparator is electrically connected to the first optocoupler;

[0028] a second loop voltage-dividing resistor, one end of which is electrically connected to a connection path between the other end of the first loop voltage-dividing resistor and the comparator;

[0029] a third circuit voltage-dividing resistor, one end of which is electrically connected to the other end of the second circuit voltage-dividing resistor;

[0030] One end of the fourth loop voltage-dividing resistor is electrically connected to the other end of the third loop voltage-dividing resistor, and the other end is also electrically connected to the first speed pulse loop end. The third loop voltage-dividing resistor is also electrically connected to the connection path between the comparator and the first optocoupler.

[0031] In the above-mentioned high-speed train speed pulse acquisition device, the speed pulse disconnection detection circuit of each line includes:

[0032] a second pulse receiving end and a second speed pulse loop end, wherein the second pulse receiving end and the second speed pulse loop end are electrically connected to the speed pulse generating circuit, receive the initial speed pulse signals of the three channels output by the speed pulse generating circuit via the second pulse receiving end, and output a return signal via the second speed pulse loop end;

[0033] a second comparator, wherein the second pulse receiving end is electrically connected to the second comparator via a second current limiting resistor;

[0034] a third comparator, the second pulse receiving end being electrically connected to the third comparator via the second current-limiting resistor;

[0035] a second optical coupler electrically connected to the second comparator and the third comparator;

[0036] a second power supply electrically connected to the second optical coupler via a third current limiting resistor;

[0037] A second RC filter plus inverter has one end electrically connected to the second optical coupler and the FPGA unit, and the other end grounded.

[0038] In the above-mentioned high-speed train speed pulse acquisition device, the speed pulse disconnection detection circuit of each path further comprises:

[0039] A first voltage-dividing resistor, one end of which is electrically connected to a second voltage reference;

[0040] a second voltage-dividing resistor, one end of which is electrically connected to the other end of the first voltage-dividing resistor, and the second comparator is also electrically connected to a connection path between the first voltage-dividing resistor and the second voltage-dividing resistor;

[0041] A third voltage-dividing resistor has one end electrically connected to the other end of the second voltage-dividing resistor, and the other end electrically connected to the second speed pulse loop end. The third comparator is also electrically connected to the connection path between the third voltage-dividing resistor and the second voltage-dividing resistor.

[0042] In the above-mentioned high-speed train speed pulse acquisition device, the speed pulse disconnection detection circuit of each path further comprises:

[0043] a second overvoltage protection device, one end of which is electrically connected to the second pulse receiving end, and the other end of which is electrically connected to the second speed pulse loop end;

[0044] A voltage conversion resistor has one end electrically connected to the connection path between the second overvoltage protection device and the second current limiting resistor, and the other end electrically connected to the first speed pulse loop end.

[0045] The above-mentioned high-speed train speed pulse acquisition device, wherein the parameter information includes pulse signal frequency, phase relationship and cumulative number of pulses, and the train parameters also include train direction and train distance. The main control unit calculates the instantaneous speed based on the pulse signal frequency, the main control unit calculates the train direction based on the phase relationship, and the main control unit calculates the train distance based on the cumulative number of pulses.

[0046] In summary, the present invention has the following advantages over the prior art:

[0047] The high-speed train speed pulse acquisition device of the present invention is compatible with universal acquisition circuits of various sensor types, reducing the frequency of hardware replacement and resource consumption, and can accurately calculate the frequency, phase relationship and pulse accumulation number of three-channel speed pulses. At the same time, it not only ensures the safe operation of high-speed trains, but also improves the quality of railway services and promotes intelligent railway management.

[0048] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 This is a schematic structural diagram of a high-speed train speed pulse acquisition device according to the present invention;

[0051] Figure 2 It is a structural diagram of the speed pulse processing circuit;

[0052] Figure 3 This is a schematic diagram of the structure of the speed pulse disconnection detection circuit;

[0053] Figure 4 This is the schematic diagram of FPGA speed sampling. DETAILED DESCRIPTION

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0055] The exemplary embodiments of the present invention and their description are used to explain the present invention, but are not intended to limit the present invention. In addition, elements / components with the same or similar reference numerals used in the drawings and embodiments are used to represent the same or similar parts.

[0056] The terms “first,” “second,” “S1,” “S2,” etc. used herein do not specifically refer to an order or sequence, nor are they intended to limit the present invention. They are merely used to distinguish elements or operations described with the same technical terms.

[0057] The directional terms used herein, such as up, down, left, right, front, or back, are only used to refer to the directions in the accompanying drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0058] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0059] As used herein, "and / or" includes any and all combinations of the items mentioned.

[0060] Regarding "plurality" in this document, "plurality" includes "two" and "more than two"; regarding "plurality groups" in this document, "plurality groups" includes "two groups" and "more than two groups".

[0061] As used herein, the terms "substantially" and "approximately" are used to modify any quantity or error that may vary slightly, but such variation or error does not alter the essence of the quantity. Generally speaking, the range of such variation or error modified by such terms may be 20% in some embodiments, 10% in some embodiments, 5% in some embodiments, or other values. Those skilled in the art will appreciate that the aforementioned values ​​may be adjusted based on actual needs and are not intended to be limiting.

[0062] Certain terms used to describe the present application are discussed below, or elsewhere in this specification, to provide additional guidance to those skilled in the art regarding the description of the present application.

[0063] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the high-speed train speed pulse acquisition device of the present invention. Figure 1As shown, the high-speed train speed pulse acquisition device of the present invention includes: two speed pulse acquisition modules with a 2-out-of-2 redundant structure, each of which includes: a speed pulse processing and line detection unit 11, an FPGA unit 12, and a main control unit 13. The speed pulse processing and line detection unit 11 is electrically connected to the speed pulse generation circuit of the speed pulse simulation platform. The speed pulse processing and line detection unit 11 receives the three-channel initial speed pulse signals output by the speed pulse generation circuit and outputs the three-channel intermediate speed pulse signals. The FPGA unit 12 calculates parameter information of the three-channel intermediate speed pulse signals based on the three-channel intermediate speed pulse signals. The main control unit 13 calculates train parameters corresponding to the initial speed pulse signals based on the parameter information. The train parameters include the train's instantaneous speed. The main control unit 13 outputs the instantaneous speed to the onboard subsystem. The speed pulse processing and line detection unit 11 also outputs three-channel line detection signals based on the three-channel initial speed pulse signals. The FPGA unit 12 performs line detection based on the line detection signals.

[0064] Furthermore, the speed pulse processing and line detection unit 11 includes: a three-channel speed pulse processing circuit 111 and a three-channel speed pulse disconnection detection circuit 112. The three-channel speed pulse processing circuit 111 outputs the three-channel intermediate speed pulse signals based on the three-channel initial speed pulse signals, and the three-channel speed pulse disconnection detection circuit 112 outputs the three-channel line detection signals based on the three-channel initial speed pulse signals.

[0065] The speed acquisition device on a high-speed train is a critical hardware component for accurately recording the train's running speed. Given the challenges of testing directly with actual vehicle speed sensors, a speed pulse simulation module was designed to simulate current and voltage speed pulses to aid system testing and verification.

[0066] In high-speed train applications, the SRIK78 current-type speed sensor is commonly used, while the EDUTA-DF16 is often used for voltage-type speed sensors. Regardless of the sensor type, the simulation module generates three speed pulse signals with a phase shift of 120 degrees. These pulse signals enter the acquisition module and are split into two paths to meet the high reliability requirements of high-speed trains. A 2-out-of-2 redundant architecture ensures that each CPU receives a complete set of three speed pulse signals with a phase shift of 120 degrees. Each channel's speed pulse signal is further split into two paths after passing through the processing circuit and line detection circuit: one for signal processing and the other for line detection. The processed speed pulse signals are then fed into the FPGA unit. The algorithm within the FPGA unit calculates the frequency and phase of the three-channel speed pulses and checks for line faults and other information. After completing these calculations, the FPGA unit packages the processed results and transmits them to the main control unit via a parallel bus interface. The main control unit further calculates the train's real-time speed based on data received from the FPGA unit and transmits this information to the onboard ATP and ATO via Ethernet, enabling effective monitoring and precise control of vehicle speed. The entire process not only demonstrates the technical complexity and advancement of modern high-speed train control systems, but also emphasizes the importance of speed acquisition platforms in ensuring safe and efficient train operation.

[0067] Please refer to Figure 2 , Figure 2 Figure 2 is a schematic diagram of the speed pulse processing circuit. Figure 2 As shown, each speed pulse processing circuit 111 includes:

[0068] a first pulse receiving terminal D1 and a first speed pulse loop terminal P1, wherein the first pulse receiving terminal D1 and the first speed pulse loop terminal P1 are electrically connected to the speed pulse generating circuit, receive the three-channel initial speed pulse signals output by the speed pulse generating circuit via the first pulse receiving terminal D1, and output a return signal via the first speed pulse loop terminal P1;

[0069] A hysteresis comparator 1111, wherein the first pulse receiving terminal D1 is electrically connected to a first input terminal of the hysteresis comparator 1111 through a filter resistor R1, a first voltage reference is electrically connected to a second input terminal of the hysteresis comparator 1111, and the hysteresis comparator 1111 is also electrically connected to the speed pulse loop terminal P1;

[0070] A first optical coupler OC1 is electrically connected to the output terminal of the hysteresis comparator 1111;

[0071] A first power source S1 is electrically connected to the first optical coupler OC1 through a first current limiting resistor R2;

[0072] The first RC filter plus inverter 1112 has one end electrically connected to the first optical coupler OC1 and the FPGA unit 12 , and the other end grounded.

[0073] Furthermore, the speed pulse processing circuit 111 further includes:

[0074] A first overvoltage protection device 1113 , one end of which is electrically connected to the first pulse receiving terminal D1 , and the other end of which is electrically connected to the first speed pulse loop terminal P1 ;

[0075] a first voltage conversion resistor R3, one end of which is electrically connected to the connection path between the first overvoltage protection device 1113 and the filter resistor R1, and the other end of which is electrically connected to the first speed pulse circuit terminal P1;

[0076] a first filter capacitor C1, one end of which is electrically connected to the connection path between the first voltage conversion resistor R3 and the filter resistor R1, and the other end of which is electrically connected to the first speed pulse loop terminal P1;

[0077] The second filter capacitor C2 has one end electrically connected to the connection path between the first input end and the filter resistor R1 , and the other end electrically connected to the first speed pulse loop end P1 .

[0078] Furthermore, the hysteresis comparator 1111 further includes:

[0079] A first circuit voltage-dividing resistor R4, one end of which is electrically connected to the first input end;

[0080] a first comparator CMP1 , the other end of the first loop voltage-dividing resistor R4 being electrically connected to the first comparator CMP1 , the reference voltage being electrically connected to the first comparator CMP1 , and the first comparator CMP1 being electrically connected to the first optocoupler OC1 ;

[0081] a second loop voltage-dividing resistor R5, one end of which is electrically connected to the connection path between the other end of the first loop voltage-dividing resistor R4 and the comparator CMP1;

[0082] a third circuit voltage-dividing resistor R6, one end of which is electrically connected to the other end of the second circuit voltage-dividing resistor R5;

[0083] One end of the fourth loop voltage-dividing resistor R7 is electrically connected to the other end of the third loop voltage-dividing resistor R6, and the other end of the fourth loop voltage-dividing resistor R7 is also electrically connected to the first speed pulse loop end P1. The third loop voltage-dividing resistor R6 is also electrically connected to the connection path between the comparator CMP1 and the first optocoupler OC1.

[0084] The speed pulse processing circuit is regulated by a feedback network formed by four loop voltage-dividing resistors. These four loop voltage-dividing resistors and the comparator form a special form of hysteresis comparator. This design not only enhances the circuit's resistance to noise, but also improves the stability and accuracy of signal conversion, and ultimately achieves the reliable conversion of voltage-type and current-type speed pulse signals into pulse signals that can be recognized by FPGA. Specifically, the design of this device for voltage-type speed pulse signals uses 15V as the high level and 0V as the low level standard. In order to ensure effective signal recognition and processing, we set a voltage reference value of 1.2V. This value is chosen to be compatible with the current-type speed pulse signal acquisition circuit in order to establish a general signal processing framework, such as Figure 2 As shown in the figure, the comparator outputs a high signal when the input voltage exceeds 1.2V; when the input voltage is below 1.2V, it outputs a low signal. To enhance system stability and reliability, the design incorporates a large-capacity voltage conversion resistor, ensuring it can withstand voltages up to 15V without compromising performance. While the voltage conversion resistor does not directly affect the output voltage in the high-level state, its presence ensures safe system operation under extreme conditions.

[0085] To reduce the impact of noise on the signal and improve comparator accuracy, a π-type filter circuit pre-processes the input voltage. The filtered voltage is passed to the comparator through a series of loop voltage-divider resistors, where the output state is determined based on a set threshold. Current-limiting resistors are added to the power supply path to limit the current, and are connected to the third loop voltage-divider resistor through the optocoupler pre-stage circuit. At this point, the current splits into two branches: one directly to the speed pulse circuit, and the other returns to the speed pulse circuit through a path consisting of the second loop voltage-divider resistor, the first loop voltage-divider resistor, the filter resistor, and the voltage conversion resistor. This causes the comparator's positive electrode voltage to exceed the reference voltage. By precisely selecting the loop voltage-divider resistor values ​​to limit the current, the optocoupler is kept in the off state, preventing subsequent circuits from turning on, thereby ensuring that the voltage collected by the back-end remains at the expected high level.

[0086] When the input is low, the comparator also outputs a low signal. At this point, the power supply forms a closed loop with the optocoupler through the current-limiting resistor, turning the optocoupler on. Simultaneously, the current splits into two paths: one to ground through the fourth-loop voltage-divider resistor, and the other to the output of comparator CMP1 through the second-loop voltage-divider resistor. Because the optocoupler is on, the voltage collected by the backend appears low, contrary to the default setting. This design utilizes the state changes of optocoupler OC1 to accurately reflect the high-low level transitions of the input signal, ensuring effective signal transmission and recognition.

[0087] For current-type speed pulse signals, 7mA represents a low level and 14mA represents a high level. Since the current signal cannot be used directly for comparison, it needs to be converted into a voltage signal through a 100-ohm voltage conversion resistor. In this way, the low level of 7mA is converted to 0.7V, and the high level of 14mA is converted to 1.4V. Therefore, for voltage-type speed pulse signals, the high level is 15V and the low level is 0V; while for current-type speed pulse signals, the high level is 1.4V and the low level is 0.7V. Based on this, the reference voltage of the comparator is set to 1.2V to distinguish the two types of pulse signals and achieve compatibility between voltage-type and current-type pulse signal circuits.

[0088] To improve signal processing accuracy and reliability, in actual applications, the input voltage to the positive terminal of comparator CMP1 is not directly 1.4V or 15V, but is instead adjusted through a feedback network formed by four loop voltage-divider resistors. These four loop voltage-divider resistors and the comparator together form a hysteresis comparator 1111 with hysteresis characteristics. This not only improves the circuit's noise immunity but also enhances the stability and accuracy of signal conversion, achieving reliable conversion of voltage- and current-type speed pulse signals into pulse signals recognizable by the FPGA.

[0089] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the speed pulse disconnection detection circuit. Figure 3 As shown, the speed pulse disconnection detection circuit 112 of each path includes:

[0090] a second pulse receiving terminal D2 and a second speed pulse loop terminal P2, wherein the second pulse receiving terminal D2 and the second speed pulse loop terminal P2 are electrically connected to the speed pulse generating circuit, receive the initial speed pulse signals of the three channels output by the speed pulse generating circuit via the second pulse receiving terminal D2, and output a return signal via the second speed pulse loop terminal P2;

[0091] a second comparator CMP2, wherein the second pulse receiving terminal D2 is electrically connected to the second comparator CMP2 via a second current limiting resistor R8;

[0092] a third comparator CMP3, wherein the second pulse receiving end D2 is electrically connected to the third comparator CMP3 via the second current limiting resistor R8;

[0093] a second optical coupler OC2 electrically connected to the second comparator CMP2 and the third comparator CMP3;

[0094] A second power source S2 is electrically connected to the second optical coupler OC2 via a third current limiting resistor R9;

[0095] The second RC filter plus inverter 1121 has one end electrically connected to the second optical coupler OC2 and the FPGA unit 12 , and the other end grounded.

[0096] Furthermore, the speed pulse disconnection detection circuit 112 of each path further includes:

[0097] A first voltage-dividing resistor R10, one end of which is electrically connected to a second voltage reference;

[0098] a second voltage-dividing resistor R11 having one end electrically connected to the other end of the first voltage-dividing resistor R10, and a second comparator CMP2 electrically connected to a connection path between the first voltage-dividing resistor R10 and the second voltage-dividing resistor R11;

[0099] The third voltage-dividing resistor R12 has one end electrically connected to the other end of the second voltage-dividing resistor R11, and the other end electrically connected to the second speed pulse loop end P2. The third comparator CMP3 is also electrically connected to the connection path between the third voltage-dividing resistor R12 and the second voltage-dividing resistor R11.

[0100] Furthermore, the speed pulse disconnection detection circuit 112 of each path further includes:

[0101] A second overvoltage protection device 1122 , one end of which is electrically connected to the second pulse receiving terminal D2 , and the other end of which is electrically connected to the second speed pulse loop terminal P2 ;

[0102] The voltage conversion resistor R13 has one end electrically connected to the connection path between the second overvoltage protection device 1122 and the second current limiting resistor R8, and the other end electrically connected to the first speed pulse loop terminal P2.

[0103] The speed pulse disconnection detection circuit uses a voltage reference for voltage division. By connecting two comparators in parallel and leveraging the characteristics of the comparator's OC output, it forms a circuit capable of detecting both speed pulse line faults and speed pulse short-circuit faults. This design provides a reference solution for the reliable detection of current-type speed pulse signals. Specifically, when a current-type speed pulse signal enters the speed pulse disconnection detection circuit, it is first converted to a corresponding voltage value through a 100-ohm voltage conversion resistor: 7mA corresponds to 0.7V, and 14mA corresponds to 1.4V. To implement line detection, a 2.5V voltage reference is introduced and divided by three voltage-dividing resistors. By carefully selecting the resistance values ​​of the voltage-dividing resistors, the voltage between the first and second voltage-dividing resistors reaches 2.2V and is connected to the positive terminal of comparator CMP2. The voltage between the second and third voltage-dividing resistors reaches 0.4V and is connected to the negative terminal of comparator CMP3, thus achieving line detection.

[0104] Under normal operating conditions, when the current pulse input is a low-level 7mA, the voltage after passing through the voltage conversion resistor becomes 0.7V. At this time, the negative terminal of comparator CMP2 receives a 0.7V signal, which is compared with the 2.2V of the positive terminal, causing the output of comparator CMP2 to be in a high-impedance state. At the same time, the positive terminal of comparator CMP3 also receives a 0.7V signal, which is higher than the 0.4V of its negative terminal, causing comparator CMP3 to also output a high-impedance state. Therefore, in this case, optocoupler OC2 is not conducting, and the FPGA unit receives the high-level signal in the default state.

[0105] When the current pulse input is high at 14mA, the voltage generated after passing through the voltage conversion resistor rises to 1.4V. The negative terminal of comparator CMP2 remains lower than the positive terminal's 2.2V, maintaining a high-impedance output. Meanwhile, the positive terminal voltage of comparator CMP3, at 1.4V, is higher than the negative terminal's 0.4V, but the output remains high-impedance. Therefore, even in this state, optocoupler OC2 is not conducting, and the FPGA unit still detects a high-level signal.

[0106] If the speed pulse signal is interrupted, indicating a line fault, the voltage across the voltage conversion resistor will drop below 0.7V. For comparator CMP2, due to the lack of a valid voltage input, its negative terminal voltage falls far below 2.2V, and its output remains in a high-impedance state. Meanwhile, for comparator CMP3, the positive terminal voltage drops below 0.4V, causing its output to remain low. When the outputs of the two comparators are connected in parallel, the final result is a low level, triggering the optocoupler to turn on. The FPGA detects the low level and thus identifies a line fault.

[0107] In the event of a short circuit, such as when the speed pulse signal is directly shorted to the power supply due to improper operation, the voltage across the voltage conversion resistor will exceed 2.2V. At this point, the negative voltage of comparator CMP2 exceeds 2.2V, and the output is low. However, the positive voltage of comparator CMP3 remains above 0.4V, and the output is in a high-impedance state. After the outputs of the two comparators are connected in parallel, the final output remains low, which also causes optocoupler OC2 to turn on. The FPGA unit detects the low level and determines it as a line fault. In this way, the system can effectively monitor and distinguish between normal operating conditions, line faults, and short circuits, ensuring the safety and reliability of high-speed train operation.

[0108] Please refer to Figure 4 , Figure 4 This is the schematic diagram of FPGA speed sampling. Figure 4As shown, the parameter information includes the pulse signal frequency, phase relationship and cumulative number of pulses, and the train parameters also include the train direction and train travel distance. The main control unit calculates the instantaneous speed based on the pulse signal frequency, the main control unit calculates the train direction based on the phase relationship, and the main control unit calculates the train travel distance based on the cumulative number of pulses.

[0109] Specifically, the FPGA plays a crucial role in the speed pulse acquisition circuit of high-speed trains. It is responsible for accurately calculating the frequency, phase relationship, and accumulated pulse count of the pulse signals from three channels, and transmitting this data to the central processing unit in real time. Frequency calculation can determine the train's instantaneous speed; phase analysis is used to determine the train's direction of travel; and pulse accumulation statistics help estimate the train's distance traveled.

[0110] like Figure 4 As shown, frequency measurement utilizes an external 25MHz crystal oscillator clock source by edge-detecting the pulse signals output by each speed sensor channel. Whenever a channel experiences a rising edge, the FPGA starts counting the 25MHz clock. When the channel falls again, counting stops and the number of clock pulses captured during the high-level period is recorded as a. Then, before the next rising edge of the same channel, the FPGA continues counting to obtain the total number of clock pulses during the low-level period, recorded as b. By calculating a + b, we obtain the total number of clock pulses in a complete pulse cycle. This value and the clock source frequency are then used to calculate the corresponding frequency. If the frequency difference between the three channels is within 0.02%, the system performs phase analysis; otherwise, an error report is issued.

[0111] Phase analysis is based on the inherent phase differences between the three speed sensor channels: During forward travel, Speed ​​Channel 2 lags Speed ​​Channel 1 by 120 degrees, and Speed ​​Channel 3 also lags Speed ​​Channel 2 by 120 degrees. The opposite is true during reverse travel. Upon detecting a rising edge on Speed ​​Channel 1, the system checks the instantaneous status of the other two channels. If Speed ​​Channel 2 is low and Speed ​​Channel 3 is high, the train is traveling in the forward direction. Conversely, if Speed ​​Channel 2 is high and Speed ​​Channel 3 is low, the train is reversing. Any deviation from these conditions is considered an anomaly, triggering the FPGA to send an error report to the central processing unit.

[0112] The FPGA also maintains a pulse accumulation counter to track the total number of valid pulses. Each time a phase relationship for forward motion is confirmed, the counter increments; when reverse motion is detected, the counter decrements. Based on the final value of the accumulation counter, specific calculations can be used to accurately determine the cumulative distance traveled by the train, enabling continuous tracking and monitoring of the train's position. This mechanism ensures the safety and efficiency of train operations and provides valuable data for optimizing train operations and services.

[0113] The advanced algorithm integrated in the FPGA can achieve accurate measurement of the speed pulse frequency and calculate the phase relationship and the number of pulse accumulation, thereby accurately obtaining the actual operating speed of the train.

[0114] In summary, the beneficial effects of the present invention are as follows:

[0115] 1. Enhanced compatibility and flexibility:

[0116] The circuit can simultaneously process two different types of high-speed train speed sensor signals, current type and voltage type, avoiding the need to frequently replace hardware due to different sensor types, reducing resource waste and improving system flexibility.

[0117] 2. Improved data accuracy and reliability:

[0118] By introducing a filter to pre-process the input voltage, using high-capacity voltage conversion resistors to ensure safe operation under extreme conditions, and designing a loop voltage-divider resistor network to optimize the state of the optocoupler, the system can still maintain accurate signal transmission and processing in complex environments, effectively reducing the false alarm rate.

[0119] 3. Real-time monitoring and fault detection:

[0120] The introduction of a line detection mechanism, which monitors and reports line faults in real time during the speed pulse acquisition process, enhances system stability and reliability. This real-time monitoring capability is crucial for ensuring the safe operation of high-speed railways.

[0121] 4. Efficient speed calculation and direction identification:

[0122] Advanced algorithms within the FPGA precisely calculate the frequency, phase relationship, and pulse accumulation of the three-channel velocity pulses, reporting these to the central processing unit in real time. This not only enables precise control of train speed but also enables accurate determination of train direction, providing reliable data support for onboard systems.

[0123] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed train speed pulse acquisition device, characterized in that: include: Two speed pulse acquisition modules with a 2-out-of-2 redundant structure, each of the speed pulse acquisition modules includes: A speed pulse processing and circuit detection unit is electrically connected to the speed pulse generation circuit of the speed pulse simulation platform, and the speed pulse processing and circuit detection unit receives the initial speed pulse signals of the three channels output by the speed pulse generation circuit and outputs intermediate speed pulse signals of the three channels; An FPGA unit calculates and obtains parameter information of the intermediate speed pulse signals of the three channels according to the intermediate speed pulse signals of the three channels; The main control unit calculates and obtains train parameters corresponding to the initial speed pulse signal based on the parameter information, wherein the train parameters include the instantaneous speed of the train, and the main control unit outputs the instantaneous speed to the on-board subsystem.

2. The high-speed train speed pulse acquisition device according to claim 1, characterized in that: The speed pulse processing and line detection unit also outputs three-channel line detection signals according to the initial speed pulse signals of the three channels, and the FPGA unit performs line detection based on the line detection signals.

3. The high-speed train speed pulse acquisition device according to claim 2, characterized in that: The speed pulse processing and line detection unit includes: The three-channel speed pulse processing circuit outputs the three-channel intermediate speed pulse signals according to the three-channel initial speed pulse signals. The three-channel speed pulse disconnection detection circuit outputs three-channel line detection signals according to the initial speed pulse signals of the three channels.

4. The high-speed train speed pulse acquisition device according to claim 3, characterized in that: Each speed pulse processing circuit includes: a first pulse receiving end and a first speed pulse loop end, wherein the first pulse receiving end and the first speed pulse loop end are electrically connected to the speed pulse generating circuit, receive the three-channel initial speed pulse signals output by the speed pulse generating circuit via the first pulse receiving end, and output a return signal via the first speed pulse loop end; a hysteresis comparator, wherein the first pulse receiving terminal is electrically connected to a first input terminal of the hysteresis comparator through a filter resistor, a first voltage reference is electrically connected to a second input terminal of the hysteresis comparator, and the hysteresis comparator is also electrically connected to the speed pulse loop terminal; a first optocoupler electrically connected to the output terminal of the hysteresis comparator; a first power supply electrically connected to the first optical coupler via a first current limiting resistor; A first RC filter plus inverter has one end electrically connected to the first optical coupler and the FPGA unit, and the other end grounded.

5. The high-speed train speed pulse acquisition device according to claim 4, characterized in that: The speed pulse processing circuit also includes: a first overvoltage protection device, one end of which is electrically connected to the first pulse receiving end, and the other end of which is electrically connected to the first speed pulse loop end; a first voltage conversion resistor, one end of which is electrically connected to the connection path between the first overvoltage protection device and the filter resistor, and the other end of which is electrically connected to the first speed pulse loop end; a first filter capacitor, one end of which is electrically connected to the connection path between the first voltage conversion resistor and the filter resistor, and the other end of which is electrically connected to the first speed pulse loop end; A second filter capacitor has one end electrically connected to the connection path between the first input end and the filter resistor, and the other end electrically connected to the first speed pulse loop end.

6. The high-speed train speed pulse acquisition device according to claim 4, characterized in that: The hysteresis comparator further includes: a first circuit voltage-dividing resistor, one end of which is electrically connected to the first input end; a first comparator, wherein the other end of the first loop voltage-dividing resistor is electrically connected to the first comparator, the reference voltage is electrically connected to the first comparator, and the first comparator is electrically connected to the first optocoupler; a second loop voltage-dividing resistor, one end of which is electrically connected to a connection path between the other end of the first loop voltage-dividing resistor and the comparator; a third circuit voltage-dividing resistor, one end of which is electrically connected to the other end of the second circuit voltage-dividing resistor; One end of the fourth loop voltage-dividing resistor is electrically connected to the other end of the third loop voltage-dividing resistor, and the other end is also electrically connected to the first speed pulse loop end. The third loop voltage-dividing resistor is also electrically connected to the connection path between the comparator and the first optocoupler.

7. The high-speed train speed pulse acquisition device according to claim 3, characterized in that: The speed pulse disconnection detection circuit of each path includes: a second pulse receiving end and a second speed pulse loop end, wherein the second pulse receiving end and the second speed pulse loop end are electrically connected to the speed pulse generating circuit, receive the initial speed pulse signals of the three channels output by the speed pulse generating circuit via the second pulse receiving end, and output a return signal via the second speed pulse loop end; a second comparator, wherein the second pulse receiving end is electrically connected to the second comparator via a second current limiting resistor; a third comparator, the second pulse receiving end being electrically connected to the third comparator via the second current-limiting resistor; a second optical coupler electrically connected to the second comparator and the third comparator; a second power supply electrically connected to the second optical coupler via a third current limiting resistor; A second RC filter plus inverter has one end electrically connected to the second optical coupler and the FPGA unit, and the other end grounded.

8. The high-speed train speed pulse acquisition device according to claim 7, characterized in that: The speed pulse disconnection detection circuit of each path further includes: A first voltage-dividing resistor, one end of which is electrically connected to a second voltage reference; a second voltage-dividing resistor, one end of which is electrically connected to the other end of the first voltage-dividing resistor, and the second comparator is also electrically connected to a connection path between the first voltage-dividing resistor and the second voltage-dividing resistor; A third voltage-dividing resistor has one end electrically connected to the other end of the second voltage-dividing resistor, and the other end electrically connected to the second speed pulse loop end. The third comparator is also electrically connected to the connection path between the third voltage-dividing resistor and the second voltage-dividing resistor.

9. The high-speed train speed pulse acquisition device according to claim 8, characterized in that: The speed pulse disconnection detection circuit of each path further includes: a second overvoltage protection device, one end of which is electrically connected to the second pulse receiving end, and the other end of which is electrically connected to the second speed pulse loop end; A voltage conversion resistor has one end electrically connected to the connection path between the second overvoltage protection device and the second current limiting resistor, and the other end electrically connected to the first speed pulse loop end.

10. The high-speed train speed pulse acquisition device according to claim 1, characterized in that: The parameter information includes the pulse signal frequency, phase relationship and cumulative number of pulses. The train parameters also include the train direction and train distance. The main control unit calculates the instantaneous speed based on the pulse signal frequency, the main control unit calculates the train direction based on the phase relationship, and the main control unit calculates the train distance based on the cumulative number of pulses.

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