Liquid-helium-free conduction-cooled quantum resistance device bench

Abstract

The application relates to a liquid-helium-free conduction cooling quantum resistor device carrier, which comprises a cooling column, the outer edge of the bottom of which is provided with a heat conduction thread for binding a cooling belt; a chip carrier, the bottom center of which is fixedly connected with the top of the cooling column; a circuit board group, which comprises an interface circuit board, a first carrier plate, a second carrier plate, a third carrier plate and a fourth carrier plate which are stacked from top to bottom, and the plates are electrically interconnected through gold-plated pins; the first carrier plate is fixed below the interface circuit board in an isolated mode, the second carrier plate and the third carrier plate are fixedly installed on the upper side of the chip carrier, and the fourth carrier plate is fixedly connected below the third carrier plate; a resistor chip is fixed on the upper surface of the chip carrier and is electrically connected with a gold-plated patch on the surface of the second carrier plate through a bonding lead; the gold-plated patch and the gold-plated pin form a passage. The operation complexity is remarkably reduced, the quantum resistor can be long-term stably operated in a liquid-helium-free environment, and the traceability accuracy of the resistance value transmission is ensured.

Description

Technical Field

[0001] This application relates to the field of quantum measurement technology, and in particular to a liquid helium-free conduction-cooled quantum resistance device stage. Background Technology

[0002] As a core component of the quantum resistance standard, the quantum Hall resistor chip plays an irreplaceable role in precision metrology, semiconductor testing, and quantum information. It requires operation in extremely low temperatures (typically below 4K), vacuum, and strong magnetic fields to ensure the stability of the quantum Hall effect. Traditional technologies rely on liquid helium refrigeration systems to maintain this cryogenic environment; however, liquid helium is expensive, complex to store and transport, and carries the risk of vaporization and leakage, limiting the widespread application of the quantum resistance standard. In recent years, liquid helium-free refrigeration technologies (such as pulse tube refrigerators and GM refrigerators) have gradually replaced liquid helium systems, but technical bottlenecks still exist in areas such as chip thermal management, interface connections, and mechanical fixation, specifically as follows: In existing helium-free devices, quantum Hall resistor chips are typically coupled to the cryoprobe of a refrigerator via thermally conductive adhesive or a metal platen. However, uneven power distribution on the chip (e.g., differences in electrode contact resistance, localized Joule heating) and design flaws in the heat conduction path (e.g., high interfacial contact thermal resistance, anisotropy of the thermally conductive material) lead to significant temperature gradients on the chip surface. This uneven heat distribution can cause temperature fluctuations that disrupt the integer quantum states of the quantum Hall resistor, resulting in resistance values ​​deviating from theoretical values.

[0003] Quantum resistor chips need to be connected to external circuits via high-temperature superconducting leads to reduce the interference of lead resistance on measurements. In existing technologies, the interface connection between the superconducting leads and the chip electrodes has poor compatibility, easily damaging the bonding leads of the resistor chip. Furthermore, the multi-layer interface (cold head-cold conductive pillar-stage-chip) introduces additional thermal resistance, leading to decreased cooling efficiency and difficulty in disassembling Hall resistor chips. They are also sensitive to electromagnetic interference, and improper lead layout (such as parallel long wires) introduces parasitic inductance. The chip stage and its fixing structure (such as near-point screws) are magnetic, causing eddy current losses and hysteresis losses in magnetic field environments. Summary of the Invention

[0004] To address the shortcomings of the existing technologies, a liquid helium-free conductive cooling quantum resistor device stage is provided to achieve highly stable conductive cooling, mechanical fixation, and superconducting lead connection of the resistor chip.

[0005] This invention provides a liquid helium-free conduction-cooled quantum resistance device stage, comprising: The cooling column has thermally conductive threads on its bottom outer edge for binding the cooling strip; The chip stage is fixedly connected at its bottom center to the top of the cooling column; The circuit board assembly includes an interface circuit board, a first carrier board, a second carrier board, a third carrier board, and a fourth carrier board stacked from top to bottom, with each board electrically interconnected via gold-plated pins; the first carrier board is fixed below the interface circuit board via an isolated interface, the second and third carrier boards are fixedly mounted on the upper side of the chip platform, and the fourth carrier board is fixedly connected below the third carrier board. A resistor chip is fixed on the upper surface of the chip carrier and electrically connected to a gold-plated patch on the surface of the second carrier via bonding leads; the gold-plated patch and the gold-plated pin form a path.

[0006] In one embodiment, the cooling column has a magnet connection hole on its sidewall, which mates with a connector to rigidly assemble a superconducting magnet.

[0007] In one embodiment, the chip stage is provided with a support structure, the upper surface of the support structure is provided with a limiting mechanism, and the lower surface is fixed with the fourth carrier plate.

[0008] In one embodiment, the limiting mechanism has a chamfered structure near the center of the chip stage to compensate for the influence of machining tolerances on the positioning of the circuit board assembly.

[0009] In one embodiment, the second, third, and fourth carrier plates are annular structures, and the inner sides of the second, third, and fourth carrier plates are provided with groove structures. The groove structures cooperate with the limiting mechanism to fix the second, third, and fourth carrier plates onto the chip platform.

[0010] In one embodiment, the top of the interface circuit board is provided with a through hole, the first through hole being connected to the internal electrical leads of the superconducting magnet; the second through hole is connected to the first carrier board through the gold-plated pin.

[0011] In one embodiment, the first through hole has a built-in superconducting lead slot. After the superconducting lead is connected through the superconducting lead slot, it passes through the gold-plated pin to the fourth carrier plate, forming a connection path with the external detection instrument.

[0012] In one embodiment, the superconducting lead slot is detachably connected to the resistor chip and the chip stage.

[0013] In one embodiment, the first carrier board is provided with gold-plated pin holes corresponding to the interface circuit board, and additional gold-plated pin holes communicating with the gold-plated pin holes, so that the resistor chip can be directly or indirectly connected to the external circuit through the gold-plated pins.

[0014] In one embodiment, the gold-plated patches and bonding wires are spaced apart from the gold-plated pins.

[0015] Compared with the prior art, the embodiments of this application use threaded coupling cooling columns connected to external cooling strips to form an efficient heat conduction path and solve the problem of local temperature drift of resistor chips; By combining the support structure and the limiting mechanism, the displacement of the circuit board assembly caused by the vibration of the GM refrigerator is suppressed; A chamfered structure is provided on the side of the limiting mechanism near the center of the stage to reduce the impact of processing and assembly errors on the bonding accuracy of the resistor chip; The superconducting lead slot and spatial isolation layout are designed to avoid mechanical damage to the bonding leads during insertion and removal operations. This application significantly reduces the operational complexity of switching and maintaining quantum resistors in traditional liquid helium-free devices, enables long-term stable operation of quantum resistors in a liquid helium-free environment, and ensures the traceability accuracy of resistance value transmission.

[0016] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the overall structure of a liquid helium-free conductive cooling quantum resistor device platform provided in an embodiment of this application; Figure 2 This is a schematic diagram of the resistor chip carrier circuit module provided in the embodiments of this application; Figure 3 This is a schematic diagram of the cooling column provided in an embodiment of this application; Figure 4 This is a schematic diagram of the resistor chip stage provided in an embodiment of this application; Figure 5 This is a schematic diagram of the first carrier plate structure provided in an embodiment of this application; Figure 6 This is a schematic diagram of the second, third, and fourth carrier plates provided in the embodiments of this application.

[0018] In the diagram: 1. First through hole; 2. Second through hole; 3. Interface circuit board; 4. First carrier board; 5. Gold-plated pin; 6. Resistor chip; 7. Bonding wire; 8. Gold-plated patch; 9. Fixing component; 10. Second carrier board; 11. Third carrier board; 12. Fourth carrier board; 13. Chip stage; 14. External thread; 15. Cooling column; 16. Magnet connection hole; 17. Thermal thread; 18. Limiting mechanism; 19. Support structure; 20. Chamfered structure; 21. Gold-plated pin hole; 22. Additional gold-plated pin hole; 23. Inner through hole; 24. Outer through hole. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0020] In the description of this invention, it should be understood that the terms "center", "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0021] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] like Figures 1-6 As shown, this application provides a liquid helium-free conduction-cooled quantum resistor device stage, comprising: The cooling column 15 has a thermally conductive thread 17 on its bottom outer edge for binding the cooling strip. Specifically, the heat-conducting thread 17 on the outer edge of the bottom of the cooling column 15 is threadedly connected to the external oxygen-free copper cooling strip to reduce the interface thermal resistance, improve the overall heat conduction efficiency, and solve the problem of local temperature drift of the resistor chip 6.

[0024] The chip stage 13 is fixedly connected at the bottom center to the top of the cooling column 15; The circuit board assembly includes an interface circuit board 3, a first carrier board 4, a second carrier board 10, a third carrier board 11, and a fourth carrier board 12 stacked from top to bottom. The boards are electrically interconnected by gold-plated pins 5. The first carrier board 4 is fixed to the bottom of the interface circuit board 3 through an isolation interface. The second carrier board 10 and the third carrier board 11 are fixedly mounted on the upper side of the chip stage 13. The fourth carrier board 12 is fixedly connected to the bottom of the third carrier board 11. For example, a Φ0.5mm gold-plated pin is used.

[0025] The resistor chip 6 is fixed on the upper surface of the chip carrier 13 and is electrically connected to the gold-plated patch 8 on the surface of the second carrier 10 through bonding leads 7; the gold-plated patch 8 and the gold-plated pin 5 form a passage.

[0026] For example, the resistor chip 6 is bonded to the upper surface of the chip stage 13 with a low-temperature epoxy adhesive with a thermal conductivity ≥1.5W / m·K; the gold wire connection between the resistor chip 6 and the gold-plated patch 8 is completed using a bonding machine.

[0027] In some embodiments of this application, such as Figure 3 As shown, the cooling column 15 has a magnet connection hole 16 on its side wall. The magnet connection hole 16 is fitted with a connector to rigidly assemble the superconducting magnet.

[0028] Specifically, the top center of the cooling column is provided with an external thread 14 for screwing onto the chip carrier 13.

[0029] For example, the cooling column 15 is a cylindrical high thermal conductivity oxygen-free copper component with a Φ6mm magnet connection hole 16 on its side wall, and is rigidly assembled with the superconducting magnet cold head by copper nails.

[0030] In some embodiments of this application, such as Figure 2 , 4 As shown, the chip stage 13 is provided with a support structure 19, the upper surface of the support structure 19 is provided with a limiting mechanism 18, and the lower surface is fixed with the fourth carrier plate 12.

[0031] Specifically, the limiting mechanism 18, together with the third carrier plate 11 and the fourth carrier plate 12, forms an anti-vibration locking mechanism to suppress the displacement of the circuit board assembly caused by the vibration of the GM refrigerator during operation and to prevent the bonding wires 7 of the resistor chip 6 from breaking.

[0032] Preferably, the support structure 19 is precision machined with a tolerance controlled within ±0.1mm, so that the surface of the gold-plated patch 8 and the bonding surface of the resistor chip 6 remain coplanar, reducing the mechanical stress of the bonding leads 7.

[0033] For example, the chip stage 13 is an oxygen-free copper substrate with an M6 internal thread at the center of the bottom; the upper surface of the support structure 19 of the chip stage 13 is provided with a lateral limiting mechanism 18 with a depth of 2mm.

[0034] In some embodiments of this application, such as Figure 3 As shown, the limiting mechanism 18 has a chamfered structure 20 on the side near the center of the chip stage 13, which is used to compensate for the influence of processing tolerance on the positioning of the circuit board assembly.

[0035] For example, the chamfer structure 20 is set to an R0.5mm chamfer.

[0036] In some embodiments of this application, such as Figure 2 , 6 As shown, the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 are annular structures. The inner sides of the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 are provided with groove structures. The groove structures cooperate with the limiting mechanism 18 to fix the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 on the chip stage 13.

[0037] Specifically, the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 are provided with through holes. The inner through hole 23 is used to fix the second carrier plate 10 and the third carrier plate 11 with gold-plated pins 5, and the outer through hole 24 is used to fix the second carrier plate 10, the third carrier plate 11 and the fourth carrier plate 12 with fasteners 9.

[0038] In some embodiments of this application, such as Figure 2 As shown, the top of the interface circuit board 3 is provided with a through hole. The first through hole 1 is connected to the internal electrical leads of the superconducting magnet; the second through hole 2 is connected to the first carrier board 4 through the gold-plated pin 5.

[0039] In some embodiments of this application, such as Figure 2 As shown, the first through hole 1 has a built-in superconducting lead slot. After the superconducting lead is connected through the superconducting lead slot, it passes through the gold-plated pin 5 to the fourth carrier plate 12, forming a connection path with the external detection instrument.

[0040] In some embodiments of this application, the superconducting lead slot is detachably connected to the resistor chip 6 and the chip stage 13.

[0041] In some embodiments of this application, such as Figure 5 As shown, the first carrier board 4 is provided with a gold-plated pin hole 21 corresponding to the interface circuit board 3, and an additional gold-plated pin hole 22 communicating with the gold-plated pin hole 21, so that the resistor chip 6 can be directly or indirectly connected to the external circuit through the gold-plated pin 5.

[0042] In some embodiments of this application, such as Figure 2 As shown, the gold-plated patch 8 and bonding wire 7 are spaced apart from the gold-plated pin 5. The spatial isolation design reduces the mechanical stress of the bonding wire 7 during the insertion and removal of the interface circuit board 3.

[0043] For example, when an embodiment of this application is tested at a temperature of 3K, its uncertainty is better than [previous value]. This verifies the effectiveness of the cooling and fixing functions of the embodiments of this application.

[0044] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A liquid helium-free conduction-cooled quantum resistance device stage, characterized in that, include: The cooling column has thermally conductive threads on its bottom outer edge for binding the cooling strip; The cooling column has a magnet connection hole on its side wall. The magnet connection hole mates with the connector to rigidly assemble the superconducting magnet. The chip stage is fixedly connected at its bottom center to the top of the cooling column; The circuit board assembly includes an interface circuit board, a first carrier board, a second carrier board, a third carrier board, and a fourth carrier board stacked from top to bottom, with each board electrically interconnected via gold-plated pins. The first carrier board is fixed below the interface circuit board via an isolation interface. The second and third carrier boards are fixedly mounted on the upper side of the chip platform, and the fourth carrier board is fixedly connected below the third carrier board. The top of the interface circuit board has a through hole. The first through hole is connected to the internal electrical leads of the superconducting magnet. The second through hole is connected to the first carrier board via the gold-plated pins. The first through hole has a built-in superconducting lead slot. After the superconducting lead is connected through the superconducting lead slot, it passes through the gold-plated pins to the fourth carrier board, forming a connection path with external detection instruments. A resistor chip is fixed on the upper surface of the chip carrier and electrically connected to a gold-plated patch on the surface of a second carrier via bonding leads; the gold-plated patch and the gold-plated pin form a path; the gold-plated patch and the bonding leads are spaced apart from the gold-plated pin. The chip stage is provided with a support structure, the upper surface of which is provided with a limiting mechanism, and the lower surface of which is fixed to the fourth carrier board; the limiting mechanism is provided with a chamfer structure near the center of the chip stage to compensate for the influence of processing tolerance on the positioning of the circuit board assembly; The second, third, and fourth carrier plates are annular structures, and the inner sides of the second, third, and fourth carrier plates are provided with groove structures. The groove structures cooperate with the limiting mechanism to fix the second, third, and fourth carrier plates onto the chip platform.

2. The liquid helium-free conduction-cooled quantum resistor device stage according to claim 1, characterized in that: The superconducting lead slot is detachably connected to the resistor chip and the chip stage.

3. The liquid helium-free conduction-cooled quantum resistance device stage according to claim 1, characterized in that: The first carrier board is provided with gold-plated pin holes corresponding to the interface circuit board, as well as additional gold-plated pin holes communicating with the gold-plated pin holes, so that the resistor chip can be directly or indirectly connected to the external circuit through the gold-plated pins.

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