Current sensor for small current measurement

Abstract

The invention discloses a current sensor for small current measurement, which is formed by sequentially connecting a current amplifier, an analog-to-digital converter and a digital processing unit in series, and the analog-to-digital converter is formed by sequentially connecting a first integral unit, a second integral unit, an analog-to-digital conversion unit and a coding module in series. According to the invention, a novel front-end current amplifier is adopted, and a nanometer ampere level or a picoampere level needing to be measured is amplified, so that minimum feedback current required by direct use of an analog-to-digital converter is avoided. Compared with the prior art, the circuit structure is not limited by the conversion speed, an amplifier with great power consumption is not needed to reduce the feedback current, and the low-power-consumption design can be achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of current sensors, and in particular relates to a current sensor for measuring small currents. Background Art

[0002] With the rapid penetration of electronic technology from traditional industrial control into new energy, the Internet of Things, and biomedical fields, the demand for current sensing has evolved from simple overcurrent protection to high-precision, multi-dimensional, and intelligent comprehensive monitoring systems. Current sensing circuits are key modules for achieving high-precision current measurement in modern electronic systems. They are widely used in power management, battery monitoring, motor drive, energy metering, and fault protection. Their core goal is to provide the system with real-time, reliable current information through the precise acquisition, conditioning, and digitization of current signals, thereby supporting functions such as closed-loop control, energy efficiency optimization, and safety monitoring.

[0003] With the development of wearable devices and implantable medical electronics, low-current sensing circuits are evolving towards nanoampere-level resolution. This requires high-precision, low-noise current sensing at extremely low signal amplitudes. Applications such as single-cell electrophysiology, DNA sequencing, and synaptic signal monitoring require resolution of sub-nanoampere to picoampere currents. Current-mode Σ-Δ analog-to-digital converters can be used to achieve nanoampere to picoampere current measurements, but these converters require extremely low feedback currents. For example, the paper [H. Zhang, H. Li, S. Zhang, Y. Zhang, L. Shen, Z. Tan, and Y. Le. A High-Sensitivity, Large-Dynamic-Range Current-Domain Continuous-Time Scaling Analog-to-Digital Converter for Current Sensing Front Ends, IEEE Journal of Sensors, Vol. 23, No. 1, January 2023, pp. 401-413] uses a pulse-width-modulated resistive DAC to reduce feedback current. However, this technique significantly limits the speed of the analog-to-digital converter, limiting its bandwidth to 100 Hz. For example, the literature [M.Amayreh, G. Baaken, JC Behrends and Y. Manoli. Fully integrated current-mode continuous-time ΔΣ modulator for biological nanopore readout, IEEE Transactions on Biomedical Circuits and Systems, February 2019, Vol. 13, No. 1, pp. 225-236] uses additional amplifiers, MOS tubes and capacitors to reduce the feedback current. Although this can effectively increase the conversion speed of the analog-to-digital converter, it greatly increases the energy consumption of the analog-to-digital converter. Summary of the Invention

[0004] In view of the above, the present invention provides a current sensor for measuring low currents, which uses a low-power current amplifier. This effectively increases the input current of the Σ-Δ analog-to-digital converter and reduces the feedback current requirements. In addition, since the input current is amplified, the noise of the analog-to-digital converter is effectively suppressed, simplifying its design.

[0005] A current sensor for measuring low currents, which consists of a current amplifier, an analog-to-digital converter, and a digital processing unit connected in series. The current amplifier is used to amplify the input current, the analog-to-digital converter is used to perform analog-to-digital conversion on the amplified input current to generate a digital code, and the digital processing unit is used to digitally process the digital code to obtain a digital output corresponding to the input current.

[0006] Furthermore, the current amplifier includes two current sources I1 and I2, six NMOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6 and six PMOS transistors Mp1, Mp2, Mp3, Mp4, Mp5, Mp6, wherein one end of I1 is connected to the power supply voltage, the other end of I1 is connected to the gate of Mn1, the drain of Mn1 and the gate of Mn2, the source of Mn1 is connected to the source of Mp1 and is externally connected to the common mode voltage, one end of I2 is grounded, the other end of I2 is connected to the gate of Mp1, the drain of Mp1 and the gate of Mp2, the source of Mn2 is connected to the source of Mp2 as the input end of the current amplifier, M The drain of n2 is connected to the gate of Mp3, the drain of Mp3, the gate of Mp4, the gate of Mp5 and the gate of Mp6, the source of Mp3 is connected to the drain of Mp5, the source of Mp5 is connected to the power supply voltage, the source of Mp4 is connected to the drain of Mp6, the source of Mp6 is connected to the power supply voltage, the drain of Mp2 is connected to the gate of Mn3, the drain of Mn3, the gate of Mn4, the gate of Mn5 and the gate of Mn6, the source of Mn3 is connected to the drain of Mn5, the source of Mn5 is grounded, the source of Mn4 is connected to the drain of Mn6, the source of Mn6 is grounded, and the drain of Mn4 is connected to the drain of Mp4 as the output end of the current amplifier.

[0007] Furthermore, the width-to-length ratio of the NMOS tube Mn4 is Q times that of Mn3, the width-to-length ratio of the NMOS tube Mn6 is Q times that of Mn5, the width-to-length ratio of the PMOS tube Mp4 is Q times that of Mp3, and the width-to-length ratio of the PMOS tube Mp6 is Q times that of Mp5, where Q is a positive integer greater than or equal to 10.

[0008] Furthermore, the analog-to-digital converter is composed of a first integration unit, a second integration unit, an analog-to-digital conversion unit, and an encoding module connected in series in sequence. The first integration unit is used to integrate the amplified input current after subtracting it from the output of the internal digital-to-analog converter DAC1, and the second integration unit is used to integrate the output of the first integration unit after subtracting it from the output of the internal digital-to-analog converter DAC2; the analog-to-digital conversion unit is used to quantize the output of the second integration unit and generate a digital code as the output result of the analog-to-digital converter; the encoding module is used to encode the digital code and generate a feedback switching signal for synchronously controlling DAC1 and DAC2.

[0009] Furthermore, the first integration unit includes a digital-to-analog converter DAC1, an operational amplifier OTA1, a switch S1 and a capacitor C1, wherein the non-inverting input terminal of OTA1 is grounded, the inverting input terminal of OTA1 is connected to the output terminal of DAC1, one end of C1 and one end of S1 as the input terminal of the first integration unit, and the other end of C1 is connected to the other end of S1 and the output terminal of OTA1 as the output terminal of the first integration unit.

[0010] Furthermore, the second integration unit includes a digital-to-analog converter DAC2, an operational amplifier OTA2, a resistor R1, a switch S2 and a capacitor C2, wherein one end of R1 is the input end of the second integration unit, the non-inverting input end of OTA2 is grounded, the other end of R1 is connected to the inverting input end of OTA2, the output end of DAC2, one end of C2 and one end of S2, and the other end of C2 is connected to the other end of S2 and the output end of OTA2 as the output end of the second integration unit.

[0011] Furthermore, the analog-to-digital conversion unit adopts a 3-level flash memory analog-to-digital converter, and the digital code generated by it is a 1.5-bit unary code word.

[0012] Furthermore, the digital-to-analog converter DAC1 has the same structure as DAC2, and the specific structure includes three switches S3, S4, and S5 and a resistor R2, wherein one end of S3 is connected to the power supply voltage, one end of S4 is connected to the common-mode voltage, one end of S5 is grounded, the other end of S3 is connected to the other end of S4, the other end of S5, and one end of R2, the other end of R2 serves as the output end of the digital-to-analog converter, and the control electrodes of S3, S4, and S5 are connected to the feedback switching signal provided by the encoding module.

[0013] Furthermore, when the number of stages of the analog-to-digital conversion unit is 3, the digital code outputted by the analog-to-digital conversion unit corresponds to three values, namely -1, 0, and 1. The encoding module encodes the digital code to generate three sets of feedback switch signals to control the switches in DAC1 and DAC2. Specifically: When the value output by the analog-to-digital conversion unit is -1, S4 and S5 are disconnected and S3 is closed; When the value output by the analog-to-digital conversion unit is 0, S3 and S5 are disconnected and S4 is closed; When the value output by the analog-to-digital conversion unit is 1, S3 and S4 are disconnected, and S5 is closed; The encoding module switches the switch states in DAC1 and DAC2 only on the rising edge of the feedback clock.

[0014] Furthermore, the digital processing unit is composed of two digital integrators in cascade, the front-stage integrator adopts a binary counter, the back-stage integrator consists of an adder and a register, the input end of the binary counter is connected to the digital code generated by the analog-to-digital converter, the reset end of the binary counter is connected to the reset clock, the output end of the binary counter is connected to the first input end of the adder, the output end of the adder is connected to the input end of the register, the reset end of the register is connected to the reset clock, the clock end of the register is connected to the feedback clock, and the output end of the register is connected to the second input end of the adder to generate a digital output corresponding to the input current.

[0015] This invention utilizes a novel front-end current amplifier that amplifies the nanoamperes or picoamperes required for measurement, avoiding the extremely small feedback currents required by direct analog-to-digital converters. Compared to existing technologies, this circuit structure eliminates conversion speed limitations and eliminates the need for high-power amplifiers to reduce feedback currents, enabling a low-power design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a structural block diagram of the current sensor of the present invention.

[0017] Figure 2 Schematic diagram of the structure of the digital-to-analog converter in the present invention.

[0018] Figure 3 Schematic diagram of the clock signal used by the current sensor of the present invention.

[0019] Figure 4 FIG. 4 is a simplified circuit diagram of the digital processing unit in the present invention.

[0020] Figure 5 Schematic diagram of the gain curve of the current amplifier in the present invention. DETAILED DESCRIPTION

[0021] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Applications such as single-cell electrophysiological analysis, DNA sequencing, and synaptic signal monitoring require analyzing sub-nanoampere to picoampere currents. To meet these low-current measurement requirements, this embodiment provides a solution that combines input current amplification with a current-mode Σ-Δ analog-to-digital converter (ADC). This solution enables low-current measurement while improving conversion speed and reducing energy consumption.

[0023] like Figure 1 As shown, the current sensor for low current measurement in this embodiment includes a current amplifier, an analog-to-digital converter, and a digital processing unit connected in series in sequence; the current amplifier receives an input current and amplifies it to obtain a first output current input to the analog-to-digital converter; the analog-to-digital converter receives the first current and performs analog-to-digital conversion on it to obtain a 1.5-bit digital code; the digital processing unit receives the digital code and performs digital processing to obtain a digital output corresponding to the input current.

[0024] In this embodiment, the current amplifier includes two current sources I1 and I2, six NMOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, and six PMOS transistors Mp1, Mp2, Mp3, Mp4, Mp5, and Mp6; one end of the current source I1 is connected to the power supply voltage V DD The other end of I1 is connected to the gate and drain of Mn1 and the gate of Mn2. The source of Mn1 is connected to the source of Mp1 and serves as the external common mode voltage V CM One end of the current source I2 is grounded, the other end of I2 is connected to the gate and drain of Mp1 and the gate of Mp2, the source of Mn2 is connected to the source of Mp2 and serves as the current input terminal, the drain of Mn2 is connected to the gate and drain of Mp3, the gate of Mp4, the gate of Mp5 and the gate of Mp6, the source of Mp3 is connected to the drain of Mp5, and the source of Mp5 is connected to the power supply voltage V DD , the source of Mp4 is connected to the drain of Mp6, and the source of Mp6 is connected to the power supply voltage V DD The drain of Mp2 is connected to the gate and drain of Mn3, the gate of Mn4, the gate of Mn5 and the gate of Mn6, the source of Mn3 is connected to the drain of Mn5, the source of Mn5 is grounded, the source of Mn4 is connected to the drain of Mn6, the source of Mn6 is grounded, and the drain of Mn4 is connected to the drain of Mp4 and serves as the current output end.

[0025] The width-to-length ratio of the NMOS transistor Mn4 is Q times that of Mn3, the width-to-length ratio of the NMOS transistor Mn6 is Q times that of Mn5, the width-to-length ratio of the PMOS transistor Mp4 is Q times that of Mp3, and the width-to-length ratio of the PMOS transistor Mp6 is Q times that of Mp5, where Q is a positive integer greater than or equal to 10.

[0026] In this embodiment, the analog-to-digital converter includes a first integration unit, a second integration unit, an analog-to-digital conversion unit, and an encoding module connected in series; wherein the first integration unit is used to integrate the first output current after taking the difference between it and the output of the internal digital-to-analog converter DAC1; the second integration unit is used to integrate the output of the first integration unit after taking the difference between it and the output of the internal digital-to-analog converter DAC2; the analog-to-digital conversion unit is used to quantize the output of the second integration unit and generate a digital code as an output result; the encoding module is used to encode the digital code generated by the analog-to-digital conversion unit and generate a feedback switching signal for controlling DAC1 and DAC2.

[0027] In this embodiment, the first integration unit includes a first digital-to-analog converter DAC1, a first operational amplifier OTA1, a first switch S1 and a first capacitor C1; wherein the non-inverting input terminal of OTA1 is grounded, the inverting input terminal of OTA1 is connected to the output terminal of DAC1, one end of C1 and one end of S1 and serves as the input terminal of the analog-to-digital converter unit, the other end of C1 is connected to the other end of S1 and the output terminal of OTA1 and serves as the output terminal of the first integration unit, and the control terminal of DAC1 is connected to the output terminal of the encoding module.

[0028] In this embodiment, the second integration unit includes a second digital-to-analog converter DAC2, a second operational amplifier OTA2, a first resistor R1, a second switch S2 and a second capacitor C2; wherein one end of R1 is the input end of the second integration unit, the non-inverting input end of OTA2 is grounded, the other end of R1 is connected to the inverting input end of OTA2, the output end of DAC2, one end of C2 and one end of S2, the other end of C2 is connected to the other end of S2 and the output end of OTA2 and serves as the output end of the second integration unit, and the control end of DAC2 is connected to the output end of the encoding module.

[0029] like Figure 2 As shown, in this embodiment, DAC1 and DAC2 have the same structure, including three switches S3~S5 and a resistor R2; one end of S3 is connected to the power supply voltage V DD , one end of S4 is connected to the common mode voltage V CM , one end of S5 is grounded, the other end of S3 is connected to the other end of S4, the other end of S5 and one end of R2, and the other end of R2 serves as the output end of the DAC.

[0030] In this embodiment, the analog-to-digital conversion unit adopts a three-level flash memory analog-to-digital converter. The digital code it outputs is a 1.5-bit binary code word corresponding to three values, namely -1, 0, and 1. The encoding module generates a switch signal based on the digital code to control the switches in DAC1 and DAC2 respectively. Specifically: When the value output by the analog-to-digital conversion unit is -1, S4 and S5 are disconnected and S3 is closed; When the value output by the analog-to-digital conversion unit is 0, S3 and S5 are disconnected and S4 is closed; When the value output by the analog-to-digital conversion unit is 1, S3 and S4 are disconnected, and S5 is closed; The encoding module only responds to the feedback clock Clk D The rising edge toggles the switch states in DAC1 and DAC2.

[0031] like Figure 4 As shown, in this embodiment, the digital processing unit is composed of two digital integrators in cascade. The front-stage integrator adopts a binary counter, and the rear-stage integrator is composed of an adder and a register. The input terminal of the binary counter is connected to the digital code generated by the analog-to-digital converter, and the reset terminal of the binary counter is connected to the reset clock Clk. RST The output of the binary counter is connected to the first input of the adder, the output of the adder is connected to the input of the register, and the reset end of the register is connected to the reset clock Clk RST , the register clock is terminated with the feedback clock Clk D The output end of the register is connected to the second input end of the adder to generate a digital output corresponding to the input current.

[0032] like Figure 3 As shown, in this embodiment, the analog-to-digital conversion unit is controlled by the quantization clock Clk Q The switching states of the digital-to-analog converters DAC1 and DAC2 are controlled by the feedback clock Clk. D Control, S1, S2 and the counters and adders in the digital processing unit are controlled by the reset clock Clk RST Control. Clk RST After every 125 clock cycles, it becomes a high level, which is a conversion. Whenever it is a high level, the digital output corresponding to the input current during this conversion period can be obtained at the digital output.

[0033] like Figure 5 As shown, when Q is 10, the gain of the current amplifier in this embodiment is 10 at low frequencies, effectively amplifying the input current by a factor of 10. This can effectively simplify the design complexity of the subsequent analog-to-digital converter. It is understood that Q can be any value greater than or equal to 10, and the magnitude of the Q value does not affect the basic function of the circuit. In addition, the current amplifier can also have two or more stages of amplification and can be improved based on smaller input currents. This will not be discussed in detail here.

[0034] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It is apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements or modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A current sensor for measuring low current, characterized in that: The current sensor consists of a current amplifier, an analog-to-digital converter, and a digital processing unit connected in series. The current amplifier is used to amplify the input current, the analog-to-digital converter is used to perform analog-to-digital conversion on the amplified input current to generate a digital code, and the digital processing unit is used to digitally process the digital code to obtain a digital output corresponding to the input current.

2. The current sensor for measuring low current according to claim 1, characterized in that: The current amplifier includes two current sources I1 and I2, six NMOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6 and six PMOS transistors Mp1, Mp2, Mp3, Mp4, Mp5, Mp6, wherein one end of I1 is connected to the power supply voltage, the other end of I1 is connected to the gate of Mn1, the drain of Mn1 and the gate of Mn2, the source of Mn1 is connected to the source of Mp1 and is externally connected to the common mode voltage, one end of I2 is grounded, the other end of I2 is connected to the gate of Mp1, the drain of Mp1 and the gate of Mp2, the source of Mn2 is connected to the source of Mp2 as the input end of the current amplifier, and the source of Mn2 is connected to the source of Mp2 as the input end of the current amplifier. The drain is connected to the gate of Mp3, the drain of Mp3, the gate of Mp4, the gate of Mp5 and the gate of Mp6, the source of Mp3 is connected to the drain of Mp5, the source of Mp5 is connected to the power supply voltage, the source of Mp4 is connected to the drain of Mp6, the source of Mp6 is connected to the power supply voltage, the drain of Mp2 is connected to the gate of Mn3, the drain of Mn3, the gate of Mn4, the gate of Mn5 and the gate of Mn6, the source of Mn3 is connected to the drain of Mn5, the source of Mn5 is grounded, the source of Mn4 is connected to the drain of Mn6, the source of Mn6 is grounded, and the drain of Mn4 is connected to the drain of Mp4 as the output end of the current amplifier.

3. The current sensor for measuring low current according to claim 2, characterized in that: The width-to-length ratio of the NMOS tube Mn4 is Q times that of Mn3, the width-to-length ratio of the NMOS tube Mn6 is Q times that of Mn5, the width-to-length ratio of the PMOS tube Mp4 is Q times that of Mp3, and the width-to-length ratio of the PMOS tube Mp6 is Q times that of Mp5, where Q is a positive integer greater than or equal to 10.

4. The current sensor for measuring low current according to claim 1, characterized in that: The analog-to-digital converter is composed of a first integration unit, a second integration unit, an analog-to-digital conversion unit, and an encoding module connected in series. The first integration unit is used to integrate the amplified input current after taking the difference between it and the output of the internal digital-to-analog converter DAC1. The second integration unit is used to integrate the difference between the output of the first integration unit and the output of the internal digital-to-analog converter DAC2. The analog-to-digital conversion unit is used to quantize the output of the second integration unit and generate a digital code as the output result of the analog-to-digital converter; the encoding module is used to encode the digital code and generate a feedback switching signal for synchronously controlling DAC1 and DAC2.

5. The current sensor for measuring low current according to claim 4, characterized in that: The first integration unit includes a digital-to-analog converter DAC1, an operational amplifier OTA1, a switch S1 and a capacitor C1, wherein the non-inverting input terminal of OTA1 is grounded, the inverting input terminal of OTA1 is connected to the output terminal of DAC1, one end of C1 and one end of S1 as the input terminal of the first integration unit, and the other end of C1 is connected to the other end of S1 and the output terminal of OTA1 as the output terminal of the first integration unit.

6. The current sensor for measuring low current according to claim 4, characterized in that: The second integration unit includes a digital-to-analog converter DAC2, an operational amplifier OTA2, a resistor R1, a switch S2 and a capacitor C2, wherein one end of R1 is the input end of the second integration unit, the non-inverting input end of OTA2 is grounded, the other end of R1 is connected to the inverting input end of OTA2, the output end of DAC2, one end of C2 and one end of S2, and the other end of C2 is connected to the other end of S2 and the output end of OTA2 as the output end of the second integration unit.

7. The current sensor for measuring low current according to claim 4, characterized in that: The analog-to-digital conversion unit adopts a 3-level flash memory analog-to-digital converter, and the digital code generated by the analog-to-digital conversion unit is a 1.5-bit unary code word.

8. The current sensor for measuring low current according to claim 4, characterized in that: The digital-to-analog converters DAC1 and DAC2 have the same structure, specifically including three switches S3, S4, and S5 and a resistor R2, wherein one end of S3 is connected to the power supply voltage, one end of S4 is connected to the common-mode voltage, one end of S5 is grounded, the other end of S3 is connected to the other end of S4, the other end of S5, and one end of R2, the other end of R2 serves as the output end of the digital-to-analog converter, and the control electrodes of S3, S4, and S5 are connected to the feedback switch signal provided by the encoding module.

9. The current sensor for measuring low current according to claim 4, characterized in that: When the number of stages of the analog-to-digital conversion unit is 3, the digital code outputted by the analog-to-digital conversion unit corresponds to three values, namely -1, 0, and 1. The encoding module encodes the digital code to generate three sets of feedback switch signals to control the switches in DAC1 and DAC2. Specifically: When the value output by the analog-to-digital conversion unit is -1, S4 and S5 are disconnected and S3 is closed; When the value output by the analog-to-digital conversion unit is 0, S3 and S5 are disconnected and S4 is closed; When the value output by the analog-to-digital conversion unit is 1, S3 and S4 are disconnected, and S5 is closed; The encoding module switches the switch states in DAC1 and DAC2 only on the rising edge of the feedback clock.

10. The current sensor for measuring low current according to claim 1, characterized in that: The digital processing unit is composed of two digital integrators in cascade. The front-stage integrator adopts a binary counter, and the rear-stage integrator consists of an adder and a register. The input end of the binary counter is connected to the digital code generated by the analog-to-digital converter, the reset end of the binary counter is connected to the reset clock, the output end of the binary counter is connected to the first input end of the adder, the output end of the adder is connected to the input end of the register, the reset end of the register is connected to the reset clock, the clock end of the register is connected to the feedback clock, and the output end of the register is connected to the second input end of the adder to generate a digital output corresponding to the input current.

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