CAN overcurrent detection circuit

Abstract

The invention relates to the technical field of communication circuits, and discloses a CAN overcurrent detection circuit, which comprises a driving module, an MOS tube M1 and an MOS tube M2, a grid electrode of the MOS tube M1 is connected to a DRVH level to control the on or off of the MOS tube M1, a drain electrode of the MOS tube M1 is connected with one end of a diode D1, the other end of the diode D1 outputs a CANH transmission signal, a source electrode of the MOS tube M2 is grounded, a grid electrode of the MOS tube M2 is connected to a DRVL level, and a drain electrode of the MOS tube M1 is connected with the other end of the diode D1. The drain electrode of the MOS tube M2 is connected with one end of the diode D2, the other end of the diode D2 outputs a CANL transmission signal, the substrate of the MOS tube M2 is connected with the input end of the substrate leakage current detection module, the output end of the substrate leakage current detection module is fed back to the driving module, and through the substrate leakage current detection module, by means of the parasitic correlation between the substrate leakage current of the MOS tube and the main current, the CANL transmission signal is output. Driving currents of an MOS tube M1 and an MOS tube M2 in a CAN circuit are indirectly monitored, and the overcurrent state is accurately recognized through voltage conversion of a sampling resistor, amplification of an operational amplifier, ADC conversion and threshold judgment.

Description

Technical Field

[0001] The present invention relates to the technical field of communication circuits, and in particular to a CAN overcurrent detection circuit. Background Art

[0002] CAN bus is a serial communication protocol and a multi-master bus. Each node in the network can act as a master node to actively communicate with other nodes. Unlike the traditional master-slave bus, only the master node can initiate communication. Differential signal transmission is often used. The signals transmitted by the CANH and CANL lines are differential with each other, which can effectively suppress common-mode interference. For example, in various electromagnetic interference environments faced by cars during driving, data can still be accurately transmitted.

[0003] like Figure 1 As shown in the figure, the traditional CAN receiving circuit usually includes a reference module, a transceiver control module, an output shaping module, a receiving module and a protection module. The reference module provides a stable reference voltage or current for the internal circuit of the chip to ensure the accurate operation of the threshold judgment, signal amplification and other functions of each module (such as driving and receiving). The transceiver control module controls the working status of the chip through RS, coordinates the flow of data in the sending path and the receiving path, and decides when to allow data to be sent and when to start receiving monitoring. The output shaping module receives the TXD signal from the MCU, regularizes the waveform of the digital signal, makes the signal conform to the electrical specifications of the CAN bus, and provides clean data to be sent to the driving module. The driver module receives the shaped signal, outputs a level with strong driving capability through DRVH and DRVL, controls the on and off of the external MOS tubes M1 and M2, and finally generates a differential voltage that complies with the CAN protocol on the CANH and CANL buses to push data to the bus. The receiving module monitors the differential voltage on the CANH and CANL buses in real time, converts it into the RXD digital level that the MCU can recognize, completes the reverse conversion of the bus signal to the chip signal, and allows the MCU to read the data on the bus. The protection module is usually responsible for overvoltage or overcurrent protection. For example, when the bus is subjected to surge impact or short circuit, it limits the voltage or current to avoid chip damage and improve system reliability.

[0004] MOS transistors M1 and M2 are often connected to diodes D1 and D2 to prevent backflow. When a reverse voltage (such as a surge or incorrect wiring) appears on the bus, the diodes are reversely cut off, preventing abnormal current from flowing back into MOS transistors M1 and M2, thereby protecting MOS transistors M1 and M2.

[0005] However, due to the lack of overcurrent detection, when an abnormal situation occurs on the CAN bus, such as a short circuit or strong external interference causing excessive current, there is no special detection mechanism. This may cause the CAN transceiver chip to be subjected to excessive current for a long time, which may lead to chip overheating, performance degradation, or even permanent damage. For example, in the complex electrical environment of a car, the cables between electrical equipment may short-circuit due to wear, extrusion, etc. At this time, if the excessive current is not effectively detected and processed, it will damage the CAN transceiver chip and affect the communication of the entire car CAN bus network.

[0006] Furthermore, in CAN receiver circuits without overcurrent detection, when a chip malfunctions, it's difficult to quickly determine whether the cause is overcurrent. Maintenance personnel must spend considerable time and effort troubleshooting various possible causes, increasing the difficulty of fault diagnosis and repair costs.

[0007] Therefore, it is necessary to provide a CAN overcurrent detection circuit to solve the above problem. Summary of the Invention

[0008] The purpose of the present invention is to provide a technical solution to solve the problems in the prior art raised in the above background technology.

[0009] To achieve the above object, the present invention adopts the following technical solutions: A CAN overcurrent detection circuit includes a driving module, a MOS transistor M1, and a MOS transistor M2. After receiving a shaped signal, the driving module transmits a DRVH level and a DRVL level to the MOS transistor M1 and the MOS transistor M2. The source of the MOS transistor M1 is connected to the chip working power supply VCC to provide a driving voltage for the MOS transistor M1. The gate of the MOS transistor M1 is connected to the DRVH level to control the on or off of the MOS transistor M1. The drain of the MOS transistor M1 is connected to one end of the diode D1, and the other end of the diode D1 outputs the CANH transmission signal. The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the DRVL level, the drain of the MOS transistor M2 is connected to one end of the diode D2, and the other end of the diode D2 outputs the CANL transmission signal. A resistor R1 is connected in series between the substrate and the source of the MOS transistor M2, and the substrate of the MOS transistor M2 is connected to the input end of the substrate leakage current detection module. The output end of the substrate leakage current detection module is fed back to the driving module.

[0010] Preferably, the substrate leakage current detection module includes an amplifier OPA0, an ADC module and a judgment module, the non-inverting input end of the amplifier OPA0 is connected to the substrate of the MOS tube M1, the output end of the amplifier OPA0 is connected to the input end of the ADC module, and the output end of the ADC module is connected to the input end of the judgment module.

[0011] Preferably, the output end of the amplifier OPA0 is connected to one end of the resistor R2, the resistor R2 is connected in series with the resistor R3, and the inverting input end of the amplifier OPA0 is connected to the other end of the resistor R2.

[0012] Preferably, the substrate of the MOS transistor M2 is grounded via a resistor R1. When a leakage current I_sub occurs in the substrate of the MOS transistor M2, a voltage drop signal Vsub is generated on the resistor R1. The voltage drop signal Vsub is amplified by an amplifier OPAO and output as an analog voltage V1. The analog voltage V1 is converted into a code value of a digital signal by an ADC module. The code value of the digital signal is input to a judgment module. The judgment module compares the code value converted by the ADC module with a preset code value and outputs a judgment result S0 to the driving module. If there is no overcurrent, S0=0; If the output is overcurrent, S0=1; The driving module adjusts the on / off state of the MOS tube M2 according to the detection result of S0.

[0013] Preferably, the source of the MOS transistor M1 is connected to the source of the MOS transistor M3, the gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level, the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M2, the gate of the MOS transistor M2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the power supply VDD.

[0014] Preferably, when the MOS transistor M1 conducts the output current Ip1, the gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level, the MOS transistor M3 mirrors the current of the MOS transistor M1, and the drain of the MOS transistor M3 outputs the current Ip2 to the MOS transistor M2. The current of the MOS transistor M1 is indirectly detected by the substrate leakage current detection module.

[0015] Preferably, it includes a first current mirror module, a second current mirror module and a current superposition module, wherein the first current mirror module is used to mirror the current of the MOS tube M1, the second current mirror module is used to mirror the current of the MOS tube M2, the current superposition module is used to superimpose the mirrored currents of the MOS tube M1 and the MOS tube M2, and the current superposition module indirectly detects the currents of the MOS tube M1 and the MOS tube M2 through the substrate leakage current detection module.

[0016] Preferably, the first current mirror module includes a MOS transistor M3, the source of the MOS transistor M1 and the source of the MOS transistor M3 are connected in common, and the gates of the MOS transistor M1 and the MOS transistor M3 are connected in common to the DRVH level.

[0017] Preferably, the second current mirror module includes a MOS transistor M4, a MOS transistor M5, and a MOS transistor M6. The gate of the MOS transistor M4 is commonly connected to the gate of the MOS transistor M2, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M5, the source of the MOS transistor M5 is commonly connected to the source of the MOS transistor M6, the gate of the MOS transistor M5 is commonly connected to the gate of the MOS transistor M6, and the gate and drain of the MOS transistor M5 are short-circuited.

[0018] Preferably, the current superposition module includes a MOS transistor M7, a MOS transistor M8, and a MOS transistor M9. The drain of the MOS transistor M7 is connected to the drain of the MOS transistor M3, the drain of the MOS transistor M8 is connected to the drain of the MOS transistor M6, the source of the MOS transistor M7 and the source of the MOS transistor M8 are both connected to the drain of the MOS transistor M9. A resistor R1 is connected in series between the substrate and the source of the MOS transistor M9. The input end of the substrate leakage current detection module is connected to the substrate of the MOS transistor M9. The gate of the MOS transistor M7 is connected to one end of the resistor R3, the gate of the MOS transistor M8 is connected to one end of the resistor R4, the gate of the MOS transistor M9 is connected to one end of the resistor R2, and the other ends of the resistors R2, R3 and R4 are all connected to the power supply VDD.

[0019] The technical effects and advantages of the present invention: Compared with the prior art, the CAN overcurrent detection circuit proposed in the present invention has the following advantages: 1. The present invention uses a substrate leakage current detection module and the parasitic correlation between the MOS tube substrate leakage current and the main current to indirectly monitor the drive current of MOS tubes M1 and MOS tubes M2 in the CAN circuit. After voltage conversion by a sampling resistor, amplification by an operational amplifier, ADC conversion, and threshold judgment, the overcurrent state is accurately identified. The drive module dynamically adjusts the on-off of MOS tubes M1 and MOS tubes M2 based on S0, quickly cutting off the overcurrent circuit, effectively preventing the chip from overheating and damage due to continuous overcurrent, significantly improving the reliability of the CAN transceiver system in complex scenarios such as automobiles. Even if the bus is short-circuited, timely protection can be provided to prevent the fault from spreading to the entire vehicle CAN network. 2. The present invention explicitly associates the fault status through the overcurrent flag S0, that is, S0=1 indicates overcurrent and S0=0 indicates normal. Through current mirroring and substrate detection, the main current anomaly is converted into easily monitored voltage and digital signals. During maintenance, engineers only need to monitor signals such as S0 and V1 to quickly determine whether overcurrent occurs and whether the overcurrent originates from M1 or M2, which greatly shortens the fault diagnosis time and reduces the cost of manual investigation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural diagram of a traditional CAN receiving circuit; Figure 2 This is a system block diagram of a CAN overcurrent detection circuit according to the present invention; Figure 3 This is a circuit diagram of embodiment 1 of the present invention; Figure 4 This is a circuit diagram of embodiment 2 of the present invention; Figure 5 This is a circuit diagram of embodiment 3 of the present invention; Figure 6 This is a signal waveform timing diagram of Example 1 of the present invention; Figure 7 This is a signal waveform timing diagram of Example 2 of the present invention; Figure 8 This is a signal waveform timing diagram of Example 3 of the present invention. DETAILED DESCRIPTION

[0021] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed solely to enable those skilled in the art to better understand and implement the subject matter described herein, and that the functions and arrangements of the elements discussed may be varied without departing from the scope of this specification. Various examples may omit, substitute, or add various processes or components as needed. Furthermore, features described for some examples may be combined in other examples.

[0022] See also Figures 2 to 8 , the embodiment provided by the present invention: Example 1

[0023] like Figure 2 and Figure 3 As shown, a CAN overcurrent detection circuit includes a driving module, a MOS transistor M1 and a MOS transistor M2. After receiving the shaped signal, the driving module transmits DRVH level and DRVL level to the MOS transistor M1 and the MOS transistor M2. The source of the MOS tube M1 is connected to the chip working power supply VCC to provide a driving voltage for the MOS tube M1. The gate of the MOS tube M1 is connected to the DRVH level to control the conduction or cutoff of the MOS tube M1. The drain of the MOS tube M1 is connected to one end of the diode D1, and the other end of the diode D1 outputs the CANH transmission signal. The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the DRVL level, the drain of the MOS transistor M2 is connected to one end of the diode D2, the other end of the diode D2 outputs the CANL transmission signal, a resistor R1 is connected in series between the substrate and the source of the MOS transistor M2, and the substrate of the MOS transistor M2 is connected to the input end of the substrate leakage current detection module, and the output end of the substrate leakage current detection module is fed back to the driving module.

[0024] The substrate leakage current detection module includes an amplifier OPA0, an ADC module and a judgment module. The non-inverting input end of the amplifier OPA0 is connected to the substrate of the MOS tube M1, the output end of the amplifier OPA0 is connected to the input end of the ADC module, the output end of the ADC module is connected to the input end of the judgment module, the output end of the amplifier OPA0 is connected to one end of the resistor R2, the resistor R2 is connected in series with the resistor R3, and the inverting input end of the amplifier OPA0 is connected to the other end of the resistor R2.

[0025] The substrate of the MOS transistor M2 is grounded through the resistor R1. When there is a leakage current I_sub in the substrate of the MOS transistor M2, a voltage drop Vsub signal is generated on the resistor R1. The current flowing through the resistor R1 generates a voltage Vsub=I_sub*r1. For MOS transistors, the ionization effect phenomenon will also occur, but the effect of this phenomenon on device characteristics is significantly different from that of bipolar transistors. This difference is because the electrons in the channel (for NMOS) generate electron-hole pairs in the drain depletion region through lattice collisions, and some of the holes flow to the substrate to form substrate current. The electrons generated in this process flow to the drain end, so the carriers generated during the ionization effect are not confined inside the device like bipolar transistors. For NMOS devices, the result can be equivalent to connecting a controlled current source in series from the drain to the substrate layer; The magnitude of the substrate current depends on the voltage drop across the drain depletion region, where the substrate leakage current formula for NMOS transistors is:

[0026] In the formula: I DB： Leakage current of the substrate of the MOS tube; K1, K2: process parameters; V DS : The voltage from the drain to the source of the MOS tube; V DS（act） : The minimum Vds voltage value of the MOS tube working amplification area; I D : Drain current of MOS tube; Therefore, the leakage current I DB and the drain current I D Therefore, Vsub can indirectly reflect the current Id of the power tube M2. The voltage drop Vsub signal is amplified by the amplifier OPAO and outputs the analog voltage V1. V1=Vsub*(R2+R3) / R3. The analog voltage V1 is converted into a digital signal code value by the ADC module. The digital signal code value is input to the judgment module. The judgment module compares the code value converted by the ADC module with the preset code value and outputs the judgment result S0 to the drive module. If there is no overcurrent, S0=0; If the output is overcurrent, S0=1; The driving module adjusts the on / off state of the MOS tube M2 according to the detection result of S0.

[0027] Detect the potential, such as Figure 6 As shown in the figure, during normal operation, IDS rises slowly with the input signal. When overcurrent occurs, IDS exceeds IDS_max and exceeds the device safety threshold. During this process, the substrate leakage current Isub is associated with IDS, and the waveform of Isub is consistent with Isub. It is smooth under normal conditions. When overcurrent occurs, it rises as Isub increases. After amplification by the amplifier OPAO, the waveform of the output analog voltage V1 is consistent with Vsub, but the amplitude is amplified to facilitate ADC acquisition. When the SO output by the judgment module is working normally, the judgment module detects that V1 is lower than the threshold and outputs S0=0, indicating no overcurrent. When overcurrent occurs, V1 exceeds the threshold and the judgment module outputs S0=1, indicating an overcurrent alarm.

[0028] Example 2

[0029] like Figure 4 As shown, based on Example 1, in order to detect the current of the MOS transistor MI and enable the driving module to further control the on and off of the MOS transistor M1, the following technical solutions are provided: The source of the MOS transistor M1 is connected to the source of the MOS transistor M3, the gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level, the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M2, the gate of the MOS transistor M2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the power supply VDD.

[0030] When the MOS transistor M1 conducts and outputs the current Ip1, the gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level. The MOS transistor M3 mirrors the current of the MOS transistor M1, so that Ip1=Ip2. The drain of the MOS transistor M3 outputs the current Ip2 to the MOS transistor M2, so that the MOS transistor M2 is in the on state. The on current of the MOS transistor M2 is determined by the mirrored current Ip2 of the MOS transistor M3 and is indirectly associated with the output current Ip1 of the MOS transistor M1. Then, the current of the MOS transistor M1 is indirectly detected by the substrate leakage current detection module in Example 1. The specific substrate leakage current detection module has been described in detail in Example 1 and will not be described in detail here.

[0031] When the MOS tube M1 is turned on, current detection is performed, such as Figure 7 As shown, when the DRVH signal is high, DRVH=1, the MOS tube M1 and the MOS tube M3 are cut off, and the performance is: Ip1, Ip2, Vsub, V1 and S0 are 0; When the DRVH signal is low, DRVH=0, MOS tubes M1 and M3 are turned on, Ip1 and Ip2 jump from 0 to a stable value. If there is overcurrent, Ip1 exceeds Ids_max, Vsub and V1 rise synchronously. If Ip1 exceeds Ids_max, V1 will also exceed V1_max, S0 jumps, and when V1 exceeds the judgment module threshold, SO=1 and an overcurrent alarm can be issued.

[0032] Example 3

[0033] like Figure 5 As shown, based on Example 2, in order to be able to indirectly detect the current of the MOS transistor M1 and the MOS transistor M2 at the same time, the following technical solution is also provided: The CAN overcurrent detection circuit also includes a first current mirror module, a second current mirror module and a current superposition module. The first current mirror module is used to mirror the current of the MOS tube M1, the second current mirror module is used to mirror the current of the MOS tube M2, and the current superposition module is used to superimpose the mirrored currents of the MOS tubes M1 and M2. The current superposition module indirectly detects the currents of the MOS tubes M1 and M2 through the substrate leakage current detection module.

[0034] Specifically, the first current mirror module includes a MOS transistor M3, the source of the MOS transistor M1 and the source of the MOS transistor M3 are connected in common, and the gates of the MOS transistor M1 and the MOS transistor M3 are connected in common to the DRVH level; The second current mirror module includes a MOS transistor M4, a MOS transistor M5, and a MOS transistor M6. The gate of the MOS transistor M4 is connected to the gate of the MOS transistor M2, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M5, the source of the MOS transistor M5 is connected to the source of the MOS transistor M6, the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M6, and the gate and drain of the MOS transistor M5 are short-circuited. The current superposition module includes MOS transistors M7, M8, and M9. The drain of MOS transistor M7 is connected to the drain of MOS transistor M3, the drain of MOS transistor M8 is connected to the drain of MOS transistor M6, the source of MOS transistor M7 and the source of MOS transistor M8 are both connected to the drain of MOS transistor M9, a resistor R1 is connected in series between the substrate and the source of MOS transistor M9, and the input end of the substrate leakage current detection module is connected to the substrate of MOS transistor M9. The gate of MOS transistor M7 is connected to one end of resistor R3, the gate of MOS transistor M8 is connected to one end of resistor R4, the gate of MOS transistor M9 is connected to one end of resistor R2, and the other ends of resistors R2, R3 and R4 are all connected to power supply VDD.

[0035] The MOS transistor M3 of the first current mirror module has the same function as the MOS transistor M3 in Example 2. The MOS transistor M3 mirrors the current of the MOS transistor M1, Ip1=Ip2, to indirectly obtain the current on the MOS transistor M1; The MOS transistors M4, M5, and M6 of the second current mirror module mirror the current In1 of the MOS transistor M2. Since the gate of the MOS transistor M4 is connected to the gate of the MOS transistor M2, the current In2 on the MOS transistor M4 is equal to In1. Then, the currents In2 ​​and In3 of the MOS transistors M5 and M6 mirroring the currents In4 are equal to In2, thereby indirectly obtaining the mirror current of the MOS transistor M2. The MOS transistors M7 and M8 of the current superposition module superpose the current Ip2 from the MOS transistor M3 and the current In3 from the MOS transistor M6. The total output current is In4=Ip2+In3. The current In4 flows through the MOS transistor M9, turning on the MOS transistor M9, thereby generating a current I_sub on the substrate of the MOS transistor M9. The principle is the same as that of the substrate current on M2 in Example 1. The difference is that the substrate current in this embodiment is affected by the magnitudes of the currents Ip2 and In3. Finally, the currents on the MOS transistors M1 and M2 are indirectly detected by the substrate leakage current detection module and fed back to the driving module. The driving module then controls the on and off of the MOS transistors M1 and M2.

[0036] like Figure 8 As shown, when the MOS tube M1 and the MOS tube M2 are turned on at the same time, current detection is performed: Phase 1: DRVH=1, DRVL=1, MOS tubes M1 and M2 are turned off, DRVH and DRVL are high, MOS tubes M3 and M4 are cut off, Ip1, In1, Vsub, V1 and S0 are 0. At this time, there is no overcurrent, and the judgment module output is 0; Phase 2: DRVH=0, DRVL=0, MOS transistors M1 and M2 are turned on, DRVH and DRVL are low, MOS transistors M3 and M4 are turned on, Ip1 and In1 increase, driving the CANH and CANL buses respectively. If overcurrent reaches Ids_max, MOS transistor M9 is turned on due to mirror current In4, substrate leakage current I_sub increases, and Vsub also increases. Amplifier OPAO amplifies Vsub, causing V1 to rise as Vsub increases. If overcurrent V1 reaches V1_max, the judgment module detects that V1>threshold value, S0 is equal to 1, and it is determined that overcurrent occurs; Phase 3: DRVH=1, DRVL=1. The driver module controls MOS transistors M1 and M2 to turn off, causing Ip1 and In1 to return to zero. This causes the substrate leakage current Isub of MOS transistor M9 to return to zero, and Vsub and V1 to return to 0. The judgment module detects that V1 is less than the threshold and S0 is equal to 0, and the overcurrent is released.

[0037] Therefore, through multi-stage current mirroring, superposition circuits and substrate leakage current detection, the driving current of MOS tubes M1 and MOS tubes M2 can be indirectly monitored without directly connecting sampling resistors in series to affect the driving capability of the main circuit. This not only protects the driving efficiency of the CAN bus, but also can accurately detect overcurrent risks.

[0038] The above describes the embodiments of the present invention, but the present invention is not limited to the above specific implementation methods. The above specific implementation methods are merely illustrative and not restrictive. Ordinary technicians in this field can also make many forms under the guidance of the present invention, all of which are protected by the present invention.

Claims

1. A CAN overcurrent detection circuit, characterized in that: It includes a driving module, a MOS transistor M1 and a MOS transistor M2. After receiving the shaped signal, the driving module transmits DRVH level and DRVL level to the MOS transistor M1 and the MOS transistor M2. The source of the MOS transistor M1 is connected to the chip working power supply VCC to provide a driving voltage for the MOS transistor M1. The gate of the MOS transistor M1 is connected to the DRVH level to control the on or off of the MOS transistor M1. The drain of the MOS transistor M1 is connected to one end of the diode D1, and the other end of the diode D1 outputs the CANH transmission signal. The source of the MOS transistor M2 is grounded, the gate of the MOS transistor M2 is connected to the DRVL level, the drain of the MOS transistor M2 is connected to one end of the diode D2, and the other end of the diode D2 outputs the CANL transmission signal. A resistor R1 is connected in series between the substrate and the source of the MOS transistor M2, and the substrate of the MOS transistor M2 is connected to the input end of the substrate leakage current detection module. The output end of the substrate leakage current detection module is fed back to the driving module.

2. A CAN overcurrent detection circuit according to claim 1, characterized in that: The substrate leakage current detection module includes an amplifier OPA0, an ADC module and a judgment module. The non-inverting input end of the amplifier OPA0 is connected to the substrate of the MOS tube M1, the output end of the amplifier OPA0 is connected to the input end of the ADC module, and the output end of the ADC module is connected to the input end of the judgment module.

3. A CAN overcurrent detection circuit according to claim 2, characterized in that: The output end of the amplifier OPA0 is connected to one end of the resistor R2 , the resistor R2 is connected in series with the resistor R3 , and the inverting input end of the amplifier OPA0 is connected to the other end of the resistor R2 .

4. A CAN overcurrent detection circuit according to claim 3, characterized in that: The substrate of the MOS transistor M2 is grounded via a resistor R1. When a leakage current I_sub occurs in the substrate of the MOS transistor M2, a voltage drop signal Vsub is generated on the resistor R1. The voltage drop signal Vsub is amplified by an amplifier OPAO and output as an analog voltage V1. The analog voltage V1 is converted into a code value of a digital signal by an ADC module. The code value of the digital signal is input to a judgment module. The judgment module compares the code value converted by the ADC module with a preset code value and outputs a judgment result S0 to the driving module. If there is no overcurrent, S0=0; If the output is overcurrent, S0=1; The driving module adjusts the on / off state of the MOS tube M2 according to the detection result of S0.

5. A CAN overcurrent detection circuit according to claim 3, characterized in that: The source of the MOS transistor M1 is connected to the source of the MOS transistor M3. The gates of the MOS transistors M1 and M3 are connected to the DRVH level. The drain of the MOS transistor M3 is connected to the drain of the MOS transistor M2. The gate of the MOS transistor M2 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the power supply VDD.

6. A CAN overcurrent detection circuit according to claim 5, characterized in that: When the MOS transistor M1 conducts and outputs the current Ip1, the gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level. The MOS transistor M3 mirrors the current of the MOS transistor M1. The drain of the MOS transistor M3 outputs the current Ip2 to the MOS transistor M2. The current of the MOS transistor M1 is indirectly detected by the substrate leakage current detection module.

7. The CAN overcurrent detection circuit according to claim 1, characterized in that: The system includes a first current mirror module, a second current mirror module and a current superposition module. The first current mirror module is used to mirror the current of the MOS tube M1, the second current mirror module is used to mirror the current of the MOS tube M2, the current superposition module is used to superimpose the mirrored currents of the MOS tube M1 and the MOS tube M2, and the current superposition module indirectly detects the currents of the MOS tube M1 and the MOS tube M2 through the substrate leakage current detection module.

8. A CAN overcurrent detection circuit according to claim 7, characterized in that: The first current mirror module includes a MOS transistor M3. The source of the MOS transistor M1 is connected to the source of the MOS transistor M3. The gates of the MOS transistor M1 and the MOS transistor M3 are connected to the DRVH level.

9. The CAN overcurrent detection circuit according to claim 8, characterized in that: The second current mirror module includes a MOS transistor M4, a MOS transistor M5, and a MOS transistor M6. The gate of the MOS transistor M4 is commonly connected to the gate of the MOS transistor M2, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M5, the source of the MOS transistor M5 is commonly connected to the source of the MOS transistor M6, the gate of the MOS transistor M5 is commonly connected to the gate of the MOS transistor M6, and the gate and drain of the MOS transistor M5 are short-circuited.

10. The CAN overcurrent detection circuit according to claim 9, characterized in that: The current superposition module includes a MOS transistor M7, a MOS transistor M8, and a MOS transistor M9. The drain of the MOS transistor M7 is connected to the drain of the MOS transistor M3, the drain of the MOS transistor M8 is connected to the drain of the MOS transistor M6, the source of the MOS transistor M7 and the source of the MOS transistor M8 are both connected to the drain of the MOS transistor M9. A resistor R1 is connected in series between the substrate and the source of the MOS transistor M9. The input end of the substrate leakage current detection module is connected to the substrate of the MOS transistor M9. The gate of the MOS transistor M7 is connected to one end of the resistor R3, the gate of the MOS transistor M8 is connected to one end of the resistor R4, the gate of the MOS transistor M9 is connected to one end of the resistor R2, and the other ends of the resistors R2, R3 and R4 are all connected to the power supply VDD.

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