High-speed gear-shifting wide-range current acquisition module

Abstract

A high-speed gear shifting wide-range current acquisition module comprises a high-speed gear shifting circuit module, a current acquisition circuit module, a data processing circuit module and a data transmitting circuit module. According to the high-speed gear-shifting wide-range current acquisition module, wide-range, multi-gear and high-speed gear shifting is achieved through the innovative design that a plurality of current sampling circuits with different ranges are connected in parallel, and the high-speed MOS switch and the differential filtering and amplifying circuit are adopted. Meanwhile, the anti-interference capability, the precision and the safety of the circuit are further improved by adding the functions of a filter circuit, data processing, instantaneous large current protection and the like. The method has a wide application prospect and an important practical value. According to the invention, the current values of different ranges are respectively measured through the plurality of shunt resistors, so that wide-range measurement is realized; according to the invention, the data processing module processes and transmits data of the acquisition module, so that real-time acquisition and processing transmission of the acquired data are realized. According to the invention, accurate measurement of large current and micro current (1uA-50A) can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of current testing, and in particular to a high-speed shifting wide-range current acquisition module. Background Art

[0002] During product development and testing, power consumption is a key consideration, as most products are battery-powered. Products typically operate in two states: active and sleep. Switching from sleep to standby and back to active, or vice versa, results in a wide range of operating current values, with rapid fluctuations.

[0003] Conventional measurement methods have significant limitations for this type of current testing. They can often only guarantee accuracy within a certain range, or require the use of multiple independent circuit modules to switch back and forth. This not only increases the complexity and cost of the circuit, but also causes delays and accuracy loss during the shifting process, resulting in a large deviation between the actual current value and the measured value when the product switches between sleep and working states. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-speed shifting wide-range current acquisition module, comprising: a high-speed shifting circuit module, a current acquisition circuit module, a data processing circuit module, and a data sending circuit module.

[0005] The high-speed gear switching circuit module is electrically connected to the current acquisition circuit module to switch the gear range of the current acquisition circuit module.

[0006] The current acquisition circuit module is used to acquire current signals.

[0007] The data processing circuit module is electrically connected to the current acquisition circuit module and is used to convert the acquired current signal to obtain converted data.

[0008] The data sending circuit module is electrically connected to the data processing circuit module and is used to transmit the converted data to the computer.

[0009] Furthermore, the circuit topology of the high-speed gear switching circuit module is as follows:

[0010] The current input port is referred to as BAT_IN, and the current output port is referred to as BAT_OUT.

[0011] The BAT_IN terminal is connected to the BAT_OUT terminal after being connected in series with resistors R6 and R23.

[0012] The BAT_IN terminal is connected in series with a resistor R6 and then connected to the drain of the switch tube T2 , and the source of the switch tube T2 is connected to the BAT_OUT terminal.

[0013] Furthermore, the switch tube T2 is a MOSFET switch, and the gate of the switch tube T2 is suspended.

[0014] Furthermore, the circuit topology of the current acquisition circuit module is as follows:

[0015] The BAT_IN terminal is connected in series with a resistor R1 and then connected to the VIN+ terminal of the operational amplifier U3. The VIN+ terminal of the operational amplifier U3 is connected in series with a capacitor C9 and then grounded.

[0016] The BAT_IN terminal is connected in series with resistors R6 and R9 in sequence and then connected to the VIN-terminal of the operational amplifier U3. The VIN-terminal of the operational amplifier U3 is connected in series with a capacitor C14 and then grounded.

[0017] The two RG ports of the operational amplifier U3 are connected in series via a resistor R7.

[0018] The V+ terminal of the operational amplifier U3 is connected to a positive power supply I, and the V- terminal of the operational amplifier U3 is connected to a negative power supply I.

[0019] The V+ terminal of the operational amplifier U3 is connected to the capacitor C6 and then to ground, and the V- terminal of the operational amplifier U3 is connected to the capacitor C8 and then to ground.

[0020] The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and a capacitor C15 and then grounded.

[0021] The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and then connected to the ADC_50A terminal.

[0022] The REF terminal of the operational amplifier U3 is grounded.

[0023] The BAT_IN terminal is connected in series with resistors R6 and R20 in sequence and then connected to the VIN+ terminal of the operational amplifier U9. The VIN+ terminal of the operational amplifier U9 is connected in series with capacitor C25 and then grounded.

[0024] The BAT_OUT terminal is connected in series with a resistor R26 and then connected to the VIN-terminal of the operational amplifier U9. The VIN-terminal of the operational amplifier U9 is connected in series with a capacitor C30 and then grounded.

[0025] The two RG ports of the operational amplifier U9 are connected in series via a resistor R24.

[0026] The V+ terminal of the operational amplifier U9 is connected to a positive power supply I, and the V- terminal of the operational amplifier U9 is connected to a negative power supply I.

[0027] The V+ terminal of the operational amplifier U9 is connected to the capacitor C22 and then grounded, and the V- terminal of the operational amplifier U9 is connected to the capacitor C24 and then grounded.

[0028] The VOUT terminal of the operational amplifier U9 is connected in series with a resistor R25 and a capacitor C31 and then grounded.

[0029] The VOUT terminal of the operational amplifier U9 is connected in series with a resistor R25 and then connected to the ADC_100mA terminal.

[0030] The REF terminal of the operational amplifier U9 is grounded.

[0031] The positive power supply I is a positive 5V power supply, and the negative power supply I is a negative 5V power supply.

[0032] Furthermore, the frequency of the current acquisition circuit module is greater than 100KHz.

[0033] Furthermore, the data processing circuit module uses an ARM chip, and the circuit topology of the data processing circuit module is as follows:

[0034] The PA0 terminal of the ARM chip is connected to the 100mA_GateOut terminal.

[0035] The PA3 terminal of the ARM chip is connected to the ControlSw_100mA terminal.

[0036] The PA5 terminal of the ARM chip is connected to the ADC_100mA terminal.

[0037] The PA7 terminal of the ARM chip is connected to the ADC_50A terminal.

[0038] The PD0 terminal of the ARM chip is connected to the / INT terminal.

[0039] The PD1 terminal of the ARM chip is connected to the / RST terminal.

[0040] The PD2 terminal of the ARM chip is connected to the / SPI_CS terminal.

[0041] The PC10 terminal of the ARM chip is connected to the SPI_CLK terminal.

[0042] The PC11 terminal of the ARM chip is connected to the SPI_MISO terminal.

[0043] The PC12 terminal of the ARM chip is connected to the SPI_MOSI terminal.

[0044] The VBAT terminal of the ARM chip is connected in series with a capacitor C58 and then grounded, and the VBAT terminal of the ARM chip is connected to a positive power supply II.

[0045] The VDD-1 terminal of the ARM chip is connected in series with a capacitor C65 and then grounded, and the VDD-1 terminal of the ARM chip is connected to a positive power supply II.

[0046] The VDD-2 terminal of the ARM chip is connected in series with a capacitor C64 and then grounded, and the VDD-2 terminal of the ARM chip is connected to a positive power supply II.

[0047] The VDD-3 terminal of the ARM chip is connected in series with a capacitor C63 and then grounded, and the VDD-3 terminal of the ARM chip is connected to a positive power supply II.

[0048] The VDD-4 terminal of the ARM chip is connected in series with a capacitor C62 and then grounded, and the VDD-4 terminal of the ARM chip is connected to a positive power supply II.

[0049] The VDD-5 terminal of the ARM chip is connected in series with a capacitor C61 and then grounded, and the VDD-5 terminal of the ARM chip is connected to a positive power supply II.

[0050] The VREF+ terminal of the ARM chip is connected in series with a capacitor C60 and then grounded, and the VREF+ terminal of the ARM chip is connected to a positive power supply III.

[0051] The VREF+ terminal of the ARM chip is connected in series with a capacitor C59 and then grounded.

[0052] The VDDA terminal of the ARM chip is connected in series with a capacitor C58 and then grounded, and the VDDA terminal of the ARM chip is connected to a positive power supply II.

[0053] The VSS-1 terminal, the VSS-2 terminal, the VSS-3 terminal, the VSS-4 terminal, the VSS-5 terminal, and the VSSA terminal of the ARM chip are grounded.

[0054] The NRST terminal of the ARM chip is connected in series with a resistor R78 and then connected to a positive power supply II.

[0055] The BOOT0 terminal of the ARM chip is connected in series with a resistor R79 and then grounded.

[0056] The OSC-IN terminal of the ARM chip is connected in series with a resistor R80 and then connected to the OSC-OUT terminal of the ARM chip.

[0057] The OSC-IN terminal of the ARM chip is connected in series with the crystal oscillator Y1 and then connected to the OSC-OUT terminal of the ARM chip.

[0058] The OSC-IN terminal of the ARM chip is connected in series with a capacitor C66 and then grounded.

[0059] The OSC-OUT terminal of the ARM chip is connected in series with a capacitor C68 and then grounded.

[0060] Furthermore, the positive power supply II is a positive 3.3V power supply, and the positive power supply III is a positive 3V power supply.

[0061] Furthermore, the data processing circuit module is connected to the high-speed gear switching circuit module via a GPIO bus.

[0062] The data processing circuit module is connected to the current acquisition circuit module through an analog quantity acquisition channel.

[0063] The data processing circuit module is connected to the data sending circuit module via an SPI bus.

[0064] Furthermore, the data transmission circuit module uses the U18 chip, and the circuit topology of the data transmission circuit module is as follows:

[0065] The TXN port of the U18 chip is connected to the TXN terminal, and the TXP port of the U18 chip is connected to the TXP terminal.

[0066] The RXN port of the U18 chip is connected to the RXN terminal, and the RXP port of the U18 chip is connected to the RXP terminal.

[0067] All AGND terminals of the U18 chip are grounded, and all AVDD terminals of the U18 chip are connected to the positive power supply IV.

[0068] The EXRES1 terminal of the U18 chip is connected in series with a resistor R73 and then grounded.

[0069] The TOCAP terminal of the U18 chip is connected in series with a capacitor C55 and then grounded.

[0070] The 1V20 terminal of the U18 chip is connected in series with a capacitor C56 and then grounded.

[0071] The RSVD terminal of the U18 chip is connected in series with a resistor R77 and then grounded.

[0072] The LINKLED port of the U18 chip is connected to the LINKLED terminal, and the ACTLED port of the U18 chip is connected to the ACTLED terminal.

[0073] The VDD terminal of the U18 chip is connected to the positive power supply II, and the GND terminal of the U18 chip is grounded.

[0074] The VDD terminal of the U18 chip is connected in series with a capacitor C57 and then connected to the GND terminal of the U18 chip.

[0075] The CLKIN port of the U18 chip is connected to the XI terminal, and the XO port of the U18 chip is connected to the XO terminal.

[0076] The XI terminal is connected in series with a resistor R83 and then connected to the XO terminal.

[0077] The XI terminal is connected in series with the crystal oscillator Y2 and then connected to the XO terminal.

[0078] The XI terminal is connected in series with a capacitor C72 and then grounded.

[0079] The XO terminal is connected in series with a capacitor C67 and then grounded.

[0080] The MOSI port of the U18 chip is connected to the SPI_MOSI terminal, the MISO port of the U18 chip is connected to the SPI_MISO terminal, and the SCLK port of the U18 chip is connected to the SPI_CLK terminal.

[0081] The SCSN port of the U18 chip is connected to the SPI_CS terminal, and the SCSN terminal of the U18 chip is connected in series with a resistor R76 and then connected to the positive power supply II.

[0082] The INTN port of the U18 chip is connected to the / INT terminal, and the INTN terminal of the U18 chip is connected in series with a resistor R75 and then connected to the positive power supply II.

[0083] The RSTN port of the U18 chip is connected to the / RST terminal, and the RSTN terminal of the U18 chip is connected in series with a resistor R74 and then connected to the positive power supply II.

[0084] All RSVD terminals of the U18 chip are connected in series with a resistor and then grounded.

[0085] The PWOD0 terminal of the U18 chip is connected in series with a resistor R82 and then connected to the positive power supply II.

[0086] The PWOD1 terminal of the U18 chip is connected in series with a resistor R85 and then connected to the positive power supply II.

[0087] The PWOD2 terminal of the U18 chip is connected in series with a resistor R87 and then connected to the positive power supply II.

[0088] The positive power supply II is connected in series with a capacitor C69 and then grounded.

[0089] The positive power supply II is connected in series with the inductor L4 and then connected to the positive power supply IV.

[0090] The positive power supply IV is connected in series with a capacitor C70 and then grounded.

[0091] The positive power supply IV is connected in series with a capacitor C71 and then grounded.

[0092] The positive power supply II is a positive 3.3V power supply, and the positive power supply IV is a positive 3.3V_A power supply.

[0093] Furthermore, the data transmission bus mode of the data transmission circuit module is Ethernet.

[0094] The data transmission speed of the data transmission circuit module is greater than 25Mhz.

[0095] The technical benefits of this invention are undeniable. This high-speed shifting, wide-range current acquisition module achieves wide-range, multi-gear, high-speed shifting through innovative designs such as the parallel connection of multiple current sampling circuits with different ranges, a high-speed MOS switch, and a differential filter amplifier circuit. Furthermore, the addition of filtering circuits, data processing, and transient high-current protection further enhances the circuit's anti-interference capability, accuracy, and safety. This invention has broad application prospects and significant practical value.

[0096] The beneficial effects of the present invention are as follows:

[0097] 1) High-speed shift measurement is achieved by controlling the switching of multiple shunt resistors through high-speed MOS switches;

[0098] 2) Multiple shunt resistors are used to measure current values ​​of different ranges, thus achieving wide-range measurement;

[0099] 3) The data processing module integrates, processes and transmits the data of the acquisition module to realize real-time acquisition, processing and transmission of the collected data.

[0100] 4) It can achieve accurate measurement of large current and micro current (1uA-50A). BRIEF DESCRIPTION OF THE DRAWINGS

[0101] Figure 1 This is a physical picture of the high-speed shift wide-range current acquisition module;

[0102] Figure 2 This is the circuit schematic diagram of the high-speed gear shift module;

[0103] Figure 3 This is the circuit schematic diagram of the current acquisition module;

[0104] Figure 4 This is the circuit schematic diagram of the data processing module;

[0105] Figure 5 This is the circuit schematic diagram of the data sending module. DETAILED DESCRIPTION

[0106] The present invention will be further described below with reference to the following examples, but it should not be understood that the scope of the present invention is limited to the following examples. Without departing from the above technical ideas of the present invention, various substitutions and modifications can be made according to common technical knowledge and customary means in the art, and all should be included in the scope of protection of the present invention.

[0107] Example 1:

[0108] See also Figures 1 to 5 A high-speed shifting wide-range current acquisition module includes: a high-speed shifting circuit module, a current acquisition circuit module, a data processing circuit module, and a data sending circuit module.

[0109] The high-speed gear switching circuit module is electrically connected to the current acquisition circuit module to switch the gear range of the current acquisition circuit module.

[0110] The current acquisition circuit module is used to acquire current signals.

[0111] The data processing circuit module is electrically connected to the current acquisition circuit module and is used to convert the acquired current signal to obtain converted data.

[0112] The data sending circuit module is electrically connected to the data processing circuit module and is used to transmit the converted data to the computer.

[0113] Example 2:

[0114] A high-speed shifting wide-range current acquisition module. The main technical content is shown in Example 1. Furthermore, the circuit topology of the high-speed shifting circuit module is as follows:

[0115] The current input port is referred to as BAT_IN, and the current output port is referred to as BAT_OUT.

[0116] The BAT_IN terminal is connected to the BAT_OUT terminal after being connected in series with resistors R6 and R23.

[0117] The BAT_IN terminal is connected in series with a resistor R6 and then connected to the drain of the switch tube T2 , and the source of the switch tube T2 is connected to the BAT_OUT terminal.

[0118] Example 3:

[0119] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 1 to 2. Furthermore, the switch tube T2 is a MOSFET switch, and the gate of the switch tube T2 is suspended.

[0120] Example 4:

[0121] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Embodiments 1 to 3. Furthermore, the circuit topology of the current acquisition circuit module is as follows:

[0122] The BAT_IN terminal is connected in series with a resistor R1 and then connected to the VIN+ terminal of the operational amplifier U3. The VIN+ terminal of the operational amplifier U3 is connected in series with a capacitor C9 and then grounded.

[0123] The BAT_IN terminal is connected in series with resistors R6 and R9 in sequence and then connected to the VIN-terminal of the operational amplifier U3. The VIN-terminal of the operational amplifier U3 is connected in series with a capacitor C14 and then grounded.

[0124] The two RG ports of the operational amplifier U3 are connected in series via a resistor R7.

[0125] The V+ terminal of the operational amplifier U3 is connected to a positive power supply I, and the V- terminal of the operational amplifier U3 is connected to a negative power supply I.

[0126] The V+ terminal of the operational amplifier U3 is connected to the capacitor C6 and then to ground, and the V- terminal of the operational amplifier U3 is connected to the capacitor C8 and then to ground.

[0127] The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and a capacitor C15 and then grounded.

[0128] The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and then connected to the ADC_50A terminal.

[0129] The REF terminal of the operational amplifier U3 is grounded.

[0130] The BAT_IN terminal is connected in series with resistors R6 and R20 in sequence and then connected to the VIN+ terminal of the operational amplifier U9. The VIN+ terminal of the operational amplifier U9 is connected in series with capacitor C25 and then grounded.

[0131] The BAT_OUT terminal is connected in series with a resistor R26 and then connected to the VIN-terminal of the operational amplifier U9. The VIN-terminal of the operational amplifier U9 is connected in series with a capacitor C30 and then grounded.

[0132] The two RG ports of the operational amplifier U9 are connected in series via a resistor R24.

[0133] The V+ terminal of the operational amplifier U9 is connected to a positive power supply I, and the V- terminal of the operational amplifier U9 is connected to a negative power supply I.

[0134] The V+ terminal of the operational amplifier U9 is connected to the capacitor C22 and then grounded, and the V- terminal of the operational amplifier U9 is connected to the capacitor C24 and then grounded.

[0135] The VOUT terminal of the operational amplifier U9 is connected in series with a resistor R25 and a capacitor C31 and then grounded.

[0136] The VOUT terminal of the operational amplifier U9 is connected in series with a resistor R25 and then connected to the ADC_100mA terminal.

[0137] The REF terminal of the operational amplifier U9 is grounded.

[0138] The positive power supply I is a positive 5V power supply, and the negative power supply I is a negative 5V power supply.

[0139] Example 5:

[0140] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 1 to 4. Furthermore, the frequency of the current acquisition circuit module is greater than 100KHz.

[0141] Example 6:

[0142] A high-speed shifting wide-range current acquisition module, the main technical content of which is as described in any one of Embodiments 1 to 5. Furthermore, the data processing circuit module uses an ARM chip, and the circuit topology of the data processing circuit module is as follows:

[0143] The PA0 terminal of the ARM chip is connected to the 100mA_GateOut terminal.

[0144] The PA3 terminal of the ARM chip is connected to the ControlSw_100mA terminal.

[0145] The PA5 terminal of the ARM chip is connected to the ADC_100mA terminal.

[0146] The PA7 terminal of the ARM chip is connected to the ADC_50A terminal.

[0147] The PD0 terminal of the ARM chip is connected to the / INT terminal.

[0148] The PD1 terminal of the ARM chip is connected to the / RST terminal.

[0149] The PD2 terminal of the ARM chip is connected to the / SPI_CS terminal.

[0150] The PC10 terminal of the ARM chip is connected to the SPI_CLK terminal.

[0151] The PC11 terminal of the ARM chip is connected to the SPI_MISO terminal.

[0152] The PC12 terminal of the ARM chip is connected to the SPI_MOSI terminal.

[0153] The VBAT terminal of the ARM chip is connected in series with a capacitor C58 and then grounded, and the VBAT terminal of the ARM chip is connected to a positive power supply II.

[0154] The VDD-1 terminal of the ARM chip is connected in series with a capacitor C65 and then grounded, and the VDD-1 terminal of the ARM chip is connected to a positive power supply II.

[0155] The VDD-2 terminal of the ARM chip is connected in series with a capacitor C64 and then grounded, and the VDD-2 terminal of the ARM chip is connected to a positive power supply II.

[0156] The VDD-3 terminal of the ARM chip is connected in series with a capacitor C63 and then grounded, and the VDD-3 terminal of the ARM chip is connected to a positive power supply II.

[0157] The VDD-4 terminal of the ARM chip is connected in series with a capacitor C62 and then grounded, and the VDD-4 terminal of the ARM chip is connected to a positive power supply II.

[0158] The VDD-5 terminal of the ARM chip is connected in series with a capacitor C61 and then grounded, and the VDD-5 terminal of the ARM chip is connected to a positive power supply II.

[0159] The VREF+ terminal of the ARM chip is connected in series with a capacitor C60 and then grounded, and the VREF+ terminal of the ARM chip is connected to a positive power supply III.

[0160] The VREF+ terminal of the ARM chip is connected in series with a capacitor C59 and then grounded.

[0161] The VDDA terminal of the ARM chip is connected in series with a capacitor C58 and then grounded, and the VDDA terminal of the ARM chip is connected to a positive power supply II.

[0162] The VSS-1 terminal, the VSS-2 terminal, the VSS-3 terminal, the VSS-4 terminal, the VSS-5 terminal, and the VSSA terminal of the ARM chip are grounded.

[0163] The NRST terminal of the ARM chip is connected in series with a resistor R78 and then connected to a positive power supply II.

[0164] The BOOT0 terminal of the ARM chip is connected in series with a resistor R79 and then grounded.

[0165] The OSC-IN terminal of the ARM chip is connected in series with a resistor R80 and then connected to the OSC-OUT terminal of the ARM chip.

[0166] The OSC-IN terminal of the ARM chip is connected in series with the crystal oscillator Y1 and then connected to the OSC-OUT terminal of the ARM chip.

[0167] The OSC-IN terminal of the ARM chip is connected in series with a capacitor C66 and then grounded.

[0168] The OSC-OUT terminal of the ARM chip is connected in series with a capacitor C68 and then grounded.

[0169] Example 7:

[0170] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 1 to 6. Furthermore, the positive power supply II is a positive 3.3V power supply, and the positive power supply III is a positive 3V power supply.

[0171] Example 8:

[0172] A high-speed gear shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 1 to 7. Furthermore, the data processing circuit module is connected to the high-speed gear switching circuit module via a GPIO bus.

[0173] The data processing circuit module is connected to the current acquisition circuit module through an analog quantity acquisition channel.

[0174] The data processing circuit module is connected to the data sending circuit module via an SPI bus.

[0175] Example 9:

[0176] A high-speed shifting wide-range current acquisition module, the main technical content of which is as described in any one of Embodiments 1 to 8. Furthermore, the data transmission circuit module uses a U18 chip, and the circuit topology of the data transmission circuit module is as follows:

[0177] The TXN port of the U18 chip is connected to the TXN terminal, and the TXP port of the U18 chip is connected to the TXP terminal.

[0178] The RXN port of the U18 chip is connected to the RXN terminal, and the RXP port of the U18 chip is connected to the RXP terminal.

[0179] All AGND terminals of the U18 chip are grounded, and all AVDD terminals of the U18 chip are connected to the positive power supply IV.

[0180] The EXRES1 terminal of the U18 chip is connected in series with a resistor R73 and then grounded.

[0181] The TOCAP terminal of the U18 chip is connected in series with a capacitor C55 and then grounded.

[0182] The 1V20 terminal of the U18 chip is connected in series with a capacitor C56 and then grounded.

[0183] The RSVD terminal of the U18 chip is connected in series with a resistor R77 and then grounded.

[0184] The LINKLED port of the U18 chip is connected to the LINKLED terminal, and the ACTLED port of the U18 chip is connected to the ACTLED terminal.

[0185] The VDD terminal of the U18 chip is connected to the positive power supply II, and the GND terminal of the U18 chip is grounded.

[0186] The VDD terminal of the U18 chip is connected in series with a capacitor C57 and then connected to the GND terminal of the U18 chip.

[0187] The CLKIN port of the U18 chip is connected to the XI terminal, and the XO port of the U18 chip is connected to the XO terminal.

[0188] The XI terminal is connected in series with a resistor R83 and then connected to the XO terminal.

[0189] The XI terminal is connected in series with the crystal oscillator Y2 and then connected to the XO terminal.

[0190] The XI terminal is connected in series with a capacitor C72 and then grounded.

[0191] The XO terminal is connected in series with a capacitor C67 and then grounded.

[0192] The MOSI port of the U18 chip is connected to the SPI_MOSI terminal, the MISO port of the U18 chip is connected to the SPI_MISO terminal, and the SCLK port of the U18 chip is connected to the SPI_CLK terminal.

[0193] The SCSN port of the U18 chip is connected to the SPI_CS terminal, and the SCSN terminal of the U18 chip is connected in series with a resistor R76 and then connected to the positive power supply II.

[0194] The INTN port of the U18 chip is connected to the / INT terminal, and the INTN terminal of the U18 chip is connected in series with a resistor R75 and then connected to the positive power supply II.

[0195] The RSTN port of the U18 chip is connected to the / RST terminal, and the RSTN terminal of the U18 chip is connected in series with a resistor R74 and then connected to the positive power supply II.

[0196] All RSVD terminals of the U18 chip are connected in series with a resistor and then grounded.

[0197] The PWOD0 terminal of the U18 chip is connected in series with a resistor R82 and then connected to the positive power supply II.

[0198] The PWOD1 terminal of the U18 chip is connected in series with a resistor R85 and then connected to the positive power supply II.

[0199] The PWOD2 terminal of the U18 chip is connected in series with a resistor R87 and then connected to the positive power supply II.

[0200] The positive power supply II is connected in series with a capacitor C69 and then grounded.

[0201] The positive power supply II is connected in series with the inductor L4 and then connected to the positive power supply IV.

[0202] The positive power supply IV is connected in series with a capacitor C70 and then grounded.

[0203] The positive power supply IV is connected in series with a capacitor C71 and then grounded.

[0204] The positive power supply II is a positive 3.3V power supply, and the positive power supply IV is a positive 3.3V_A power supply.

[0205] Example 10:

[0206] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 1 to 9. Furthermore, the data transmission bus mode of the data transmission circuit module is Ethernet.

[0207] The data transmission speed of the data transmission circuit module is greater than 25Mhz.

[0208] Example 11:

[0209] See also Figures 1 to 5 A high-speed shifting wide-range current acquisition module includes: a high-speed shifting circuit module, a current acquisition circuit module, a data processing circuit module, and a data sending circuit module.

[0210] The high-speed gear switching circuit module is electrically connected to the current acquisition circuit module to switch the gear range of the current acquisition circuit module.

[0211] The current acquisition circuit module is used to acquire current signals.

[0212] The data processing circuit module is electrically connected to the current acquisition circuit module and is used to convert the acquired current signal to obtain converted data.

[0213] The data processing circuit module first converts the collected ADC value into voltage data, then converts the voltage data into current data through the voltage-current conversion ratio, and finally obtains the converted data;

[0214] The data sending circuit module is electrically connected to the data processing circuit module and is used to transmit the converted data to the computer.

[0215] Example 12:

[0216] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in Example 11. Furthermore, the circuit topology of the high-speed shifting circuit module is as follows:

[0217] The current input port is referred to as BAT_IN, and the current output port is referred to as BAT_OUT.

[0218] The BAT_IN terminal is connected to the BAT_OUT terminal after being connected in series with resistors R6 and R23.

[0219] The BAT_IN terminal is connected in series with a resistor R6 and then connected to the drain of the switch tube T2 , and the source of the switch tube T2 is connected to the BAT_OUT terminal.

[0220] Example 13:

[0221] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 11 to 12. Furthermore, the switch tube T2 is a MOSFET switch, and the gate of the switch tube T2 is suspended.

[0222] The switch tube T2 is a MOSFET switch, and the switching speed of the switch tube T2 reaches 100ns, achieving high-speed switching.

[0223] Example 14:

[0224] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 11 to 13. Furthermore, a filtering circuit is added to the current acquisition circuit module to improve the anti-interference ability of the current acquisition circuit and the accuracy of the output results.

[0225] The filter circuit includes a differential filter circuit at the input end and a low-pass filter circuit at the output end.

[0226] The interference signal in the measurement circuit can be filtered out by the differential filter circuit at the input end and the low-pass filter at the output end, further improving the accuracy and stability of the current acquisition circuit.

[0227] The differential amplifier circuit receives the analog signal output by the parallel current sampling circuit, filters out the interference signal in the line through the filter circuit, and then amplifies the sampling signal in different proportions through the differential amplifier circuit. After further amplification, the sampling signal passes through the low-pass filter circuit and is output to the data processing module circuit, that is, the signal sampling port of the RAM.

[0228] The circuit topology of the current acquisition circuit module is as follows:

[0229] The BAT_IN terminal is connected in series with a resistor R1 and then connected to the VIN+ terminal of the operational amplifier U3. The VIN+ terminal of the operational amplifier U3 is connected in series with a capacitor C9 and then grounded.

[0230] The BAT_IN terminal is connected in series with resistors R6 and R9 in sequence and then connected to the VIN-terminal of the operational amplifier U3. The VIN-terminal of the operational amplifier U3 is connected in series with a capacitor C14 and then grounded.

[0231] The two RG ports of the operational amplifier U3 are connected in series via a resistor R7.

[0232] The V+ terminal of the operational amplifier U3 is connected to a positive power supply I, and the V- terminal of the operational amplifier U3 is connected to a negative power supply I.

[0233] The V+ terminal of the operational amplifier U3 is connected to the capacitor C6 and then to ground, and the V- terminal of the operational amplifier U3 is connected to the capacitor C8 and then to ground.

[0234] The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and a capacitor C15 and then grounded.

[0235] The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and then connected to the ADC_50A terminal.

[0236] The REF terminal of the operational amplifier U3 is grounded.

[0237] The BAT_IN terminal is connected in series with resistors R6 and R20 in sequence and then connected to the VIN+ terminal of the operational amplifier U9. The VIN+ terminal of the operational amplifier U9 is connected in series with capacitor C25 and then grounded.

[0238] The BAT_OUT terminal is connected in series with a resistor R26 and then connected to the VIN-terminal of the operational amplifier U9. The VIN-terminal of the operational amplifier U9 is connected in series with a capacitor C30 and then grounded.

[0239] The two RG ports of the operational amplifier U9 are connected in series via a resistor R24.

[0240] The V+ terminal of the operational amplifier U9 is connected to a positive power supply I, and the V- terminal of the operational amplifier U9 is connected to a negative power supply I.

[0241] The V+ terminal of the operational amplifier U9 is connected to the capacitor C22 and then grounded, and the V- terminal of the operational amplifier U9 is connected to the capacitor C24 and then grounded.

[0242] The VOUT terminal of the operational amplifier U9 is connected in series with a resistor R25 and a capacitor C31 and then grounded.

[0243] The VOUT terminal of the operational amplifier U9 is connected in series with a resistor R25 and then connected to the ADC_100mA terminal.

[0244] The REF terminal of the operational amplifier U9 is grounded.

[0245] The positive power supply I is a positive 5V power supply, and the negative power supply I is a negative 5V power supply.

[0246] Example 15:

[0247] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 11 to 14. Furthermore, the frequency of the current acquisition circuit module is greater than 100KHz.

[0248] Example 16:

[0249] A high-speed shifting wide-range current acquisition module, the main technical content of which is as described in any one of Examples 11 to 15. Furthermore, the data processing circuit module uses an ARM chip, and the circuit topology of the data processing circuit module is as follows:

[0250] The PA0 terminal of the ARM chip is connected to the 100mA_GateOut terminal.

[0251] The PA3 terminal of the ARM chip is connected to the ControlSw_100mA terminal.

[0252] The PA5 terminal of the ARM chip is connected to the ADC_100mA terminal.

[0253] The PA7 terminal of the ARM chip is connected to the ADC_50A terminal.

[0254] The PD0 terminal of the ARM chip is connected to the / INT terminal.

[0255] The PD1 terminal of the ARM chip is connected to the / RST terminal.

[0256] The PD2 terminal of the ARM chip is connected to the / SPI_CS terminal.

[0257] The PC10 terminal of the ARM chip is connected to the SPI_CLK terminal.

[0258] The PC11 terminal of the ARM chip is connected to the SPI_MISO terminal.

[0259] The PC12 terminal of the ARM chip is connected to the SPI_MOSI terminal.

[0260] The VBAT terminal of the ARM chip is connected in series with a capacitor C58 and then grounded, and the VBAT terminal of the ARM chip is connected to a positive power supply II.

[0261] The VDD-1 terminal of the ARM chip is connected in series with a capacitor C65 and then grounded, and the VDD-1 terminal of the ARM chip is connected to a positive power supply II.

[0262] The VDD-2 terminal of the ARM chip is connected in series with a capacitor C64 and then grounded, and the VDD-2 terminal of the ARM chip is connected to a positive power supply II.

[0263] The VDD-3 terminal of the ARM chip is connected in series with a capacitor C63 and then grounded, and the VDD-3 terminal of the ARM chip is connected to a positive power supply II.

[0264] The VDD-4 terminal of the ARM chip is connected in series with a capacitor C62 and then grounded, and the VDD-4 terminal of the ARM chip is connected to a positive power supply II.

[0265] The VDD-5 terminal of the ARM chip is connected in series with a capacitor C61 and then grounded, and the VDD-5 terminal of the ARM chip is connected to a positive power supply II.

[0266] The VREF+ terminal of the ARM chip is connected in series with a capacitor C60 and then grounded, and the VREF+ terminal of the ARM chip is connected to a positive power supply III.

[0267] The VREF+ terminal of the ARM chip is connected in series with a capacitor C59 and then grounded.

[0268] The VDDA terminal of the ARM chip is connected in series with a capacitor C58 and then grounded, and the VDDA terminal of the ARM chip is connected to a positive power supply II.

[0269] The VSS-1 terminal, the VSS-2 terminal, the VSS-3 terminal, the VSS-4 terminal, the VSS-5 terminal, and the VSSA terminal of the ARM chip are grounded.

[0270] The NRST terminal of the ARM chip is connected in series with a resistor R78 and then connected to a positive power supply II.

[0271] The BOOT0 terminal of the ARM chip is connected in series with a resistor R79 and then grounded.

[0272] The OSC-IN terminal of the ARM chip is connected in series with a resistor R80 and then connected to the OSC-OUT terminal of the ARM chip.

[0273] The OSC-IN terminal of the ARM chip is connected in series with the crystal oscillator Y1 and then connected to the OSC-OUT terminal of the ARM chip.

[0274] The OSC-IN terminal of the ARM chip is connected in series with a capacitor C66 and then grounded.

[0275] The OSC-OUT terminal of the ARM chip is connected in series with a capacitor C68 and then grounded.

[0276] Example 17:

[0277] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 11 to 16. Furthermore, the positive power supply II is a positive 3.3V power supply, and the positive power supply III is a positive 3V power supply.

[0278] Example 18:

[0279] A high-speed gear shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 11 to 17. Furthermore, the data processing circuit module is connected to the high-speed gear switching circuit module via a GPIO bus.

[0280] The data processing circuit module is connected to the current acquisition circuit module through an analog quantity acquisition channel.

[0281] The data processing circuit module is connected to the data sending circuit module via an SPI bus.

[0282] Example 19:

[0283] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Embodiments 11 to 18. Furthermore, the data transmission circuit module uses a U18 chip, and the circuit topology of the data transmission circuit module is as follows:

[0284] The TXN port of the U18 chip is connected to the TXN terminal, and the TXP port of the U18 chip is connected to the TXP terminal.

[0285] The RXN port of the U18 chip is connected to the RXN terminal, and the RXP port of the U18 chip is connected to the RXP terminal.

[0286] All AGND terminals of the U18 chip are grounded, and all AVDD terminals of the U18 chip are connected to the positive power supply IV.

[0287] The EXRES1 terminal of the U18 chip is connected in series with a resistor R73 and then grounded.

[0288] The TOCAP terminal of the U18 chip is connected in series with a capacitor C55 and then grounded.

[0289] The 1V20 terminal of the U18 chip is connected in series with a capacitor C56 and then grounded.

[0290] The RSVD terminal of the U18 chip is connected in series with a resistor R77 and then grounded.

[0291] The LINKLED port of the U18 chip is connected to the LINKLED terminal, and the ACTLED port of the U18 chip is connected to the ACTLED terminal.

[0292] The VDD terminal of the U18 chip is connected to the positive power supply II, and the GND terminal of the U18 chip is grounded.

[0293] The VDD terminal of the U18 chip is connected in series with a capacitor C57 and then connected to the GND terminal of the U18 chip.

[0294] The CLKIN port of the U18 chip is connected to the XI terminal, and the XO port of the U18 chip is connected to the XO terminal.

[0295] The XI terminal is connected in series with a resistor R83 and then connected to the XO terminal.

[0296] The XI terminal is connected in series with the crystal oscillator Y2 and then connected to the XO terminal.

[0297] The XI terminal is connected in series with a capacitor C72 and then grounded.

[0298] The XO terminal is connected in series with a capacitor C67 and then grounded.

[0299] The MOSI port of the U18 chip is connected to the SPI_MOSI terminal, the MISO port of the U18 chip is connected to the SPI_MISO terminal, and the SCLK port of the U18 chip is connected to the SPI_CLK terminal.

[0300] The SCSN port of the U18 chip is connected to the SPI_CS terminal, and the SCSN terminal of the U18 chip is connected in series with a resistor R76 and then connected to the positive power supply II.

[0301] The INTN port of the U18 chip is connected to the / INT terminal, and the INTN terminal of the U18 chip is connected in series with a resistor R75 and then connected to the positive power supply II.

[0302] The RSTN port of the U18 chip is connected to the / RST terminal, and the RSTN terminal of the U18 chip is connected in series with a resistor R74 and then connected to the positive power supply II.

[0303] All RSVD terminals of the U18 chip are connected in series with a resistor and then grounded.

[0304] The PWOD0 terminal of the U18 chip is connected in series with a resistor R82 and then connected to the positive power supply II.

[0305] The PWOD1 terminal of the U18 chip is connected in series with a resistor R85 and then connected to the positive power supply II.

[0306] The PWOD2 terminal of the U18 chip is connected in series with a resistor R87 and then connected to the positive power supply II.

[0307] The positive power supply II is connected in series with a capacitor C69 and then grounded.

[0308] The positive power supply II is connected in series with the inductor L4 and then connected to the positive power supply IV.

[0309] The positive power supply IV is connected in series with a capacitor C70 and then grounded.

[0310] The positive power supply IV is connected in series with a capacitor C71 and then grounded.

[0311] The positive power supply II is a positive 3.3V power supply, and the positive power supply IV is a positive 3.3V_A power supply.

[0312] Example 20:

[0313] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in any one of Examples 11 to 19. Furthermore, the data transmission bus mode of the data transmission circuit module is Ethernet.

[0314] The data transmission speed of the data transmission circuit module is greater than 25Mhz.

[0315] Example 21:

[0316] See also Figures 1 to 5 A high-speed shifting wide-range current acquisition module includes: a high-speed shifting circuit module, a current acquisition circuit module, a data processing circuit module, and a data sending circuit module.

[0317] The high-speed gear switching circuit module is electrically connected to the current acquisition circuit module to switch the gear range of the current acquisition circuit module.

[0318] The current acquisition circuit module is electrically connected to the data processing circuit module to transmit the current signal to the data processing module.

[0319] The data processing circuit module is electrically connected to the data sending circuit module to transmit the processed data to the computer.

[0320] The high-speed shifting circuit topology is shown below:

[0321] The current input port BAT_IN is connected in series with resistors R6 and R23 and then output from the current output port BAT_OUT. Pins 2 and 3 of the high-speed MOS switch T2 are connected to both ends of the resistor R23 respectively.

[0322] The high-speed MOS switch T2 is FDB86363-F085, and its high-speed switching speed can reach within 231ns.

[0323] The current acquisition circuit topology is shown below:

[0324] The current input port BAT_IN is connected in series with resistors R6 and R23 and then output from the current output port BAT_OUT.

[0325] Resistors R1 and R9 are connected to both ends of resistor R6 respectively. One end pin of capacitor C9 and capacitor C14 are connected to resistor R1 and resistor R9 respectively and then connected to pins 2 and 3 of op amp U3. The other end pin of capacitor C9 and capacitor C14 are connected to GND.

[0326] Resistors R20 and R26 are connected to both ends of resistor R23 respectively. One end pin of capacitor C25 and capacitor C30 are connected to resistor R20 and resistor R26 respectively and then connected to pins 2 and 3 of op amp U9. The other end pin of capacitor C25 and capacitor C30 are connected to GND.

[0327] One end of capacitor C6 is connected to pin 7 of op amp U3 and an external positive 5V power supply, and the other end is connected to power supply GND.

[0328] One end of capacitor C8 is connected to pin 4 of op amp U3 and an external negative 5V power supply, and the other end is connected to power supply GND.

[0329] One end of capacitor C22 is connected to pin 7 of op amp U9 and an external positive 5V power supply, and the other end is connected to the power supply GND.

[0330] One end of capacitor C24 is connected to pin 4 of op amp U9 and an external negative 5V power supply, and the other end is connected to power supply GND.

[0331] Resistor R7 is connected to pin 1 and pin 8 of op amp U3 respectively.

[0332] Resistor R24 ​​is connected to pin 1 and pin 8 of op amp U9 respectively.

[0333] One end of resistor R8 is connected to pin 6 of op amp U3, and the other end is connected to capacitor C15 and ADC_50A terminal. The other end of the capacitor is connected to the power supply GND.

[0334] One end of resistor R24 ​​is connected to pin 6 of op amp U9, and the other end is connected to capacitor C31 and ADC_100mA terminal. The other end of the capacitor is connected to power supply GND.

[0335] The data processing circuit topology is shown below:

[0336] Connect terminal 22 of the ARM chip to the 100mA_GateOut terminal.

[0337] Connect terminal 25 of the ARM chip to the ControlSw_100mA terminal.

[0338] Connect terminal 29 of the ARM chip to the ADC_100mA terminal.

[0339] Connect terminal 31 of the ARM chip to the ADC_50A terminal.

[0340] Terminal 81 of the ARM chip is connected to the / INT terminal.

[0341] Terminal 82 of the ARM chip is connected to the / RST terminal.

[0342] Connect terminal 83 of the ARM chip to the / SPI_CS terminal.

[0343] Connect terminal 78 of the ARM chip to the SPI_CLK terminal.

[0344] Connect terminal 79 of the ARM chip to the SPI_MISO terminal.

[0345] Connect terminal 80 of the ARM chip to the SPI_MOSI terminal.

[0346] Terminal 6 of the ARM chip is connected in series with capacitor C58 and then grounded.

[0347] Terminal 50 of the ARM chip is connected in series with capacitor C65 and then grounded.

[0348] Terminal 75 of the ARM chip is connected in series with capacitor C64 and then grounded.

[0349] Terminal 100 of the ARM chip is connected in series with capacitor C63 and then grounded.

[0350] Terminal 27 of the ARM chip is connected in series with capacitor C62 and then grounded.

[0351] Terminal 11 of the ARM chip is connected in series with capacitor C61 and then grounded.

[0352] Terminal 20 of the ARM chip is connected in series with capacitors C59 and C60 and then grounded.

[0353] Terminal 51 of the ARM chip is connected in series with capacitor C58 and then grounded.

[0354] Connect terminals 6, 50, 75, 100, 27, 11, 20, and 21 of the ARM chip to 3.3V_A.

[0355] Terminals 10, 74, 99, 26, 49, and 19 of the ARM chip are grounded.

[0356] Connect terminal 14 of the ARM chip to resistor R78 and then to positive 3.3V.

[0357] Terminal 94 of the ARM chip is connected to resistor R79 and then grounded.

[0358] Connect resistor R80 and crystal oscillator Y1 between terminals 12 and 13 of the ARM chip, and then connect capacitors C66 and C68 respectively, and then ground.

[0359] The ARM chip model is STM32H750VB, and the frequency is greater than 480MHz.

[0360] The crystal oscillator frequency is 8 MHz.

[0361] The data processing module is connected to the high-speed shifting module via a GPIO bus.

[0362] The data processing module is connected to the current measurement module through an analog quantity acquisition channel.

[0363] The data processing module is connected to the data sending module via the SPI bus.

[0364] The current measurement module includes a measurement circuit with two-speed high-speed switching to achieve two-speed high-speed shifting and wide-range current acquisition.

[0365] The frequency of the current measurement module is greater than 100 KHz.

[0366] The data transmission circuit topology is shown below:

[0367] Pin 1 of the U18 chip is connected to the TXN terminal.

[0368] Pin 2 of the U18 chip is connected to the TXP terminal.

[0369] Connect pin 5 of the U18 chip to the RXN terminal.

[0370] Pin 6 of the U18 chip is connected to the RXP terminal.

[0371] Pin 37 of the U18 chip is connected to resistor R74 and then to the / RST terminal, and the other end of resistor R74 is connected to positive 3.3V.

[0372] Pin 36 of the U18 chip is connected to resistor R75 and to the / INT terminal, and the other end of resistor R75 is connected to positive 3.3V.

[0373] Pin 35 of the U18 chip is connected to the SPI_MOSI terminal.

[0374] Pin 34 of the U18 chip is connected to the SPI_MISO terminal.

[0375] Pin 33 of the U18 chip is connected to the SPI_CLK terminal.

[0376] Pin 32 of the U18 chip is connected to resistor R76 and then to the / SPI_CS terminal. The other end of resistor R76 is connected to positive 3.3V.

[0377] Pins 3, 9, 14, 16, 19, 29, and 48 of the U18 chip are grounded.

[0378] Connect pins 4, 8, 11, 15, 17, 21, and 48 of the U18 chip to 3.3V.

[0379] Pin 10 of the U18 chip is connected to resistor R73 and then to ground.

[0380] Pin 20 of the U18 chip is connected to capacitor C55 and then to ground.

[0381] Pin 22 of the U18 chip is connected to capacitor C56 and then to ground.

[0382] Pin 23 of the U18 chip is connected to resistor R77 and then to ground.

[0383] Pin 28 of the U18 chip is connected to 3.3V, and is also connected to capacitor C57 and then grounded.

[0384] Pin 38 of the U18 chip is connected to resistor R72 and then to ground.

[0385] Pin 39 of the U18 chip is connected to resistor R71 and then to ground.

[0386] Pin 40 of the U18 chip is connected to resistor R70 and then to ground.

[0387] Pin 41 of the U18 chip is connected to resistor R69 and then to ground.

[0388] Pin 42 of the U18 chip is connected to resistor R68 and then to ground.

[0389] Pin 43 of the U18 chip is connected to resistor R87 and then to positive 3.3V.

[0390] Pin 44 of the U18 chip is connected to resistor R85 and then to positive 3.3V.

[0391] Pin 45 of the U18 chip is connected to resistor R82 and then to positive 3.3V.

[0392] Resistor R83 and crystal oscillator Y2 are connected between the XO and XI terminals, and capacitors C67 and C72 are connected to ground respectively.

[0393] Positive 3.3V_A is connected to capacitors C70 and C71 and then to ground. At the same time, inductor L4 is connected between it and positive 3.3V. Positive 3.3V is connected to capacitor C69 and then to ground.

[0394] The U18 chip model mentioned is W5500.

[0395] The data transmission bus mode is Ethernet.

[0396] The data transmission speed is greater than 25Mhz.

[0397] Example 22:

[0398] A high-speed shifting wide-range current acquisition module, the main technical content of which is shown in Example 21. Furthermore, this embodiment adds a filtering circuit to improve the anti-interference ability of the current acquisition circuit and the accuracy of the output results.

[0399] The filter circuit includes a differential filter circuit at the input end and a low-pass filter circuit at the output end.

[0400] Resistors R1 and R9 are connected to both ends of resistor R6 respectively. One end pin of capacitor C9 and capacitor C14 are connected to resistor R1 and resistor R9 respectively and then connected to pins 2 and 3 of op amp U3. The other end pin of capacitor C9 and capacitor C14 are connected to GND.

[0401] Resistors R20 and R26 are connected to both ends of resistor R23 respectively. One end pin of capacitor C25 and capacitor C30 are connected to resistor R20 and resistor R26 respectively and then connected to pins 2 and 3 of op amp U9. The other end pin of capacitor C25 and capacitor C30 are connected to GND.

[0402] One end of resistor R8 is connected to pin 6 of op amp U3, and the other end is connected to capacitor C15 and then grounded.

[0403] One end of the resistor R24 ​​is connected to pin 6 of the operational amplifier U9, and the other end is connected to the capacitor C31 and then to ground.

[0404] The interference signal in the measurement circuit can be filtered out by the differential filter circuit at the input end and the low-pass filter at the output end, further improving the accuracy and stability of the current acquisition circuit.

[0405] Example 23:

[0406] A high-speed shifting, wide-range current acquisition module, the main technical content of which is described in any one of Examples 21 to 22. Furthermore, this embodiment details the implementation of sampling signal processing and high-speed MOS switch control. A differential amplifier circuit receives the analog signal output by the parallel current sampling circuit. After filtering out interference signals in the circuit through a filter circuit, the differential amplifier circuit amplifies the sampled signal at different ratios. The sampled signal is further amplified and then passes through a low-pass filter circuit before being output to the signal sampling port of the data processing module circuit, i.e., the RAM.

[0407] Pin 6 of U3 is connected to the ADC_50A terminal through resistor R8 and pin 31 of the ARM chip.

[0408] Pin 6 of U9 is connected to the ADC_100mA terminal through resistor R24 ​​and pin 29 of the ARM chip.

[0409] The current input port BAT_IN is connected in series with resistors R6 and R23 and then output from the current output port BAT_OUT. Pins 2 and 3 of the high-speed MOS switch T2 are connected to both ends of the resistor R23 respectively.

[0410] The data processing circuit processes and analyzes the current in the current loop in real time to determine the current value, thereby selectively controlling the opening and closing of the high-speed MOS switch.

[0411] In addition, this embodiment also provides specific steps for implementing current grading and high-speed MOS switch switching. For example, when the high-range gear is selected, the corresponding high-speed MOS switch is turned on, allowing a large current to flow through the large-range sampling resistor and out through the high-speed MOS switch. The electrical signals sampled by the sampling resistor are then output to the differential operational amplifier circuit for differential amplification. The low-pass filter circuit then ensures that the voltage value of the sampled signal reaching the ARM is as close as possible to the maximum voltage value that the ARM can sample. This results in a more accurate and stable current signal.

[0412] Example 24:

[0413] A high-speed shifting, wide-range current acquisition module, the main technical content of which is described in any one of Examples 21 to 23. Furthermore, this embodiment adds a transient high-current protection function based on any one of Examples 21 to 23. When the current suddenly increases during a small-range measurement, the preceding current acquisition circuit detects the high current and quickly opens a high-speed MOS switch, thereby protecting the small-range measurement circuit. This function improves the safety and reliability of the current acquisition circuit.

Claims

1. A high-speed shifting wide-range current acquisition module, characterized in that: include: High-speed gear switching circuit module, current acquisition circuit module, data processing circuit module, data sending circuit module; The high-speed gear switching circuit module is electrically connected to the current acquisition circuit module to switch the gear range of the current acquisition circuit module; The current acquisition circuit module is used to acquire current signals. The data processing circuit module is electrically connected to the current acquisition circuit module and is used to convert the acquired current signal to obtain converted data; The data sending circuit module is electrically connected to the data processing circuit module and is used to transmit the converted data to the computer.

2. The high-speed shifting wide-range current acquisition module according to claim 1, characterized in that: The circuit topology of the high-speed gear switching circuit module is as follows: The current input port is called BAT_IN, and the current output port is called BAT_OUT. The BAT_IN terminal is connected to the BAT_OUT terminal after being connected in series with resistors R6 and R23. The BAT_IN terminal is connected in series with a resistor R6 and then connected to the drain of the switch tube T2 , and the source of the switch tube T2 is connected to the BAT_OUT terminal.

3. The high-speed shifting wide-range current acquisition module according to claim 2, characterized in that: The switch tube T2 is a MOSFET switch, and the gate of the switch tube T2 is suspended.

4. The high-speed shifting wide-range current acquisition module according to claim 2, characterized in that: The circuit topology of the current acquisition circuit module is as follows: The BAT_IN terminal is connected in series with a resistor R1 and then connected to the VIN+ terminal of the operational amplifier U3. The VIN+ terminal of the operational amplifier U3 is connected in series with a capacitor C9 and then grounded. The BAT_IN terminal is connected in series with resistors R6 and R9, and then connected to the VIN- terminal of the operational amplifier U3. The VIN- terminal of the operational amplifier U3 is connected in series with capacitor C14 and then grounded. The two RG ports of the operational amplifier U3 are connected in series through a resistor R7; The V+ terminal of the operational amplifier U3 is connected to the positive power supply I, and the V- terminal of the operational amplifier U3 is connected to the negative power supply I; The V+ terminal of the operational amplifier U3 is connected to the capacitor C6 and then to ground, and the V- terminal of the operational amplifier U3 is connected to the capacitor C8 and then to ground; The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and a capacitor C15 and then grounded; The VOUT terminal of the operational amplifier U3 is connected in series with a resistor R8 and then connected to the ADC_50A terminal; The REF terminal of the operational amplifier U3 is grounded; The BAT_IN terminal is connected in series with resistors R6 and R20, and then connected to the VIN+ terminal of the operational amplifier U9. The VIN+ terminal of the operational amplifier U9 is connected in series with capacitor C25 and then grounded. The BAT_OUT terminal is connected in series with a resistor R26 and then connected to the VIN- terminal of the operational amplifier U9. The VIN- terminal of the operational amplifier U9 is connected in series with a capacitor C30 and then grounded. The two RG ports of the operational amplifier U9 are connected in series through a resistor R24; The V+ terminal of the operational amplifier U9 is connected to the positive power supply I, and the V- terminal of the operational amplifier U9 is connected to the negative power supply I; The V+ terminal of the operational amplifier U9 is connected to the capacitor C22 and then to ground, and the V- terminal of the operational amplifier U9 is connected to the capacitor C24 and then to ground; The VOUT terminal of the operational amplifier U9 is connected in series with a resistor R25 and a capacitor C31 and then grounded; The VOUT terminal of the operational amplifier U9 is connected in series with the resistor R25 and then connected to the ADC_100mA terminal; The REF terminal of the operational amplifier U9 is grounded; The positive power supply I is a positive 5V power supply, and the negative power supply I is a negative 5V power supply.

5. The high-speed shifting wide-range current acquisition module according to claim 4, characterized in that: The frequency of the current acquisition circuit module is greater than 100KHz.

6. The high-speed shifting wide-range current acquisition module according to claim 1, characterized in that: The data processing circuit module uses an ARM chip, and the circuit topology of the data processing circuit module is as follows: The PA0 terminal of the ARM chip is connected to the 100mA_GateOut terminal; The PA3 terminal of the ARM chip is connected to the ControlSw_100mA terminal; The PA5 terminal of the ARM chip is connected to the ADC_100mA terminal; The PA7 terminal of the ARM chip is connected to the ADC_50A terminal; The PD0 terminal of the ARM chip is connected to the / INT terminal; The PD1 terminal of the ARM chip is connected to the / RST terminal; The PD2 terminal of the ARM chip is connected to the / SPI_CS terminal; The PC10 terminal of the ARM chip is connected to the SPI_CLK terminal; The PC11 terminal of the ARM chip is connected to the SPI_MISO terminal; The PC12 terminal of the ARM chip is connected to the SPI_MOSI terminal; The VBAT terminal of the ARM chip is connected in series with a capacitor C58 and then grounded, and the VBAT terminal of the ARM chip is connected to a positive power supply II; The VDD-1 terminal of the ARM chip is connected in series with a capacitor C65 and then grounded, and the VDD-1 terminal of the ARM chip is connected to a positive power supply II; The VDD-2 terminal of the ARM chip is connected in series with a capacitor C64 and then grounded, and the VDD-2 terminal of the ARM chip is connected to a positive power supply II; The VDD-3 terminal of the ARM chip is connected in series with a capacitor C63 and then grounded, and the VDD-3 terminal of the ARM chip is connected to a positive power supply II; The VDD-4 terminal of the ARM chip is connected in series with a capacitor C62 and then grounded, and the VDD-4 terminal of the ARM chip is connected to a positive power supply II; The VDD-5 terminal of the ARM chip is connected in series with a capacitor C61 and then grounded, and the VDD-5 terminal of the ARM chip is connected to a positive power supply II; The VREF+ terminal of the ARM chip is connected in series with a capacitor C60 and then grounded, and the VREF+ terminal of the ARM chip is connected to a positive power supply III; The VREF+ terminal of the ARM chip is connected in series with a capacitor C59 and then grounded; The VDDA terminal of the ARM chip is connected in series with capacitor C58 and then grounded, and the VDDA terminal of the ARM chip is connected to the positive power supply II; The VSS-1, VSS-2, VSS-3, VSS-4, VSS-5 and VSSA terminals of the ARM chip are grounded; The NRST terminal of the ARM chip is connected in series with a resistor R78 and then connected to a positive power supply II; The BOOT0 terminal of the ARM chip is connected in series with a resistor R79 and then grounded; The OSC-IN terminal of the ARM chip is connected in series with a resistor R80 and then connected to the OSC-OUT terminal of the ARM chip; The OSC-IN terminal of the ARM chip is connected in series with the crystal oscillator Y1 and then connected to the OSC-OUT terminal of the ARM chip; The OSC-IN terminal of the ARM chip is connected in series with a capacitor C66 and then grounded; The OSC-OUT terminal of the ARM chip is connected in series with a capacitor C68 and then grounded.

7. The high-speed shifting wide-range current acquisition module according to claim 6, characterized in that: The positive power supply II is a positive 3.3V power supply, and the positive power supply III is a positive 3V power supply.

8. The high-speed shifting wide-range current acquisition module according to claim 1, characterized in that: The data processing circuit module is connected to the high-speed gear switching circuit module via a GPIO bus; The data processing circuit module is connected to the current acquisition circuit module through an analog acquisition channel; The data processing circuit module is connected to the data sending circuit module via an SPI bus.

9. The high-speed shifting wide-range current acquisition module according to claim 1, characterized in that: The data transmission circuit module uses the U18 chip, and the circuit topology of the data transmission circuit module is as follows: The TXN port of the U18 chip is connected to the TXN terminal, and the TXP port of the U18 chip is connected to the TXP terminal; The RXN port of the U18 chip is connected to the RXN terminal, and the RXP port of the U18 chip is connected to the RXP terminal; All AGND terminals of the U18 chip are grounded, and all AVDD terminals of the U18 chip are connected to the positive power supply IV; The EXRES1 terminal of the U18 chip is connected in series with a resistor R73 and then grounded; The TOCAP end of the U18 chip is connected in series with a capacitor C55 and then grounded; The 1V20 terminal of the U18 chip is connected in series with a capacitor C56 and then grounded; The RSVD terminal of the U18 chip is connected in series with a resistor R77 and then grounded; The LINKLED port of the U18 chip is connected to the LINKLED terminal, and the ACTLED port of the U18 chip is connected to the ACTLED terminal; The VDD terminal of the U18 chip is connected to the positive power supply II, and the GND terminal of the U18 chip is grounded; The VDD terminal of the U18 chip is connected in series with a capacitor C57 and then connected to the GND terminal of the U18 chip; The CLKIN port of the U18 chip is connected to the XI terminal, and the XO port of the U18 chip is connected to the XO terminal; The XI terminal is connected in series with a resistor R83 and then connected to the XO terminal; The XI terminal is connected in series with the crystal oscillator Y2 and then connected to the XO terminal; The XI terminal is connected in series with a capacitor C72 and then grounded; The XO terminal is connected in series with a capacitor C67 and then grounded; The MOSI port of the U18 chip is connected to the SPI_MOSI terminal, the MISO port of the U18 chip is connected to the SPI_MISO terminal, and the SCLK port of the U18 chip is connected to the SPI_CLK terminal; The SCSN port of the U18 chip is connected to the SPI_CS terminal, and the SCSN terminal of the U18 chip is connected in series with a resistor R76 and then connected to the positive power supply II; The INTN port of the U18 chip is connected to the / INT terminal, and the INTN terminal of the U18 chip is connected in series with a resistor R75 and then connected to the positive power supply II; The RSTN port of the U18 chip is connected to the / RST terminal, and the RSTN terminal of the U18 chip is connected in series with a resistor R74 and then connected to the positive power supply II; All RSVD terminals of the U18 chip are connected in series with a resistor and then grounded; The PWOD0 terminal of the U18 chip is connected in series with a resistor R82 and then connected to the positive power supply II; The PWOD1 terminal of the U18 chip is connected in series with a resistor R85 and then connected to the positive power supply II; The PWOD2 terminal of the U18 chip is connected in series with a resistor R87 and then connected to the positive power supply II; The positive power supply II is connected in series with capacitor C69 and then grounded; The positive power supply II is connected in series with the inductor L4 and then connected to the positive power supply IV; The positive power supply IV is connected in series with a capacitor C70 and then grounded; The positive power supply IV is connected in series with a capacitor C71 and then grounded; The positive power supply II is a positive 3.3V power supply, and the positive power supply IV is a positive 3.3V_A power supply.

10. The high-speed shifting wide-range current acquisition module according to claim 1, characterized in that: The data transmission bus mode of the data transmission circuit module is Ethernet; The data transmission speed of the data transmission circuit module is greater than 25Mhz.

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