Test circuit, test method, chip and electronic equipment

Abstract

The invention relates to the technical field of testing, in particular to a testing circuit, a testing method, a chip and electronic equipment. The test circuit comprises a first test point, a first matching circuit, a second matching circuit, a third matching circuit, a tested chip, a first switch, a second switch and a second test point. When a first frequency band radio frequency signal is tested, the first switch is in a first switch state, the second switch is in a second switch state, and the first test point, the first switch, the first matching circuit, the tested chip M, the second switch and the second test point are conducted to form a first test path. When a second frequency band radio frequency signal is tested, the first switch is in a third switch state, the second switch is in a fourth switch state, and the first test point, the first switch, the second matching circuit, the first matching circuit, the tested chip, the second switch, the third matching circuit and the second test point are conducted to form a second test path; the frequency of the first frequency band radio frequency signal is greater than that of the second frequency band radio frequency signal.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a testing circuit, a testing method, a chip, and an electronic device. Background Art

[0002] Low-noise amplifiers (LNAs) are an essential component of wireless communication devices and electromagnetic compatibility testing equipment. They are primarily used for pre-amplification in radio receivers, enhancing the sensitivity of received RF signals. LNA chips have the ability to adjust their operating frequency band based on external matching circuits. During mass production testing of LNA chips, such as those with dual-band operation, the chip's technical specifications are typically tested in both the high and low frequency bands, with different matching circuits required for testing in different frequency bands.

[0003] At present, the mass production test methods of LNA chips include: Figure 1A The method of the two-station test is shown. Figure 1A The first test station, Z1, is used to test high-band RF signals, while the second test station, Z2, is used to test low-band RF signals. In this testing method, both the first and second test stations, Z1 and Z2, are equipped with a complete set of test equipment. Each LNA chip must be tested at both stations, making the entire testing process relatively complex.

[0004] To simplify the complexity of the testing process, in some embodiments, the mass production testing method of the LNA chip includes some single-station testing methods. However, the test results of the existing single-station testing methods are less accurate. Summary of the Invention

[0005] To solve the above problems, the present application provides a test circuit, a test method, a chip, and an electronic device, which can reduce the complexity of the test process of the LNA chip.

[0006] In a first aspect, the present application provides a test circuit, comprising: a first test point, a first matching circuit, a second matching circuit, a third matching circuit, a first switch, a second switch, and a second test point; wherein the first test point is connected to the first end of the first switch, the second end of the first switch is connected to the first end of the first matching circuit, the third end of the first switch is connected to the first end of the second matching circuit, and the fourth end of the first switch is connected to the second end of the second matching circuit; the second end of the first matching circuit is used to connect to the first end of the chip under test, the first end of the second switch is used to connect to the second end of the chip under test, the second end of the second switch is connected to the second test point, the third end of the second switch is connected to the first end of the third matching circuit, and the fourth end of the second switch is connected to the second end of the second matching circuit. The fourth end is connected to the second end of the third matching circuit; when using the first frequency band RF signal for testing, the first switch is in the first switch state, the second switch is in the second switch state, the first test point, the first switch, the first matching circuit, the chip under test, the second switch, and the second test point are turned on to form a first test path; when using the second frequency band RF signal for testing, the first switch is in the third switch state, the second switch is in the fourth switch state, the first test point, the first switch, the second matching circuit, the first matching circuit, the chip under test, the second switch, the third matching circuit, and the second test point are turned on to form a second test path, wherein the frequency of the first frequency band RF signal is greater than the frequency of the second frequency band RF signal.

[0007] Based on the above test circuit, in the test of the first frequency band RF signal, there are no redundant electronic components between the first matching circuit and the chip under test. In the test of the second frequency band RF signal, there are no redundant electronic components between the second matching circuit, the first matching circuit, and the chip under test. The RF signal loss transmitted by the test path is small, and the test results are more accurate.

[0008] Furthermore, it is understood that the above-described test circuit can form different test paths in a single test station by using different conduction states of the first switch and the second switch, thereby enabling testing of the LNA chip for high-band RF signals and low-band RF signals, thereby reducing the complexity of the LNA chip testing process.

[0009] In a possible implementation of the first aspect above, the test circuit further includes a control circuit, wherein the control circuit is configured to, when testing using a first frequency band radio frequency signal, output a low-level signal to the first switch and the second switch, so that the first switch is in a first switch state and the second switch is in a second switch state; and the control circuit is configured to, when testing using a second frequency band radio frequency signal, output a high-level signal to the first switch and the second switch, so that the first switch is in a third switch state and the second switch is in a fourth switch state.

[0010] In a possible implementation of the first aspect above, the first switch includes a first double-pole double-throw RF switch, and the second switch includes a second double-pole double-throw RF switch; the first end of the first switch is the first static end of the first double-pole double-throw RF switch, the second end of the first switch is the first moving end of the first double-pole double-throw RF switch, the third end of the first switch is the second static end of the first double-pole double-throw RF switch, the fourth end of the first switch is the second moving end of the first double-pole double-throw RF switch, the first end of the second switch is the first static end of the second double-pole double-throw RF switch, the second end of the second switch is the first moving end of the second double-pole double-throw RF switch, the third end of the second switch is the second static end of the second double-pole double-throw RF switch, and the fourth end of the second switch is the second moving end of the second double-pole double-throw RF switch.

[0011] In a possible implementation of the first aspect above, when the first double-pole double-throw RF switch is in a first switching state, the first static end of the first double-pole double-throw RF switch is connected to the first moving end of the first double-pole double-throw RF switch, and the second static end of the first double-pole double-throw RF switch is connected to the second moving end of the first double-pole double-throw RF switch; when the second double-pole double-throw RF switch is in a second switching state, the first static end of the second double-pole double-throw RF switch is connected to the first moving end of the second double-pole double-throw RF switch, and the second static end of the second double-pole double-throw RF switch is connected to the second moving end of the second double-pole double-throw RF switch.

[0012] In a possible implementation of the first aspect above, when the first double-pole double-throw RF switch is in the third switching state, the first static end of the first double-pole double-throw RF switch is connected to the second moving end of the first double-pole double-throw RF switch, and the second static end of the first double-pole double-throw RF switch is connected to the first moving end of the first double-pole double-throw RF switch; when the second double-pole double-throw RF switch is in the fourth switching state, the first static end of the second double-pole double-throw RF switch is connected to the second moving end of the second double-pole double-throw RF switch, and the second static end of the second double-pole double-throw RF switch is connected to the first moving end of the second double-pole double-throw RF switch.

[0013] In a possible implementation of the first aspect above, the first matching circuit includes a first inductor and a second inductor, and the second matching circuit includes a third inductor and a fourth inductor; wherein, the first end of the first test point is grounded, the second end of the first test point is connected to the first static end of the first double-pole double-throw RF switch, the second static end of the first double-pole double-throw RF switch is connected to the first end of the third inductor, the second end of the third inductor is respectively connected to the first end of the fourth inductor and the second moving end of the first double-pole double-throw RF switch, the second end of the fourth inductor is grounded, the first moving end of the first double-pole double-throw RF switch is respectively connected to the first end of the first inductor and the first end of the second inductor, the second end of the first inductor is grounded, and the second end of the second inductor is used to connect to the first end of the chip under test.

[0014] In a possible implementation of the first aspect above, the third matching circuit includes a fifth inductor, a sixth inductor, and a seventh inductor; the second static end of the second double-pole double-throw RF switch is used to connect to the second end of the chip under test, the first static end of the second double-pole double-throw RF switch is respectively connected to the first end of the fifth inductor and the first end of the sixth inductor, the second end of the fifth inductor is grounded, the second end of the sixth inductor is respectively connected to the first end of the seventh inductor and the first moving end of the second double-pole double-throw RF switch, the second end of the seventh inductor is grounded, the second moving end of the second double-pole double-throw RF switch is connected to the first end of the second test point, and the second end of the second test point is grounded.

[0015] In a possible implementation of the first aspect above, the test circuit also includes a first capacitor, a second capacitor, and a power supply (or an external power supply); the third end of the first double-pole double-throw RF switch is respectively connected to the first end of the first capacitor and the power supply, the fourth end of the first double-pole double-throw RF switch is respectively connected to the first end of the second capacitor and the control circuit, and the second end of the first capacitor, the second end of the second capacitor, and the fifth end of the first double-pole double-throw RF switch are grounded.

[0016] In a possible implementation of the first aspect above, the test circuit also includes a third capacitor, a fourth capacitor, and a power supply (or an external power supply); the third end of the second double-pole double-throw RF switch is respectively connected to the first end of the fourth capacitor and the power supply, the fourth end of the second double-pole double-throw RF switch is respectively connected to the first end of the third capacitor and the control circuit, and the second end of the third capacitor, the second end of the fourth capacitor, and the fifth end of the second double-pole double-throw RF switch are grounded.

[0017] In a second aspect, the present application provides a testing method for an electronic device, the electronic device including the circuit of the first aspect and any one of the various possible implementations of the first aspect, the method including: when using a first frequency band radio frequency signal for testing, the control circuit inputs a first control signal to the first switch and the second switch, the first switch is in a first switching state, the second switch is in a second switching state, the first test point, the first switch, the first matching circuit, the chip under test, the second switch, and the second test point are turned on to form a first test path; when using a second frequency band radio frequency signal for testing, the control circuit inputs a second control signal to the first switch and the second switch, the first switch is in a third switching state, the second switch is in a fourth switching state, the first test point, the first switch, the second matching circuit, the first matching circuit, the chip under test, the second switch, the third matching circuit, and the second test point are turned on to form a second test path.

[0018] In a third aspect, the present application provides a chip comprising the circuit of the first aspect and any one of the various possible implementations of the first aspect.

[0019] In a fourth aspect, the present application provides an electronic device comprising the chip in the third aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A According to some embodiments, a schematic diagram of a test circuit for an LNA chip is shown;

[0021] Figure 1B According to some embodiments, a schematic diagram of another LNA chip test circuit is shown;

[0022] Figure 2A According to some embodiments, a schematic diagram of another LNA chip test circuit is shown;

[0023] Figure 2B According to some embodiments, a schematic diagram of another LNA chip test circuit is shown;

[0024] Figure 3A According to some embodiments, a schematic diagram of another LNA chip test circuit is shown;

[0025] Figure 3B According to some embodiments, a schematic diagram of another LNA chip test circuit is shown;

[0026] Figure 3C According to some embodiments, a schematic diagram of another LNA chip test circuit is shown;

[0027] Figure 4A According to some embodiments, a schematic flow chart of a testing method is shown;

[0028] Figure 4B According to some embodiments, a flowchart of another testing method is shown. DETAILED DESCRIPTION

[0029] Illustrative embodiments of the present application include, but are not limited to, a test circuit, a test method, a chip, and an electronic device.

[0030] The following is an introduction to some terms of this application.

[0031] 1. Matching circuit (MC): A group of passive components inserted into the RF circuit to achieve impedance transformation of the RF port, usually composed of capacitors or inductors.

[0032] 2. Single-pole double-throw (SPDT) RF switch: This switch consists of a moving terminal and a static terminal (also known as a stationary terminal). The moving terminal is the so-called "pole" and connects to the incoming RF signal, which is also the signal source. The static terminal is the output terminal of the RF signal. The SPDT RF switch can switch the RF signal between the two output ports.

[0033] 3. Double-pole double throw (DPDT) RF switch: In some embodiments, a DPDT RF switch can be composed of two single-pole double-throw RF switches in parallel. Each switch part is called a "pole", and each pole can be connected to two different "throw" positions. The RF switches are exactly the same.

[0034] 4. Insertion loss (IL): Transmission loss when the switch is in the on state, usually referred to as attenuation. Insertion loss is expressed in decibels (dB) corresponding to the signal level.

[0035] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following embodiments are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0036] As described in the background technology, in the dual-station test of the LNA chip, each LNA chip needs to pass Figure 1A The first test station Z1 and the second test station Z2 are shown to perform tests to obtain technical indicators of the LNA chip in high-frequency band RF signals and low-frequency band RF signals, such as gain, return loss, reverse isolation, etc.

[0037] Because the LNA chip's internal output is matched for high frequencies, no matching circuit is required when testing with high-band RF signals. However, a matching circuit is required when testing with low-band RF signals. When testing with high-band RF signals, the first test station Z1 includes matching circuit MC100 (input matching). When testing with low-band RF signals, the second test station Z2 includes matching circuit MC200 (input matching) and matching circuit MC300 (output matching). Both test stations Z1 and Z2 are equipped with a complete set of test equipment.

[0038] Figure 1AIn the first test station Z1, the first test point 1, matching circuit MC100, chip under test M, and second test point 2 are connected in series. In the second test station Z2, the third test point 3, matching circuit MC200, chip under test M, matching circuit MC300, and fourth test point 4 are connected in series. During the test of chip under test M at the first test station Z1, the RF signal is input from the first test point 1, passes through the matching circuit MC100, enters the chip under test M, and then enters the second test point 2 through the chip under test M, forming a test path including the first test point 1, matching circuit MC100, chip under test M, and second test point 2. During the test of the chip M under test at the second test station Z2, the RF signal is input from the third test point 3, passes through the matching circuit MC200, inputs the chip M under test, and then passes through the chip M under test and the matching circuit MC300 to input the fourth test point 4, forming a test path including the third test point 3, the matching circuit MC200, the chip M under test, the matching circuit MC300, and the fourth test point 4.

[0039] In some embodiments, Figure 1A The specific circuit structure of the test circuit shown can be as follows Figure 1B shown. Figure 1B In the embodiment, matching circuit MC100 includes inductor L100, matching circuit MC200 includes inductor L200, and matching circuit MC300 includes inductor L300. It is understood that matching circuit MC100, matching circuit MC200, and matching circuit MC300 may also include other electronic components, which are not specifically limited in the embodiment of the present application.

[0040] In the first test station Z1, the first end of the first test point 1 is grounded, the second end of the first test point 1 is connected to the first end of the inductor L100, the second end of the inductor L100 is connected to the first end of the chip under test M, the second end of the chip under test M is connected to the first end of the second test point 2, and the second end of the second test point 2 and the third end of the chip under test M are both grounded. Inductor L100 is only one example of matching circuit MC100. In the embodiments of the present application, the specific form of matching circuit MC100 is not specifically limited.

[0041] In the second test station Z2, the first end of the third test point 3 is grounded, the second end of the third test point 3 is connected to the first end of the inductor L200, the second end of the inductor L200 is connected to the first end of the chip under test M, the second end of the chip under test M is connected to the first end of the inductor L300, the second end of the inductor L300 is connected to the first end of the fourth test point 4, and the third end of the chip under test M and the second end of the fourth test point 4 are both grounded. Inductor L200 is only an example of matching circuit MC200, and inductor L300 is only an example of matching circuit MC300. In the embodiments of the present application, the specific forms of matching circuit MC200 and matching circuit MC300 are not specifically limited.

[0042] During the test, the first test point 1 outputs a high-frequency RF signal, which passes through inductor L100 and the chip under test M and is output to the second test point 2. Furthermore, the third test point 3 outputs a low-frequency RF signal, which passes through inductor L200, the chip under test M, and inductor L300 and is output to the fourth test point 4. The test equipment can test the technical indicators of the high-frequency RF signal of the chip under test M, such as gain, return loss, and reverse isolation, by collecting signals from the first test point 1 and the second test point 2. Furthermore, the test equipment can test the technical indicators of the low-frequency RF signal of the chip under test M, such as gain, return loss, and reverse isolation, by collecting signals from the third test point 3 and the fourth test point 4.

[0043] Understandably, during dual-station testing of LNA chips, each chip must pass through two test stations, making the testing process complex and prone to missed tests. Furthermore, since each test station requires a complete set of test equipment, including a vector network analyzer, signal source, and spectrum analyzer, this not only increases costs but also makes maintenance of the equipment difficult.

[0044] To solve the above problems, in some embodiments, during the mass production test of the LNA chip, the following is provided: Figure 2A A single-station test method for an LNA chip is shown. Figure 2A Two sets of matching circuits are set on the first test station Z1 in the test. Four single-pole double-throw RF switches, such as the first single-pole double-throw RF switch D1, the second single-pole double-throw RF switch D2, the third single-pole double-throw RF switch D3, and the fourth single-pole double-throw RF switch D4, are used to switch different matching circuits to complete the test.

[0045] Among them, the first test point 1 is connected to the static end of the first single-pole double-throw RF switch D1, the first moving end of the first single-pole double-throw RF switch D1 is connected to the first end of the matching circuit MC100 (input matching), the second moving end of the first single-pole double-throw RF switch D1 is connected to the first end of the matching circuit MC200 (input matching), the second end of the matching circuit MC100 is connected to the first moving end of the second single-pole double-throw RF switch D2, and the second end of the matching circuit MC200 is connected to the second moving end of the second single-pole double-throw RF switch D2. The static end of the second single-pole double-throw RF switch D2 is connected to the first end of the chip under test M, the second end of the chip under test M is connected to the static end of the third single-pole double-throw RF switch D3, the first moving end of the third single-pole double-throw RF switch D3 is connected to the first moving end of the fourth single-pole double-throw RF switch D4, the second moving end of the third single-pole double-throw RF switch D3 is connected to the first end of the matching circuit MC300 (output matching), the second end of the matching circuit MC300 (output matching) is connected to the second moving end of the fourth single-pole double-throw RF switch D4, and the static end of the fourth single-pole double-throw RF switch D4 is connected to the second test point 2.

[0046] During the test of the chip M under test at the first test station Z1, the first single-pole double-throw RF switch D1, the second single-pole double-throw RF switch D2, the third single-pole double-throw RF switch D3, and the fourth single-pole double-throw RF switch D4 can respectively connect the matching circuit MC100, the matching circuit MC200, and the matching circuit MC300 to the test path, thereby completing the test.

[0047] For example, after the high-frequency RF signal is output from the first test point 1, it can pass through the first single-pole double-throw RF switch D1, the matching circuit MC100, the second single-pole double-throw RF switch D2, the chip under test M, the third single-pole double-throw RF switch D3, the fourth single-pole double-throw RF switch D4 and the second test point 2 in sequence.

[0048] Alternatively, after the low-frequency band RF signal is output from the first test point 1, it can pass through the first single-pole double-throw RF switch D1, the matching circuit MC200, the second single-pole double-throw RF switch D2, the chip under test M, the third single-pole double-throw RF switch D3, the matching circuit MC300, the fourth single-pole double-throw RF switch D4 and the second test point 2 in sequence.

[0049] In some embodiments, Figure 2A Matching circuit MC100 may include inductor L100 and capacitor C100, matching circuit MC200 may include inductor L200 and capacitor C200, and matching circuit MC300 may include inductor L300 and capacitor C300. It is understood that matching circuit MC100, matching circuit MC200, and matching circuit MC300 may also include other electronic components, which are not specifically limited in the embodiments of the present application. Figure 2B Shown with Figure 2AThe corresponding specific circuit structure.

[0050] like Figure 2B As shown, the first end of the first test point 1 is connected to the static terminal of the first single-pole double-throw RF switch D1, and the second end of the first test point 1 is grounded. The first moving end of the first single-pole double-throw RF switch D1 is respectively connected to the first end of the inductor L100 (input matching) and the first end of the capacitor C100, and the second end of the capacitor C100 is grounded. The second moving end of the first single-pole double-throw RF switch D1 is respectively connected to the first end of the inductor L200 (input matching) and the first end of the capacitor C200, and the second end of the capacitor C200 is grounded. The second end of the inductor L100 is connected to the first moving end of the second single-pole double-throw RF switch D2, and the second end of the inductor L200 is connected to the second moving end of the second single-pole double-throw RF switch D2. The static terminal of the second single-pole double-throw RF switch D2 is connected to the first end of the chip under test M, the second end of the chip under test M is connected to the static terminal of the third single-pole double-throw RF switch D3, and the third end of the chip under test M is grounded. The first moving end of the third single-pole double-throw RF switch D3 is connected to the first moving end of the fourth single-pole double-throw RF switch D4, the second moving end of the third single-pole double-throw RF switch D3 is connected to the first end of the inductor L300 (output matching), the second end of the inductor L300 (output matching) is respectively connected to the second moving end of the fourth single-pole double-throw RF switch D4 and the first end of the capacitor C300, the second end of the capacitor C300 is grounded, and the static end of the fourth single-pole double-throw RF switch D4 is connected to the second test point 2.

[0051] During the test of the chip M under test at the first test station Z1, the first single-pole double-throw RF switch D1, the second single-pole double-throw RF switch D2, the third single-pole double-throw RF switch D3, and the fourth single-pole double-throw RF switch D4 can respectively connect the inductor L100, the inductor L200, and the inductor L300 to the test path to complete the test.

[0052] For example, after the high-frequency RF signal is output from the first test point 1, it can pass through the first single-pole double-throw RF switch D1, the inductor L100, the second single-pole double-throw RF switch D2, the chip under test M, the third single-pole double-throw RF switch D3, the fourth single-pole double-throw RF switch D4 and the second test point 2 in sequence.

[0053] Alternatively, after the low-frequency band RF signal is output from the first test point 1, it can pass through the first single-pole double-throw RF switch D1, the inductor L200, the second single-pole double-throw RF switch D2, the chip under test M, the third single-pole double-throw RF switch D3, the inductor L300, the fourth single-pole double-throw RF switch D4 and the second test point 2 in sequence.

[0054] The above method can form a test path including the first test point 1, the first single-pole double-throw RF switch D1, the matching circuit MC100 (such as the inductor L100), the second single-pole double-throw RF switch D2, the chip under test M, the third single-pole double-throw RF switch D3, the fourth single-pole double-throw RF switch D4, and the second test point 2 through four single-pole double-throw RF switches; and a test path including the first test point 1, the first single-pole double-throw RF switch D1, the matching circuit MC200 (such as the inductor L200), the second single-pole double-throw RF switch D2, the chip under test M, the third single-pole double-throw RF switch D3, the matching circuit MC300 (such as the inductor L300), the fourth single-pole double-throw RF switch D4, and the second test point 2.

[0055] It can be understood that the above method can save test equipment and reduce the workload of equipment maintenance. In addition, because the second single-pole double-throw RF switch D2 is inserted between the input matching (such as matching circuit MC100 or matching circuit MC200) and the chip under test M, the RF signal transmitted through the test path in this method has additional insertion loss, resulting in lower test result accuracy.

[0056] In view of this, the present application proposes a test circuit, which includes two double-pole double-throw radio frequency switches and three matching circuits. The test circuit can connect different matching circuits to the test path through the two double-pole double-throw radio frequency switches. Figure 3AAs shown, the test circuit includes: a first test point 1, a first matching circuit MC1, a second matching circuit MC2, a third matching circuit MC3, a chip under test M, a first switch S1, a second switch S2, and a second test point 2; wherein the first test point 1 is connected to the first end of the first switch S1, the second end of the first switch S1 is connected to the first end of the first matching circuit MC1, the third end of the first switch S1 is connected to the first end of the second matching circuit MC2, and the fourth end of the first switch S1 is connected to the second end of the second matching circuit MC2; the second end of the first matching circuit MC1 is connected to the first end of the chip under test M, the second end of the chip under test M is connected to the first end of the second switch S2, the second end of the second switch S2 is connected to the second test point 2, and the third end of the second switch S2 is connected to the third The first end of the matching circuit MC3 and the fourth end of the second switch S2 are connected to the second end of the third matching circuit MC3; when using a high-frequency band RF signal for testing, the first switch S1 is in the first switching state, the second switch S2 is in the second switching state, the first test point 1, the first switch S1, the first matching circuit MC1, the chip under test M, the second switch S2, and the second test point 2 are turned on to form a first test path; when using a low-frequency band RF signal for testing, the first switch S1 is in the third switching state, the second switch S2 is in the fourth switching state, the first test point 1, the first switch S1, the second matching circuit MC2, the first matching circuit MC1, the chip under test M, the second switch S2, the third matching circuit MC3 and the second test point 2 are turned on to form a second test path.

[0057] In this way, based on the test circuit provided in the embodiment of the present application, in the test of high-frequency RF signals, there are no redundant electronic components between the first matching circuit and the chip under test, and in the test of low-frequency RF signals, there are no redundant electronic components between the second matching circuit, the first matching circuit, and the chip under test. Therefore, the RF signal loss transmitted in the test path in this test method is small, and the accuracy of the test results is also high.

[0058] Furthermore, the test circuit provided in the embodiments of the present application can control the conduction states of two double-pole double-throw (DPDT) RF switches using two control signals. This allows the LNA chip to be tested for both high-band and low-band RF signals within a single test station, thereby reducing the complexity of the LNA chip testing process.

[0059] And, continue to combine Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 4A and Figure 4B , which introduces the various embodiments of the present application in detail.

[0060] In some embodiments, Figure 3B FIG. 4 shows a schematic diagram of a test circuit for another LNA chip, as shown in FIG. Figure 3B As shown, the first switch S1 includes a first double-pole double-throw RF switch S100, and the second switch S2 includes a second double-pole double-throw RF switch S200. The first end of the first switch S1 is the first static terminal RF2 of the first double-pole double-throw RF switch S100, the second end of the first switch S1 is the first dynamic terminal RF4 of the first double-pole double-throw RF switch S100, the third end of the first switch S1 is the second static terminal RF1 of the first double-pole double-throw RF switch S100, and the fourth end of the first switch S1 is the second dynamic terminal RF3 of the first double-pole double-throw RF switch S100. The first end of the second switch S2 is the first static terminal RF2 of the second double-pole double-throw RF switch S200, the second end of the second switch S2 is the first dynamic terminal RF4 of the second double-pole double-throw RF switch S200, the third end of the second switch S2 is the second static terminal RF1 of the second double-pole double-throw RF switch S200, and the fourth end of the second switch S2 is the second dynamic terminal RF3 of the second double-pole double-throw RF switch S200.

[0061] The first test point 1 is connected to the first static terminal RF2 of the first double-pole double-throw RF switch S100, the first dynamic terminal RF4 of the first double-pole double-throw RF switch S100 is connected to the first end of the first matching circuit MC1, the second end of the first matching circuit MC1 is connected to the first end of the chip under test M, the second end of the chip under test M is connected to the first static terminal RF2 of the second double-pole double-throw RF switch S200, and the first dynamic terminal RF4 of the second double-pole double-throw RF switch S200 is connected to the second test point 2. In addition, the second static terminal RF1 of the first double-pole double-throw RF switch S100 is connected to the first end of the second matching circuit MC2, the second end of the second matching circuit MC2 is connected to the second dynamic terminal RF3 of the first double-pole double-throw RF switch S100, the second static terminal RF1 of the second double-pole double-throw RF switch S200 is connected to the first end of the third matching circuit MC3, and the second end of the third matching circuit MC3 is connected to the second dynamic terminal RF3 of the second double-pole double-throw RF switch S200.

[0062] In some embodiments, the test circuit in the present application may include a control circuit (not shown in the drawings of the present application). When using a high-frequency band RF signal test, the control circuit outputs a first control signal (such as a low-level signal) to the first switch S1 and the second switch S2, and the first double-pole double-throw RF switch S100 is in the first switching state. The first static terminal RF2 of the first double-pole double-throw RF switch S100 is connected to the first dynamic terminal RF4, and the second static terminal RF1 of the first double-pole double-throw RF switch S100 is connected to the second dynamic terminal RF3. In addition, the second double-pole double-throw RF switch S200 is in the second switching state. The first static terminal RF2 of the second double-pole double-throw RF switch S200 is connected to the first dynamic terminal RF4, and the second static terminal RF1 of the second double-pole double-throw RF switch S200 is connected to the second dynamic terminal RF3.

[0063] In this way, the above test circuit forms a first test path, and the first matching circuit MC1 is connected to the first test path, serving as a matching circuit for the first end of the chip under test M in the first test path. The first test path includes a first test point 1, a first double-pole double-throw RF switch S100, a first matching circuit MC1, the chip under test M, a second double-pole double-throw RF switch S200, and a second test point 2.

[0064] When testing using a low-frequency RF signal, the control circuit outputs a second control signal (e.g., a high-level signal) to the first switch S1 and the second switch S2, causing the first double-pole double-throw RF switch S100 to be in a third switching state, with the first static terminal RF2 of the first double-pole double-throw RF switch S100 conducting with the second dynamic terminal RF3, and the second static terminal RF1 of the first double-pole double-throw RF switch S100 conducting with the first dynamic terminal RF4. Furthermore, the second double-pole double-throw RF switch S200 is in a fourth switching state, with the first static terminal RF2 of the second double-pole double-throw RF switch S200 conducting with the second dynamic terminal RF3, and the second static terminal RF1 of the second double-pole double-throw RF switch S200 conducting with the first dynamic terminal RF4.

[0065] In this way, the above test circuit forms a second test path. The first matching circuit MC1 and the second matching circuit MC2 are connected to the second test path, serving as the matching circuit for the first end of the chip under test M in the second test path. The third matching circuit MC3 is connected to the second test path, serving as the matching circuit for the second end of the chip under test M in the second test path. The second test path includes the first test point 1, the first double-pole double-throw RF switch S100, the second matching circuit MC2, the first matching circuit MC1, the chip under test M, the second double-pole double-throw RF switch S200, the third matching circuit MC3, and the second test point 2.

[0066] In some embodiments, Figure 3B The specific circuit structure of the test path shown can be as follows Figure 3C shown. Figure 3C In the embodiment, the first matching circuit MC1 includes a first inductor L1 and a second inductor L2, the second matching circuit MC2 includes a third inductor L3 and a fourth inductor L4, and the third matching circuit MC3 includes a fifth inductor L5, a sixth inductor L6, and a seventh inductor L7. The first end of the first test point 1 is grounded, and the second end of the first test point 1 is connected to the first static terminal RF2 of the first double-pole double-throw RF switch S100. The second static terminal RF1 of the first double-pole double-throw RF switch S100 is connected to the first end of the third inductor L3, and the second end of the third inductor L3 is respectively connected to the first end of the fourth inductor L4 and the second dynamic terminal RF3 of the first double-pole double-throw RF switch S100. The second end of the fourth inductor L4 is grounded.

[0067] The first moving end RF4 of the first double-pole double-throw RF switch S100 is respectively connected to the first end of the first inductor L1 and the first end of the second inductor L2, and the second end of the first inductor L1 is grounded. The VDD of the first double-pole double-throw RF switch S100 (or the fifth end of the first double-pole double-throw RF switch S100) is respectively connected to the first end of the first capacitor C1 and the power supply (or an external power supply). The CTL of the first double-pole double-throw RF switch S100 (or the sixth end of the first double-pole double-throw RF switch S100) is respectively connected to the first end of the second capacitor C2 and the control circuit (not shown in the figures of the present application), the second end of the first capacitor C1, the second end of the second capacitor C2, and the GND of the first double-pole double-throw RF switch S100 (or the seventh end of the first double-pole double-throw RF switch S100) are grounded. The second end of the second inductor L2 is connected to the first end of the chip under test M, and the third end of the chip under test M is grounded.

[0068] Furthermore, the second end of the chip under test M is connected to the first static terminal RF2 of the second double-pole double-throw RF switch S200. The second static terminal RF1 of the second double-pole double-throw RF switch S200 is respectively connected to the first end of the fifth inductor L5 and the first end of the sixth inductor L6, and the second end of the fifth inductor L5 is grounded. The second end of the sixth inductor L6 is respectively connected to the first end of the seventh inductor L7 and the second dynamic terminal RF3 of the second double-pole double-throw RF switch S200, and the second end of the seventh inductor L7 is grounded. The first dynamic terminal RF4 of the second double-pole double-throw RF switch S200 is connected to the first end of the second test point 2, and the second end of the second test point 2 is grounded. VDD of the second double-pole double-throw RF switch S200 (or the fifth end of the second double-pole double-throw RF switch S200) is respectively connected to the first end of the fourth capacitor C4 and the power supply (or the external power supply). The CTL of the second double-pole double-throw RF switch S200 (or the sixth end of the second double-pole double-throw RF switch S200) is respectively connected to the first end of the third capacitor C3 and the control circuit (not shown in the figures of this application), and the second end of the third capacitor C3, the second end of the fourth capacitor C4, and the GND of the second double-pole double-throw RF switch S200 or the seventh end of the second double-pole double-throw RF switch S200 are grounded.

[0069] I understand. Figure 2A and Figure 2B In the test circuit shown, four SPDT selection test paths are used. The control logic of the SPDT in each test path is different. For example, the control logic of the first SPDT RF switch D1 and the second SPDT RF switch D2 are different, and the control logic of the third SPDT RF switch D3 and the fourth SPDT RF switch D4 are different. That is, each test path requires a high-level signal and a low-level signal to control the four SPDTs at the same time, so that the corresponding test method requires more control resources for testing. Therefore, compared with Figure 2Aand Figure 2B The test circuit shown, Figures 3A to 3C In the test path shown, the same control signal can be used to simultaneously control two double-pole double-throw RF switches, which can greatly save control resources.

[0070] For example, according to Figure 3C In the test circuit shown, during the test of the chip under test, the first test point 1 outputs a first frequency band RF signal (a high-frequency RF signal, such as 1575.42 MHz), and uses a low-level signal to control the first double-pole double-throw RF switch S100 and the second double-pole double-throw RF switch S200. The first static terminal RF2 of the first double-pole double-throw RF switch S100 and the first dynamic terminal RF4 of the first double-pole double-throw RF switch S100 are conductive, the second static terminal RF1 of the first double-pole double-throw RF switch S100 and the second dynamic terminal RF3 of the first double-pole double-throw RF switch S100 are conductive, the first static terminal RF2 of the second double-pole double-throw RF switch S200 and the first dynamic terminal RF4 of the second double-pole double-throw RF switch S200 are conductive, and the second static terminal RF1 of the second double-pole double-throw RF switch S200 and the second dynamic terminal RF3 of the second double-pole double-throw RF switch S200 are conductive. Therefore, during the high-frequency RF signal testing process, the first test path includes the first test point 1, the first double-pole double-throw RF switch S100, the first matching circuit MC1, the chip under test M, the second double-pole double-throw RF switch S200, and the second test point 2. This allows various technical indicators of the chip under test M to be tested under high-frequency RF signals, such as gain, return loss, and reverse isolation.

[0071] Alternatively, the first test point 1 outputs a second frequency band RF signal, which is a low frequency band RF signal, such as 1176.45 MHz, and uses a high-level signal to control the first double-pole double-throw RF switch S100 and the second double-pole double-throw RF switch S200. The first static terminal RF2 of the first double-pole double-throw RF switch S100 and the second dynamic terminal RF3 of the first double-pole double-throw RF switch S100 are conductive, the second static terminal RF1 of the first double-pole double-throw RF switch S100 and the first dynamic terminal RF4 of the first double-pole double-throw RF switch S100 are conductive, the first static terminal RF2 of the second double-pole double-throw RF switch S200 and the second dynamic terminal RF3 of the second double-pole double-throw RF switch S200 are conductive, and the second static terminal RF1 of the second double-pole double-throw RF switch S200 and the first dynamic terminal RF4 of the second double-pole double-throw RF switch S200 are conductive. Therefore, during the low-frequency RF signal test, the second test path includes the first test point 1, the first double-pole double-throw RF switch S100, the second matching circuit MC2, the first matching circuit MC1, the chip under test M, the second double-pole double-throw RF switch S200, the third matching circuit MC3, and the test path of the second test point 2. In this way, various technical indicators of the chip under test M can be tested under low-frequency RF signals, such as gain, return loss, reverse isolation, etc. under low-frequency RF signals. In the embodiment of the present application, the frequency of the first-frequency-band RF signal is greater than the frequency of the second-frequency-band RF signal.

[0072] In some embodiments, the standing wave ratio (VSWR) can be used to measure the matching between a transmission line and a load. VSWR is a key parameter for measuring transmission line impedance matching and is defined as the ratio of the voltage antinode to the voltage trough. A higher VSWR indicates a poorer matching between the transmission line and the load.

[0073] in, (Γ is the reflection coefficient). Where Γ=(Z L -Z0) / (Z L +Z0). Z L is the load impedance; Z0 is the characteristic impedance, such as 50Ω.

[0074] according to Figure 3C The test circuit, the first test path, Z L It can include the impedance of the first inductor L1 connected to the first test path, the impedance of the second inductor L2, the impedance of the trace on the PCB board, etc. LThis may include the impedance of the third inductor L3, the impedance of the fourth inductor L4, the impedance of the first inductor L1, the impedance of the second inductor L2, the impedance of the fifth inductor L5, the impedance of the sixth inductor L6, the impedance of the seventh inductor L7, and the impedance of the traces on the PCB. Furthermore, the values ​​of the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, and the seventh inductor L7 are in the range of [1,100] mH. By adjusting the impedance of each inductor in different test paths, the VSWR value can be made close to 1, thereby achieving maximum power transmission from the RF signal source to the chip under test M to a large extent.

[0075] In some embodiments, Figure 3A The test circuit shown may include a control circuit (not shown in the figures of this application). Figure 3A , Figure 4A A test method is shown. The test method is performed by an electronic device, such as any test device. The test method may include but is not limited to the following steps:

[0076] S410, when using the first frequency band RF signal test, the control circuit inputs the first control signal to the first switch S1 and the second switch S2, the first switch S1 is in the first switch state, and the second switch S2 is in the second switch state, and the test circuit forms a first test path, which includes the first test point 1, the first switch S1, the first matching circuit MC1, the chip under test M, the second switch S2 and the second test point 2.

[0077] It can be understood that the radio frequency signal in the first frequency band is a radio frequency signal in a high frequency band. The first matching circuit MC1 serves as a matching circuit for the first end of the chip under test M in the first test path.

[0078] The first control signal may be a signal used to control the first switch S1 to be in the first switching state and the second switch S2 to be in the second switching state. For example, the first control signal may be a low-level signal. Furthermore, the signal used to control the first switch S1 to be in the first switching state and the signal used to control the second switch S2 to be in the second switching state may be the same or different. In the embodiments of the present application, the number and content of the first control signals are not specifically limited.

[0079] S420, when using the second frequency band RF signal test, the control circuit inputs a second control signal to the first switch S1 and the second switch S2, the first switch S1 is in the third switch state, and the second switch S2 is in the fourth switch state, and the test circuit forms a second test path, which includes the first test point 1, the first switch S1, the second matching circuit MC2, the first matching circuit MC1, the chip under test M, the second switch S2, the third matching circuit MC3, and the second test point 2.

[0080] It can be understood that the second frequency band RF signal is a low frequency band RF signal. The first matching circuit MC1 and the second matching circuit MC2 serve as the matching circuit for the first end of the chip under test M in the second test path, and the third matching circuit MC3 serves as the matching circuit for the second end of the chip under test M in the second test path. The second control signal can be a signal for controlling the first switch S1 to be in the third switching state and the second switch S2 to be in the fourth switching state. For example, the second control signal can be a high-level signal. Furthermore, the signal for controlling the first switch S1 to be in the third switching state and the signal for controlling the second switch S2 to be in the fourth switching state can be the same or different. In the embodiment of the present application, there is no specific limitation on the number and content of the second control signals.

[0081] It can be understood that the control signal transmitted by the control circuit can cause the first switch S1 and the second switch S2 to present different switch states, thereby forming different test paths, thereby realizing the testing of the LNA chip in high-frequency band RF signals and low-frequency band RF signals.

[0082] It is understood that there is no specific order for steps S410 and S420. That is, for testing the LNA chip, step S410 can be performed first, followed by step S420, or step S410 can be performed first, followed by step S420. This is not specifically limited in the present embodiment.

[0083] The above-mentioned test method can control the conduction paths of two double-pole double-branch RF switches through control signals, thereby forming two test paths including different matching circuits when high-band RF signals and low-band RF signals are input respectively, and further testing the technical indicators of the LNA chip under high-band RF signals and low-band RF signals.

[0084] Furthermore, this testing method eliminates the need for additional electronic components, such as switches, between the first matching circuit MC1 of the first test path and the chip under test M, and between the first matching circuit MC1, the second matching circuit MC2 of the second test path, and the chip under test M. Consequently, signal loss in both test paths is minimal, and the technical indicators obtained during testing are highly accurate. Furthermore, this testing method requires only one set of testing equipment to complete testing of the chip under test M under signals in different frequency bands, reducing testing costs and enabling its application to a wide range of LNA chip testing scenarios.

[0085] Next, continue to combine Figure 3B A test circuit is shown, introducing Figure 4B A test method is shown. The test method is performed by an electronic device, such as any test device. The test method may include but is not limited to the following steps.

[0086] S430 , inputting a first control signal to the first double-pole double-throw radio frequency switch S100 and the second double-pole double-throw radio frequency switch S200 to obtain a first test path including the first matching circuit MC1 .

[0087] It can be understood that during the test process, a first control signal can be input to the first double-pole double-throw RF switch S100 and the second double-pole double-throw RF switch S200 through a control circuit (not shown in the figures of this application), thereby controlling the connection between each moving end and each static end in the first double-pole double-throw RF switch S100, and the connection between each moving end and each static end in the second double-pole double-throw RF switch S200.

[0088] In some embodiments, the first control signal can be a low-level signal, which connects the first static terminal RF2 of the first double-pole double-throw RF switch S100 to the first dynamic terminal RF4, connects the second static terminal RF1 of the first double-pole double-throw RF switch S100 to the second dynamic terminal RF3, and connects the first static terminal RF2 of the second double-pole double-throw RF switch S200 to the first dynamic terminal RF4, and connects the second static terminal RF1 of the second double-pole double-throw RF switch S200 to the second dynamic terminal RF3. In this way, during the test process, a first test path including the first matching circuit MC1 can be formed.

[0089] S440: Input a radio frequency signal of the first frequency band to the first test point 1, and obtain technical indicators of the chip under test M under the radio frequency signal of the first frequency band according to the signal received by the second test point 2.

[0090] In some embodiments, a first frequency band radio frequency signal, ie, a high frequency band radio frequency signal (eg, 1575.42 MHz) may be input to the first test point 1. Z ), and receives a signal at the second test point 2 at the end of the first test path. Based on the received signal, the technical indicators of the chip under test M under high-frequency RF signals are tested. It will be appreciated that the technical indicators under high-frequency RF signals may include the technical indicators of the LNA chip under high-frequency RF signals, such as gain, return loss, and reverse isolation. In the embodiments of the present application, the technical indicators under high-frequency RF signals and high-frequency RF signals are not specifically limited.

[0091] S450 , input a second control signal to the first double-pole double-throw RF switch S100 and the second double-pole double-throw RF switch S200 to obtain a second test path including the first matching circuit MC1 , the second matching circuit MC2 , and the third matching circuit MC3 .

[0092] In some embodiments, after the LNA chip's technical indicator test is completed under a high-frequency RF signal, a second control signal, such as a high-level signal, can be input to the first DPDT RF switch S100 and the second DPDT RF switch S200, respectively, to connect the first static terminal RF2 of the first DPDT RF switch S100 to the second dynamic terminal RF3, connect the second static terminal RF1 of the first DPDT RF switch S100 to the first dynamic terminal RF4, and connect the first static terminal RF2 of the second DPDT RF switch S200 to the second dynamic terminal RF3, and connect the second static terminal RF1 of the second DPDT RF switch S200 to the first dynamic terminal RF4. In this way, during the test, a second test path can be formed, including the second matching circuit MC2, the first matching circuit MC1, and the third matching circuit MC3.

[0093] It is understood that in step S410 and step S430, the control signal for controlling the first double-pole double-throw RF switch S100 and the second double-pole double-throw RF switch S200 can be a high-level signal or a low-level signal, as well as other signals that can be used to control double-pole double-throw RF switches. The control signals of the first double-pole double-throw RF switch S100 and the second double-pole double-throw RF switch S200 can be the same or different. In the embodiment of the present application, the content and quantity of the first control signal and the second control signal are not specifically limited.

[0094] S460: Input a second frequency band radio frequency signal to the first test point 1, and test the technical indicators of the chip under test M under the second frequency band radio frequency signal based on the signal received by the second test point 2.

[0095] In some embodiments, a first frequency band radio frequency signal, ie, a low frequency band radio frequency signal (eg, 1176.45 MHz) may be input to the first test point 1. Z ), and receives a signal at the second test point 2 at the end of the second test path. Based on the received signal, the technical indicators of the chip under test M under low-band RF signals are tested. It is understood that the technical indicators under low-band RF signals may include the technical indicators of the LNA chip under low-band RF signals, such as gain, return loss, and reverse isolation. In the embodiments of the present application, the low-band RF signals and the technical indicators under low-band RF signals are not specifically limited.

[0096] It is understood that there is no specific order in which steps S430 and S440, as well as steps S450 and S460, can be performed. That is, when testing the LNA chip, steps S430 and S440 can be performed first, followed by steps S450 and S460, or steps S450 and S460 can be performed first, followed by steps S430 and S440. This is not specifically limited in the present embodiments.

[0097] The above-described testing method controls the conduction paths of two double-pole, double-throw (DPDT) RF switches via control signals. This allows the LNA chip's technical specifications under high-band RF signals and low-band RF signals to be tested using two test paths with different matching circuits, respectively. Furthermore, in this testing method, no additional electronic components, such as switches, are present between the first matching circuit MC1 of the first test path and the chip under test M, and between the first matching circuit MC1 and the second matching circuit MC2 of the second test path and the chip under test M. Consequently, signal loss in both test paths is minimal, the voltage standing wave ratio (VSWR) is close to 1, the test specifications are highly accurate, and the test results are excellent. Furthermore, this testing method requires only one set of testing equipment to complete testing of the chip under test M under both high-band and low-band RF signals, reducing testing costs and enabling its application to a wide range of LNA chip testing scenarios.

[0098] It can be understood that the above-described testing method, by controlling the conduction paths of two double-pole, double-throw (DPDT) RF switches, enables the acquisition of two test paths for high-band and low-band RF signals during LNA chip testing. Each test path includes a different matching circuit. Furthermore, because there are no additional electronic components, such as switches, between the matching circuit and the first end of the chip under test M, signal loss in the test paths is minimized, achieving better matching and ultimately achieving maximum power transmission.

[0099] It can be understood that the test circuit disclosed in this application is different from the dual-station test circuit (such as Figure 1A and 1B The test circuit shown in the figure can save test equipment, including the number of boards in the test equipment, reduce test equipment costs, reduce the space occupied by the test equipment, and improve resource utilization. Furthermore, the single-station testing method based on the test circuit disclosed in this application simplifies the operation and maintenance process, reduces the workload of equipment maintenance, reduces manual intervention, improves work efficiency, reduces the risk of missed tests, and has significant operational convenience and safety.

[0100] It can be understood that compared with other single-station test circuits (such as Figure 2A and 2BThe test circuit shown in the figure) has no additional electronic components between the input matching and the test chip of the test circuit disclosed in the present application, which avoids the insertion loss caused by additional electronic components (such as single-pole single-throw RF switches), resulting in poor matching of high-frequency RF signals, and even the risk of unavailability of the test circuit in certain specific scenarios. The test circuit disclosed in the present application is highly feasible. When using high-frequency RF signal testing, the input RF signal and the output RF signal of the chip M under test only pass through one switch, such as the second double-pole double-throw RF switch S200, and the signal loss is smaller. In addition, the above Figures 3A to 3B The test circuit shown requires only two switches, which is less than other single-station test circuits (such as Figure 2A and 2B The test circuit shown in FIG5 is reduced by half, and only one control signal is needed for the switch, saving the control resource overhead.

[0101] It can be understood that the test circuit disclosed in the present application can be used in application fields such as wireless communication technology, electromagnetic compatibility testing, and radio frequency switch design, and has broad application prospects.

[0102] For example, in the field of wireless communications, LNAs are typically used to amplify signals in a fixed frequency band. The test circuit disclosed in this application allows an LNA to switch matching circuits through electronic control, thereby achieving dual-band switching. This allows an LNA to operate in two frequency bands in a time-sharing manner. In certain specific scenarios, this can simplify receiver design and save circuit costs and overhead.

[0103] For example, electromagnetic compatibility testing is a crucial step in ensuring that electronic devices function properly in complex electromagnetic environments. It is a mandatory test for LNAs before they leave the factory. In this area of ​​electromagnetic compatibility testing, the test circuit disclosed in this application avoids the high cost of dual-station solutions, which require two test environments, while also addressing the poor matching performance of traditional single-station solutions.

[0104] For another example, in the field of radio frequency receiver design, such as the design of electronic devices such as televisions, mobile phones, radios, and locators, the test circuit disclosed in this application can also be applied to related circuits at a lower cost.

[0105] In some embodiments of the present application, a chip is further provided. The chip includes the test circuit proposed in the above embodiments, and the test circuit is used to execute the above test method.

[0106] In some embodiments of the present application, an electronic device is also provided, comprising the above-mentioned chip.

[0107] The specific application form of the test circuit design solution is not limited in this embodiment. Optionally, the application scope of the test circuit design solution includes but is not limited to LNA chips, etc.

[0108] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0109] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0110] Program code can be implemented with a high-level programming language or an object-oriented programming language to communicate with the processing system. Where necessary, program code can also be implemented in assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0111] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy disks, optical disks, optical discs, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0112] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features.

[0113] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0114] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the presence of other identical elements in the process, method, article or device that includes the above elements.

[0115] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. A test circuit, characterized in that: The circuit includes: a first test point, a first matching circuit, a second matching circuit, a third matching circuit, a first switch, a second switch, and a second test point; The first test point is connected to the first end of the first switch, the second end of the first switch is connected to the first end of the first matching circuit, the third end of the first switch is connected to the first end of the second matching circuit, and the fourth end of the first switch is connected to the second end of the second matching circuit; The second end of the first matching circuit is used to connect to the first end of the chip under test, the first end of the second switch is used to connect to the second end of the chip under test, the second end of the second switch is connected to the second test point, the third end of the second switch is connected to the first end of the third matching circuit, and the fourth end of the second switch is connected to the second end of the third matching circuit; When testing using a radio frequency signal in a first frequency band, the first switch is in a first switch state, the second switch is in a second switch state, the first test point, the first switch, the first matching circuit, the chip under test, the second switch, and the second test point are connected to form a first test path; When testing using a second frequency band RF signal, the first switch is in a third switch state, the second switch is in a fourth switch state, the first test point, the first switch, the second matching circuit, the first matching circuit, the chip under test, the second switch, the third matching circuit, and the second test point are sequentially turned on to form a second test path, wherein the frequency of the first frequency band RF signal is greater than the frequency of the second frequency band RF signal.

2. The test circuit according to claim 1, wherein: Also includes control circuit, The control circuit is configured to output a first control signal to the first switch and the second switch when testing with a radio frequency signal in a first frequency band, so that the first switch is in a first switch state and the second switch is in a second switch state; The control circuit is configured to output a second control signal to the first switch and the second switch when testing with a second frequency band radio frequency signal, so that the first switch is in a third switch state and the second switch is in a fourth switch state.

3. The test circuit according to claim 2, wherein: The first switch includes a first double-pole double-throw radio frequency switch, and the second switch includes a second double-pole double-throw radio frequency switch; The first end of the first switch is the first static end of the first double-pole double-throw radio frequency switch, the second end of the first switch is the first moving end of the first double-pole double-throw radio frequency switch, the third end of the first switch is the second static end of the first double-pole double-throw radio frequency switch, and the fourth end of the first switch is the second moving end of the first double-pole double-throw radio frequency switch. The first end of the second switch is the first static end of the second double-pole double-throw RF switch, the second end of the second switch is the first moving end of the second double-pole double-throw RF switch, the third end of the second switch is the second static end of the second double-pole double-throw RF switch, and the fourth end of the second switch is the second moving end of the second double-pole double-throw RF switch.

4. The test circuit according to claim 3, characterized in that: When the first double-pole double-throw radio frequency switch is in a first switching state, the first static terminal of the first double-pole double-throw radio frequency switch is conductively connected to the first dynamic terminal of the first double-pole double-throw radio frequency switch, and the second static terminal of the first double-pole double-throw radio frequency switch is conductively connected to the second dynamic terminal of the first double-pole double-throw radio frequency switch; When the second double-pole double-throw radio frequency switch is in the second switching state, the first static end of the second double-pole double-throw radio frequency switch is connected to the first dynamic end of the second double-pole double-throw radio frequency switch, and the second static end of the second double-pole double-throw radio frequency switch is connected to the second dynamic end of the second double-pole double-throw radio frequency switch.

5. The test circuit according to claim 3, characterized in that: When the first double-pole double-throw RF switch is in the third switching state, the first static terminal of the first double-pole double-throw RF switch is conductively connected to the second dynamic terminal of the first double-pole double-throw RF switch, and the second static terminal of the first double-pole double-throw RF switch is conductively connected to the first dynamic terminal of the first double-pole double-throw RF switch; When the second double-pole double-throw radio frequency switch is in the fourth switching state, the first static end of the second double-pole double-throw radio frequency switch is conductively connected to the second dynamic end of the second double-pole double-throw radio frequency switch, and the second static end of the second double-pole double-throw radio frequency switch is conductively connected to the first dynamic end of the second double-pole double-throw radio frequency switch.

6. The test circuit according to claim 3, characterized in that: The first matching circuit includes a first inductor and a second inductor, and the second matching circuit includes a third inductor and a fourth inductor; Among them, the first end of the first test point is grounded, the second end of the first test point is connected to the first static end of the first double-pole double-throw RF switch, the second static end of the first double-pole double-throw RF switch is connected to the first end of the third inductor, the second end of the third inductor is respectively connected to the first end of the fourth inductor and the second moving end of the first double-pole double-throw RF switch, the second end of the fourth inductor is grounded, the first moving end of the first double-pole double-throw RF switch is respectively connected to the first end of the first inductor and the first end of the second inductor, the second end of the first inductor is grounded, and the second end of the second inductor is used to connect to the first end of the chip under test.

7. The test circuit according to claim 3, wherein: The third matching circuit includes a fifth inductor, a sixth inductor, and a seventh inductor; The second static end of the second double-pole double-throw RF switch is used to connect to the second end of the chip under test, the first static end of the second double-pole double-throw RF switch is respectively connected to the first end of the fifth inductor and the first end of the sixth inductor, the second end of the fifth inductor is grounded, the second end of the sixth inductor is respectively connected to the first end of the seventh inductor and the first moving end of the second double-pole double-throw RF switch, the second end of the seventh inductor is grounded, the second moving end of the second double-pole double-throw RF switch is connected to the first end of the second test point, and the second end of the second test point is grounded.

8. The test circuit according to claim 7, characterized in that: The test circuit further includes a first capacitor, a second capacitor, and a power supply; The fifth end of the first double-pole double-throw RF switch is respectively connected to the first end of the first capacitor and the power supply, the sixth end of the first double-pole double-throw RF switch is respectively connected to the first end of the second capacitor and the control circuit, the second end of the first capacitor, the second end of the second capacitor, and the seventh end of the first double-pole double-throw RF switch are grounded.

9. The test circuit according to claim 7, characterized in that: The test circuit further includes a third capacitor, a fourth capacitor, and a power supply; The fifth end of the second double-pole double-throw RF switch is respectively connected to the first end of the fourth capacitor and the power supply, the sixth end of the second double-pole double-throw RF switch is respectively connected to the first end of the third capacitor and the control circuit, and the second end of the third capacitor, the second end of the fourth capacitor, and the seventh end of the second double-pole double-throw RF switch are grounded.

10. A testing method, characterized in that: For use in an electronic device, the electronic device comprising the test circuit according to any one of claims 1 to 9, the method comprising: When testing using a radio frequency signal in a first frequency band, the control circuit inputs a first control signal to the first switch and the second switch, the first switch is in a first switch state, the second switch is in a second switch state, the first test point, the first switch, the first matching circuit, the chip under test, the second switch, and the second test point are connected to form a first test path; When testing using a second frequency band radio frequency signal, the control circuit inputs a second control signal to the first switch and the second switch, the first switch is in a third switch state, the second switch is in a fourth switch state, the first test point, the first switch, the second matching circuit, the first matching circuit, the chip under test, the second switch, the third matching circuit, and the second test point are connected to form a second test path.

11. A chip, characterized in that: The test circuit comprises the test circuit according to any one of claims 1 to 9.

12. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 11.

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