FPGA chip test method, device and system and storage medium

Abstract

The invention discloses an FPGA chip testing method, device and system and a storage medium. The method comprises the steps that first testing configuration data, first testing excitation data and reference testing response data of an FPGA chip in a first testing mode are acquired; configuring the FPGA chip according to the first test configuration data; executing a function corresponding to the first test configuration data based on the first test excitation data through the FPGA chip to obtain first test response data; determining a first deviation degree between the reference test response data and the first test response data; when the first deviation degree is in a first preset range, determining that the FPGA chip passes the test; and when the first deviation degree is not in the first preset range, determining that the FPGA chip test is not passed. By adopting the method and the device, the test intelligence of the FPGA chip can be improved, so that the performance of the FPGA chip is ensured.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a method, device, system and storage medium for testing an FPGA chip. Background Art

[0002] With the rapid development of electronic information technology, the use of Field-Programmable Gate Array (FPGA) chips has become increasingly popular. In addition, in actual use, users have increasingly higher performance requirements for FPGA chips. Therefore, the problem of how to improve the test intelligence of FPGA chips needs to be solved urgently. Summary of the Invention

[0003] The embodiments of the present application provide an FPGA chip testing method, device, system and storage medium, which can improve the testing intelligence of FPGA chips to ensure the performance of FPGA chips.

[0004] In a first aspect, an embodiment of the present application provides a method for testing an FPGA chip, which is applied to an electronic device, wherein the electronic device includes an FPGA chip. The method includes:

[0005] Acquire first test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode;

[0006] Configuring the FPGA chip according to the first test configuration data;

[0007] Executing, by the FPGA chip, a function corresponding to the first test configuration data based on the first test stimulus data, to obtain first test response data;

[0008] determining a first degree of deviation between the reference test response data and the first test response data;

[0009] When the first deviation is within a first preset range, determining that the FPGA chip test has passed;

[0010] When the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed.

[0011] In a second aspect, an embodiment of the present application provides an FPGA chip testing device, which is applied to an electronic device, wherein the electronic device includes an FPGA chip, and the device includes: an acquisition unit, a configuration unit, an execution unit, and a determination unit, wherein:

[0012] The acquisition unit is used to acquire first test configuration data, first test stimulus data and reference test response data of the FPGA chip in a first test mode;

[0013] The configuration unit is configured to configure the FPGA chip according to the first test configuration data;

[0014] The execution unit is configured to execute a function corresponding to the first test configuration data based on the first test stimulus data through the FPGA chip to obtain first test response data;

[0015] The determination unit is used to determine a first deviation between the reference test response data and the first test response data; when the first deviation is within a first preset range, it is determined that the FPGA chip test has passed; when the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed.

[0016] In a third aspect, an embodiment of the present application provides an FPGA chip testing system, which includes the FPGA chip testing device described in the second aspect.

[0017] In a fourth aspect, an embodiment of the present application provides an electronic device comprising a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the program comprises instructions for executing the steps in the first aspect of the embodiment of the present application.

[0018] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the above-mentioned computer-readable storage medium stores a computer program for electronic data exchange, wherein the above-mentioned computer program enables a computer to execute some or all of the steps described in the first aspect of the embodiment of the present application.

[0019] In a sixth aspect, embodiments of the present application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, wherein the computer program is operable to cause a computer to execute some or all of the steps described in the first aspect of the embodiments of the present application. The computer program product may be a software installation package.

[0020] The implementation of the embodiments of the present application has the following beneficial effects:

[0021] It can be seen that the FPGA chip testing method, device, system and storage medium described in the embodiments of the present application are applied to an electronic device, which includes an FPGA chip, obtains first test configuration data, first test stimulus data and reference test response data of the FPGA chip in a first test mode, configures the FPGA chip according to the first test configuration data, executes a function corresponding to the first test configuration data based on the first test stimulus data by the FPGA chip, obtains first test response data, determines a first deviation between the reference test response data and the first test response data, and determines that the FPGA chip test has passed when the first deviation is within a first preset range, and determines that the FPGA chip test has failed when the first deviation is not within the first preset range. First, the corresponding test configuration data, test stimulus data and reference test response data can be configured based on a specific test mode, and the FPGA chip is configured with the first test configuration data so that the FPGA chip is deeply configured with the test mode. Second, when the FPGA chip is deeply configured with the test mode, the first deviation between the test data and the reference test response data is determined, and the test result verification is completed based on the first deviation. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 This is a flow chart of an FPGA chip testing method provided in an embodiment of the present application;

[0024] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0025] Figure 3 is a structural diagram of another electronic device provided in an embodiment of the present application;

[0026] Figure 4 This is a block diagram of the functional units of an FPGA chip testing device provided in an embodiment of the present application;

[0027] Figure 5 This is a structural diagram of an FPGA chip testing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0030] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] In the embodiments of the present application, the electronic devices involved may be devices with testing capabilities, and the electronic devices may include various handheld devices with wireless communication functions, wearable devices (smart glasses, smart bracelets, Internet of Things devices (such as smart refrigerators, smart washing machines, smart TVs), smart watches, etc.), vehicle-mounted devices, computing devices or other processing devices connected to wireless modems, as well as various forms of user equipment (UE), mobile stations (MS), terminal devices, test equipment, etc.

[0032] In a specific implementation, the electronic device may further include an FPGA chip, and the electronic device may be understood as a test device for testing the FPGA chip.

[0033] The following is a detailed introduction to the embodiments of the present application.

[0034] See also Figure 1 , Figure 1This is a flow chart of an FPGA chip testing method provided in an embodiment of the present application, which is applied to an electronic device including an FPGA chip. The FPGA chip testing method includes:

[0035] 101. Obtain first test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode.

[0036] In the embodiment of this application, Figure 2 As shown, the electronic device may include an FPGA chip, and different test modes may correspond to test configuration data. The test configuration data may include at least one of the following: hardware environment configuration data, software environment configuration data, specified program configuration data, etc., which are not limited here.

[0037] Among them, the hardware environment configuration data may include at least one of the following: hardware resource scheduling configuration data, hardware running score, hardware mode configuration, etc., which are not limited here.

[0038] Among them, the software environment configuration data may include at least one of the following: operating system configuration data, software resource scheduling configuration data, software version, cache configuration data, memory configuration data, protocol configuration data, application interface configuration data, network configuration data, etc., which are not limited here.

[0039] Among them, the specified program configuration data can be pre-set or system default, and the specified program configuration data corresponding to different test cases in different test modes may be different. The specified program configuration data is used to implement corresponding functions in the FPGA chip based on the stimulus data to generate corresponding test response data.

[0040] In a specific implementation, a mapping relationship between preset test modes and test configuration data may be pre-stored, and then, the first test configuration data corresponding to the first test mode may be determined based on the mapping relationship.

[0041] Among them, the mapping relationship between the test mode and the test stimulus data can be pre-tested, and then the first test stimulus data corresponding to the first test mode can be determined based on the mapping relationship. Of course, different test stimulus data correspond to different test response data, that is, the test stimulus data and the test response data correspond one to one.

[0042] Among them, the test stimulus data can be understood as test input data, and the test response data can be understood as test output data. The test response data may include the calculation results for the test stimulus data, and / or, after running the test stimulus data, obtain the test duration of the test response data, and / or, after running the test stimulus data, obtain the resource changes generated by the test response data.

[0043] 102. Configure the FPGA chip according to the first test configuration data.

[0044] In an embodiment of the present application, the FPGA chip can be configured according to the first test configuration data so that the FPGA chip conforms to the test environment corresponding to the first test mode. Specifically, the hardware environment configuration data and the software environment configuration data can be made to conform to the first test mode, and the specified program configuration data can be burned into the FPGA chip.

[0045] 103. Execute, by the FPGA chip, a function corresponding to the first test configuration data based on the first test stimulus data to obtain first test response data.

[0046] In an embodiment of the present application, the FPGA chip can execute a function corresponding to the first test configuration data once or multiple times based on the first test stimulus data to obtain first test response data, and the first test response data may include one or more test response data.

[0047] 104. Determine a first deviation between the reference test response data and the first test response data.

[0048] In a specific implementation, for example, when the first test response data represents a single test and includes a single test result, the first deviation = (first test response data - reference test response data) / reference test response data.

[0049] 105. When the first deviation is within a first preset range, determine that the FPGA chip test passes.

[0050] The first preset range can be pre-set or set by the system default. Different test modes may correspond to different preset ranges, depending on the actual situation. In a specific implementation, a mapping relationship between the test mode and the preset range can be pre-set, and then the first preset range corresponding to the first test mode can be determined based on the mapping relationship.

[0051] In a specific implementation, when the first deviation is within a first preset range, it indicates that the test result is normal, and it is determined that the FPGA chip test has passed.

[0052] 106. When the first deviation is not within the first preset range, determine that the FPGA chip test has failed.

[0053] In a specific implementation, when the first deviation is not within the first preset range, it indicates that the test result deviates from the normal situation, and it is determined that the FPGA chip test has failed.

[0054] Optionally, the first test response data includes n test response data, where n is an integer greater than 1; the above step 104, determining the first deviation between the reference test response data and the first test response data, can be implemented as follows:

[0055] Determine the mean of the n test response data to obtain a first mean;

[0056] Determine the standard deviation of the n test response data to obtain a first standard deviation;

[0057] When the first standard deviation is less than or equal to a first preset standard deviation, the first degree of deviation is determined according to the first mean and the reference test response data.

[0058] In a specific implementation, the first test response data may include n test response data, where n is an integer greater than 1. Of course, when each of the n test response data includes multiple data, a weight of each of the multiple data may be determined to obtain multiple weights, the sum of which is 1. A weighted operation is then performed on the multiple data and the multiple weights to obtain fused test response data, which can reflect the overall test situation.

[0059] In a specific implementation, the mean of n test response data may be determined to obtain a first mean, which reflects the central tendency of the test data.

[0060] Next, the standard deviation of the n test response data may be determined to obtain a first standard deviation, which reflects the stability of the FPGA chip.

[0061] Among them, the first preset standard deviation can be pre-set or system default. When the first standard deviation is less than or equal to the first preset standard deviation, it means that the FPGA stability is good, and the first deviation can be determined based on the first mean and the reference test response data, that is, the first deviation = (first mean - reference test response data) / reference test response data. In this way, not only can the test results be used to detect the stability of the FPGA chip, but also the corresponding first deviation can be determined when the stability of the FPGA chip meets the requirements, thereby helping to complete the test result verification based on the first deviation. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0062] Optionally, the following steps may also be included:

[0063] When the first standard deviation is greater than the first preset standard deviation and less than the second preset standard deviation, obtaining a recording time corresponding to each test response data in the n test response data to obtain n recording times; the first preset standard deviation is less than the second preset standard deviation;

[0064] Determining a fitted response straight line according to the n recorded moments and the n test response data;

[0065] Determining first limit test response data and second limit test response data based on the first preset range and the reference test response data; the first limit test response data is smaller than the second limit test response data, the first limit test response data corresponds to the lower limit threshold of the first preset range, and the second limit test response data corresponds to the upper limit threshold of the first preset range;

[0066] Predicting a first position corresponding to the first extreme test response data and a second position corresponding to the second extreme test response data in the fitted response line;

[0067] determining a first duration between the first position and the second position;

[0068] Determine the test durations corresponding to the n test response data to obtain n test durations;

[0069] Determining an average test duration of the n test durations;

[0070] When the ratio between the first duration and the average test duration is greater than a preset ratio, the step of determining the first deviation according to the first mean value and the reference test response data is performed.

[0071] Among them, the first preset standard deviation is smaller than the second preset standard deviation. When the first standard deviation is greater than the first preset standard deviation and smaller than the second preset standard deviation, it indicates that the stability of the FPGA is general. Then, the recording time corresponding to each test response data in the n test response data can be obtained to obtain n recording times. That is, during each test process, when the test response data is obtained, the generation time of the test response data can be recorded to obtain the corresponding recording time.

[0072] Next, a fitting response line is determined based on the n recording moments and the n test response data. That is, since each test response data and its corresponding recording moment can be regarded as a coordinate point, the n recording moments and the n test response data can be regarded as n coordinate points. Then, fitting is performed based on the n coordinate points to obtain a fitting response line, where the horizontal axis of the fitting response line is time and the vertical axis is response data.

[0073] Accordingly, since the first preset range includes an upper threshold and a lower threshold, and the lower threshold is less than the upper threshold, the first and second extreme test response data can be determined based on the first preset range and the reference test response data. The first extreme test response data is less than the second extreme test response data, and the first extreme test response data corresponds to the lower threshold of the first preset range, while the second extreme test response data corresponds to the upper threshold of the first preset range. For example, (first extreme test response data - reference test response data) / reference test response data = the lower threshold. Accordingly, (second extreme test response data - reference test response data) / reference test response data = the upper threshold. By reverse calculation, the corresponding first and second extreme test response data can be obtained.

[0074] Next, the first position corresponding to the first extreme test response data and the second position corresponding to the second extreme test response data can be predicted in the fitting response line, and then the first duration between the first position and the second position can be determined. The first position and the second position can be understood as two coordinate points. The first duration reflects the durability and robustness of the FPGA chip to a certain extent. Then, the test duration corresponding to n test response data (that is, the test duration of n tests) can be determined to obtain n test durations, and then the average of the n test durations is determined to obtain the average test duration. When the ratio between the first duration and the average test duration is greater than the preset ratio, it means that the durability and robustness of the FPGA chip meet the test requirements, and then the step of determining the first deviation based on the first mean and the reference test response data can be executed. Then, not only can the FPGA chip test depth be guaranteed, but the durability and robustness of the FPGA chip can also be deeply detected, and it is helpful to complete the test result verification based on the first deviation. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0075] Of course, when the ratio between the first duration and the average test duration is less than or equal to the preset ratio, it means that the durability and robustness of the FPGA chip do not meet the test requirements, and it is determined that the FPGA chip test has failed. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0076] Optionally, the following steps may be included:

[0077] When the first standard deviation is greater than or equal to the second preset standard deviation, it is determined that the FPGA chip test has failed.

[0078] In an embodiment of the present application, when the first standard deviation is greater than or equal to the second preset standard deviation, it indicates that the stability of the FPGA chip is poor, and it is determined that the FPGA chip test has failed. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0079] Optionally, the following steps may also be included:

[0080] Obtaining a start time and an end time of executing a function corresponding to the first test configuration data based on the first test stimulus data;

[0081] Acquire temperature data and current data of the FPGA chip between the start time and the end time;

[0082] Determine a fitted temperature straight line according to the temperature data;

[0083] Obtaining a first slope of the fitted temperature line;

[0084] Determining a fitted current straight line according to the current data;

[0085] Obtaining a second slope of the fitted current straight line;

[0086] When the first slope is within a second preset range and the second slope is within a third preset range, the step of determining a first deviation between the reference test response data and the first test response data is performed.

[0087] In a specific implementation, when the FPGA chip is tested through a single test, the start and end times of executing the function corresponding to the first test configuration data based on the first test stimulus data can be obtained, and then the temperature data and current data of the FPGA chip between the start and end times can be obtained, wherein each temperature data includes multiple temperature values, each temperature value corresponds to a time point, and each current data can also include multiple current values, each current value corresponds to a time point.

[0088] Correspondingly, the temperature data can be regarded as multiple coordinate points, and then fitting is performed based on the multiple coordinate points to obtain a fitted temperature line. The horizontal axis of the fitted temperature line is time and the vertical axis is the temperature value. The first slope of the fitted temperature line is obtained. The first slope reflects the temperature change during a test run, or the first slope reflects the computing power stability of the FPGA chip.

[0089] Correspondingly, the current data can be regarded as multiple coordinate points, and then fitting is performed based on the multiple coordinate points to obtain a fitted current straight line. The horizontal axis of the fitted current straight line is time and the vertical axis is the current value. The second slope of the fitted current straight line is obtained. The second slope reflects the current change during a test run, that is, the second slope reflects the hardware stability of the FPGA chip.

[0090] The second preset range may be preset or set by system default, and the third preset range may be preset or set by system default.

[0091] Next, when the first slope is within the second preset range and the second slope is within the third preset range, it indicates that both the computing power stability of the FPGA chip and the hardware stability of the FPGA chip meet the test requirements. Then, the step of determining the first deviation between the reference test response data and the first test response data can be performed, thereby facilitating the completion of the test result verification based on the first deviation. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0092] Optionally, the following steps may also be included:

[0093] When the first slope is not within the second preset range, determining that the FPGA chip test has failed;

[0094] or,

[0095] When the second slope is not within the third preset range, determining that the FPGA chip test has failed;

[0096] or,

[0097] When the first slope is not within the second preset range and the second slope is not within the third preset range, it is determined that the FPGA chip test has failed.

[0098] In a specific implementation, when the first slope is not within the second preset range, it indicates that the computing power stability of the FPGA does not meet the test requirements, and it is determined that the FPGA chip test has failed. In this way, high-performance testing of the FPGA chip can be guaranteed, thereby improving the test intelligence of the FPGA chip to ensure the performance of the FPGA chip.

[0099] In a specific implementation, when the second slope is not within the third preset range, it indicates that the hardware stability of the FPGA chip does not meet the test requirements, and it is determined that the FPGA chip test has failed. In this way, high-performance testing of the FPGA chip can be guaranteed, thereby improving the test intelligence of the FPGA chip to ensure the performance of the FPGA chip.

[0100] In a specific implementation, when the first slope is not within the second preset range and the second slope is not within the third preset range, it indicates that both the computing power stability of the FPGA chip and the hardware stability of the FPGA chip do not meet the test requirements, and it is determined that the FPGA chip test has failed. In this way, high-performance testing of the FPGA chip can be guaranteed, thereby improving the test intelligence of the FPGA chip to ensure the performance of the FPGA chip.

[0101] It can be seen that the FPGA chip testing method described in the embodiments of the present application is applied to an electronic device, which includes an FPGA chip. First test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode are obtained, the FPGA chip is configured according to the first test configuration data, the FPGA chip executes a function corresponding to the first test configuration data based on the first test stimulus data, obtains first test response data, determines a first deviation between the reference test response data and the first test response data, and determines that the FPGA chip test has passed when the first deviation is within a first preset range. When the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed. First, the corresponding test configuration data, test stimulus data, and reference test response data can be configured based on a specific test mode, and the FPGA chip is configured with the first test configuration data so that the FPGA chip is deeply configured with the test mode. Second, when the FPGA chip is deeply configured with the test mode, the first deviation between the test data and the reference test response data is determined, and the test result verification is completed based on the first deviation. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0102] See also Figure 3 , Figure 3 : is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device includes a processor, a memory, a communication interface, and one or more programs. The one or more programs are stored in the memory and are configured to be executed by the processor. In the embodiment of the present application, the electronic device includes an FPGA chip, and the program includes instructions for performing the following steps:

[0103] Acquire first test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode;

[0104] Configuring the FPGA chip according to the first test configuration data;

[0105] Executing, by the FPGA chip, a function corresponding to the first test configuration data based on the first test stimulus data, to obtain first test response data;

[0106] determining a first degree of deviation between the reference test response data and the first test response data;

[0107] When the first deviation is within a first preset range, determining that the FPGA chip test has passed;

[0108] When the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed.

[0109] Optionally, the first test response data includes n test response data, where n is an integer greater than 1; and in determining the first deviation between the reference test response data and the first test response data, the program includes instructions for performing the following steps:

[0110] Determine the mean of the n test response data to obtain a first mean;

[0111] Determine the standard deviation of the n test response data to obtain a first standard deviation;

[0112] When the first standard deviation is less than or equal to a first preset standard deviation, the first degree of deviation is determined according to the first mean and the reference test response data.

[0113] Optionally, the program further includes instructions for executing the following steps:

[0114] When the first standard deviation is greater than the first preset standard deviation and less than the second preset standard deviation, obtaining a recording time corresponding to each test response data in the n test response data to obtain n recording times; the first preset standard deviation is less than the second preset standard deviation;

[0115] Determining a fitted response straight line according to the n recorded moments and the n test response data;

[0116] Determining first limit test response data and second limit test response data based on the first preset range and the reference test response data; the first limit test response data is smaller than the second limit test response data, the first limit test response data corresponds to the lower limit threshold of the first preset range, and the second limit test response data corresponds to the upper limit threshold of the first preset range;

[0117] Predicting a first position corresponding to the first extreme test response data and a second position corresponding to the second extreme test response data in the fitted response line;

[0118] determining a first duration between the first position and the second position;

[0119] Determine the test durations corresponding to the n test response data to obtain n test durations;

[0120] Determining an average test duration of the n test durations;

[0121] When the ratio between the first duration and the average test duration is greater than a preset ratio, the step of determining the first deviation according to the first mean value and the reference test response data is performed.

[0122] Optionally, the program further includes instructions for executing the following steps:

[0123] When the first standard deviation is greater than or equal to the second preset standard deviation, it is determined that the FPGA chip test has failed.

[0124] Optionally, the program further includes instructions for executing the following steps:

[0125] Obtaining a start time and an end time of executing a function corresponding to the first test configuration data based on the first test stimulus data;

[0126] Acquire temperature data and current data of the FPGA chip between the start time and the end time;

[0127] Determine a fitted temperature straight line according to the temperature data;

[0128] Obtaining a first slope of the fitted temperature line;

[0129] Determining a fitted current straight line according to the current data;

[0130] Obtaining a second slope of the fitted current straight line;

[0131] When the first slope is within a second preset range and the second slope is within a third preset range, the step of determining a first deviation between the reference test response data and the first test response data is performed.

[0132] Optionally, the program further includes instructions for executing the following steps:

[0133] When the first slope is not within the second preset range, determining that the FPGA chip test has failed;

[0134] or,

[0135] When the second slope is not within the third preset range, determining that the FPGA chip test has failed;

[0136] or,

[0137] When the first slope is not within the second preset range and the second slope is not within the third preset range, it is determined that the FPGA chip test has failed.

[0138] It can be seen that the FPGA chip testing method described in the embodiments of the present application is applied to an electronic device, which includes an FPGA chip. First test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode are obtained, the FPGA chip is configured according to the first test configuration data, the FPGA chip executes a function corresponding to the first test configuration data based on the first test stimulus data, obtains first test response data, determines a first deviation between the reference test response data and the first test response data, and determines that the FPGA chip test has passed when the first deviation is within a first preset range. When the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed. First, the corresponding test configuration data, test stimulus data, and reference test response data can be configured based on a specific test mode, and the FPGA chip is configured with the first test configuration data so that the FPGA chip is deeply configured with the test mode. Second, when the FPGA chip is deeply configured with the test mode, the first deviation between the test data and the reference test response data is determined, and the test result verification is completed based on the first deviation. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0139] Figure 4 This is a functional unit block diagram of an FPGA chip testing device 400 involved in an embodiment of the present application. The FPGA chip testing device 400 is applied to an electronic device, and the electronic device includes an FPGA chip. The FPGA chip testing device 400 includes: an acquisition unit 401, a configuration unit 402, an execution unit 403, and a determination unit 404, wherein:

[0140] The acquisition unit 401 is configured to acquire first test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode;

[0141] The configuration unit 402 is configured to configure the FPGA chip according to the first test configuration data;

[0142] The execution unit 403 is configured to execute a function corresponding to the first test configuration data based on the first test stimulus data through the FPGA chip to obtain first test response data;

[0143] The determination unit 404 is used to determine a first deviation between the reference test response data and the first test response data; when the first deviation is within a first preset range, it is determined that the FPGA chip test has passed; when the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed.

[0144] Optionally, the first test response data includes n test response data, where n is an integer greater than 1; in determining the first deviation between the reference test response data and the first test response data, the determining unit 404 is specifically configured to:

[0145] Determine the mean of the n test response data to obtain a first mean;

[0146] Determine the standard deviation of the n test response data to obtain a first standard deviation;

[0147] When the first standard deviation is less than or equal to a first preset standard deviation, the first degree of deviation is determined according to the first mean and the reference test response data.

[0148] Optionally, the FPGA chip testing device 400 is further specifically configured to:

[0149] When the first standard deviation is greater than the first preset standard deviation and less than the second preset standard deviation, obtaining a recording time corresponding to each test response data in the n test response data to obtain n recording times; the first preset standard deviation is less than the second preset standard deviation;

[0150] Determining a fitted response straight line according to the n recorded moments and the n test response data;

[0151] Determining first limit test response data and second limit test response data based on the first preset range and the reference test response data; the first limit test response data is smaller than the second limit test response data, the first limit test response data corresponds to the lower limit threshold of the first preset range, and the second limit test response data corresponds to the upper limit threshold of the first preset range;

[0152] Predicting a first position corresponding to the first extreme test response data and a second position corresponding to the second extreme test response data in the fitted response line;

[0153] determining a first duration between the first position and the second position;

[0154] Determine the test durations corresponding to the n test response data to obtain n test durations;

[0155] Determining an average test duration of the n test durations;

[0156] When the ratio between the first duration and the average test duration is greater than a preset ratio, the step of determining the first deviation according to the first mean value and the reference test response data is performed.

[0157] Optionally, the FPGA chip testing device is further specifically used for:

[0158] When the first standard deviation is greater than or equal to the second preset standard deviation, it is determined that the FPGA chip test has failed.

[0159] Optionally, the FPGA chip testing device 400 is further specifically configured to:

[0160] Obtaining a start time and an end time of executing a function corresponding to the first test configuration data based on the first test stimulus data;

[0161] Acquire temperature data and current data of the FPGA chip between the start time and the end time;

[0162] Determine a fitted temperature straight line according to the temperature data;

[0163] Obtaining a first slope of the fitted temperature line;

[0164] Determining a fitted current straight line according to the current data;

[0165] Obtaining a second slope of the fitted current straight line;

[0166] When the first slope is within a second preset range and the second slope is within a third preset range, the step of determining a first deviation between the reference test response data and the first test response data is performed.

[0167] Optionally, the FPGA chip testing device 400 is further specifically configured to:

[0168] When the first slope is not within the second preset range, determining that the FPGA chip test has failed;

[0169] or,

[0170] When the second slope is not within the third preset range, determining that the FPGA chip test has failed;

[0171] or,

[0172] When the first slope is not within the second preset range and the second slope is not within the third preset range, it is determined that the FPGA chip test has failed.

[0173] It can be seen that the FPGA chip testing device described in the embodiment of the present application is applied to an electronic device, which includes an FPGA chip. The device obtains first test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode, configures the FPGA chip according to the first test configuration data, and executes a function corresponding to the first test configuration data based on the first test stimulus data by the FPGA chip to obtain first test response data. A first deviation between the reference test response data and the first test response data is determined. When the first deviation is within a first preset range, it is determined that the FPGA chip test has passed. When the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed. First, the corresponding test configuration data, test stimulus data, and reference test response data can be configured based on a specific test mode, and the FPGA chip can be configured with the first test configuration data so that the FPGA chip is deeply configured with the test mode. Second, when the FPGA chip is deeply configured with the test mode, the first deviation between the test data and the reference test response data is determined, and the test result verification is completed based on the first deviation. In this way, the test intelligence of the FPGA chip can be improved to ensure the performance of the FPGA chip.

[0174] It can be understood that the functions of each program module of the FPGA chip testing device of this embodiment can be specifically implemented according to the method in the above method embodiment. The specific implementation process can refer to the relevant description of the above method embodiment and will not be repeated here.

[0175] Figure 5 This is an FPGA chip test system involved in the embodiment of the present application, and the FPGA chip test system includes the following Figure 4 The FPGA chip testing device shown, the FPGA chip testing system can be used to implement any function of the FPGA chip testing device, and can implement any of the above-mentioned FPGA chip testing methods.

[0176] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any method described in the above method embodiments.

[0177] The present application also provides a computer program product comprising a non-transitory computer-readable storage medium storing a computer program, wherein the computer program is operable to cause a computer to execute some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package.

[0178] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0179] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0180] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0181] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0182] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0183] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the above-mentioned methods of each embodiment of the present application. The aforementioned memory includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0184] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0185] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A FPGA chip testing method, characterized in that: Applied to an electronic device, the electronic device includes an FPGA chip, and the method includes: Acquire first test configuration data, first test stimulus data, and reference test response data of the FPGA chip in a first test mode; Configuring the FPGA chip according to the first test configuration data; Executing, by the FPGA chip, a function corresponding to the first test configuration data based on the first test stimulus data, to obtain first test response data; determining a first degree of deviation between the reference test response data and the first test response data; When the first deviation is within a first preset range, determining that the FPGA chip test has passed; When the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed.

2. The method according to claim 1, characterized in that The first test response data includes n test response data, where n is an integer greater than 1; and determining a first deviation between the reference test response data and the first test response data includes: Determine the mean of the n test response data to obtain a first mean; Determine the standard deviation of the n test response data to obtain a first standard deviation; When the first standard deviation is less than or equal to a first preset standard deviation, the first degree of deviation is determined according to the first mean and the reference test response data.

3. The method according to claim 2, characterized in that The method further comprises: When the first standard deviation is greater than the first preset standard deviation and less than the second preset standard deviation, obtaining a recording time corresponding to each test response data in the n test response data to obtain n recording times; the first preset standard deviation is less than the second preset standard deviation; Determining a fitted response straight line according to the n recorded moments and the n test response data; Determining first limit test response data and second limit test response data based on the first preset range and the reference test response data; the first limit test response data is smaller than the second limit test response data, the first limit test response data corresponds to the lower limit threshold of the first preset range, and the second limit test response data corresponds to the upper limit threshold of the first preset range; Predicting a first position corresponding to the first extreme test response data and a second position corresponding to the second extreme test response data in the fitted response line; determining a first duration between the first position and the second position; Determine the test durations corresponding to the n test response data to obtain n test durations; Determining an average test duration of the n test durations; When the ratio between the first duration and the average test duration is greater than a preset ratio, the step of determining the first deviation according to the first mean value and the reference test response data is performed.

4. The method according to claim 3, characterized in that The method further comprises: When the first standard deviation is greater than or equal to the second preset standard deviation, it is determined that the FPGA chip test has failed.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Obtaining a start time and an end time of executing a function corresponding to the first test configuration data based on the first test stimulus data; Acquire temperature data and current data of the FPGA chip between the start time and the end time; Determine a fitted temperature straight line according to the temperature data; Obtaining a first slope of the fitted temperature line; Determining a fitted current straight line according to the current data; Obtaining a second slope of the fitted current straight line; When the first slope is within a second preset range and the second slope is within a third preset range, the step of determining a first deviation between the reference test response data and the first test response data is performed.

6. The method according to claim 5, characterized in that The method further comprises: When the first slope is not within the second preset range, determining that the FPGA chip test has failed; or, When the second slope is not within the third preset range, determining that the FPGA chip test has failed; or, When the first slope is not within the second preset range and the second slope is not within the third preset range, it is determined that the FPGA chip test has failed.

7. An FPGA chip testing device, characterized in that: Applied to electronic equipment, the electronic equipment includes an FPGA chip, the device includes: an acquisition unit, a configuration unit, an execution unit, and a determination unit, wherein: The acquisition unit is used to acquire first test configuration data, first test stimulus data and reference test response data of the FPGA chip in a first test mode; The configuration unit is configured to configure the FPGA chip according to the first test configuration data; The execution unit is configured to execute a function corresponding to the first test configuration data based on the first test stimulus data through the FPGA chip to obtain first test response data; The determination unit is used to determine a first deviation between the reference test response data and the first test response data; when the first deviation is within a first preset range, it is determined that the FPGA chip test has passed; when the first deviation is not within the first preset range, it is determined that the FPGA chip test has failed.

8. An FPGA chip testing system, characterized in that: The FPGA chip testing system includes the FPGA chip testing device as described in claim 7.

9. An electronic device, characterized in that: The method comprises a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for executing the steps in the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method according to any one of claims 1 to 6.

Images