Vertical pipe short circuit fault detection and identification method in NPP circuit topology

Abstract

The invention discloses a vertical tube short circuit fault detection and identification method in NPP circuit topology, and the method comprises the steps: triggering a grid driver to generate a fault signal with a fixed time length t3 if the collector-emitter voltage of a vertical tube is lower than a target voltage during the time when the vertical tube is turned off and a horizontal tube is turned on; and when the controller detects the fault signal with the duration of t3, the controller judges that the vertical pipe has a short-circuit fault, and identifies the bit number of the faulted vertical pipe according to the hardware interface address for feeding back the fault signal. Compared with the prior art, the method has the advantages that the short-circuit fault of the standpipe can be detected and the bit number of the faulted standpipe can be identified before the bus straight-through fault, so that the bus straight-through fault can be pre-judged, and fault expansion is avoided. Besides, the gate driver utilizes the monostable trigger to realize that the fault signal is continuous in the monostable time, and the controller can judge that the corresponding vertical pipe has a short-circuit fault when receiving the fault signal and the duration of the fault signal is equal to the monostable time, so that misjudgment can be prevented.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a method for detecting and identifying a riser short-circuit fault in an NPP circuit topology. Background Art

[0002] Current protection technologies for switching devices such as IGBTs, IEGTs, and IGCTs have two major limitations: 1) overcurrent / short-circuit detection is limited to the switch's on-time; 2) overvoltage detection is limited to the switch's off-time. When a switching device short circuits due to non-electrical factors (such as thermal cycling fatigue, package damage, solder failure, bond wire breakage, process failure, or ionization failure) in an NPP topology, the fault can only be detected through a busbar-through fault. This can shorten the device's lifespan and escalate the fault.

[0003] Therefore, the existing technology has the problem that it is unable to effectively detect and identify the short-circuit fault of the switching device in the NPP topology before the busbar through-fault occurs, and thus is unable to pre-judge the busbar through-fault. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for detecting and identifying riser short-circuit faults in an NPP circuit topology, so as to solve the problem in the prior art that the short-circuit faults of switching devices in the NPP topology cannot be effectively detected and identified before the busbar through-fault occurs, and thus the pre-judgment of the busbar through-fault cannot be performed.

[0005] The present invention provides a method for detecting and identifying a riser short-circuit fault in an NPP circuit topology. During the time when the riser is turned off and the horizontal tube is turned on, the method determines whether a short-circuit fault occurs in the riser based on the collector-emitter voltage of the riser, and identifies the position number of the riser when a short-circuit fault occurs in the riser.

[0006] The above-mentioned method for detecting and identifying riser short-circuit faults in an NPP circuit topology determines whether a riser short-circuit fault has occurred based on the riser's collector-emitter voltage during the period when the riser is off and the crossbar is on. It also identifies the position of the riser if a short-circuit fault occurs. Compared to existing technologies, this method can detect riser short-circuit faults and identify the position of the faulty riser before a busbar through-fault occurs, thereby enabling pre-diagnosis of busbar through-faults and preventing them from escalating. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0008] Figure 1 This is a typical NPP circuit topology diagram;

[0009] Figure 2 Schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the riser Hu1 is short-circuited;

[0010] Figure 3 Schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the riser Hu2 is short-circuited;

[0011] Figure 4 Schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the riser Hd1 is short-circuited;

[0012] Figure 5 Schematic diagram of the current path and voltage distribution of a typical NPP circuit topology when the riser Hd2 is short-circuited;

[0013] Figure 6 This is the NPP three-level multi-switch device circuit topology diagram;

[0014] Figure 7 1 is a flow chart of a method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to an embodiment of the present invention;

[0015] Figure 8 1 is an NPP circuit topology in one embodiment of the present invention;

[0016] Figure 9 Schematic diagram of signal flow between a controller and a gate driver in an NPP circuit topology according to an embodiment of the present invention;

[0017] Figure 10 for Figure 7 Flow chart of step S10 in FIG.

[0018] Figure 11 for Figure 7 Schematic diagram of the process of step S20 in ;

[0019] Figure 12 FIG. 1 is an example diagram of fault detection and identification signals when a riser fault occurs during the switching dynamic process of a semiconductor device in one embodiment of the present invention.

[0020] Figure 13 1 is a flow chart of a method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to another embodiment of the present invention;

[0021] Figure 14 Schematic diagram of signal flow between a controller and a gate driver in an NPP circuit topology according to an embodiment of the present invention;

[0022] Figure 15 for Figure 13 Flow chart of step S110 in FIG.

[0023] Figure 16 for Figure 13 Schematic diagram of the flow of step S120 in . DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0025] Figure 1 shows a typical NPP circuit topology, such as Figure 1 As shown, the single-phase bridge arm circuit of the typical NPP circuit topology includes a horizontal pipe b1, a horizontal pipe b2, a vertical pipe Hu1, a vertical pipe Hu2, a vertical pipe Hd1, a vertical pipe Hd2, a first voltage-dividing capacitor C1 and a second voltage-dividing capacitor C2. The horizontal pipes b1 and b2 are connected in series to form a horizontal bridge, the vertical pipes Hu1 and Hu2 are connected in series to form an upper bridge of the vertical bridge, and the vertical pipes Hd1 and Hd2 are connected in series to form a lower bridge of the vertical bridge. One end of the vertical bridge is connected to the positive electrode BUS+ of the DC power supply, and the other end of the vertical bridge is connected to the negative electrode BUS- of the DC power supply. The first voltage-dividing capacitor C1 and the second voltage-dividing capacitor C2 are connected in series and then connected between the positive electrode and the negative electrode of the DC power supply. O1 is the series connection point of the upper bridge and the lower bridge, connected to the output end, O2 is the series connection point of the first voltage-dividing capacitor C1 and the second voltage-dividing capacitor C2, and the horizontal bridge is connected between O1 and O2. The horizontal pipe b1, horizontal pipe b2, vertical pipe Hu1, vertical pipe Hu2, vertical pipe Hd1, and vertical pipe Hd2 are all semiconductor devices, each of which has an anti-parallel diode. The semiconductor devices include but are not limited to IGBT, IEGT, and IGCT.

[0026] Figure 2 The figure shows the current path and voltage distribution of a typical NPP circuit topology when the riser Hu1 is short-circuited.

[0027] Figure 2As shown in the figure, "0" indicates that the switch device is turned off, and "1" indicates that the switch device is turned on. When a short-circuit fault occurs in the riser Hu1 during the process from turning on to turning off, the fault cannot be detected. When the cross pipes b1 and b2 are turned on, regardless of whether the current is flowing out or in, the voltage at the end of the riser Hu1 is zero, and the riser Hu2 is subjected to half the bus voltage Vdc / 2. The risers Hd1 and Hd2 are jointly subjected to half the bus voltage Vdc / 2. When the risers Hd1 and Hd2 are turned on, the riser Hu2 will fail due to being subjected to the full bus voltage Vdc, inducing a bus through fault.

[0028] Figure 3 The current path and voltage distribution of a typical NPP circuit topology when the riser Hu2 is short-circuited are shown.

[0029] Figure 3 As shown in the figure, when a short-circuit fault occurs in riser Hu2 during the process from opening to closing, the fault cannot be detected. When cross pipes b1 and b2 are opened, regardless of whether the current is flowing out or in, the voltage at the end of riser Hu2 is zero, and riser Hu1 bears half the bus voltage Vdc / 2. Riser Hd1 and riser Hd2 bear half the bus voltage Vdc / 2 together. When risers Hd1 and Hd2 are opened, riser Hu1 will fail due to bearing the full bus voltage Vdc, inducing a bus through fault.

[0030] Figure 4 The figure shows the current path and voltage distribution of a typical NPP circuit topology when the riser Hd1 is short-circuited.

[0031] Figure 4 As shown in the figure, when a short-circuit fault occurs in riser Hd1 during the process from opening to closing, the fault cannot be detected. When cross pipes b1 and b2 are opened, regardless of whether the current is flowing out or in, the voltage at the end of riser Hd1 is zero, and riser Hd2 bears half the bus voltage Vdc / 2. Riser Hu1 and riser Hu2 bear half the bus voltage Vdc / 2 together. When riser Hu1 and riser Hu2 are opened, riser Hd2 will fail due to bearing the full bus voltage Vdc, inducing a bus through fault.

[0032] Figure 5 The figure shows the current path and voltage distribution of a typical NPP circuit topology when the riser Hd2 is short-circuited.

[0033] Figure 5As shown in the figure, when a short-circuit fault of riser Hd2 occurs between the opening and closing process, the fault cannot be detected. When cross pipes b1 and b2 are opened, regardless of whether the current is flowing out or in, the voltage at the end of riser Hd2 is zero, and riser Hd1 bears half the bus voltage Vdc / 2. Riser Hu1 and riser Hu2 both bear half the bus voltage Vdc / 2. When riser Hu1 and riser Hu2 are opened, riser Hd1 will fail due to bearing the full bus voltage Vdc, inducing a bus through fault.

[0034] From the above, it can be seen that when a short circuit fault occurs in the risers (riser Hu1, riser Hu2, riser Hd1, riser Hd2) in the typical NPP circuit topology, a busbar through fault will be induced.

[0035] Figure 6 The NPP three-level multi-switch device circuit topology is shown. In this circuit topology, the number of vertical pipes is greater than 4, and the number of horizontal pipes is greater than 2. Figure 6 As shown, risers Hu1 through Tun are connected in series to form the upper bridge of the vertical bridge arm circuit, risers Hd1 through Tdn are connected in series to form the lower bridge arm of the vertical bridge arm circuit, and crossbars b1 through bn are connected in series to form the crossbar arm of the bridge arm circuit. When a short circuit occurs in the risers (Hu1 through Tun, Hd1 through Tdn) in the NPP three-level multi-switch device circuit topology, a busbar shoot-through fault can also be induced.

[0036] In summary, when a short-circuit fault occurs in a riser in an NPP circuit topology, a busbar through-fault will be induced. Based on this, it is possible to determine whether a short-circuit fault occurs in the riser by detecting the collector-emitter voltage of the riser during the opening of the cross-tube, and to implement pre-judgment of a busbar through-fault based on the fault judgment result.

[0037] The present invention provides a method for detecting and identifying riser short-circuit faults in an NPP circuit topology. This method is applicable to NPP circuit topologies with four or more risers. During the time between the riser being off and the crossbar being on, the method determines whether a riser short-circuit fault has occurred based on the riser's collector-emitter voltage. If a riser short-circuit fault occurs, the position of the riser is identified. This method can detect riser short-circuit faults and identify the position of the faulty riser before a busbar through-fault occurs, thereby enabling pre-diagnosis of busbar through-faults and preventing them from escalating.

[0038] Figure 7 FIG1 shows a flow chart of a method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to an embodiment of the present invention. Figure 7 As shown, the method for detecting and identifying a riser short circuit fault in an NPP circuit topology in this embodiment includes steps S10 to S20:

[0039] S10: After the riser is turned off for t1, within t2, if the collector-emitter voltage of the riser is detected to be lower than the preset target voltage, the gate driver triggers the generation of a fault signal with a fixed duration of t3;

[0040] S20: When the controller detects the fault signal with a duration of t3, it determines that a short circuit fault occurs in the riser, and identifies the position number of the faulty riser according to the hardware interface address of the feedback fault signal.

[0041] The settings of t1 and t2 ensure that the cross pipe is open, that is, to ensure that short-circuit fault detection of the riser pipe occurs during the time between the riser pipe being closed and the cross pipe being open. T1 is greater than or equal to the dead time between the riser and cross pipes and less than the minimum pulse width of the cross pipe. T2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the cross pipe.

[0042] like Figure 8 As shown, the gates of the horizontal tube and the vertical tube in the NPP circuit topology are both connected to a gate driver, and the gate driver is connected to a controller.

[0043] like Figure 9 As shown, the gate driver includes a drive module, a switch state identification module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module, a gate circuit module, and a monostable trigger; the controller includes a PWM signal module, a fault detection module, and a fault identification module. The drive module is used to drive the riser on and off; the switch state identification module is used to identify the switch state of the riser; the delay module is used to enable the gate circuit module for a period of time t2 after the riser is turned off for a period of time t1; the collector-emitter voltage detection module is used to detect the collector-emitter voltage of the riser, which is obtained by resistor voltage division; the target voltage module is used to provide a target voltage, which is obtained by resistor voltage division, and the amplitude of the target voltage is set accordingly according to the bus voltage; the comparator module is used to compare the collector-emitter voltage of the riser with the target voltage; the gate circuit module is used to enable the monostable trigger, which connects the delay module and the comparator module; and the monostable trigger is used to generate a fault signal with a fixed monostable duration of t3, so that the controller can identify whether a short circuit fault has occurred in the riser. The PWM signal module is used to generate a PWM switching signal, which is the original signal for driving semiconductor devices. The input of the fault detection module is connected to the gate driver, and the output is connected to the fault identification module and the PWM signal module. When the gate driver feeds back a fault signal, the fault detection module needs to immediately detect the fault, execute the fault processing logic, and obtain the hardware interface address of the feedback fault signal at the same time, and send the fault signal and the obtained hardware interface address to the fault identification module.

[0044] like Figure 10As shown, in one embodiment, step S10, i.e., after the riser is turned off for time t1, within time t2, if it is detected that the collector-emitter voltage of the riser is lower than a preset target voltage, the gate driver triggers the generation of a fault signal with a fixed duration of t3, includes steps S11 to S15:

[0045] S11: The driving module generates a driving signal according to the PWM switching signal output by the controller to drive the vertical pipe to turn off. Specifically, the driving module generates a driving signal according to the PWM switching signal output by the controller to drive the vertical pipe of the upper bridge or the lower bridge in the vertical bridge to turn off.

[0046] S12: The switch state identification module identifies the switch state of the riser according to the driving signal and outputs a standpipe switch state signal.

[0047] S13: The comparator module compares the vertical tube collector-emitter voltage obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module, and outputs a first enable signal when the vertical tube collector-emitter voltage is lower than the target voltage. Specifically, the comparator module compares the vertical tube collector-emitter voltage obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module. When the vertical tube collector-emitter voltage is lower than the target voltage, the comparator module outputs a high level, enabling the gate circuit module; when the vertical tube collector-emitter voltage is greater than or equal to the target voltage, the comparator module outputs a low level, disabling the gate circuit module.

[0048] S14: The delay module receives the riser switch status signal and outputs a second enable signal for a duration of t2 after the riser is turned off for a duration of t1. Specifically, the delay module outputs a high level for a duration of t2 after the riser is turned off for a duration of t1, enabling the gate circuit module. After the duration of t2, the delay module outputs a negative level, disabling the gate circuit module.

[0049] S15: Upon receiving the first enable signal and the second enable signal simultaneously, the gate circuit module enables the monostable trigger, which triggers the generation and output of a fault signal with a fixed duration of t3. Specifically, the gate circuit module outputs a high level to enable the monostable trigger only when the delay module and the comparator module are simultaneously enabled, causing the monostable trigger to generate and output a fault signal with a fixed monostable duration of t3. The specific duration of t3 can be set as needed.

[0050] like Figure 11 As shown, in one embodiment, step S20, i.e., when the controller detects a fault signal with a duration of t3, determines that a short circuit fault occurs in the riser, and identifies the position number of the faulty riser according to the hardware interface address of the feedback fault signal, includes steps S21 to S22:

[0051] S21: When receiving the fault signal fed back by the gate driver, the fault detection module obtains the hardware interface address of the fed back fault signal, and sends the fault signal and the obtained hardware interface address to the fault identification module.

[0052] S22: Upon detecting that the fault signal has a duration of t3, the fault identification module determines that a short circuit fault has occurred in the riser, and identifies the position number of the faulty riser based on the hardware interface address. Specifically, after receiving the fault signal, the fault identification module further detects whether the fault signal has a duration of t3. If so, the riser is determined to have a short circuit fault; otherwise, the riser fault is determined to be another fault. The controller connects to the gate drivers of different semiconductor devices via different hardware interfaces, and different hardware interfaces correspond to different semiconductor devices. Therefore, the fault identification module can identify the position number of the faulty riser based on the hardware interface address of the feedback fault signal.

[0053] See again Figure 11 In a preferred embodiment, step S20 further includes the following steps:

[0054] S23: The fault identification module sends the fault type and number of the faulty riser to the human-machine interface. Specifically, the fault identification module sends the fault type and number of the faulty riser to the human-machine interface, which displays the fault type and number of the faulty riser on the human-machine interface, thereby pre-diagnosing and identifying the NPP circuit topology busbar through-fault.

[0055] In a preferred embodiment, the step S21 further includes: when the fault detection module receives the fault signal fed back by the gate driver, executing the fault processing logic, and controlling the PWM signal module to stop outputting the PWM switch signal to the corresponding riser.

[0056] Figure 12 An example diagram of fault detection and identification signals for a riser fault occurring during the switching dynamics of a semiconductor device.

[0057] like Figure 12As shown, the vertical tube switch state changes from off to on and then to off as a cycle. When the vertical tube is off, the horizontal tube is turned on, the vertical tube collector-emitter voltage is greater than the target voltage, the gate driver short-circuit fault signal is not enabled, and short-circuit fault detection is not performed under this working condition; after the horizontal tube is turned off and the dead time is delayed, the vertical tube is turned on. During this process, the vertical tube collector-emitter voltage is uncertain, which is determined by the change of load current. At this time, the gate driver short-circuit fault signal is not enabled, and short-circuit fault detection is not performed under this working condition; after the vertical tube is turned on, the horizontal tube must be turned off, and the vertical tube collector-emitter voltage is approximately equal to zero. At this time, the gate driver short-circuit fault signal is not enabled, and short-circuit fault detection is not performed under this working condition; the vertical tube switches from on to off, and the horizontal tube passes through the dead time It is then turned on. During this process, the collector-emitter voltage of the vertical tube is uncertain and is determined by the change of the load current. At this time, the short-circuit fault signal of the gate driver is not enabled, and short-circuit fault detection is not performed under this working condition. When the vertical tube is turned off and delayed for t1 time, t1 must be greater than or equal to the dead time and less than the minimum pulse width of the horizontal tube. At this time, the horizontal tube must be in the on state, and the gate driver short-circuit fault signal is enabled. To ensure that the horizontal tube is in the on state, the time t2 is limited. The time t2 is between t1 time and within the minimum pulse width of the horizontal tube. The collector-emitter voltage of the vertical tube is detected. If the collector-emitter voltage of the vertical tube is lower than the target voltage, it means that the vertical tube has a short-circuit fault. The gate driver uses a monostable trigger to realize that the fault signal lasts for t3 time. The controller receives the fault signal fed back by the gate driver, sets the riser fault position signal to 1, and obtains the hardware interface address of the feedback fault signal. When the controller detects that the duration of the fault signal is t3, it determines that a short circuit fault has occurred in the corresponding riser, and identifies the position number of the faulty riser based on the hardware interface address of the feedback fault signal. Finally, the fault type and position number of the faulty riser are sent to the human-machine interface for display, realizing the pre-judgment and fault identification of the busbar through-fault in the NPP circuit topology.

[0058] The method for detecting and identifying riser short-circuit faults in an NPP circuit topology, provided by an embodiment of the present invention, can detect riser short-circuit faults and identify the faulty riser before a busbar through-fault occurs, thereby enabling pre-diagnosis of a busbar through-fault and preventing the fault from escalating. Furthermore, the gate driver utilizes a monostable trigger to ensure that the fault signal persists within the monostable time (t3). After receiving the fault signal, the controller also detects the fault signal's duration. Only when the detected fault signal's duration equals the monostable time can the corresponding riser be determined to have a short-circuit fault, thus preventing misjudgments.

[0059] Figure 13 FIG1 shows a flow chart of a method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to an embodiment of the present invention. Figure 13As shown, the method for detecting and identifying a riser short circuit fault in an NPP circuit topology in this embodiment includes steps S110 to S120:

[0060] S110 : After the riser is turned off for time t1 , within time t2 , if it is detected that the collector-emitter voltage of the riser is lower than a preset target voltage, the gate driver triggers to generate a fault signal.

[0061] S120: When the controller receives the fault signal fed back by the gate driver, it determines that a short circuit fault occurs in the riser, and identifies the position number of the faulty riser according to the hardware interface address of the fed back fault signal.

[0062] The settings of t1 and t2 ensure that the cross pipe is open, that is, to ensure that short-circuit fault detection of the riser pipe occurs during the time between the riser pipe being closed and the cross pipe being open. T1 is greater than or equal to the dead time between the riser and cross pipes and less than the minimum pulse width of the cross pipe. T2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the cross pipe.

[0063] The method for detecting and identifying a riser short circuit fault in an NPP circuit topology in this embodiment is applied to an NPP circuit topology. The gates of the horizontal and vertical pipes in the NPP circuit topology are both connected to a gate driver, which is connected to a controller.

[0064] like Figure 14 As shown, the gate driver includes a driving module, a switch state identification module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module, and a gate circuit module; the controller includes a PWM signal module, a fault detection module, and a fault identification module. The specific definitions of the various modules within the gate driver and controller in this embodiment can be referred to Figure 9 The specific definitions of the gate driver and the various modules within the controller in the illustrated embodiment are not repeated here.

[0065] like Figure 15 As shown, in one embodiment, the step S110, i.e., after the riser is turned off for time t1, within time t2, if it is detected that the collector-emitter voltage of the riser is lower than a preset target voltage, the gate driver triggers a fault signal, includes steps S111 to S115:

[0066] S111: The driving module generates a driving signal according to the PWM switching signal output by the controller to drive the vertical pipe to turn off. Specifically, the driving module generates a driving signal according to the PWM switching signal output by the controller to drive the vertical pipe of the upper bridge or the lower bridge in the vertical bridge to turn off.

[0067] S112: The switch state identification module identifies the switch state of the riser according to the driving signal and outputs a standpipe switch state signal;

[0068] S113: The comparator module compares the vertical tube collector-emitter voltage obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module, and outputs a first enable signal when the vertical tube collector-emitter voltage is lower than the target voltage. Specifically, the comparator module compares the vertical tube collector-emitter voltage obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module. When the vertical tube collector-emitter voltage is lower than the target voltage, the comparator module outputs a high level, enabling the gate circuit module; when the vertical tube collector-emitter voltage is greater than or equal to the target voltage, the comparator module outputs a low level, disabling the gate circuit module.

[0069] S114: The delay module receives the riser switch status signal and outputs a second enable signal for a duration of t2 after the riser is turned off for a duration of t1. Specifically, the delay module outputs a high level for a duration of t2 after the riser is turned off for a duration of t1, enabling the gate circuit module. After the duration of t2, the delay module outputs a negative level, disabling the gate circuit module.

[0070] S115: When the gate circuit module receives the first enable signal and the second enable signal simultaneously, it enables the gate driver to generate and output a fault signal. Specifically, the gate circuit module can trigger the generation and output of the fault signal only when the delay module and the comparator module are enabled simultaneously.

[0071] like Figure 16 As shown, in one embodiment, step S120, that is, when the controller receives the fault signal fed back by the gate driver, determines that a short circuit fault occurs on the riser, and identifies the position number of the faulty riser according to the hardware interface address of the fed back fault signal, includes steps S121 to S122:

[0072] S121: When receiving the fault signal fed back by the gate driver, the fault detection module obtains the hardware interface address of the fed back fault signal, and sends the fault signal and the obtained hardware interface address to the fault identification module.

[0073] S122: Upon receiving the fault signal, the fault identification module determines that a short circuit fault has occurred in the riser, and identifies the position number of the faulty riser based on the hardware interface address. Specifically, upon receiving the fault signal, the fault identification module determines that a short circuit fault has occurred in the riser; and since the controller is connected to gate drivers of different semiconductor devices via different hardware interfaces, different hardware interfaces correspond to different semiconductor devices. The fault identification module can identify the position number of the faulty riser based on the hardware interface address of the feedback fault signal.

[0074] See again Figure 16 In a preferred embodiment, the step S120 further includes the following steps:

[0075] S123: The fault identification module sends the fault type and number of the faulty riser to the human-machine interface. Specifically, the fault identification module sends the fault type and number of the faulty riser to the human-machine interface, which displays the fault type and number of the faulty riser on the human-machine interface, thereby pre-diagnosing and identifying the NPP circuit topology busbar through-fault.

[0076] In a preferred embodiment, the step S121 further includes: when the fault detection module receives the fault signal fed back by the gate driver, executing the fault processing logic, and controlling the PWM signal module to stop outputting the PWM switch signal to the corresponding riser.

[0077] The method for detecting and identifying riser short-circuit faults in an NPP circuit topology provided by an embodiment of the present invention can detect riser short-circuit faults and identify the position number of the faulty riser before a busbar through-fault occurs, thereby enabling pre-judgment of a busbar through-fault and avoiding fault escalation.

[0078] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A method for detecting and identifying a riser short circuit fault in an NPP circuit topology, characterized in that: During the time when the vertical tube is turned off and the horizontal tube is turned on, it is determined whether a short circuit fault occurs in the vertical tube according to the vertical tube collector-emitter voltage, and the position number of the vertical tube is identified when a short circuit fault occurs in the vertical tube.

2. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 1, wherein: The gates of the horizontal and vertical tubes in the NPP circuit topology are both connected to a gate driver, which is connected to a controller; The method of determining whether a short circuit fault occurs in the vertical tube according to the vertical tube collector-emitter voltage during the time when the vertical tube is turned off and the horizontal tube is turned on, and identifying the position number of the vertical tube when a short circuit fault occurs in the vertical tube, includes: After the riser is turned off for time t1, within time t2, if the collector-emitter voltage of the riser is detected to be lower than the preset target voltage, the gate driver triggers to generate a fault signal; When the controller receives the fault signal fed back by the gate driver, it determines that a short circuit fault has occurred in the riser and identifies the position number of the faulty riser according to the hardware interface address of the feedback fault signal; Among them, t1 is greater than or equal to the dead time between the vertical pipe and the horizontal pipe and less than the minimum pulse width of the horizontal pipe, and t2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the horizontal pipe.

3. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 2, wherein: The gate driver includes a driving module, a switch state identification module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module and a gate circuit module; After the riser is turned off for time t1, within time t2, if it is detected that the collector-emitter voltage of the riser is lower than a preset target voltage, the gate driver triggers a fault signal, including: The driving module generates a driving signal according to the PWM switching signal output by the controller to drive the riser to turn off; The switch state recognition module recognizes the switch state of the riser according to the driving signal and outputs a standpipe switch state signal; The comparator module compares the vertical tube collector-emitter voltage obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module, and outputs a first enable signal when the vertical tube collector-emitter voltage is lower than the target voltage; The delay module receives the riser switch status signal and outputs a second enable signal for a period of time t2 after the riser is turned off for a period of time t1; The gate circuit module enables the gate driver to generate and output a fault signal when receiving the first enable signal and the second enable signal at the same time.

4. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 3, wherein: The controller includes a fault detection module and a fault identification module; When the controller receives the fault signal fed back by the gate driver, it determines that a short circuit fault occurs on the riser, and identifies the position number of the faulty riser according to the hardware interface address of the fed back fault signal, including: When receiving the fault signal fed back by the gate driver, the fault detection module obtains the hardware interface address of the feedback fault signal, and sends the fault signal and the obtained hardware interface address to the fault identification module; The fault identification module determines that a short circuit fault occurs in the riser when receiving the fault signal, and identifies the position number of the faulty riser according to the hardware interface address.

5. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 1, wherein: The gates of the horizontal and vertical tubes in the NPP circuit topology are both connected to a gate driver, which is connected to a controller; The method of determining whether a short circuit fault occurs in the vertical tube according to the vertical tube collector-emitter voltage during the time when the vertical tube is turned off and the horizontal tube is turned on, and identifying the position number of the vertical tube when a short circuit fault occurs in the vertical tube, includes: After the riser is turned off for time t1, within time t2, if the collector-emitter voltage of the riser is detected to be lower than the preset target voltage, the gate driver triggers the generation of a fault signal with a fixed duration of t3; When the controller detects a fault signal with a duration of t3, it determines that a short circuit fault has occurred in the riser and identifies the position number of the faulty riser according to the hardware interface address of the feedback fault signal; Among them, t1 is greater than or equal to the dead time between the vertical pipe and the horizontal pipe and less than the minimum pulse width of the horizontal pipe, and t2 starts at the end point of t1 and ends at the end point of the minimum pulse width of the horizontal pipe.

6. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 5, characterized in that: The gate driver includes a driving module, a switch state identification module, a delay module, a collector-emitter voltage detection module, a target voltage module, a comparator module, a gate circuit module and a monostable trigger; After the riser is turned off for time t1, within time t2, if it is detected that the collector-emitter voltage of the riser is lower than a preset target voltage, the gate driver triggers to generate a fault signal with a fixed duration of t3, including: The driving module generates a driving signal according to the PWM switching signal output by the controller to drive the riser to turn off; The switch state recognition module recognizes the switch state of the riser according to the driving signal and outputs a standpipe switch state signal; The comparator module compares the vertical tube collector-emitter voltage obtained by the collector-emitter voltage detection module with the target voltage provided by the target voltage module, and outputs a first enable signal when the vertical tube collector-emitter voltage is lower than the target voltage; The delay module receives the riser switch status signal and outputs a second enable signal for a period of time t2 after the riser is turned off for a period of time t1; When the gate circuit module receives the first enable signal and the second enable signal at the same time, it enables the monostable trigger, and the monostable trigger is triggered to generate and output a fault signal with a fixed duration of t3.

7. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 6, wherein: The controller includes a fault detection module and a fault identification module; When the controller detects a fault signal with a duration of t3, it determines that a short circuit fault occurs in the riser, and identifies the position number of the faulty riser according to the hardware interface address of the feedback fault signal, including: When receiving the fault signal fed back by the gate driver, the fault detection module obtains the hardware interface address of the feedback fault signal, and sends the fault signal and the obtained hardware interface address to the fault identification module; The fault identification module determines that a short circuit fault occurs in the riser when detecting that the duration of the fault signal is t3, and identifies the position number of the faulty riser according to the hardware interface address.

8. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 4 or 7, characterized in that: The fault identification module sends the fault type and bit number of the faulty riser to the human-machine interface.

9. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to claim 4 or 7, characterized in that: When the fault detection module receives the fault signal fed back by the gate driver, it executes the fault processing logic and controls the PWM signal module to stop outputting the PWM switch signal to the corresponding riser.

10. The method for detecting and identifying a riser short circuit fault in an NPP circuit topology according to any one of claims 1 to 7, characterized in that: The number of risers in the NPP circuit topology is greater than or equal to 4.

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