Turntable high-precision control method and system based on FPGA

Abstract

The invention discloses an FPGA-based turntable high-precision control method and system, and relates to the technical field of turntable control, and the method comprises the steps: receiving a turntable control demand in a periodic scene, and carrying out the decomposition to determine a sub-control demand; a programmable gating array is introduced, gating programming deployment is carried out on sub-control requirements, a gating combination relation is determined according to a coupling relation, a logic processing circuit arranged in an FPGA is formed, the FPGA is in communication connection with a main control chip, and an externally expanded static memory is arranged in a communication bus; and establishing a control loop of the turntable driving component, the FPGA and the main control chip, receiving a control task, triggering the logic processing circuit based on the FPGA to execute logic processing, and executing turntable control management in response to the turntable driving component based on the main control planning of the main control chip. The technical problems of large control response delay and insufficient execution precision of the turntable in the prior art are solved, and the technical effect of improving the action response speed and the control precision of the turntable is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of turntable control, and in particular to a high-precision turntable control method and system based on FPGA. Background Art

[0002] Turntable control places high demands on motion response speed and execution accuracy in applications such as precision positioning and dynamic adjustment. In conventional turntable control architectures, the main control chip usually periodically reads the status of the drive components through serial communication, and combines software algorithms to complete the planning and issuance of motion instructions. This model is limited by the communication link bandwidth, processor decoding capabilities, and task load distribution, resulting in problems such as command response lag and coarse control granularity during the execution of the action, making it difficult to meet the needs of continuous action and high dynamic precision adjustment. Especially in complex cycle scenarios or multi-stage action switching, the delay between task parsing and execution feedback is further amplified, affecting the dynamic response performance and motion consistency of the entire turntable. Summary of the Invention

[0003] The present application provides a high-precision turntable control method and system based on FPGA, which is used to solve the technical problems of large turntable control response delay and insufficient execution accuracy in the prior art.

[0004] In view of the above problems, the present application provides a high-precision control method and system for a turntable based on FPGA.

[0005] A first aspect of the present application provides a high-precision control method for a turntable based on an FPGA, the method comprising:

[0006] The turntable control requirements in the receiving cycle scenario are decomposed to determine the sub-control requirements, wherein the minimum requirement unit is used as the decomposition standard, and the sub-control requirements are identified with a coupling relationship; a programmable gate array is introduced to perform gate programming deployment on the sub-control requirements, and the gate combination relationship is determined based on the coupling relationship to form a logic processing circuit built into the FPGA, wherein a communication connection is established between the FPGA and the main control chip, and an externally extended static memory is provided in the communication bus; a control loop of the turntable drive component-FPGA-main control chip is established, the control task is received, and the FPGA-based logic processing circuit is triggered to perform logic processing, and the main control planning based on the main control chip is responded to by the turntable drive component to perform turntable control management.

[0007] The second aspect of the present application provides a high-precision turntable control system based on FPGA, the system comprising:

[0008] A sub-control demand determination module is used to receive the turntable control demand in a periodic scenario and decompose and determine the sub-control demand, wherein the minimum demand unit is used as the decomposition standard, and the sub-control demand identifier has a coupling relationship; a logic processing circuit construction module is used to introduce a programmable gate array, perform gate programming deployment on the sub-control demand, determine the gate combination relationship based on the coupling relationship, and constitute a logic processing circuit built into the FPGA, wherein the FPGA establishes a communication connection with the main control chip, and an externally extended static memory is opened in the communication bus; a turntable control management module is used to establish a control loop of the turntable drive component-FPGA-main control chip, receive control tasks, trigger the FPGA-based logic processing circuit to perform logic processing, and perform turntable control management in response to the turntable drive component with the main control planning based on the main control chip.

[0009] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0010] The present application receives the turntable control demand in a periodic scenario, decomposes and determines the sub-control demand, wherein the minimum demand unit is used as the decomposition standard, and the sub-control demand identifier has a coupling relationship; introduces a programmable gate array, performs gate programming deployment on the sub-control demand, and determines the gate combination relationship based on the coupling relationship to form a logic processing circuit built into the FPGA, wherein the FPGA establishes a communication connection with the main control chip, and an externally extended static memory is opened in the communication bus; establishes a control loop of the turntable drive component-FPGA-main control chip, receives the control task, triggers the FPGA-based logic processing circuit to perform logic processing, and responds to the main control planning based on the main control chip to execute turntable control management in response to the turntable drive component. The present invention solves the technical problems of large turntable control response delay and insufficient execution accuracy in the prior art, and achieves the technical effect of improving the turntable action response speed and control accuracy by introducing a programmable gate array to construct a logic processing circuit built into the FPGA and establishing a hierarchical control loop of the turntable drive component-FPGA-main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A schematic flow chart of a high-precision control method for a turntable based on FPGA provided in an embodiment of the present application;

[0013] Figure 2A schematic diagram of the structure of a high-precision turntable control system based on FPGA provided in an embodiment of the present application.

[0014] Description of the accompanying drawings: sub-control requirement determination module 11, logic processing circuit construction module 12, turntable control management module 13. DETAILED DESCRIPTION

[0015] This application provides a high-precision turntable control method and system based on FPGA, aiming to solve the technical problems of large turntable control response delay and insufficient execution accuracy in the existing technology. By introducing a programmable gate array to construct a logic processing circuit built into the FPGA, and establishing a hierarchical control loop of turntable drive component-FPGA-main control chip, the technical effect of improving the turntable action response speed and control accuracy is achieved.

[0016] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0017] It should be noted that any variations of the terms "include" and "have" are intended to cover non-exclusive inclusions. For example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products or devices.

[0018] Example 1, as Figure 1 As shown, the present application provides a high-precision control method for a turntable based on FPGA, the method comprising:

[0019] Step S100: receiving a turntable control demand in a periodic scenario, and decomposing and determining sub-control demands, wherein the minimum demand unit is used as a decomposition standard, and the sub-control demands are identified as having a coupling relationship.

[0020] In the embodiment of the present application, the turntable control requirements in a periodic scenario are first received. A periodic scenario refers to a set of control objectives that the turntable needs to achieve in each stage within a continuous time period, such as angle adjustment, acceleration / deceleration switching, and position maintenance in different time periods.

[0021] After receiving the cyclical control requirements, we systematically break them down into their smallest required units using a functional unit decomposition approach. These units are defined as basic control actions that cannot be further broken down, such as a single, subtle angle change, a short-term speed change, or a single position lock. During this decomposition process, we use a classification technique based on the characteristics of the control actions to break down the entire cyclical requirement into several distinct and well-defined sub-control requirements, based on action independence and execution atomicity (i.e., the properties that each action can be completed independently and cannot be further divided).

[0022] When identifying sub-control requirements, an identification mechanism based on action characteristic normalization is applied. This mechanism analyzes the input conditions, target output, and timing requirements of each control requirement, and identifies control actions with independent logical closed-loop characteristics as a single sub-control requirement. This process ensures that each sub-control requirement is functionally independent and can be independently deployed into the FPGA logic circuit for efficient processing.

[0023] While identifying sub-control requirements, the coupling relationships between them are further identified. Coupling relationships refer to the interdependencies between sub-control requirements due to logical execution order, synchronous triggering requirements, or resource access conflicts. Through logical relationship analysis, it is possible to identify whether there are sequential execution requirements (i.e., one action must be executed after another), synchronous triggering requirements (i.e., multiple actions must be initiated simultaneously), or resource mutual exclusion relationships (i.e., actions conflict with shared resources during execution) between sub-control requirements. By forming a clear coupling relationship identification matrix, a rigorous logical dependency basis can be provided for subsequent FPGA gating logic combination.

[0024] Step S200: Introduce a programmable gate array, perform gate programming deployment on the sub-control requirements, determine the gate combination relationship based on the coupling relationship, and form a logic processing circuit built into the FPGA, wherein the FPGA establishes a communication connection with the main control chip, and an externally extended static memory is opened in the communication bus.

[0025] In the embodiment of the present application, a programmable gate array is first introduced, that is, by dynamically configuring logic gates, lookup tables (LUTs), flip-flops and other logic resources inside the FPGA, a freely programmable and adjustable hardware logic module is built.

[0026] After introducing the programmable gate array (PGA), gate programming is deployed for each identified sub-control requirement. Specifically, based on the control characteristics of each sub-control requirement (such as angle adjustment, speed regulation, position locking, etc.), its input, output, and state change conditions are analyzed, and its logical function is converted into corresponding hardware gating logic. Each sub-control requirement is independently compiled into a gated logic block and deployed within the PGA, forming a structured and independently callable control module, thereby enabling rapid combination and real-time execution of functional units within the FPGA.

[0027] After gate control programming is deployed, further processing is performed based on the coupling relationships between sub-control requirements. Coupling relationships describe the dependencies between different sub-control actions in terms of logical execution order, synchronous triggering, or resource utilization. For example, certain actions must be completed before subsequent actions can be triggered (sequential dependency), or multiple actions must be initiated simultaneously (parallel dependency). Through logical relationship analysis methods, the coupling types between sub-control requirements are identified, forming a coupling relationship matrix that serves as an important basis for subsequent gate control logic combination.

[0028] After obtaining the coupling relationship, the gated combination relationship is determined. This means that the deployed gated logic modules are combined and configured according to the coupling properties of the sub-control requirements. Sequentially dependent sub-control requirements are connected through timing logic (such as synchronous triggers and state machine switching), while sub-control requirements that execute in parallel are linked through parallel combinational logic (such as multi-input AND gates and OR gates). By constructing this gated combination relationship, a logic processing circuit built into the FPGA is ultimately formed, realizing a hardware logic control network in which each sub-control action is strictly dependent, executed in sequence, or executed in parallel, thereby supporting the complex and high-precision turntable control requirements in periodic scenarios.

[0029] In order to achieve efficient data interaction between the FPGA's internal logic processing circuit and the system's main control chip and establish a communication connection, a 16-bit data bus and 18-bit address bus standard design is adopted to ensure the high speed and stability of data read and write operations.

[0030] To further enhance data buffering and access flexibility, an external static random access memory (SRAM) is implemented within the communication bus. SRAM offers fast access speeds and strong data retention, making it suitable for use as a temporary buffer during high-speed data exchange.

[0031] Furthermore, in the method provided in the embodiment of the application, an externally extended static memory is provided in the communication bus, and further includes:

[0032] An external interface is opened in the communication bus; a static memory of a preset capacity is expanded in the external interface; and directional function requirements are determined according to the turntable control requirements and the deployment architecture based on the FPGA and the main control chip, and the static memory is initialized and deployed.

[0033] In the embodiments of the present application, an external interface is first established in the communication bus between the FPGA and the main control chip. By reserving an expandable port in the data bus design and configuring a dedicated address mapping mechanism, the direct mounting and management of external devices is achieved, thus opening up a high-speed communication data channel between the main control chip and the FPGA. After the external interface is established, a static random access memory (SRAM) with a preset capacity is connected through this interface. SRAM has the characteristics of no refresh requirement, fast read and write speeds, and low access latency. It can be used as a data cache area for storing encoder analysis values, intermediate processing data, and instruction interaction content, thereby effectively alleviating the communication bottleneck problem that may be caused by frequent data access between the main control chip and the FPGA.

[0034] After the hardware expansion is completed, combined with the characteristics of the periodic turntable control requirements, and based on the deployment architecture of FPGA as the logic processing unit and the main control chip as the instruction planning unit, the directional functional requirements are further analyzed and determined. Targeted functional requirements include the classification of cached data types, priority management of read and write access, and the setting of data synchronization methods, to ensure that the expanded static memory can accurately support the data requirements of the turntable control actions at each stage and meet the requirements of high-frequency and high-real-time data exchange. Finally, based on the determined directional functional requirements, the static memory is initialized and deployed, and the address mapping table configuration, access permission setting, and cache strategy initialization are completed, so that the expanded storage module can continuously and stably assume the functions of high-speed data caching and access support throughout the turntable control process, effectively improving control accuracy and response efficiency.

[0035] Furthermore, in the method provided in the embodiment of the application, gate programming deployment is performed on the sub-control requirements, and a gate combination relationship is determined based on the coupling relationship to form a logic processing circuit built into the FPGA, which also includes:

[0036] For each control sub-requirement, a programmable gate is matched respectively, and the programmable gate conversion of the control sub-requirement is performed and deployed on the programmable gate to determine the gate deployment array; based on the coupling relationship, the gate combination relationship is determined, wherein the gate combination relationship includes combinational logic and timing logic; based on the combinational logic and the timing logic, the gate deployment array is logically associated to determine the logic processing circuit.

[0037] In the embodiments of this application, a functional mapping method is first used to match a programmable gate to each sub-control requirement. Specifically, by analyzing the input variables, logical functions, and target outputs of the sub-control requirements, logic resources within the FPGA (such as lookup tables (LUTs) or routing resources) are selected to convert the logic of each sub-requirement into the functional configuration of a programmable gate unit. Programmable gates are hardware modules that can dynamically define logical functions. They offer flexible programming features and can efficiently adapt to the mapping requirements of different control logics.

[0038] After matching sub-control requirements with programmable gates, logic synthesis is used to further programmatically transform the control sub-requirements. Logic synthesis generates a state machine model based on the functional description of the sub-requirements and compiles it into low-level hardware description language (HDL) logic recognizable by the FPGA, achieving the transition from functional to circuit implementation. Logic synthesis completes the circuit representation of the sub-control actions, enabling each control logic to operate independently at the hardware level and meet the requirements for rapid trigger response.

[0039] A physical layout method is then used to deploy the programmed gates within the FPGA, forming a gate array. This method involves allocating specific FPGA logic block resources to each gate unit and arranging routing paths to minimize communication latency between units. A gate array is a collection of independent gate units arranged according to specific rules within the FPGA chip, laying the foundation for subsequent logic combination and timing control.

[0040] After the gated deployment array is constructed, dependency analysis methods are applied to determine the gated combination relationships based on the coupling relationships between sub-control requirements. Coupling relationships refer to the logical dependencies between sub-control actions during execution, such as sequential dependencies, synchronous triggering, or resource mutual exclusion. Dependency analysis forms a logical connection structure, clarifying which gated units require sequential series connection and which require parallel combination, thereby providing constraints for the logical combination.

[0041] After determining the gate control combination relationships, we further employ combinational logic design methods to configure the combinational logic. Combinatorial logic refers to logic that directly determines output based on input, independent of timing signals. For example, when two gate control units need to meet conditions simultaneously, an AND gate is used to achieve the combination; when any gate control unit can be triggered if it meets a condition, an OR gate is used; and when detecting the difference between two signal states, an XOR gate is used. Combinatorial logic design uses logic gate combinations to establish a parallel OR conditional triggering mechanism for each gate control unit, ensuring the correct reasoning of the control logic.

[0042] When addressing timing-related sub-control requirements, sequential logic design methods are used to configure sequential logic structures. Sequential logic, unlike combinational logic, relies on clock signals and historical states and is often constructed using flip-flops (such as D flip-flops) or finite state machines (FSMs). Sequential logic design ensures that sub-control requirements with execution order requirements, delayed triggering, or synchronous updates are executed in an orderly manner at the correct time points, avoiding signal conflicts and logic desynchronization.

[0043] Finally, a logic integration approach was applied to logically link the gated deployment array based on combinational logic and sequential logic to determine the logic processing circuit. Logic integration involves connecting the independent gated units through combinational logic and sequential logic to form a complete hardware execution chain. The resulting logic processing circuit responds to control tasks issued by the main control chip within the FPGA using extremely low-latency, high-concurrency hardware execution, enabling high-precision, real-time attitude adjustment and motion control for the turntable in complex cycle scenarios.

[0044] Furthermore, the method provided in the application embodiment also includes:

[0045] The gate deployment array is expandable, including expansion of the number of gates and update expansion of internal control programming content.

[0046] In the embodiments of this application, a scalable design approach is employed to enable flexible expansion of the gated deployment array. A gated deployment array refers to a pre-organized set of programmable gated cells within the FPGA, used to handle the hardware mapping and logic execution of sub-control requirements. Through a modular logic cell layout and reservable resource design, the number of gates can be expanded. That is, when new sub-control requirements are added, new gated cells can be added directly to the array without disrupting the existing logic layout, ensuring seamless integration of the added logic.

[0047] Combined with dynamic programming update methods, this technology supports flexible updates to the internal control programming of existing gate-controlled units in the array. Internal control programming refers to the specific logical functions implemented within each gate-controlled unit, such as input signal processing, conditional judgment, and output control. By updating the internal logic configuration, control strategies can be adjusted promptly based on new control requirements. By expanding the number of gates and updating the internal control logic, gate-controlled deployment arrays can continuously adapt to complex and changing application scenarios while maintaining control accuracy and response speed.

[0048] Furthermore, the method provided in the application embodiment also includes:

[0049] The logic processing circuit further includes a clock circuit based on an encoder; wherein, if low-precision driving is used, the clock circuit is used as output; if high-precision driving is used, the clock circuit is used as input.

[0050] In this embodiment of the present application, the logic processing circuit also includes an encoder-based clock circuit. This circuit uses the encoder sampling signal as a reference to generate standardized timing signals for synchronization control, coordinating the movement rhythm of the turntable's drive components. First, a precision identification method is used to automatically identify the required clock signal granularity and synchronization accuracy based on the current turntable drive type (low-precision or high-precision), and dynamically adjust the clock circuit's operating mode accordingly.

[0051] When a low-precision drive is identified, a direct output configuration method is applied. This uses the basic time pulses set within the clock circuit as the control output, eliminating the need for more complex time series encoding or fine-tuning analysis. In low-precision scenarios, due to the lower overall control accuracy requirements, a certain degree of synchronization error is tolerated between turntable movements. Therefore, the clock circuit primarily provides a standard periodic pulse signal, directly driving the execution of each sub-control logic unit to meet general motion control requirements.

[0052] When a high-precision drive is identified, an input collaborative analysis method is employed, using the clock circuit output as an input reference for the subsequent fine-grained control logic. In high-precision drive scenarios, the turntable is comprised of multiple components working together (such as motor drive, position detection, and speed synchronization modules), placing extremely high demands on the consistency and accuracy of the time series. A single standard pulse signal cannot meet these requirements for direct use. At this point, the clock circuit provides a preliminary synchronization signal, based on which the collaborative components perform secondary analysis and fine-grained adjustments, such as microsecond-level delay calibration, phase alignment, and time window segmentation, to ultimately determine the specific time parameters that meet the requirements of high-precision motion control, ensuring the synchronization and accuracy of the overall motion process.

[0053] Step S300: Establish a control loop of turntable drive component-FPGA-main control chip, receive control tasks, trigger the FPGA-based logic processing circuit to perform logic processing, and respond to the turntable drive component with the main control planning based on the main control chip to perform turntable control management.

[0054] In an embodiment of the present application, a control loop is first established by a control loop construction method, which includes a turntable drive component, an FPGA, and a main control chip. In this loop, two key modules, a task register and a status register, are introduced. The task register is used to store real-time control tasks issued by the main control chip, and the status register is used to store status feedback information generated after processing on the FPGA side. The main control chip determines the control task that needs to be updated or executed by reading the task register and sends the updated instruction to the FPGA. The FPGA parses and executes the control task based on the internal logic processing circuit and writes the generated first control information into the status register. The main control chip then obtains real-time feedback data by synchronously reading the status register.

[0055] After completing the control loop, a closed-loop control process from task analysis to action execution is further implemented through a logic trigger and response mechanism. Specifically, the FPGA first receives the control task and completes the analysis and decomposition of the control task based on the fine-grained standards of the sub-control requirements. It then triggers the internal logic processing circuit and completes signal decoding, logical operations, and the generation of the first control information according to the gate matching strategy. Finally, the main control chip, based on its own main control plan, that is, according to the periodic task scheduling and global control strategy, comprehensively analyzes the feedback results of the first control information, dynamically adjusts the turntable action instructions, and finally responds to the actual operating status of the turntable drive components to accurately complete the control management of the turntable.

[0056] Furthermore, in the method provided in the embodiment of the application, establishing a control loop of the turntable drive component-FPGA-main control chip also includes:

[0057] A task register and a status register are introduced, wherein the main control chip determines the updated control task based on the task register and sends it to the FPGA; the FPGA stores the first control information obtained based on the logic processing circuit into the status register, and the main control chip synchronizes the status register to receive the first control information; wherein, the task register and the status register are assisted to execute the reconstruction of the roadbed processing circuit based on the change of the turntable control requirements.

[0058] In this embodiment, a register interaction mechanism is employed to introduce task registers and status registers into the turntable drive assembly-FPGA-master control chip control loop. The task register is used to cache control tasks or logic adjustment instructions generated and issued by the master control chip, while the status register is used to store feedback information (i.e., primary control information) generated by the FPGA based on real-time execution results, and is synchronously read by the master control chip, thereby enabling bidirectional communication between task issuance and status feedback.

[0059] In the specific process, task management methods are first applied, with the main control chip monitoring the current turntable control requirements. When a change in the action chain, an adjustment to control precision, or the insertion of a new task is detected, the main control chip determines an updated control task based on the task register. This involves writing new instructions or logic update requirements into the task register and sending them to the FPGA via the communication bus. At this point, the main control chip does not directly control underlying execution, but instead implements task scheduling and dynamic dispatching through the register mechanism, improving the real-time and flexibility of overall instruction transmission.

[0060] The FPGA periodically checks the contents of task registers and, using task parsing and logic processing methods, invokes internal logic processing circuits for rapid response. The logic processing circuit is a hardware execution unit deployed within the FPGA, built using a combination of gated programming logic and sequential logic. Upon receiving a control task, it directly performs signal decoding, logical judgment, and action decision-making. When the FPGA generates a control response based on the parsed results, it forms the corresponding first control information, which reflects the current turntable status, logic processing adjustment results, or subtask execution feedback.

[0061] Then, a state synchronization method is applied to write the first control information into the status register in real time. By synchronously accessing the contents of the status register, the master control chip can promptly understand the action execution and logic adjustment status on the FPGA side. Based on this real-time feedback, the overall master control planning and instruction scheduling strategy can be dynamically adjusted to ensure high consistency between control instructions and execution results.

[0062] In particular, when the periodic scenario changes, resulting in a change in the turntable control requirements, the reconstruction of the roadbed processing circuit based on the change in turntable control requirements is performed through the logic reconstruction method. Roadbed processing circuit reconstruction refers to dynamically adjusting the configuration and logical connection relationship of the programmable gate control unit based on the original FPGA logic processing circuit according to the new control requirements, including adding and deleting sub-control units, adjusting the gate combination method, and redefining the timing logic, so that the logic processing circuit can always accurately map the current control scenario. The entire reconstruction process is assisted by the task register and the status register. Through the closed-loop mechanism of instruction issuance and status feedback, the dynamic optimization and evolution of the logic processing circuit are realized, ensuring the efficient and precise operation of the turntable under different complex working conditions.

[0063] Furthermore, in the method provided in the embodiment of the application, triggering the FPGA-based logic processing circuit to perform logic processing, and responding to the turntable drive component to perform turntable control management based on the main control planning of the main control chip, further includes:

[0064] Analyze the control task and determine the decomposed control task based on the sub-control requirements; trigger the logic processing circuit in the FPGA to perform gate matching on the decomposed control task, and determine the first control information by performing signal decoding and processing; the main control chip receives the first control information, executes control planning, and performs control management in response to the turntable drive component.

[0065] In an embodiment of the present application, a control task parsing method is first adopted, and the main control chip determines the decomposition of the control task based on the current motion target and environmental state of the turntable. Specifically, after receiving the control task issued by the high-level dispatcher, the main control chip decomposes the overall task into multiple basic action units in a fine-grained manner based on the sub-control requirements. Sub-control requirements refer to the smallest operation unit that cannot be further subdivided at the logic and execution level, such as a single angle adjustment (such as +10° rotation), short-term acceleration, or single-point position calibration. By establishing action dependencies and sequential logic models, the main control chip parses complex multi-stage control targets into a set of independent sub-tasks that can be directly mapped to the FPGA hardware logic, ensuring that each sub-task has a clear input and output definition and execution boundary.

[0066] After the control task is refined, a logic processing feedback generation method is used. The logic processing circuitry within the FPGA performs specific control logic operations based on the sub-control requirements to determine the first control information. The logic processing circuitry is composed of programmable gated units (such as lookup tables (LUTs) and timing flip-flops), supporting high-speed parallel computing and real-time action decision-making. In this process, the FPGA activates the logic modules corresponding to the sub-control requirements through a gate matching mechanism. It receives real-time signal input from sensors and decodes and processes the signals to determine the execution status of the action in real time. The first control information refers to standardized feedback data generated after logic processing, including action completion indicators, error measurements, and status confirmation results. For example, in an angle adjustment task, the first control information might be "The current angle has reached the target angle, with a position error within 0.5°," providing direct decision-making support for upper-level master control planning.

[0067] The main control chip then uses control planning and dynamic response methods. After receiving the first control information, it dynamically adjusts subsequent control strategies and performs control management based on the current action execution status and overall operation plan. Control management refers to the main control chip optimizing and scheduling the turntable's subsequent control instructions based on real-time feedback results, combined with periodic task planning, anomaly detection mechanisms, and action priority adjustment mechanisms. For example, when it is discovered that an unexpected displacement error has occurred during the execution of a certain sub-control requirement, the main control chip can immediately insert a corrective action, adjust the next sub-control command, or re-plan the remaining action path, thereby avoiding the impact of error accumulation on the overall action accuracy. At the same time, the main control chip maintains real-time synchronization with the FPGA end by managing the contents of the task register and status register, ensuring closed-loop operation of task issuance and status feedback. Through this dynamic planning mechanism, not only is the continuity and accuracy of the turntable's movement during high-speed motion guaranteed, but it can also adapt to the challenges of complex environmental changes to control accuracy.

[0068] Furthermore, the method provided in the application embodiment also includes:

[0069] In the control loop, the static memory externally expanded in the communication bus is selectively activated, and the function of the static memory is selectively triggered.

[0070] In an embodiment of the present application, in the control loop constructed by the turntable drive component-FPGA-main control chip, in order to enhance the flexibility of data processing and adapt to complex control requirements, a static memory is extended and connected in the communication bus, and an optional activation and function optional triggering mechanism is designed.

[0071] During control loop operation, the static memory is dynamically managed using an optional activation strategy based on task processing complexity and data caching requirements. When the turntable is performing basic motion control and data volume is limited, the static memory remains mounted but inactive to conserve communication bandwidth and energy. However, when a need for continuous recording, cross-cycle comparison, or multi-stage data integration is detected, the static memory can be dynamically activated to participate in caching logic processing information.

[0072] Furthermore, the static memory uses a selectable trigger mechanism to flexibly enable corresponding data processing functions based on current control requirements. When the turntable requires continuous analysis, the FPGA, while executing each sub-control requirement, temporarily stores the generated logic processing information—intermediate results such as the execution status of each action unit, error data, and position information—into the static memory in real time.

[0073] After continuous action or multi-point acquisition is completed, the main control chip uses a batch call mechanism to centrally extract the logical processing information from the static memory for comprehensive analysis. Comprehensive analysis refers to comprehensive judgments such as trend identification, state assessment, and path optimization based on feedback from multiple action executions, thereby optimizing subsequent action planning or adjusting the current control strategy. For example, when performing continuous angle fine-tuning, the overall posture adjustment path can be uniformly corrected based on the accumulated error information of multiple sub-actions to avoid large-scale offsets caused by the accumulation of single-step errors.

[0074] By introducing the optional activation of static memory and optional triggering of functions in the control loop, and combining it with the temporary storage and overall analysis mechanism of logical processing information, the batch data processing capability and dynamic decision-making level under complex working conditions can be improved while ensuring real-time action control.

[0075] In the embodiments of the present application, in summary, the embodiments of the present application have at least the following technical effects:

[0076] The present application receives the turntable control demand in a periodic scenario, decomposes and determines the sub-control demand, wherein the minimum demand unit is used as the decomposition standard, and the sub-control demand identifier has a coupling relationship; introduces a programmable gate array, performs gate programming deployment on the sub-control demand, and determines the gate combination relationship based on the coupling relationship to form a logic processing circuit built into the FPGA, wherein the FPGA establishes a communication connection with the main control chip, and an externally extended static memory is opened in the communication bus; establishes a control loop of the turntable drive component-FPGA-main control chip, receives the control task, triggers the FPGA-based logic processing circuit to perform logic processing, and responds to the main control planning based on the main control chip to execute turntable control management in response to the turntable drive component. The present invention solves the technical problems of large turntable control response delay and insufficient execution accuracy in the prior art, and achieves the technical effect of improving the turntable action response speed and control accuracy by introducing a programmable gate array to construct a logic processing circuit built into the FPGA and establishing a hierarchical control loop of the turntable drive component-FPGA-main control chip.

[0077] The second embodiment is based on the same inventive concept as the high-precision control method of the turntable based on FPGA in the above embodiment. Figure 2 As shown, the present application provides a high-precision turntable control system based on FPGA. The system and method embodiments in the present application are based on the same inventive concept. The system includes:

[0078] The sub-control requirement determination module 11 is used to receive the turntable control requirement in a periodic scenario, decompose and determine the sub-control requirement, wherein the minimum requirement unit is used as the decomposition standard, and the sub-control requirement identifier has a coupling relationship; the logic processing circuit construction module 12 is used to introduce a programmable gate array, perform gate programming deployment on the sub-control requirement, determine the gate combination relationship based on the coupling relationship, and constitute a logic processing circuit built into the FPGA, wherein the FPGA establishes a communication connection with the main control chip, and an externally extended static memory is opened in the communication bus; the turntable control management module 13 is used to establish a control loop of the turntable drive component-FPGA-main control chip, receive control tasks, trigger the FPGA-based logic processing circuit to perform logic processing, and perform turntable control management in response to the turntable drive component with the main control planning based on the main control chip.

[0079] Furthermore, the system is also used to implement the following functions:

[0080] An external interface is opened in the communication bus; a static memory of a preset capacity is expanded in the external interface; and directional function requirements are determined according to the turntable control requirements and the deployment architecture based on the FPGA and the main control chip, and the static memory is initialized and deployed.

[0081] Furthermore, the system is also used to implement the following functions:

[0082] For each control sub-requirement, a programmable gate is matched respectively, and the programmable gate conversion of the control sub-requirement is performed and deployed on the programmable gate to determine the gate deployment array; based on the coupling relationship, the gate combination relationship is determined, wherein the gate combination relationship includes combinational logic and timing logic; based on the combinational logic and the timing logic, the gate deployment array is logically associated to determine the logic processing circuit.

[0083] Furthermore, the system is also used to implement the following functions:

[0084] The gate deployment array is expandable, including expansion of the number of gates and update expansion of internal control programming content.

[0085] Furthermore, the system is also used to implement the following functions:

[0086] The logic processing circuit further includes a clock circuit based on an encoder; wherein, if low-precision driving is used, the clock circuit is used as output; if high-precision driving is used, the clock circuit is used as input.

[0087] Furthermore, the system is also used to implement the following functions:

[0088] Analyze the control task and determine the decomposed control task based on the sub-control requirements; trigger the logic processing circuit in the FPGA to perform gate matching on the decomposed control task, and determine the first control information by performing signal decoding and processing; the main control chip receives the first control information, executes control planning, and performs control management in response to the turntable drive component.

[0089] Furthermore, the system is also used to implement the following functions:

[0090] In the control loop, the static memory externally expanded in the communication bus is selectively activated, and the function of the static memory is selectively triggered.

[0091] Furthermore, the system is also used to implement the following functions:

[0092] A task register and a status register are introduced, wherein the main control chip determines the updated control task based on the task register and sends it to the FPGA; the FPGA stores the first control information obtained based on the logic processing circuit into the status register, and the main control chip synchronizes the status register to receive the first control information; wherein, the task register and the status register are assisted to execute the reconstruction of the roadbed processing circuit based on the change of the turntable control requirements.

[0093] It should be noted that the order in which the embodiments of the present application are presented is for illustrative purposes only and does not necessarily represent the superiority or inferiority of the embodiments. Furthermore, the foregoing descriptions of specific embodiments of this specification are provided. The processes depicted in the accompanying drawings do not necessarily require the specific order or sequential sequence shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0094] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

[0095] This specification and drawings are merely illustrative of the present application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of this application. Thus, this application is intended to include such modifications and variations as fall within the scope of this application and its equivalents.

Claims

1. A high-precision control method for a turntable based on FPGA, characterized in that: The method comprises: The turntable control requirements in the receiving cycle scenario are decomposed to determine sub-control requirements, wherein the minimum requirement unit is used as the decomposition standard, and the sub-control requirements are identified as having a coupling relationship; A programmable gate array is introduced to perform gate programming deployment for the sub-control requirements, and a gate combination relationship is determined based on the coupling relationship to form a logic processing circuit built into the FPGA, wherein the FPGA establishes a communication connection with the main control chip, and an externally extended static memory is opened in the communication bus; Establish a control loop of turntable drive component-FPGA-main control chip, receive control tasks, trigger the FPGA-based logic processing circuit to perform logic processing, and respond to the turntable drive component with the main control planning based on the main control chip to perform turntable control management.

2. The high-precision control method for a turntable based on FPGA according to claim 1, characterized in that: The communication bus is equipped with externally extended static memory, including: Opening an external interface in the communication bus; Expanding a static memory of a preset capacity in the external interface; According to the turntable control requirements and the deployment architecture based on the FPGA and the main control chip, the directional function requirements are determined and the static memory is initialized and deployed.

3. The high-precision control method for a turntable based on FPGA according to claim 1, characterized in that: Perform gate programming deployment on the sub-control requirements, determine the gate combination relationship based on the coupling relationship, and form a logic processing circuit built into the FPGA, including: For each control sub-requirement, a programmable gate is matched, the programmable conversion of the control sub-requirement is performed, and the gate is deployed on the programmable gate to determine the gate deployment array; Determining the gate combination relationship according to the coupling relationship, wherein the gate combination relationship includes combinational logic and sequential logic; The gated deployment array is logically associated according to the combinational logic and the sequential logic to determine the logic processing circuit.

4. The high-precision control method for a turntable based on FPGA according to claim 3, characterized in that: The gate deployment array is expandable, including expansion of the number of gates and update expansion of internal control programming content.

5. The high-precision control method for a turntable based on FPGA according to claim 1, characterized in that: The logic processing circuit further includes a clock circuit based on an encoder; Among them, if it is a low-precision drive, the clock circuit is used as the output; If high-precision driving is required, the clock circuit is used as input.

6. The high-precision control method for a turntable based on FPGA according to claim 1, characterized in that: Triggering the FPGA-based logic processing circuit to perform logic processing, and responding to the turntable drive component to perform turntable control management based on the main control planning of the main control chip, including: Analyze the control task and determine the decomposed control task based on the sub-control requirements; triggering a logic processing circuit within the FPGA to perform gate matching on the decomposed control task, and determining first control information by performing signal decoding and processing; The main control chip receives the first control information, and performs control management in response to the turntable drive component by executing control planning.

7. The high-precision control method for a turntable based on FPGA according to claim 6, characterized in that: In the control loop, the static memory externally expanded in the communication bus is selectively activated, and the function of the static memory is selectively triggered.

8. The high-precision control method for a turntable based on FPGA according to claim 1, characterized in that: Establish the control loop of the turntable drive component, FPGA, and main control chip, including: Introducing a task register and a status register, wherein the main control chip determines the update control task based on the task register and sends it to the FPGA; The FPGA stores the first control information obtained based on the logic processing circuit into a status register, and the main control chip synchronizes the status register to receive the first control information; Among them, the task register and the status register are assisted to execute the reconstruction of the roadbed processing circuit based on the change of the turntable control requirements.

9. A high-precision turntable control system based on FPGA, characterized in that: The system comprises: a sub-control requirement determination module, configured to receive a turntable control requirement in a periodic scenario, decompose and determine sub-control requirements, wherein the minimum requirement unit is used as a decomposition standard, and the sub-control requirements are identified as having a coupling relationship; A logic processing circuit construction module is used to introduce a programmable gate array, perform gate programming deployment on the sub-control requirements, determine the gate combination relationship based on the coupling relationship, and form a logic processing circuit built into the FPGA, wherein the FPGA establishes a communication connection with the main control chip, and an externally extended static memory is provided in the communication bus; The turntable control management module is used to establish a control loop between the turntable drive component, FPGA, and main control chip, receive control tasks, trigger the FPGA-based logic processing circuit to perform logic processing, and respond to the turntable drive component with the main control planning based on the main control chip to perform turntable control management.

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