A calculation method and calculator based on the Posit data format

Abstract

This invention relates to the field of artificial intelligence technology, and in particular to a computation method and arithmetic unit based on the Posit data format. The method includes obtaining the sign bit, exponent extension bit, mantissa bit, and exponent bit of the Posit data format; preprocessing each position of the Posit data format; defining a bit width allocation priority rule; multiplying the two mantissa bits obtained from decoding to obtain a mantissa product and a mask sequence; determining the number of leading zeros in the mantissa product based on the mask sequence; performing a unified logical shift on the mantissa product; rounding the shifted mantissa part; converting the mantissa product into a fixed-point number format based on the sign bit, exponent extension bit, and exponent bit; performing addition based on the fixed-point number; and outputting the accumulated result. This invention uses one-complement encoding, and the input / output processing only requires logical inversion to complete the sign-related operation, reducing circuit area and power consumption, eliminating the need for complex timing control, and reducing logic resource consumption.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to a calculation method and arithmetic unit based on the Posit data format. Background Technology

[0002] Artificial intelligence technologies, represented by deep neural networks, have been applied on a large scale in fields such as image recognition, natural language processing, and autonomous driving. Their core relies on the efficient numerical computation capabilities of the computing circuits in AI computing chips. However, the inherent computational and memory-intensive nature of deep learning models leads to two key problems for the computing circuits of AI computing chips: first, the computational energy consumption is too high, making it difficult to meet the low power consumption requirements of edge devices; second, the computational latency is relatively large, making it unsuitable for application scenarios with high real-time requirements.

[0003] In AI computing, the Posit data format, as a novel data format, achieves a dynamic range close to that of traditional floating-point numbers with a relatively small bit width by dynamically allocating the bit width of the exponent and mantissa. Furthermore, its tapered data distribution better matches the distribution characteristics of parameters and data in deep learning models, demonstrating significant potential in deep learning computing. However, the dynamic bit width characteristic of the Posit data format requires real-time resolution of the exponent and mantissa boundaries, necessitating additional logic modules, such as bit width detection circuits, to extract and verify the components. This increases hardware circuit area and redundant operations, directly leading to increased energy consumption. On the other hand, mantissa multiplication can only begin after the complete decoding of the exponent and mantissa, resulting in increased computational latency. This severely restricts the practical application of Posit data format-based AI computing chips. Currently, a computing method and arithmetic unit based on the Posit data format are needed. Summary of the Invention

[0004] To address the issues of high computational power consumption and latency in AI computing chips, this invention provides a computation method and processor based on the Posit data format.

[0005] Firstly, the present invention provides a calculation method based on the Posit data format, which adopts the following technical solution:

[0006] A calculation method based on the Posit data format includes:

[0007] Obtain the sign bit, exponent extension bit, mantissa bit, and exponent bit of the Posit data format, and preprocess each position of the Posit data format to obtain SR-Posit data.

[0008] The bit width allocation priority rule is defined based on the preprocessed sign bit, exponent extension bit, mantissa bit and exponent bit, and the SR-Posit data is encoded using one-complement form;

[0009] Using two encoded SR-Posit data as input data, and performing a decoding operation on the input data, the two mantissa bits obtained by decoding are multiplied to obtain the mantissa product and the mask sequence;

[0010] The number of leading zeros in the mantissa product is determined based on the mask sequence. Based on the number of exponent extension bits and the number of leading zeros in the mantissa product, a unified logical shift is performed on the mantissa product.

[0011] The mantissa portion after shifting is rounded, and the mantissa is concatenated with the equivalent exponent and then combined with the sign bit to obtain the product of the SR-Posit data.

[0012] Based on the sign bit, exponent extension bit, and exponent bit, the mantissa product is converted into a fixed-point number format, and addition is performed based on the fixed-point number to output the accumulated result.

[0013] Furthermore, the preprocessing of each position in the Posit data format includes setting the sign bit width of the Posit data format to 1-bit, the exponent extension bit consisting of a continuous sequence of numbers, with a 1-bit wide binary bit opposite to the sequence value at the end of the sequence as the end marker, the mantissa bit using normalized encoding and hiding the highest bit 1, the exponent bit using a fixed value width and encoded as an unsigned integer, and sorted sequentially according to the order of sign bit, exponent extension bit, mantissa bit, and exponent bit.

[0014] Furthermore, the defined bit width allocation priority rule includes removing the sign bit from the total bit width to obtain the total available bit width, and allocating the total available bit width to the exponent extension bit first. The bit width requirement of the exponent extension bit includes the bit width occupied by its sequence itself and the end flag at the end of the sequence. The end flag bit is 1 bit and is opposite to the value of the continuous sequence. When the length of the continuous sequence is equal to the total available bit width, the bit width of the exponent extension bit is the length of the continuous sequence, and there is no need to allocate the end flag bit. When there is still a remaining bit width after the total available bit width is allocated to the exponent extension bit, the remaining bit width is first allocated to the exponent bit, and then the remaining bit width after being allocated to the exponent bit is allocated to the mantissa bit.

[0015] Further, the decoding operation of the input data includes receiving two encoded SR-Posit data IN1 and IN2, removing the sign bits of IN1 and IN2, calculating the number of leading zeros r1 and r2 for the remaining data using a leading zero counter, determining the exponent extension bits Rg1 and Rg2 based on r1 and r2 respectively, extracting the fixed-width bits of the lowest exponent bit after the end bits of Rg1 and Rg2 as exponent bits E1 and E2, removing the sign bit, exponent extension bit, and exponent bit from IN1 and IN2 respectively, using the remaining bits as mantissa bits F1 and F2, using the 1 in the end bits of Rg1 and Rg2 as hidden bits, and concatenating them with F1 and F2 respectively to obtain the complete valid mantissa;

[0016] Where E1 represents the exponent of input data IN1, E2 represents the exponent of IN2, F1 represents the mantissa of IN1, F2 represents the mantissa of IN2, r1 and r2 represent the number of leading zeros in IN1 and IN2 respectively, and Rg1 and Rg2 represent the exponent extension bits of IN1 and IN2 respectively.

[0017] Furthermore, the multiplication operation of the two mantissa bits obtained by decoding includes performing a multiplication operation on the complete and valid mantissa to obtain the mantissa product, generating a correction vector according to the bit width occupied by the exponent extension bits in IN1 and IN2, performing a logical OR operation on the bits of the lower total bit width of the mantissa product with Pcorr to correct the mantissa product, and finally generating a mask sequence according to the length of the exponent extension in IN1 and IN2.

[0018] Furthermore, determining the number of leading zeros in the mantissa product based on the mask sequence includes performing a bitwise logical AND operation on the mantissa product and the mask sequence to generate an intermediate result vector, performing a reduction logical OR operation on all bits of the intermediate result vector to obtain an overflow flag, and calculating the number of leading zeros in the mantissa product based on the overflow flag.

[0019] Furthermore, the unified logical shift of the mantissa product includes concatenating the exponent extension bits of IN1 and IN2 with the exponent bits to obtain the equivalent exponent bits, calculating the number of exponent extension bits of the product based on the equivalent exponent bits, adding the number of exponent extension bits of the product with the number of leading zeros to obtain the shift amount, performing a logical left shift operation on the mantissa product according to the shift amount, shifting the valid numerical part to the high bit and the leading zero sequence to the low bit, and using the shifted leading zero sequence as the basis for the exponent extension bits of the final product, and outputting the normalized mantissa product, the number of leading zeros, and the logical shift amount.

[0020] Furthermore, the product result of the SR-Posit data is obtained by calculating the exponent extension bit and the exponent bit of the product based on the equivalent exponent bits of IN1 and IN2. The exponent extension bit, the rounded mantissa, and the exponent bit of the product are concatenated in order from the most significant bit to the least significant bit to obtain a bit sequence without a sign bit. The XOR result of the sign bits of IN1 and IN2 is concatenated with the bit sequence to form a complete bit sequence and then the final encoding adjustment is performed to output the product result.

[0021] Furthermore, the addition operation based on fixed-point numbers includes converting the product into a fixed-point number format of a precise accumulator based on the mantissa product, sign bit, exponent extension bit, and exponent bit; placing the mantissa product to the right of the least significant bit of the precise accumulator; performing a sign extension on the mantissa product based on the XOR result of the sign bits of IN1 and IN2; performing a logical left shift on the sign-extended mantissa product based on the displacement to obtain a product in fixed-point number format; performing an addition operation between the fixed-point number format product and an externally input fixed-point number; and outputting the final accumulation result.

[0022] Secondly, a calculator based on the Posit data format includes:

[0023] The data acquisition module is configured to: acquire the sign bit, exponent extension bit, mantissa bit and exponent bit of the Posit data format, and preprocess each position of the Posit data format to obtain SR-Posit data;

[0024] The encoding module is configured to define a bit width allocation priority rule based on the preprocessed sign bit, exponent extension bit, mantissa bit, and exponent bit, and to encode the SR-Posit data using a two's complement form.

[0025] The mantissa multiplication module is configured to: use two encoded SR-Posit data as input data, perform decoding operations on the input data, and multiply the two mantissa bits obtained by decoding to obtain the mantissa product and the mask sequence;

[0026] The normalization module is configured to: determine the number of leading zeros in the mantissa product based on the mask sequence, and perform a unified logical shift on the mantissa product based on the number of exponent extension bits and the number of leading zeros in the mantissa product;

[0027] The product encoding module is configured to: perform a rounding operation on the shifted mantissa, concatenate the mantissa bits with the equivalent exponent bits and combine them with the sign bit to obtain the product result of the SR-Posit data;

[0028] The accumulation module is configured to convert the mantissa product into a fixed-point number format based on the sign bit, exponent extension bit, and exponent bit, perform addition operations based on the fixed-point number, and output the accumulation result.

[0029] In summary, the present invention has the following beneficial technical effects:

[0030] 1. This invention places the exponent in the least significant bit, so that the exponent extension bit is directly connected to the mantissa bit. After a simple logical inversion, the mantissa bit can be extracted, realizing the parallel execution of mantissa multiplication and exponent extension bit decoding. This solves the delay problem in the traditional Posit format, which requires waiting for complete decoding before starting mantissa multiplication.

[0031] 2. The mantissa product of the present invention is only shifted once in the encoding stage, replacing the redundant operation of shifting in the decoding and encoding stages in the traditional method, reducing the number of operation layers of shift logic and reducing critical path delay.

[0032] 3. This invention converts the mantissa product into a fixed-point number and then directly performs addition operations, eliminating the need for exponent alignment operations required for floating-point accumulation, thus further shortening the delay of the accumulation path.

[0033] 4. This invention uses one-component complement encoding. Input and output processing only requires logical inversion to complete the sign-related operations, avoiding the adder required for the addition operation in the two-component complement solution process, reducing circuit area and power consumption. The rounding operation is implemented through combinational circuits to achieve simple rounding judgment bit logic, without the need for complex timing control, thus reducing logic resource consumption. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the multiplication operation logic in a calculation method based on the Posit data format according to Embodiment 1 of the present invention.

[0035] Figure 2 This is a schematic diagram of the data format in a calculation method based on the Posit data format according to Embodiment 1 of the present invention.

[0036] Figure 3 This is a schematic diagram of the accumulator format in a calculation method based on the Posit data format according to Embodiment 1 of the present invention.

[0037] Figure 4 This is a schematic diagram of the multiplication and accumulation logic in a calculation method based on the Posit data format according to Embodiment 1 of the present invention.

[0038] Figure 5 This is a schematic diagram of a logical shift operation in a calculation method based on the Posit data format according to Embodiment 1 of the present invention. Detailed Implementation

[0039] The present invention will be further described in detail below with reference to the accompanying drawings.

[0040] Example 1

[0041] Reference Figure 1 This embodiment of a calculation method based on the Posit data format includes:

[0042] Obtain the sign bit, exponent extension bit, mantissa bit, and exponent bit of the Posit data format, and preprocess each position of the Posit data format to obtain SR-Posit data.

[0043] The bit width allocation priority rule is defined based on the preprocessed sign bit, exponent extension bit, mantissa bit and exponent bit, and the SR-Posit data is encoded using one-complement form;

[0044] Using two encoded SR-Posit data as input data, and performing a decoding operation on the input data, the two mantissa bits obtained by decoding are multiplied to obtain the mantissa product and the mask sequence;

[0045] The number of leading zeros in the mantissa product is determined based on the mask sequence. Based on the number of exponent extension bits and the number of leading zeros in the mantissa product, a unified logical shift is performed on the mantissa product.

[0046] The mantissa portion after shifting is rounded, and the mantissa is concatenated with the equivalent exponent and then combined with the sign bit to obtain the product of the SR-Posit data.

[0047] Based on the sign bit, exponent extension bit, and exponent bit, the mantissa product is converted into a fixed-point number format, and addition is performed based on the fixed-point number to output the accumulated result.

[0048] Specifically, a calculation method based on the Posit data format includes the following steps:

[0049] like Figure 2 As shown, the sign bit, exponent extension bit, mantissa bit, and base bit segment that can be used as exponent bit are first extracted from the original Posit data. The sign bit is taken from the most significant bit of the original Posit data, the exponent extension bit corresponds to the dynamic part of the original Posit used to represent the exponent range, the mantissa bit corresponds to the part of the original Posit that represents the numerical precision, and the exponent bit is separated from the part of the exponent extension bit that can be fixed in width. Then, each extracted component is preprocessed: the sign bit is set to a 1-bit width, 0 represents a positive number and 1 represents a negative number, and it is placed in the most significant bit of the SR-Posit format.

[0050] The exponent extension bit consists of a continuous sequence of 0s or 1s, with a sequence length denoted as r. To clearly define its boundary with subsequent bit segments, a 1-bit end flag is added to the end of the sequence. Here, 1 bit represents one binary digit, and the end flag is the opposite of the sequence value. For example, the end flag for a 0 sequence is 1. If the sequence length r has already filled the total available bit width, where the total available bit width is the total bit width nb minus the sign bit (nb-1 bits), then there is no need to add an end flag. At the same time, the Rg value corresponding to the 0 sequence is defined as -r, and the Rg value corresponding to the 1 sequence is r-1. The exponent extension bit is placed after the sign bit. The mantissa bits use normalized encoding. The highest bit 1 of all valid mantissa bits is used as a hidden bit and is not actually stored to save bit width and improve precision. Its bit width is the total available bit width minus the remaining bit width after the exponent extension bit (including the end flag) and the exponent bit, and is placed after the exponent extension bit.

[0051] The exponent bit uses a fixed bit width (denoted as es, such as 2-bit) and is encoded as an unsigned integer to represent small-range adjustments of the exponent. It is placed after the mantissa bit as the least significant bit of the SR-Posit data. Then, the preprocessed bit segments are concatenated from the most significant bit to the least significant bit in the order of sign bit (S) to exponent extension bit (Rg) to mantissa bit (F) to exponent bit (E). Through the above preprocessing, the SR-Posit data has the characteristics of fixed sign bit and exponent bit width, clear exponent extension bit boundary, and improved mantissa bit precision. Moreover, the overall sorting makes the exponent extension bit and mantissa bit directly adjacent, which provides a basis for the parallel execution of mantissa multiplication and decoding in subsequent operations. The generated SR-Posit data can be directly entered into the subsequent encoding steps.

[0052] The total bit width is nb, which includes the bit width of all components. Since the sign bit is fixed at 1 bit in the preprocessing stage, the total available bit width is the total bit width nb minus the bit width of the sign bit, i.e., the total available bit width = nb - 1. This total available bit width will be used for the allocation of the exponent extension bit, mantissa bit, and exponent bit. Next, the priority rules for bit width allocation are defined: the total available bit width is first allocated to the exponent extension bit. The bit width requirement of the exponent extension bit is determined by the length of its continuous sequence itself and the end flag bit at the end of the sequence. The length of the continuous sequence is r, where r ≥ 1. The end flag bit is 1 bit, the binary bit opposite to the sequence value. When the sequence does not fill the total available bit width, the total bit width of the exponent extension bit is r + 1, i.e., the sequence length plus the end flag bit. If the length r of the continuous sequence is already equal to the total available bit width (i.e., r = nb - 1), then there is no need to allocate the end flag bit. At this time, the bit width of the exponent extension bit is directly r (i.e., nb - 1), and the total available bit width allocation is completed.

[0053] If there are remaining bits after allocating the exponent extension bits (i.e., remaining bits = total available bits - exponent extension bits > 0), then the remaining bits are allocated in the order of exponent bits first, then mantissa bits: First, they are allocated to the exponent bits, whose width is a fixed value es defined in the preprocessing stage (e.g., 2 bits). If the remaining bits are greater than or equal to es, then the exponent bits are allocated es width; if the remaining bits are less than es, then the exponent bits are allocated the entire remaining bit width. In this case, the actual width of the exponent bits is less than the preset es, where nb is the total bit width and es is the fixed width of the exponent bits, but its encoding rules still follow unsigned integer encoding. After completion, if there is still remaining bit width, i.e., remaining bit width = total available bit width - exponent extension bit width - exponent bit width > 0, then all remaining bit width is allocated to the mantissa bits as the effective bit width of the mantissa bits. The implicit highest bit of the mantissa bits (1) does not occupy this bit width. After bit width allocation, the SR-Posit data is encoded using two's complement. Specifically: for positive numbers (sign bit S=0), the exponent extension bits, mantissa bits, and exponent bits are encoded according to their actual values; for negative numbers (sign bit S=1), except for the sign bit, the exponent extension bits, mantissa bits, and exponent bits are all logically inverted, i.e., the characteristics of two's complement encoding, requiring no additional addition of 1. For positive numbers, i.e., sign bit S=0, the original values ​​of the exponent extension bit, mantissa bit, and exponent bit are kept unchanged during encoding. That is, the continuous sequence of exponent extension bits (0 sequence or 1 sequence) and its end flag bit are directly encoded according to the actual binary value, the effective bits of the mantissa bit are encoded according to the normalized original value, and the exponent bit is encoded according to the actual value of the unsigned integer. For example, if the exponent extension bit of a positive number is 001, which represents the 0 sequence "00" and the end flag "1", the mantissa bit is 101, the exponent bit is 01, and the sign bit S=0, then its encoding result is "0 001 101 01" concatenated in the order of sign bit, exponent extension bit, mantissa bit, and exponent bit.

[0054] For negative numbers (sign bit S=1), only the sign bit is kept as 1 during encoding. For all other bit segments except the sign bit, the exponent extension bit, mantissa bit, and exponent bit are logically inverted. Unlike two's complement encoding, there is no need to perform an additional increment operation after inversion. For example, if the positive number encoding (excluding the sign bit) corresponding to a negative number is "001 101 01", that is, exponent extension bit 001, mantissa bit 101, and exponent bit 01, then during encoding, the sign bit is first set to 1, and then the remaining bit segments are inverted bit by bit to obtain exponent extension bit "110", mantissa bit "010", and exponent bit "10". The final encoding result is 1 110 010 10.

[0055] The core advantage of this one-component encoding characteristic is that the conversion between positive and negative values ​​only needs to be achieved through a logic inversion circuit, without the need for additional adders, which significantly simplifies the hardware encoding logic. At the same time, the restoration of negative numbers during decoding only requires performing a logic inversion on the bit segment excluding the sign bit, avoiding the complex operation of subtracting 1 and then inverting in two-component encoding. In addition, the encoding process must follow the encoding rules for special values: when all bits are 0, it represents the value 0; when the sign bit is 1 and all other bits are 0, it represents an undefined value, similar to NaN or NaR. Through the definition of the above bit width allocation priority rules and one-component encoding, the SR-Posit format achieves flexible adaptation of the exponent and mantissa bit widths while ensuring the dynamic representation range, and the one-component encoding simplifies the conversion logic between positive and negative values.

[0056] like Figure 1 As shown, the system receives two encoded formatted data inputs, IN1 and IN2. First, the sign bits S1 and S2 are extracted. The highest bit (0 for positive, 1 for negative) is used. Based on the sign bit, it determines whether preprocessing is needed. If the sign bit is 1, all bits except the sign bit are logically inverted. Based on the one-two's complement encoding characteristics, the exponent extension bits are uniformly converted to the standard format "000…01". If the sign bit is 0, the original data except the sign bit is directly retained. After sign bit extraction and preprocessing, decoding is performed on IN1 and IN2 respectively. Operation: After removing the sign bit, the total bit width of the remaining data is nb-1, where nb is the total bit width of the SR-Posit format data. This part of the data includes the exponent extension bit, the mantissa bit, and the exponent bit, with the exponent extension bit located on the far left, i.e., in the direction of the most significant bit. When this nb-1 bit of data is input into the zero-prefix counter LZC, the core function of the zero-prefix counter is to scan the input data sequentially from the most significant bit to the least significant bit and count the number of consecutive 0s starting from the most significant bit. This number is the number of zeros in the zero-prefix counter.

[0057] Specifically, for decoding IN1: After removing its sign bit, we get nb-1 bits of data D1. D1 is input into a leading zero counter. The counter checks each bit sequentially, starting from the most significant bit. If the first bit (most significant bit) is 0, the count is incremented by 1. We continue checking the next bit; if it's still 0, the count continues to increment until the first non-zero bit is detected. This bit is the end marker of the exponent extension. Since the 0 sequence of the exponent extension ends with a 1, the counter stops counting. The current count result is the number of leading zeros r1 in IN1. Similarly, after removing the sign bit from IN2, we get nb-1 bits of data D2. D2 is input into a leading zero counter, and the number of consecutive 0s starting from the most significant bit is counted according to the same scanning rule to obtain IN2. The number of leading zeros is r2, where r1 represents the number of leading zeros in IN1 and r2 represents the number of leading zeros in IN2. This number is the sequence length of the exponent extension bit Rg. The value of Rg is determined based on the number of leading zeros. If it is a sequence of 0, then Rg1 = -r1 and Rg2 = -r2.

[0058] Next, the exponent bits are extracted. The first 1 after the leading zero sequence is located at the end of the exponent extension Rg. Then, the lowest es bit is truncated and used as the exponent bits E1 and E2. E1 represents the exponent of IN1, and E2 represents the exponent of IN2. es is a predefined fixed width for the exponent bits. If the sequence length r1 or r2 of Rg has filled nb-1 bits, meaning there are no remaining bits for the exponent bits, then the corresponding exponent bits E1 or E2 are set to 0. Next, the mantissa bits are extracted: after removing the sign bit, exponent extension Rg, and the exponent bits, the remaining bits are the mantissa bits F1 and F2. F1 represents the mantissa of IN1, and F2 represents the mantissa of IN2. The 1 at the end of Rg is used as the hidden mantissa bit, concatenated with F1 and F2 respectively to obtain the complete and valid mantissa, i.e., 1 + 1 / 2. During the decoding operations of F1 and 1+F2, the mantissa multiplication operation is initiated simultaneously: First, the two concatenated complete and valid mantissas are multiplied to obtain the initial mantissa product Pf. Then, a correction vector Pcorr is generated based on the bit width occupied by the exponent extension bits of IN1 and IN2. If the Rg bit width (r1+1) of IN1 is greater than nb-3 and the Rg bit width of IN2 is less than or equal to nb-3, then Pcorr = the mantissa value of IN2; if the Rg bit width of IN2 is greater than nb-3 and the Rg bit width of IN1 is less than or equal to nb-3, then Pcorr = the mantissa value of IN1; if the Rg bit width of both is greater than nb-3, then Pcorr = 1. Here, Pcorr represents the correction vector, which is a compensation value generated based on the Rg bit width of IN1 and IN2.

[0059] The lower nb bits of the mantissa product Pf are logically ORed with Pcorr to correct Pf and solve the problem of missing mantissa information caused by the excessive bit width of Rg. Specifically, the initial result obtained by multiplying the complete valid mantissas (1+F1 and 1+F2) of IN1 and IN2 has a bit width greater than the total bit width nb of the SR-Posit format. The lower nb bits refer to the consecutive nb bits in the mantissa product Pf starting from the least significant bit (rightmost bit). Finally, a mask sequence Mk is generated. The bit width of Mk is consistent with the corrected mantissa product Pf. The r1+r2 bits from left to right are set to 1, and the remaining bits are 0. This is used to determine the number of leading zeros in the mantissa product. Through the above operation, decoding and mantissa multiplication are executed in parallel, avoiding the delay of waiting for decoding to be completed before multiplication in the traditional Posit format. At the same time, the corrected mantissa product and mask sequence provide accurate data for subsequent normalization and can be directly used to determine the number of leading zeros and logical shift operations.

[0060] The number of leading zeros in the mantissa product is determined based on the mask sequence. The mask sequence Mk is generated in the previous step based on the number of leading zeros r1 and r2 of the exponent extension bits of the two input data IN1 and IN2. r1 and r2 are the exponent extension bits of IN1 and IN2, respectively. Their bit width is consistent with the mantissa product Pf, and only the (r1+r2)th bit from left to right is 1, while the rest are 0.Performing a bitwise logical AND operation between the mantissa product Pf and the mask sequence Mk yields the intermediate result vector Pfm. Each bit of Pfm is the result of the logical AND operation between the corresponding bit of Pf and the corresponding bit of Mk. Since only the (r1+r2)th bit of Mk is 1, only this bit in Pfm can be 1, with all other bits being 0. Specifically, since the mask sequence Mk is generated based on the number of leading zeros r1 in IN1 and r2 in IN2, its bit width is exactly the same as the mantissa product Pf. Furthermore, the binary structure of Mk is unique, with only the (r1+r2)th bit from left to right (from the most significant bit to the least significant bit) set to 1, and all other bits being 0. This structure determines that when performing a bitwise logical AND operation between Mk and the mantissa product Pf, each bit of the intermediate result vector Pfm is determined solely by the logical AND operation between the corresponding bit of Pf and the corresponding bit of Mk. The result of the logical AND operation between corresponding bits determines the result. When both corresponding bits are 1, the result is 1; otherwise, the result is 0. Based on this, for all bits in Mk except for the (r1+r2)th bit, which are all 0, regardless of whether the bit value at the corresponding position of Pf is 0 or 1, the logical AND result between them will always be 0. However, for the unique 1st bit in Mk (r1+r2), the logical AND result between it and the corresponding position (r1+r2) of Pf depends entirely on Pf. The value of this bit is used to perform a reduction logical OR operation on all bits of the intermediate result vector Pfm. That is, a logical OR operation is performed on each bit of Pfm in turn to obtain the overflow flag Pfovf. If Pfovf is 1, it means that the (r1+r2)th bit of Pf is 1. At this time, the number of leading zeros LZcnt in the mantissa product Pf is equal to the sum of r1 and r2, that is, LZcnt = r1 + r2. If Pfovf is 0, it means that the (r1+r2)th bit of Pf is 0. At this time, the number of leading zeros LZcnt is the sum of r1 and r2 plus 1, that is, LZcnt = r1 + r2 + 1. After determining the number of leading zeros, a unified logical shift operation is performed: first determine To determine the number of exponent extension bits for the product, the exponent extension bits Rg1 and E1 of IN1 are concatenated, and the exponent extension bits Rg2 and E2 of IN2 are concatenated to obtain the equivalent exponent bits Eeff1 and Eeff2. The concatenation method is to combine them in bit order, preserving the numerical representation meaning. Eeff1 and Eeff2 are then added to obtain the total equivalent exponent bits Eeff_total. Then, according to the bit width allocation rule of the SR-Posit format (prioritizing the allocation of exponent extension bits), the exponent extension bits Rg_prod of the product are separated from Eeff_total. The number of bits in Rg_prod is the number of exponent extension bits for the product.

[0061] Next, the logical shift amount shamt is calculated. The formula is shamt = number of exponent extension bits of the product + number of leading zeros LZcnt. Here, the number of exponent extension bits of the product refers to the number of bits occupied by the product exponent extension bits (Rg_prod) after the equivalent exponent bits of the two input data IN1 and IN2 are added together, according to the bit width allocation rules. This number of bits is determined by the large range adjustment requirements of the exponent and reflects the core allocation of the product result in the dynamic range of the exponent. The number of leading zeros LZcnt refers to the number of consecutive 0s starting from the most significant bit after the mantissa product is corrected. It is determined by the logical AND operation of the mask sequence and the mantissa product and the logical OR operation of the reduction logic. It reflects the starting position of the effective value part of the mantissa product. The core purpose of the logical shift is to move the effective value part of the mantissa product to the high bit so that the mantissa meets the normalization requirements, and at the same time move the leading zero sequence to the low bit as the basis for the product exponent extension bits.

[0062] The mantissa product Pf is logically shifted left according to the shift amount, moving the significant numerical part (excluding leading zeros) in Pf to the high-order bits and the leading zero sequence to the low-order bits. After the shift, the original leading zero sequence will serve as the basis for the exponent extension bits Rg_prod of the final product, while the significant mantissa part will be retained for subsequent rounding steps. Finally, the normalized mantissa product (Pf after logical left shift), the number of leading zeros LZcnt, and the logical shift amount shamt are output. These data will be directly used for subsequent mantissa rounding, exponent and mantissa concatenation, and other operations.

[0063] The rounding operation is performed on the effective mantissa portion after logical shifting in the previous step. The shifted mantissa includes core effective bits and redundant bits. The core effective bits are the number of bits to be retained, which are determined by the total bit width and bit width allocation rules of the SR-Posit format. The redundant bits are the part that exceeds the core effective bits. The highest bit of the redundant bits is taken as the rounding judgment bit. The rounding judgment bit is detected by the combinational circuit. If the bit is 1, the core effective bits are incremented by 1, i.e., rounded up. If it is 0, the core effective bits remain unchanged, i.e., rounded down. Then all redundant bits are truncated, and the rounded core effective mantissa is retained. For the combinational circuit, its core function is to generate the rounded core effective bits in real time based on the highest bit of the redundant bits, i.e., the rounding judgment bit. The combinational circuit contains three key modules: input interface module, judgment logic module, and increment logic module. The input interface module receives two sets of data: the core valid bit, determined by the total bit width nb and the bit width allocation rules, and the highest bit of the redundant bit, which is the rounding judgment bit, i.e., R. The judgment logic module is the core of the circuit, which consists of an NOT gate and an AND gate. When the rounding judgment bit R=1, the judgment logic module outputs a high-level signal (logic 1), triggering the increment logic module to work; when R=0, the judgment logic module outputs a low-level signal (logic 0), and the increment logic module does not work.

[0064] The increment logic module is essentially an m-bit binary adder. Its input is connected to the core valid bit and the output signal of the judgment logic module. When a high-level trigger signal (R=1) is received, the adder performs a binary increment operation on the core valid bit and 1. For example, if the core valid bit is 1011, the result after incrementing is 1100. If a carry is generated during the increment process, such as if the core valid bit is 1111 and the result after incrementing is 10000, only the lower m bits are retained as the result, i.e., 0000. The carry is truncated. Since the width of the core valid bit is fixed, the excess part does not need to be retained. When no trigger signal R=0 is received, the increment logic module directly outputs the original core valid bit.

[0065] The circuit output is connected to a truncation module. Regardless of whether an increment operation is performed, all redundant bits will be truncated, leaving only m core valid bits. The final output is the rounded core valid mantissa. For example, if the core valid bits are 101 (3 bits) and the highest redundant bit R=1, the combinational circuit will output 110 after increment logic; if R=0, it will directly output 101.

[0066] Next, the mantissa and equivalent exponent are concatenated. First, the exponent extension and exponent of the product are determined: based on the equivalent exponent Eeff1 of IN1 (the result of concatenating Rg1 and E1) and the equivalent exponent Eeff2 of IN2 (the result of concatenating Rg2 and E2) from the previous step, the two are added together to obtain the total equivalent exponent Eeff_total. Then, according to the bit width allocation priority rule of the SR-Posit format (prioritizing the exponent extension and allocating the remaining bits to the exponent), the exponent extension Rg_prod and the exponent E_prod of the product are separated from Eeff_total. In order from the most significant bit to the least significant bit, Rg_prod, the rounded mantissa, and E_prod are concatenated to form a bit sequence without the sign bit.

[0067] Next, the sign bit is combined and the final encoding is adjusted: the sign bit Spd of the product is the XOR result of the sign bit S1 of IN1 and the sign bit S2 of IN2, that is, Spd = S1 ⊕ S2, where ⊕ represents the XOR sign, and S1 and S2 represent the sign bits of IN1 and IN2, respectively. Spd is placed in the most significant bit of the aforementioned bit sequence without the sign bit to form a complete bit sequence. The sign of Rg_prod is used to determine whether logical inversion is needed. If Rg_prod is negative, that is, the sequence starts with 1, then logical inversion is performed on all bits except Spd. The result after encoding adjustment is the defined product data, which includes the sign bit, the exponent extension bit Rg_prod, the rounded mantissa bits, and the exponent E_prod, and can be directly used for storage or subsequent calculations.

[0068] like Figure 3 , Figure 5 As shown, the final step is to convert the mantissa product to a fixed-point format, targeting the fixed-point format of the precise accumulator Qr. The precise accumulator has a total bit width of 16nb, where nb is the total bit width of the SR-Posit format. This format includes a sign bit, a 31-bit extension bit, an 8nb-16-bit integer part, and an 8nb-16-bit fractional part to avoid precision loss during accumulation. During the conversion, the mantissa product Pf obtained in the previous steps is first placed at the right end of the least significant bit of the precise accumulator Qr, i.e., the rightmost least significant bit region. Then, based on the XOR result of the sign bits IN1 and IN2, i.e., the product sign bit Spd, Pf is sign-expanded. If Spd=0 (positive number), then 0 is padded to the high bits of Pf; if Spd=1, then 1 is padded to the high bits of Pf, until the total bit width after expansion reaches 16nb, consistent with the bit width of the precise accumulator Qr. Then, according to the shift amount determined in the previous steps, shamt=the number of exponent extension bits of the product + the number of leading zeros LZcnt, where shamt represents the shift amount, a logical left shift is performed on the sign-expanded Pf to adjust the value to the position matching the integer / fractional bits of the fixed-point number. Only the high 16nb bits of the result after left shift are retained, and the low redundant bits are truncated to obtain the product Qr_prod in fixed-point format.

[0069] like Figure 4 As shown, after the conversion is completed, the addition operation is performed. The third fixed-point number Qr_acc, which is the current value of the accumulator, is received from the external input. It is in the precise accumulator Qr format, with a 16nb bit width, including the sign bit, extension bit, integer part, and fractional part. The 16nb bit width adder performs the addition operation on Qr_prod and Qr_acc. Here, Qr_prod represents the product in fixed-point format, and Qr_acc represents the value currently stored in the accumulator. The adder directly performs the addition on the corresponding bits of the two fixed-point numbers without additional exponent alignment. Because the fixed-point format has already achieved numerical alignment through shifting, and the bit width covers all bit fields, including the 31-bit extension bit, the precision loss caused by accumulation overflow is avoided.

[0070] After the addition operation is completed, the final accumulated result is output. This result is retained as a fixed-point number (16nb bit width) in the format of a precise accumulator Qr, which can be directly used for the next multiply-accumulate operation, i.e., as a new Qr_acc, or converted to SR-Posit format for output as needed.

[0071] In the computational circuit of AI computing chips, the multiplication and accumulation results of this embodiment are used in core computations such as convolution and matrix multiplication in deep learning. These computations require multiplication and accumulation operations on large amounts of data, such as element-wise multiplication and accumulation of convolution kernels and input feature maps, and multiplication and accumulation of weights of fully connected layers and input vectors. In this solution, the multiplication results can be directly used in scenarios requiring high-precision single-step multiplication, such as temporary storage of intermediate results. The multiplication and accumulation process (mantissa product to fixed-point number and fixed-point number addition) is adapted to the continuous multiplication and accumulation requirements. The computational circuit can integrate the aforementioned fixed-point adder and shift logic, and realize the pipelined execution of multiplication, conversion, and accumulation through hardware pipelined design, reducing data interaction latency. At the same time, the extended bit design of the precise accumulator is adapted to the precision requirements of multiple accumulations of small values ​​in AI computation. The 16nb wide fixed-point number format can be directly connected to the adder through hardware registers, supporting parallel computation and significantly improving the computational efficiency and adaptability of AI computing chips.

[0072] Example 2

[0073] The difference between this embodiment and Embodiment 1 is that this embodiment provides a calculator based on the Posit data format, including:

[0074] The data acquisition module is configured to: acquire the sign bit, exponent extension bit, mantissa bit and exponent bit of the Posit data format, and preprocess each position of the Posit data format to obtain SR-Posit data;

[0075] The encoding module is configured to define a bit width allocation priority rule based on the preprocessed sign bit, exponent extension bit, mantissa bit, and exponent bit, and to encode the SR-Posit data using a two's complement form.

[0076] The mantissa multiplication module is configured to: use two encoded SR-Posit data as input data, perform decoding operations on the input data, and multiply the two mantissa bits obtained by decoding to obtain the mantissa product and the mask sequence;

[0077] The normalization module is configured to: determine the number of leading zeros in the mantissa product based on the mask sequence, and perform a unified logical shift on the mantissa product based on the number of exponent extension bits and the number of leading zeros in the mantissa product;

[0078] The product encoding module is configured to: perform a rounding operation on the shifted mantissa, concatenate the mantissa bits with the equivalent exponent bits and combine them with the sign bit to obtain the product result of the SR-Posit data;

[0079] The accumulation module is configured to convert the mantissa product into a fixed-point number format based on the sign bit, exponent extension bit, and exponent bit, perform addition operations based on the fixed-point number, and output the accumulation result.

[0080] The above are all preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Therefore, all equivalent changes made in accordance with the structure, shape and principle of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A calculation method based on the Posit data format, characterized in that, include: The sign bit, exponent extension bit, mantissa bit, and exponent bit of the Posit data format are obtained, and each position of the Posit data format is preprocessed, including setting the sign bit width of the Posit data format to 1-bit, the exponent extension bit consisting of a continuous sequence of numbers, and ending the sequence with a 1-bit wide binary bit that is opposite to the sequence value as an end marker, the mantissa bit using normalized encoding and hiding the highest bit 1, and the exponent bit using a fixed value width and encoding with an unsigned integer, and sorting them in the order of sign bit, exponent extension bit, mantissa bit, and exponent bit to obtain SR-Posit data; A bit width allocation priority rule is defined based on the preprocessed sign bit, exponent extension bit, mantissa bit, and exponent bit. SR-Posit data is encoded using a two's complement. The bit width allocation priority rule includes removing the sign bit from the total bit width to obtain the total available bit width. The total available bit width is first allocated to the exponent extension bit. The bit width requirement of the exponent extension bit includes the bit width occupied by its sequence itself and the end flag at the end of the sequence. The end flag bit of the exponent extension bit is 1 bit and is the opposite of the value of the sequence itself. When the length of the sequence itself is equal to the total available bit width, the bit width of the exponent extension bit is the length of the sequence itself, and no end flag bit needs to be allocated. When there is still a remaining bit width after the total available bit width is allocated to the exponent extension bit, the remaining bit width is first allocated to the exponent bit, and then the remaining bit width after being allocated to the exponent bit is allocated to the mantissa bit. Using two encoded SR-Posit data as input data, and performing a decoding operation on the input data, the two mantissa bits obtained by decoding are multiplied to obtain the mantissa product and the mask sequence; The number of leading zeros in the mantissa product is determined based on the mask sequence. Based on the number of exponent extension bits and the number of leading zeros in the mantissa product, a unified logical shift is performed on the mantissa product. The unified logical shift of the mantissa product includes concatenating the exponent extension bits of IN1 and IN2 with the exponent bits to obtain the equivalent exponent bits. The number of exponent extension bits of the product is calculated based on the equivalent exponent bits. The number of exponent extension bits and the number of leading zeros in the product are added to obtain the displacement. A logical left shift operation is performed on the mantissa product according to the displacement, shifting the effective value part to the high bit and the leading zero sequence to the low bit. The shifted leading zero sequence is used as the basis for the exponent extension bits of the final product. The normalized mantissa product, the number of leading zeros, and the logical shift amount are output. The mantissa portion after shifting is rounded, and the mantissa bits are concatenated with the equivalent exponent bits and combined with the sign bit to obtain the product result of the SR-Posit data. Finally, the mantissa product is converted to a fixed-point number format, with the fixed-point number format of the precise accumulator Qr as the target. The total bit width of the precise accumulator is 16nb, where nb is the total bit width of the SR-Posit format. Based on the sign bit, exponent extension bit, and exponent bit, the mantissa product is converted into a fixed-point number format. Addition is performed based on the fixed-point number, the accumulated result is output, and the accumulated result is stored as a fixed-point number in the format of a precise accumulator Qr. By integrating fixed-point adders and shift logic into the arithmetic circuit of AI computing chips, and implementing pipelined execution of multiplication, conversion, and accumulation through hardware pipelined design, fixed-point numbers are directly connected to the adders through hardware registers, supporting parallel computing and improving the computing efficiency of AI computing chips.

2. The calculation method based on the Posit data format according to claim 1, characterized in that, The decoding operation of the input data includes receiving two encoded SR-Posit data IN1 and IN2, removing the sign bits of IN1 and IN2, calculating the number of leading zeros r1 and r2 for the remaining data using a leading zero counter, determining the exponent extension bits Rg1 and Rg2 based on r1 and r2 respectively, extracting the fixed-width bits of the lowest exponent bit after the end bits of Rg1 and Rg2 as exponent bits E1 and E2, removing the sign bit, exponent extension bit, and exponent bit from IN1 and IN2 respectively, using the remaining bits as mantissa bits F1 and F2, using the 1 in the end bits of Rg1 and Rg2 as hidden bits, and concatenating them with F1 and F2 respectively to obtain the complete valid mantissa; Where E1 represents the exponent of input data IN1, E2 represents the exponent of IN2, F1 represents the mantissa of IN1, F2 represents the mantissa of IN2, r1 and r2 represent the number of leading zeros in IN1 and IN2 respectively, and Rg1 and Rg2 represent the exponent extension bits of IN1 and IN2 respectively.

3. The calculation method based on the Posit data format according to claim 1, characterized in that, The process of multiplying the two mantissa bits obtained from decoding includes performing a multiplication operation on the complete and valid mantissas of IN1 and IN2 to obtain a mantissa product, generating a correction vector based on the bit width occupied by the exponent extension bits in IN1 and IN2, performing a logical OR operation on the lower bits of the mantissa product with the correction vector to correct the mantissa product, and finally generating a mask sequence with the exponent extension bits of IN1 and IN2 as the length. The bit width of the mask sequence is consistent with the bit width of the mantissa product, and only the position of the sum of the exponent extension bits of IN1 and IN2 from left to right is set to 1, while all other bits are 0.

4. The calculation method based on the Posit data format according to claim 1, characterized in that, The step of determining the number of leading zeros in the mantissa product based on the mask sequence includes performing a bitwise logical AND operation on the mantissa product and the mask sequence to generate an intermediate result vector, performing a reduction logical OR operation on all bits of the intermediate result vector to obtain an overflow flag, and calculating the number of leading zeros in the mantissa product based on the overflow flag.

5. The calculation method based on the Posit data format according to claim 1, characterized in that, The product result of the obtained SR-Posit data includes the exponent extension bit and the exponent bit of the product calculated based on the equivalent exponent bits of IN1 and IN2. The exponent extension bit, the rounded mantissa, and the exponent bit of the product are concatenated in order from the most significant bit to the least significant bit to obtain a bit sequence without a sign bit. The XOR result of the sign bits of IN1 and IN2 is concatenated with the bit sequence to form a complete bit sequence. The final encoding adjustment is then performed, and the product result is output.

6. The calculation method based on the Posit data format according to claim 1, characterized in that, The fixed-point addition operation includes converting the product into a fixed-point format of a precise accumulator based on the mantissa product, sign bit, exponent extension bit, and exponent bit, and placing it at the right end of the least significant bit of the precise accumulator; extending the mantissa product by the XOR result of the sign bits of IN1 and IN2; performing a logical left shift on the sign-extended mantissa product according to the displacement to obtain the fixed-point format product; adding the fixed-point format product with the externally input fixed-point number; and outputting the final accumulation result.

7. A computation unit based on the Posit data format, executing the method of claim 1, characterized in that, include: The data acquisition module is configured to: acquire the sign bit, exponent extension bit, mantissa bit and exponent bit of the Posit data format, and preprocess each position of the Posit data format to obtain SR-Posit data; The encoding module is configured to define a bit width allocation priority rule based on the preprocessed sign bit, exponent extension bit, mantissa bit and exponent bit, and encode the SR-Posit data using a two's complement form. The mantissa multiplication module is configured to: use two encoded SR-Posit data as input data, perform decoding operations on the input data, and multiply the two mantissa bits obtained by decoding to obtain the mantissa product and the mask sequence; The normalization module is configured to: determine the number of leading zeros in the mantissa product based on the mask sequence, and perform a unified logical shift on the mantissa product based on the number of exponent extension bits and the number of leading zeros in the mantissa product; The product encoding module is configured to: perform a rounding operation on the shifted mantissa, concatenate the mantissa bits with the equivalent exponent bits and combine them with the sign bit to obtain the product result of the SR-Posit data; The accumulation module is configured to convert the mantissa product into a fixed-point number format based on the sign bit, exponent extension bit, and exponent bit, perform addition operations based on the fixed-point number, and output the accumulation result.

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