Data processing device and method, electronic equipment and storage medium

Abstract

The invention provides a data processing device, and relates to the technical field of artificial intelligence, in particular to the technical field of chips and the technical field of processor assembly lines. The device comprises: N computing units, N being an integer greater than or equal to 1; the counting units correspond to the N calculation units; the control unit is configured to determine the initial count value of the current instruction according to the execution duration of the current instruction in response to the determination that the current instruction starts to be executed by the N calculation units, and the execution duration comprises the duration of a plurality of execution cycles; providing an initial count value of the current instruction to a counting unit; acquiring a current count value of the current instruction from a counting unit in an execution period when the current instruction is executed; and in response to determining that the current count value of the current instruction and the execution duration of the later instruction of the current instruction meet the preset condition, controlling the later instruction to be provided to at least one computing unit in the N computing units. The invention further provides a data processing method, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, in particular to the field of chip technology and processor pipeline technology. More specifically, the present disclosure provides a data processing device, method, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, in various application scenarios, Domain Specific Architecture (DSA) chips can better meet the computing power requirements. Summary of the Invention

[0003] The present disclosure provides a data processing apparatus, method, device, and storage medium.

[0004] According to one aspect of the present disclosure, a data processing device is provided, which includes: N computing units, where N is an integer greater than or equal to 1; a counting unit corresponding to the N computing units; a control unit configured to: in response to determining that a current instruction begins to be executed by the N computing units, determine an initial count value of the current instruction based on the execution duration of the current instruction, where the execution duration includes the duration of multiple execution cycles; provide the initial count value of the current instruction to the counting unit; obtain the current count value of the current instruction from the counting unit in the execution cycle in which the current instruction is executed; and in response to determining that a preset condition is satisfied between the current count value of the current instruction and the execution duration of a subsequent instruction of the current instruction, control the subsequent instruction to be provided to at least one computing unit among the N computing units.

[0005] According to another aspect of the present disclosure, an electronic device is provided, including: the data processing device provided by the present disclosure.

[0006] According to another aspect of the present disclosure, a data processing method is provided, the method comprising: in response to determining that a current instruction begins to be executed by N computing units, determining an initial count value of the current instruction according to the execution duration of the current instruction, wherein the execution duration includes the duration of multiple execution cycles, and N is an integer greater than or equal to 1; providing the initial count value of the current instruction to a counting unit, wherein the counting unit corresponds to the N computing units; in the execution cycle in which the current instruction is executed, obtaining a current count value of the current instruction from the counting unit; and in response to determining that a preset condition is satisfied between the current count value of the current instruction and the execution duration of a subsequent instruction of the current instruction, controlling the subsequent instruction to be provided to at least one computing unit among the N computing units.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method provided according to the present disclosure.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0009] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements the method provided according to the present disclosure when executed by a processor.

[0010] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0012] Figure 1 is a schematic diagram of an exemplary system architecture of an artificial intelligence chip according to one embodiment of the present disclosure;

[0013] Figure 2 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram of multiple computing units according to one embodiment of the present disclosure;

[0015] Figure 4 is a schematic diagram of multiple computing units according to one embodiment of the present disclosure;

[0016] Figure 5 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure;

[0017] Figure 6 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure; and

[0018] Figure 7 is a block diagram of an electronic device to which a data processing method according to an embodiment of the present disclosure can be applied. DETAILED DESCRIPTION

[0019] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0020] Domain-specific architecture chips can include general-purpose graphics processing units (GPGPUs), tensor processing units (TPUs), and neural network processing units (NPUs). Domain-specific architecture chips can accelerate specific tasks (such as deep learning tasks) and improve task execution efficiency.

[0021] Deep learning algorithms are computationally intensive. To improve computational throughput, deep learning instructions can be fused. These instructions combine the functionality of multiple single instructions. Examples include multiply-add instructions and add-multiply instructions. Different deep learning instructions require varying computing resources and computation times, significantly increasing the difficulty of hardware design. Some complex deep learning instructions can take dozens of clock cycles to execute. Furthermore, the mixed execution of different deep learning instructions can potentially cause hardware pipeline blockages, impacting computational throughput and resulting in performance losses.

[0022] Figure 1 2 is a schematic diagram of an exemplary system architecture of an artificial intelligence chip according to an embodiment of the present disclosure.

[0023] like Figure 1 As shown, chip 100 may include an instruction fetch module 101, a decoding module 102, an execution module 103, a memory access module 104, and a write-back module 105. Each module may function as a first stage of a pipeline. Instruction fetch module 101 may fetch instructions. Decoding module 102 may decode the instructions and obtain a decoding result. Based on the decoding result, execution module 103 may perform operations corresponding to the instructions and obtain an execution result. Memory access module 104 may read data from a storage unit or write data to a storage unit. Write-back module 105 may write the execution result to a register.

[0024] The execution module 103 may correspond to multiple computing units. These may include an addition and subtraction computing unit 1101, a multiplication computing unit 1102, a division computing unit 1103, ..., and a logic computing unit 1104. Different types of instructions may utilize different types, quantities, and cycles of computing units. If the chip 100 is a vector processor, it may be difficult for the chip 100 to implement reordering between instructions and to fully optimize the pipeline between successive instructions.

[0025] In order to improve the accuracy and efficiency of the chip, in some embodiments, when the execution module 103 obtains the current instruction and the subsequent instructions of the current instruction, after the current instruction completely releases each computing unit, the related operations of the subsequent instructions can be executed by the execution module 103. However, when switching between different instructions, the operation of some computing units will stagnate, and it is difficult to improve the efficiency of the pipeline, resulting in chip performance loss and waste of computing resources. When the instruction granularity is large, this loss or waste can be ignored. However, when the instruction granularity is small, this loss or waste is difficult to be ignored, the execution efficiency of the chip will drop significantly, and the advantages of the vector processor cannot be reflected. It can be understood that the instruction granularity can be the number of operations involved in executing the instruction. The advantages of the vector processor are pipelining and parallelism.

[0026] To improve chip accuracy and efficiency, in some embodiments, different computing units can be synchronized to the same latency to implement pipelining in some scenarios. However, synchronizing different computing units to the same latency introduces additional register ticking logic, resulting in increased area and power consumption due to data movement.

[0027] Based on this, in order to improve the performance of the chip, the present disclosure provides a data processing device, which will be described below.

[0028] Figure 2 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure.

[0029] like Figure 2 As shown, the apparatus 200 may include N computing units 210, counting units 220, and control units 230. N may be an integer greater than or equal to 1.

[0030] The N computing units 210 may be configured to perform various operations. For example, the N computing units may correspond to the execution module 103 .

[0031] The counting unit 220 may correspond to the N computing units. In the embodiment of the present disclosure, the counting unit 220 may perform a counting operation based on an initial count value and a preset value. For example, the counting unit 220 may perform an addition operation based on the initial count value and the preset value, or may perform a subtraction operation based on the initial count value and the preset value.

[0032] The control unit 230 may be configured to, in response to determining that the current instruction begins execution by N computing units, determine an initial count value for the current instruction based on the execution duration of the current instruction. For example, the execution duration of the current instruction may be determined based on the number of computing units involved in the current instruction. The execution duration may include the duration of multiple execution cycles. The execution cycle may be a clock cycle. For another example, the initial count value may be zero or the execution duration of the current instruction.

[0033] The control unit 230 may also be configured to provide an initial count value of the current instruction to the counting unit. For example, the initial count value may be provided to the counting unit 220 so that the counting unit 220 begins counting. For another example, if the initial count value is zero, then at each execution cycle, the counting unit 220 may determine the sum of the count value of the previous execution cycle and a preset value. If the initial count value is the execution duration of the current instruction, then at each execution cycle, the counting unit 220 may determine the difference between the count value of the previous execution cycle and the preset value.

[0034] The control unit 230 may also be configured to obtain a current count value of the current instruction from the counting unit during the execution cycle of the current instruction. For example, the current instruction may be executed in multiple execution cycles. The current count value of the current instruction may be obtained during one or more execution cycles of the current instruction.

[0035] The control unit 230 may also be configured to: in response to determining that a preset condition is satisfied between a current count value of the current instruction and an execution time of a subsequent instruction of the current instruction, control the subsequent instruction to be provided to at least one of the N computing units.

[0036] In the embodiment of the present disclosure, the current instruction and the subsequent instruction may be different. For example, the current instruction may be a multiply-add instruction, and the subsequent instruction may be an addition instruction.

[0037] In an embodiment of the present disclosure, the preset condition may be: when the current count value of the current instruction is less than or equal to the initial count value of the current instruction, the current count value of the current instruction is less than or equal to the execution duration of the subsequent instruction. For example, as described above, if the initial count value is the execution duration of the current instruction, in each execution cycle, the counting unit 220 may determine the difference between the count value of the previous execution cycle and the preset value. Thus, for the current instruction, the current count value may be less than or equal to the initial count value. When the current count value is less than or equal to the execution duration of the subsequent instruction, the subsequent instruction may be controlled to be executed by the corresponding computing unit in the N computing units 110.

[0038] Through the embodiments of the present disclosure, a counting unit is set corresponding to the computing unit. When the count value of the counting unit and the execution time of the subsequent instruction meet the preset conditions, the subsequent instruction is executed, which can fully realize instruction order preservation, avoid result conflicts and resource conflicts between instructions, improve the pipeline execution efficiency of the processing device, and also improve the accuracy of the data processing device.

[0039] It can be understood that the device 200 can be obtained by setting a corresponding counting unit for the calculation unit of the chip 100 and configuring the control unit of the chip 100.

[0040] It can be understood that the above describes the data processing device of the present disclosure, and the current instruction and subsequent instructions of the present disclosure will be further described below.

[0041] In some embodiments, the execution time of the subsequent instruction is less than or equal to the execution time of the current instruction. For example, the current instruction may be a fusion instruction, which may be implemented as:

[0042] i=d*e+f*g+h (Formula 1)

[0043] The instruction following the current instruction may be a multiplication instruction, which can be implemented as follows:

[0044] c=a*b (Formula 2)

[0045] d, e, f, g, and h can be the input data of the fusion instruction, and i can be the execution result of the fusion instruction. a and b can be the input data of the multiplication instruction, and c can be the execution result of the multiplication instruction.

[0046] For another example, the execution time of a fusion instruction may be 9 execution cycles, and the execution time of a multiplication instruction may be 3 execution cycles.

[0047] It can be understood that the instructions of the present disclosure are described above, and the apparatus of the present disclosure will be further described below in conjunction with the result conflict.

[0048] Figure 3 is a schematic diagram of multiple computing units according to one embodiment of the present disclosure.

[0049] like Figure 3 As shown, the plurality of calculation units may include a multiplication calculation unit M30, a multiplication calculation unit M31, an addition calculation unit A30, and an addition calculation unit A31.

[0050] The multiple computing units can execute the above fusion instruction. In the embodiment of the present disclosure, the N computing units that execute the current instruction include a first computing unit and a second computing unit. Figure 3As shown, multiple computing units can execute the above-mentioned fused instruction from the first to the third time periods. For example, in the first time period T30, the multiplication computing unit M30 may multiply input data d30 and input data e30 to obtain a first multiplication result. In the second time period T31, the addition computing unit A30 may add input data h30 and the first multiplication result to obtain a first addition result. Furthermore, in the second time period T31, the multiplication computing unit M31 may multiply input data f30 and input data g30 to obtain a second multiplication result. Next, in the third time period T32, the addition computing unit A31 may add the first addition result and the second multiplication result to obtain the execution result res30 of the fused instruction. The first time period T30 may, for example, include three first execution cycles, namely, the first to the third execution cycles. The second time period T31 may include three second execution cycles, namely, the fourth to the sixth execution cycles. The multiplication computing unit M30 may serve as the first computing unit. The addition calculation unit A30 may serve as a second calculation unit.

[0051] The subsequent instruction of the fusion instruction may be the above-mentioned multiplication instruction. In an embodiment of the present disclosure, at least one computing unit that executes the subsequent instruction includes a first computing unit. For example, if the above-mentioned multiplication instruction and the fusion instruction are provided to the pipeline at the same time, the multiplication computing unit M30 among the multiple computing units is in an idle state after the first time period, and the multiplication instruction can be executed. For example, in the second time period T31, the multiplication computing unit M30 can multiply the input data a30 and the input data b30 to obtain the execution result res31 of the multiplication instruction. That is, after the second time period T31, the multiplication instruction has been executed. The execution result res31 will appear before the execution result res30, which may cause an error in the instruction execution order and a problem with the result. It can be understood that the first time period T30, the second time period T31 and the third time period T32 can each include 3 execution cycles.

[0052] Therefore, in order to alleviate the result conflict, the data processing device provided by the present disclosure can be used to execute the above fused instruction and multiplication instruction. The fused instruction can be first provided to the pipeline so that multiple computing units start to execute the fused instruction.

[0053] In some embodiments, the control unit may be configured to, in response to determining that the current instruction begins to be executed by the N computing units, determine an initial count value for the current instruction based on the execution duration of the current instruction. For example, the execution duration of the fused instruction may be 9 execution cycles. When the fused instruction begins to be executed by the multiplication computing unit M30 in the plurality of computing units, the initial count value for the fused instruction may be determined to be 9 based on the execution duration of the fused instruction.

[0054] In some embodiments, the control unit may be further configured to provide an initial count value of the current instruction to the counting unit. For example, the initial count value 9 of the fused instruction may be provided to the counting unit so that the counting unit starts counting.

[0055] In some embodiments, the counting unit may be configured to determine a current count value of the current instruction during an execution cycle in which the current instruction is executed. For example, the current count value of the current instruction may be less than or equal to an initial count value of the current instruction.

[0056] In an embodiment of the present disclosure, the counting unit may further be configured to: when the current execution cycle is the starting execution cycle for the current instruction, receive the initial count value of the current instruction, and use the initial count value of the current instruction as the current count value of the current instruction. For example, the starting execution cycle may be the first execution cycle in which the fused instruction is executed. In the first execution cycle, the counting unit may use the initial count value of 9 of the fused instruction as the current count value for the first execution cycle.

[0057] In an embodiment of the present disclosure, the counting unit may further be configured to determine, when the current execution cycle is not the starting execution cycle, the current count value of the current instruction based on the difference between the previous count value and the preset value. The previous count value is the count value of the current instruction in the execution cycle before the current execution cycle. For example, in the second execution cycle in which the fused instruction is executed, the previous count value may be 9, the preset value may be 1, and the difference between the two is 8, which may be used as the current count value of the fused instruction in the second execution cycle.

[0058] In some embodiments, the control unit may be further configured to obtain the current count value of the current instruction from the counting unit during the execution cycle in which the current instruction is executed. For example, the control unit may obtain the current count value of the fused instruction from the counting unit during each execution cycle, and determine whether the current count value is less than or equal to the execution duration of the subsequent instruction during each execution cycle. In the second execution cycle, the control unit may obtain a current count value of 8 from the counting unit. If the current count value of 8 is greater than the execution duration of 3 of the subsequent instruction, the control unit may repeat the operation of obtaining the current count value in the next execution cycle.

[0059] In some embodiments, the control unit can also be configured to: in response to determining that a preset condition is satisfied between the current count value of the current instruction and the execution time of the subsequent instruction of the current instruction, control the subsequent instruction to be provided to at least one computing unit among the N computing units.

[0060] In an embodiment of the present disclosure, in response to determining that the current count value of the current instruction is less than or equal to the execution duration of the subsequent instruction, a control signal is generated. The control signal is provided to the firing unit. For example, in the seventh execution cycle, the current count value of the fused instruction may be 3. The current count value is equal to the execution duration of the subsequent instruction. The control unit may generate a control signal and provide the control signal to the firing unit.

[0061] In an embodiment of the present disclosure, the emission unit may be further configured to, in response to receiving a control signal, provide a subsequent instruction to at least one of the N computation units. For example, the emission unit may provide the aforementioned multiplication instruction to the multiplication computation unit M30. Thus, for example, in the 8th or 9th execution cycle of the fused instruction, the multiplication computation unit M30 may multiply the input data a30 and the input data b30 to obtain an execution result res31.

[0062] In addition, the control unit can also be configured to: in response to determining that the subsequent instruction begins to be executed by at least one computing unit, determine the initial count value of the subsequent instruction based on the execution time of the subsequent instruction. Provide the initial count value of the subsequent instruction to the counting unit. For example, after the multiplication instruction begins to be executed, the corresponding initial count value can be determined based on the execution time of the multiplication instruction, and the initial count value can be provided to the counting unit so that the counting unit restarts counting. It can be understood that the processing method of the counting unit and the control unit for the subsequent instruction is the same or similar to the processing method for the current instruction, and the present disclosure will not be repeated here.

[0063] Through the embodiments of the present disclosure, result conflicts can be effectively alleviated, so that multiple instructions can be executed in sequence. Pipeline resources can also be fully utilized to improve the smoothness of the pipeline and reduce pipeline stagnation.

[0064] It can be understood that the above description of the apparatus of the present disclosure is combined with a method for alleviating result conflicts, and the following description of the data processing apparatus of the present disclosure is further combined with a method for alleviating resource conflicts.

[0065] In some embodiments, the execution time of the subsequent instruction is less than or equal to the execution time of the current instruction. For example, the current instruction may be a fused instruction, which may be implemented as the above formula 1.

[0066] Different from the subsequent instruction corresponding to the above formula 2, the subsequent instruction of the current instruction may be an addition instruction, which can be implemented as:

[0067] c′=a+b (Formula 3)

[0068] a and b can be the input data of the multiplication instruction, and c' can be the execution result of the addition instruction.

[0069] For another example, the execution time of a fusion instruction may be 9 execution cycles, and the execution time of an addition instruction may be 3 execution cycles.

[0070] Figure 4 is a schematic diagram of multiple computing units according to one embodiment of the present disclosure.

[0071] like Figure 4 As shown, the plurality of calculation units may include a multiplication calculation unit M40, a multiplication calculation unit M41, an addition calculation unit A40, and an addition calculation unit A41.

[0072] The multiple computing units can execute the above fusion instruction. In the embodiment of the present disclosure, the N computing units that execute the current instruction include a first computing unit and a second computing unit. Figure 4 As shown, multiple computing units can execute the above-mentioned fused instruction from the first to the third time periods. For example, in the first time period T40, the multiplication computing unit M40 may multiply input data d40 and input data e40 to obtain a first multiplication result. In the second time period T41, the addition computing unit A40 may add input data h40 and the first multiplication result to obtain a first addition result. Furthermore, in the second time period T41, the multiplication computing unit M41 may multiply input data f40 and input data g40 to obtain a second multiplication result. Next, in the third time period T42, the addition computing unit A41 may add the first addition result and the second multiplication result to obtain the execution result res40 of the fused instruction. The first time period T40 may, for example, include three first execution cycles, namely, the first to the third execution cycles. The second time period T41 may include three second execution cycles, namely, the fourth to the sixth execution cycles. The multiplication computing unit M40 may serve as the first computing unit. The addition calculation unit A40 may serve as a second calculation unit.

[0073] The subsequent instruction of the fusion instruction may be the above-mentioned addition instruction. In an embodiment of the present disclosure, at least one computing unit that executes the subsequent instruction includes a second computing unit. For example, if the above-mentioned addition instruction and the fusion instruction are provided to the pipeline at the same time, in the first time period T40, the computing unit that executes the fusion instruction does not include the addition computing unit A40. Thus, the addition computing unit A40 can execute the addition instruction. However, in the second time period T41, the addition computing unit A40 is to add the first multiplication calculation result and the input data h40. Since the addition computing unit A40 executes the addition instruction in the first time period T40, the addition computing unit A40 may not be released and cannot execute the related operations of the fusion instruction in time, resulting in a computing resource conflict.

[0074] Therefore, in order to alleviate computing resource conflicts, the data processing apparatus of the present disclosure can be used to execute the above fused instruction and addition instruction. The fused instruction can be first provided to the pipeline so that multiple computing units start to execute the fused instruction.

[0075] In some embodiments, the control unit may be configured to, in response to determining that the current instruction begins to be executed by the N computing units, determine an initial count value for the current instruction based on the execution duration of the current instruction. For example, the execution duration of the fused instruction may be 9 execution cycles. When the fused instruction begins to be executed by the multiplication computing unit M40 in the plurality of computing units, the initial count value for the fused instruction may be determined to be 9 based on the execution duration of the fused instruction.

[0076] In some embodiments, the control unit may be further configured to provide an initial count value of the current instruction to the counting unit. For example, the initial count value 9 of the fused instruction may be provided to the counting unit so that the counting unit starts counting.

[0077] In some embodiments, the counting unit may be configured to determine a current count value of the current instruction during an execution cycle in which the current instruction is executed. For example, the current count value of the current instruction may be less than or equal to an initial count value of the current instruction.

[0078] In an embodiment of the present disclosure, the counting unit may further be configured to: when the current execution cycle is the starting execution cycle for the current instruction, receive the initial count value of the current instruction, and use the initial count value of the current instruction as the current count value of the current instruction. For example, the starting execution cycle may be the first execution cycle in which the fused instruction is executed. In the first execution cycle, the counting unit may use the initial count value of 9 of the fused instruction as the current count value for the first execution cycle.

[0079] In an embodiment of the present disclosure, the counting unit may further be configured to determine, when the current execution cycle is not the starting execution cycle, the current count value of the current instruction based on the difference between the previous count value and the preset value. The previous count value is the count value of the current instruction in the execution cycle before the current execution cycle. For example, in the second execution cycle in which the fused instruction is executed, the previous count value may be 9, the preset value may be 1, and the difference between the two is 8, which may be used as the current count value of the fused instruction in the second execution cycle.

[0080] In some embodiments, the control unit may be further configured to obtain the current count value of the current instruction from the counting unit during the execution cycle in which the current instruction is executed. For example, the control unit may obtain the current count value of the fused instruction from the counting unit during each execution cycle, and determine whether the current count value is less than or equal to the execution duration of the subsequent instruction during each execution cycle. In the second execution cycle, the control unit may obtain a current count value of 8 from the counting unit. If the current count value of 8 is greater than the execution duration of 3 of the subsequent instruction, the control unit may repeat the operation of obtaining the current count value in the next execution cycle.

[0081] In some embodiments, the control unit can also be configured to: in response to determining that a preset condition is satisfied between the current count value of the current instruction and the execution time of the subsequent instruction of the current instruction, control the subsequent instruction to be provided to at least one computing unit among the N computing units.

[0082] In an embodiment of the present disclosure, in response to determining that the current count value of the current instruction is less than or equal to the execution duration of the subsequent instruction, a control signal is generated. The control signal is provided to the firing unit. For example, in the seventh execution cycle, the current count value of the fused instruction may be 3. The current count value is equal to the execution duration of the subsequent instruction. The control unit may generate a control signal and provide the control signal to the firing unit.

[0083] In an embodiment of the present disclosure, the emission unit may be further configured to, in response to receiving a control signal, provide a subsequent instruction to at least one of the N computation units. For example, the emission unit may provide the aforementioned multiplication instruction to the addition computation unit A40. Thus, for example, in the 8th or 9th execution cycle of the fused instruction, the addition computation unit A40 may add the input data a40 and the input data b40 to obtain an execution result res42.

[0084] In addition, the control unit can also be configured to: in response to determining that the subsequent instruction begins to be executed by at least one computing unit, determine the initial count value of the subsequent instruction based on the execution time of the subsequent instruction. Provide the initial count value of the subsequent instruction to the counting unit. For example, after the addition instruction begins to be executed, the corresponding initial count value can be determined based on the execution time of the addition instruction, and the initial count value can be provided to the counting unit so that the counting unit restarts counting. It can be understood that the processing method of the counting unit and the control unit for the subsequent instruction is the same or similar to the processing method for the current instruction, and the present disclosure will not be repeated here.

[0085] Through the embodiments of the present disclosure, resource conflicts can be effectively alleviated, so that multiple instructions can be executed in sequence. Pipeline resources can also be fully utilized to improve the smoothness of the pipeline and reduce pipeline stagnation.

[0086] It can be understood that the above description uses the current count value of the current instruction as an example to illustrate the present disclosure. However, the present disclosure is not limited to this. The current count value of the current instruction can also be greater than the initial count value of the current instruction. Figure 4 Provide explanation.

[0087] In some embodiments, the control unit may be configured to: in response to determining that the current instruction begins to be executed by the N computing units, determine an initial count value for the current instruction based on the execution duration of the current instruction. For example, the execution duration of the fused instruction may be 9 execution cycles. When the fused instruction begins to be executed by the multiplication computing unit M40 in the plurality of computing units, the initial count value for the fused instruction may be determined to be 0 based on the execution duration of the fused instruction.

[0088] In some embodiments, the control unit may be further configured to provide an initial count value of the current instruction to the counting unit. For example, the initial count value 0 of the fused instruction may be provided to the counting unit so that the counting unit starts counting.

[0089] In some embodiments, the counting unit may be configured to determine a current count value of the current instruction during an execution cycle in which the current instruction is executed. For example, the current count value of the current instruction may be greater than or equal to an initial count value of the current instruction.

[0090] In an embodiment of the present disclosure, the counting unit may further be configured to: when the current execution cycle is the starting execution cycle for the current instruction, receive the initial count value of the current instruction, and use the initial count value of the current instruction as the current count value of the current instruction. For example, the starting execution cycle may be the first execution cycle in which the fused instruction is executed. In the first execution cycle, the counting unit may use the initial count value of 0 of the fused instruction as the current count value for the first execution cycle.

[0091] In an embodiment of the present disclosure, the counting unit may further be configured to determine, when the current execution cycle is not the starting execution cycle, the current count value of the current instruction based on the sum of the previous count value and the preset value. The previous count value is the count value of the current instruction in the execution cycle before the current execution cycle. For example, in the second execution cycle in which the fused instruction is executed, the previous count value may be 0, the preset value may be 1, and the sum of the two is 1, which may be used as the current count value of the fused instruction in the second execution cycle.

[0092] In some embodiments, the control unit may also be configured to obtain the current count value of the current instruction from the counting unit in the execution cycle in which the current instruction is executed. The control unit may obtain the current count value of the fused instruction from the counting unit in each execution cycle, and determine whether the current count value is greater than or equal to the execution duration difference in each execution cycle. The execution duration difference may be the difference between the execution duration of the current instruction and the execution duration of the subsequent instruction. For example, the execution duration of the fused instruction is 9, and the execution duration of the subsequent instruction is 3. Thus, the execution duration difference is 6. In the second execution cycle, the control unit may obtain the current count value of 1 from the counting unit. The current count value 1 is less than the execution duration difference 6, and the control unit may repeat the operation of obtaining the current count value in the next execution cycle.

[0093] In some embodiments, the control unit may be further configured to, in response to determining that a preset condition is satisfied between a current count value of the current instruction and an execution duration of a subsequent instruction of the current instruction, control the subsequent instruction to be provided to at least one of the N computing units. The preset condition may be that the current count value of the current instruction is greater than or equal to the execution duration difference.

[0094] In an embodiment of the present disclosure, in response to determining that the current count value of the current instruction is greater than or equal to the execution duration difference, a control signal is generated. The control signal is provided to the emission unit. For example, in the seventh execution cycle, the current count value of the fused instruction may be 6. The current count value is equal to the execution duration difference. The control unit may generate a control signal and provide the control signal to the emission unit to provide the subsequent instruction to at least one computing unit.

[0095] It can be understood that the above describes the device of the present disclosure, and the following will describe an electronic device including the device.

[0096] Figure 5 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

[0097] like Figure 5 As shown, the device 5000 may include a data processing apparatus 500. The data processing apparatus 500 may be the apparatus 200 described above.

[0098] It can be understood that the above describes the device of the present disclosure, and the following will describe the method of the present disclosure.

[0099] Figure 6 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure.

[0100] like Figure 6 As shown, method M600 may include operations S610 to S640.

[0101] In operation S610 , in response to determining that the current instruction begins to be executed by N computing units, an initial count value of the current instruction is determined according to the execution time of the current instruction.

[0102] For example, the execution duration includes the durations of multiple execution cycles. N is an integer greater than or equal to 1.

[0103] In operation S620 , an initial count value of the current instruction is provided to a counting unit.

[0104] For example, a counting unit corresponds to N computing units.

[0105] In operation S630 , a current count value of the current instruction is obtained from a counting unit in an execution cycle in which the current instruction is executed.

[0106] In operation S640 , in response to determining that a preset condition is satisfied between the current count value of the current instruction and the execution duration of the subsequent instruction of the current instruction, the subsequent instruction is controlled to be provided to at least one computing unit among the N computing units.

[0107] It can be understood that method M600 can be executed by the control unit 230 of the device 200.

[0108] In some embodiments, the method M600 may further include: determining a current count value of the current instruction during an execution cycle in which the current instruction is executed. For example, this operation may be performed by the counting unit 220 of the apparatus 200 .

[0109] In some embodiments, the current count value of the current instruction is less than or equal to the initial count value of the current instruction. In an execution cycle in which the current instruction is executed, determining the current count value of the current instruction includes: receiving the initial count value of the current instruction when the current execution cycle is a starting execution cycle in which the current instruction is executed, and using the initial count value of the current instruction as the current count value of the current instruction.

[0110] In some embodiments, determining the current count value of the current instruction in an execution cycle in which the current instruction is executed includes: determining the current count value of the current instruction based on a difference between a previous count value and a preset value when the current execution cycle is not a starting execution cycle. The previous count value is the count value of the current instruction in an execution cycle previous to the current execution cycle.

[0111] In some embodiments, the execution time of the subsequent instruction is less than or equal to the execution time of the current instruction.

[0112] In some embodiments, the N computing units executing the current instruction include a first computing unit and a second computing unit. In multiple execution cycles of the current instruction, the first computing unit corresponds to a first execution cycle, the second computing unit corresponds to a second execution cycle, and the first execution cycle precedes the second execution cycle. The at least one computing unit executing a subsequent instruction includes the first computing unit.

[0113] In some embodiments, the N computing units executing the current instruction include a first computing unit and a second computing unit. In multiple execution cycles of the current instruction, the first computing unit corresponds to a first execution cycle, the second computing unit corresponds to a second execution cycle, and the first execution cycle precedes the second execution cycle. The at least one computing unit executing a subsequent instruction includes the second computing unit.

[0114] In some embodiments, the method further includes: in response to determining that the subsequent instruction begins to be executed by at least one computing unit, determining an initial count value of the subsequent instruction according to the execution time of the subsequent instruction, and providing the initial count value of the subsequent instruction to a counting unit.

[0115] In some embodiments, the preset condition includes at least one of the following: when the current count value of the current instruction is less than or equal to the initial count value of the current instruction, the current count value of the current instruction is less than or equal to the execution duration of the subsequent instruction. When the current count value of the current instruction is greater than or equal to the initial count value of the current instruction, the current count value of the current instruction is greater than or equal to the execution duration difference. The execution duration difference is the difference between the execution duration of the current instruction and the execution duration of the subsequent instruction.

[0116] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0117] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0118] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0119] like Figure 7 As shown, the device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 into a random access memory (RAM) 703. Various programs and data required for the operation of the device 700 can also be stored in the RAM 703. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0120] Various components in device 700 are connected to I / O interface 705, including an input unit 706, such as a keyboard, mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, optical disk, etc.; and a communication unit 709, such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0121] The computing unit 701 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the data processing method described above can be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to execute the data processing method in any other appropriate manner (for example, by means of firmware).

[0122] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0123] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0124] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0125] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0126] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0127] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A data processing device, comprising: N computing units, where N is an integer greater than or equal to 1; a counting unit corresponding to the N computing units; A control unit configured as follows: In response to determining that a current instruction begins to be executed by the N computing units, determining an initial count value of the current instruction according to an execution duration of the current instruction, wherein the execution duration includes durations of multiple execution cycles; providing an initial count value of the current instruction to the counting unit; In the execution cycle in which the current instruction is executed, obtaining a current count value of the current instruction from the counting unit; and In response to determining that a preset condition is satisfied between the current count value of the current instruction and the execution time of a subsequent instruction of the current instruction, the subsequent instruction is controlled to be provided to at least one of the N computing units.

2. The device according to claim 1, wherein The counting unit is configured to determine a current counting value of the current instruction in the execution cycle in which the current instruction is executed.

3. The device according to claim 2, wherein The current count value of the current instruction is less than or equal to the initial count value of the current instruction, The counting unit is further configured to perform the following operations to determine a current counting value of the current instruction in the execution cycle in which the current instruction is executed: In a case where the current execution cycle is a starting execution cycle for executing the current instruction, receiving an initial count value of the current instruction; and The initial count value of the current instruction is used as the current count value of the current instruction.

4. The device according to claim 3, wherein The counting unit is further configured to perform the following operations to determine a current counting value of the current instruction in the execution cycle in which the current instruction is executed: In a case where the current execution cycle is not the starting execution cycle, the current count value of the current instruction is determined based on the difference between the previous count value and a preset value, wherein the previous count value is the count value of the current instruction in the previous execution cycle of the current execution cycle.

5. The device according to claim 1, further comprising a transmitting unit, in, The control unit is further configured to perform the following operations to control the subsequent instruction to be provided to at least one of the N computing units: generating a control signal in response to determining that the current count value of the current instruction is less than or equal to the execution duration of a subsequent instruction; as well as providing the control signal to the transmitting unit; The transmitting unit is configured to provide the subsequent instruction to at least one of the N computing units in response to receiving the control signal.

6. The device according to claim 1, wherein The execution time of the subsequent instruction is less than or equal to the execution time of the current instruction.

7. The device according to claim 6, wherein The N computing units executing the current instruction include a first computing unit and a second computing unit, In the plurality of execution cycles of the current instruction, the first calculation unit corresponds to a first execution cycle, the second calculation unit corresponds to a second execution cycle, and the first execution cycle is before the second execution cycle. The at least one computing unit that executes the subsequent instruction includes the first computing unit.

8. The device according to claim 6, wherein The N computing units executing the current instruction include a first computing unit and a second computing unit, In the plurality of execution cycles of the current instruction, the first calculation unit corresponds to a first execution cycle, the second calculation unit corresponds to a second execution cycle, and the first execution cycle is before the second execution cycle. The at least one computing unit that executes the subsequent instruction includes the second computing unit.

9. The device according to claim 1, wherein The control unit is further configured to: In response to determining that the subsequent instruction starts to be executed by at least one of the computing units, determining an initial count value of the subsequent instruction according to an execution time of the subsequent instruction; and An initial count value of the subsequent instruction is provided to the counting unit.

10. The device according to claim 1, wherein The preset conditions include at least one of the following: In a case where the current count value of the current instruction is less than or equal to the initial count value of the current instruction, the current count value of the current instruction is less than or equal to the execution duration of the subsequent instruction; When the current count value of the current instruction is greater than or equal to the initial count value of the current instruction, the current count value of the current instruction is greater than or equal to the execution time difference, wherein the execution time difference is the difference between the execution time of the current instruction and the execution time of the subsequent instruction.

11. An electronic device comprising the data processing device according to any one of claims 1 to 10.

12. A data processing method, comprising: In response to determining that the current instruction begins to be executed by N computing units, determining an initial count value of the current instruction according to an execution duration of the current instruction, wherein the execution duration includes durations of multiple execution cycles, and N is an integer greater than or equal to 1; providing an initial count value of the current instruction to the counting unit, wherein the counting unit corresponds to N of the computing units; In the execution cycle in which the current instruction is executed, obtaining a current count value of the current instruction from the counting unit; and In response to determining that a preset condition is satisfied between the current count value of the current instruction and the execution time of a subsequent instruction of the current instruction, the subsequent instruction is controlled to be provided to at least one of the N computing units.

13. The method according to claim 12, further comprising: In the execution cycle in which the current instruction is executed, a current count value of the current instruction is determined.

14. The method according to claim 13, wherein The current count value of the current instruction is less than or equal to the initial count value of the current instruction, In the execution cycle in which the current instruction is executed, determining the current count value of the current instruction includes: In a case where the current execution cycle is a starting execution cycle for executing the current instruction, receiving an initial count value of the current instruction; and The initial count value of the current instruction is used as the current count value of the current instruction.

15. The method according to claim 14, wherein In the execution cycle in which the current instruction is executed, determining the current count value of the current instruction includes: In a case where the current execution cycle is not the starting execution cycle, the current count value of the current instruction is determined based on the difference between the previous count value and a preset value, wherein the previous count value is the count value of the current instruction in the previous execution cycle of the current execution cycle.

16. The method according to claim 12, wherein: The execution time of the subsequent instruction is less than or equal to the execution time of the current instruction.

17. The method according to claim 16, wherein The N computing units executing the current instruction include a first computing unit and a second computing unit, In the plurality of execution cycles of the current instruction, the first calculation unit corresponds to a first execution cycle, the second calculation unit corresponds to a second execution cycle, and the first execution cycle is before the second execution cycle. The at least one computing unit that executes the subsequent instruction includes the first computing unit.

18. The method according to claim 16, wherein The N computing units executing the current instruction include a first computing unit and a second computing unit, In the plurality of execution cycles of the current instruction, the first calculation unit corresponds to a first execution cycle, the second calculation unit corresponds to a second execution cycle, and the first execution cycle is before the second execution cycle. The at least one computing unit that executes the subsequent instruction includes the second computing unit.

19. The method according to claim 12, further comprising: In response to determining that the subsequent instruction starts to be executed by at least one of the computing units, determining an initial count value of the subsequent instruction according to an execution time of the subsequent instruction; as well as An initial count value of the subsequent instruction is provided to the counting unit.

20. The method according to claim 12, wherein The preset conditions include at least one of the following: In a case where the current count value of the current instruction is less than or equal to the initial count value of the current instruction, the current count value of the current instruction is less than or equal to the execution duration of the subsequent instruction; When the current count value of the current instruction is greater than or equal to the initial count value of the current instruction, the current count value of the current instruction is greater than or equal to the execution time difference, wherein the execution time difference is the difference between the execution time of the current instruction and the execution time of the subsequent instruction.

21. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 12 to 20.

22. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 12 to 20.

23. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 12 to 20.

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