Data processing methods, apparatuses, system-on-a-chip, readable storage media, and program products for non-volatile memory.

Abstract

This application relates to the field of data processing technology, specifically a data processing method, apparatus, system-on-a-chip (SoC), readable storage medium, and program product for non-volatile memory. The method is applied to a coprocessor of a SoC and includes: receiving a first coprocessor program sent by a main processor, the first coprocessor program containing programming commands matching the non-volatile memory, the programming commands containing a target address; retrieving target plaintext data from the memory based on the target address; sending the target plaintext data to an encryption component to obtain ciphertext data corresponding to the target plaintext data; and sending the ciphertext data and programming commands to a data transmission interface, so that the data transmission interface forwards the ciphertext data and programming commands to the non-volatile memory, and the non-volatile memory writes the ciphertext data based on the programming commands. This method allows the SoC chip to flexibly connect to different types of external FLASH memory during subsequent practical use.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing method, apparatus, system-on-a-chip, computer-readable storage medium, and computer program product using a non-volatile memory. Background Technology

[0002] Currently, System-on-Chips (SoCs) typically connect to external FLASH memory via an SSI (Synchronous Serial Interface) to expand storage capacity. In certain security-sensitive applications, to protect the data stored in FLASH from unauthorized access, it is necessary to store the data in encrypted form to ensure that no plaintext information appears in the FLASH. Therefore, the SoC chip must be able to encrypt and decrypt data in the external FLASH in real time.

[0003] To achieve this functionality, an SOC chip typically requires a dedicated hardware state machine to control the encryption and decryption logic. However, different FLASH models may use different command sets, necessitating the design of the hardware state machine to be adapted for specific FLASH models.

[0004] If the command set for a particular FLASH model is not considered during the design phase, the SOC chip will be unable to support that model of FLASH memory in practical applications. Furthermore, attempting to be compatible with multiple FLASH models during chip design becomes exceptionally complex, increasing chip area and power consumption, and often still failing to cover all possible FLASH models in practical applications. This limitation forces the SOC chip to specify the exact model of the external FLASH memory during the design phase, reducing the SOC chip's flexibility and scalability. Summary of the Invention

[0005] Therefore, it is necessary to provide a data processing method, apparatus, system-on-a-chip, computer-readable storage medium, and computer program product that allows SOC chips to flexibly connect to different types of FLASH memory in subsequent practical use, addressing the aforementioned technical problems.

[0006] In a first aspect, this application provides a data processing method for non-volatile memory, applied to a coprocessor of a system-on-a-chip (SoC), wherein the SoC further includes a main processor, memory, encryption components, and a data transmission interface, and the SoC is electrically connected to the non-volatile memory; the method includes:

[0007] The system receives a first coprocessor program sent by the main processor. The first coprocessor program contains programming commands that match the non-volatile memory, and the programming commands contain a target address.

[0008] Based on the target address, retrieve the target plaintext data from the memory;

[0009] The target plaintext data is sent to the encryption component to obtain the ciphertext data corresponding to the target plaintext data;

[0010] The encrypted data and the programming command are sent to the data transmission interface, so that the data transmission interface forwards the encrypted data and the programming command to the non-volatile memory, and the non-volatile memory writes the encrypted data based on the programming command.

[0011] In one embodiment, the system-on-a-chip further includes a decryption component, and the method further includes:

[0012] The system-on-a-chip also includes a decryption component, and the method further includes:

[0013] Receive a second coprocessor program sent by the main processor, the second coprocessor program containing read commands that match the non-volatile memory;

[0014] The read command is sent to the data transmission interface, so that the data transmission interface forwards the read command to the non-volatile memory, and the non-volatile memory reads the first target ciphertext data based on the read command and returns the first target ciphertext data to the data transmission interface;

[0015] The first target ciphertext data is sent to the decryption component to obtain the plaintext data corresponding to the first target ciphertext data;

[0016] The plaintext data is sent to the main processor.

[0017] In one embodiment, the method further includes:

[0018] Receive a third coprocessor program sent by the main processor, the third coprocessor program containing an erase command that matches the non-volatile memory;

[0019] The erase command is sent to the data transmission interface, so that the data transmission interface forwards the erase command to the non-volatile memory, and the non-volatile memory erases the second target ciphertext data based on the erase command.

[0020] In one embodiment, retrieving target plaintext data from the memory based on the target address includes:

[0021] Based on the target address, the target plaintext data is retrieved from the memory via the bus of the system-on-a-chip.

[0022] In one embodiment, the main processor is configured to determine the type of the non-volatile memory when the system-on-a-chip is electrically connected to the non-volatile memory; the main processor is also configured to send a coprocessor matching the type to the coprocessor.

[0023] In one embodiment, the coprocessor includes a central processing unit, and the area occupied by the coprocessor in the system-on-a-chip is smaller than the area occupied by the main processor in the system-on-a-chip.

[0024] Secondly, this application also provides a data processing apparatus for non-volatile memory, comprising:

[0025] A receiving module is configured to receive a first coprocessor program sent by the main processor, the first coprocessor program containing programming commands that match the non-volatile memory, the programming commands containing a target address;

[0026] The acquisition module is used to acquire target plaintext data from the memory based on the target address;

[0027] The sending module is used to send the target plaintext data to the encryption component to obtain the ciphertext data corresponding to the target plaintext data;

[0028] The sending module is further configured to send the encrypted data and the programming command to the data transmission interface, so that the data transmission interface forwards the encrypted data and the programming command to the non-volatile memory, and the non-volatile memory writes the encrypted data based on the programming command.

[0029] Thirdly, this application also provides a system-on-a-chip, including a memory, a main processor, and a coprocessor, wherein the memory stores a computer program, and the coprocessor executes the computer program to implement the steps of the method described in any of the above-mentioned embodiments.

[0030] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0031] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the above claims.

[0032] The aforementioned data processing methods, apparatuses, system-on-a-chip (SoC), computer-readable storage media, and computer program products for non-volatile memory utilize a coprocessor to replace the hardware state machine in the data processing of external non-volatile memory. This eliminates the need to fix the control logic for specific non-volatile memory models during the SoC design phase. Later, when adapting to different non-volatile memory models, only the coprocessor program needs to be updated. When data needs to be encrypted and stored in non-volatile memory, a matching coprocessor program is dynamically injected into the coprocessor to achieve encrypted storage, thus improving the compatibility of the SoC with non-volatile memory. Furthermore, data in non-volatile memory can be decrypted using the coprocessor. Furthermore, data in non-volatile memory can be erased using the coprocessor. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a data flow diagram for protecting non-volatile memory using a hardware state machine in related technologies.

[0035] Figure 2 This is a flowchart illustrating a data processing method for non-volatile memory in one embodiment;

[0036] Figure 3 This is a data flow diagram illustrating data protection of non-volatile memory via a coprocessor in one embodiment.

[0037] Figure 4 This is a flowchart illustrating a data processing method for non-volatile memory in another embodiment;

[0038] Figure 5 This is a flowchart illustrating a data processing method for non-volatile memory in yet another embodiment;

[0039] Figure 6 This is a flowchart illustrating a data processing method for non-volatile memory in another embodiment;

[0040] Figure 7This is a structural block diagram of a data processing device with non-volatile memory in one embodiment;

[0041] Figure 8 This is an internal structure diagram of a system-on-a-chip in one embodiment. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0044] Please refer to Figure 1 , Figure 1 This is a data flow diagram illustrating how a hardware state machine protects data from non-volatile memory in related technologies. The hardware state machine has a fixed design and can only handle commands for specific types of non-volatile memory. Specifically, the hardware state machine consists of a state register and combinational logic circuits. It can transition between pre-defined states based on control signals and acts as the control center, coordinating related signal actions and completing specific operations. When the hardware state machine detects a command for an external non-volatile memory (e.g., FLASH memory), it triggers the corresponding state transition, working in conjunction with encryption / decryption components to protect the data from the non-volatile memory. If the hardware state machine design does not consider the type of external non-volatile memory, the state machine cannot trigger the corresponding state transition, leading to commands being ignored, misinterpreted, or failing to meet the timing requirements of the external non-volatile memory.

[0045] Based on this, this application provides a data processing method for non-volatile memory. This embodiment illustrates this method by applying it to a coprocessor in a system-on-a-chip (SoC). The SoC further includes a main processor, memory, encryption components, and a data transmission interface, and is electrically connected to the non-volatile memory. In this embodiment, as... Figure 2 As shown, the method includes the following steps:

[0046] Step S101: Receive a first coprocessor program sent by the main processor. The first coprocessor program contains programming commands that match the non-volatile memory. The programming commands contain a target address.

[0047] The main processor can be a Central Processing Unit (CPU). Non-volatile memory can be used as external memory for the system-on-a-chip (SoC). The non-volatile memory can be FLASH memory. The first coprocessor program can be matched to the model of the non-volatile memory currently electrically connected to the SoC, containing programming commands that the non-volatile memory model can recognize. For example, for each model of external FLASH memory, a matching coprocessor program can be pre-coded and stored. Specifically, the coprocessor program can be a set of operation instructions for a specific model of non-volatile memory, used to store commands matching the non-volatile memory model, define operation timing, and specify data formats, etc.

[0048] For example, the coprocessor can listen to the instruction transfer channel of the main processor via the internal bus. When the main processor needs to operate on non-volatile memory, it can construct a coprocessor package containing specific commands. This package can be passed to the coprocessor via shared memory regions or direct register writes.

[0049] Step S102: Based on the target address, retrieve the target plaintext data from the memory.

[0050] Step S103: Send the target plaintext data to the encryption component to obtain the ciphertext data corresponding to the target plaintext data.

[0051] The encryption component can be hardware-based and is used to execute encryption logic. Specifically, the coprocessor can parse the first coprocessor program, extract encryption parameters, and configure the encryption component accordingly for encryption.

[0052] In step S104, the encrypted data and programming commands are sent to the data transmission interface, so that the data transmission interface forwards the encrypted data and programming commands to the non-volatile memory, and the non-volatile memory writes the encrypted data based on the programming commands.

[0053] The data transmission interface can be an SSI (Synchronous Serial Interface) interface or an SPI (Serial Peripheral Interface) interface.

[0054] Please refer to Figure 3 , Figure 3 This is a data flow diagram for data protection of non-volatile memory via a coprocessor in one embodiment.

[0055] In the aforementioned data processing method for non-volatile memory, a coprocessor replaces the hardware state machine in the data processing of the external non-volatile memory. This eliminates the need to solidify the control logic for a specific non-volatile memory model during the system-on-a-chip (SoC) design phase. When adapting to different non-volatile memory models later, only the coprocessor program needs to be updated. When data needs to be encrypted and stored in the non-volatile memory, a matching coprocessor program is dynamically injected into the coprocessor to achieve encrypted storage, thus improving the compatibility of the SoC with non-volatile memory.

[0056] In one exemplary embodiment, data in non-volatile memory can also be decrypted based on a coprocessor, such as... Figure 4 As shown, the aforementioned system-on-a-chip also includes a decryption component, and the data processing method for the aforementioned non-volatile memory further includes:

[0057] Step S105: Receive a second coprocessor program sent by the main processor. The second coprocessor program contains read commands that match the non-volatile memory.

[0058] The second coprocessor program can be matched to the model of the non-volatile memory currently electrically connected to the system-on-a-chip, and contains read commands that this type of non-volatile memory can recognize. The read commands contain the address of the first target encrypted data.

[0059] For example, the coprocessor can receive a second coprocessor program from the main processor via an internal bus. The second coprocessor program may include the access address of non-volatile memory, the data length, and the operation type identifier.

[0060] Step S106: A read command is sent to the data transmission interface, so that the data transmission interface forwards the read command to the non-volatile memory, and the non-volatile memory reads the first target ciphertext data based on the read command and returns the first target ciphertext data to the data transmission interface.

[0061] For example, the coprocessor can construct a read command frame conforming to the data transmission interface protocol according to the second coprocessor program, and send the command frame to the data transmission interface through a dedicated interface channel; the data transmission interface can forward the command frame to non-volatile memory to initiate a read operation, and receive the returned serial data stream, reassemble it into parallel data blocks and store it in the interface buffer.

[0062] Step S107: Send the first target ciphertext data to the decryption component to obtain the plaintext data corresponding to the first target ciphertext data.

[0063] The decryption component can be hardware-based and is used to execute the decryption logic. Specifically, the coprocessor can parse the second coprocessor program, extract the decryption parameters, and configure the corresponding decryption component to perform decryption.

[0064] For example, the coprocessor moves ciphertext data from the interface buffer to the input FIFO (First Input First Output) of the decryption component via direct memory access; after the coprocessor detects a decryption completion interruption, it can read plaintext data from the output buffer of the decryption component.

[0065] Step S108: Send plaintext data to the main processor.

[0066] Furthermore, the coprocessor can automatically clear the intermediate data in the decryption component and buffer after the transmission is completed.

[0067] In one exemplary embodiment, data in non-volatile memory can also be erased based on the coprocessor, such as... Figure 5 As shown, the data processing method for the above-mentioned non-volatile memory further includes:

[0068] Step S109: Receive a third coprocessor program sent by the main processor. The third coprocessor program contains an erase command that matches the non-volatile memory.

[0069] The third coprocessor program can be matched to the model of the non-volatile memory currently electrically connected to the system-on-a-chip, and contains erase commands that can be recognized by that model of non-volatile memory. The erase command contains the address of the second target encrypted data.

[0070] In step S110, an erase command is sent to the data transmission interface, so that the data transmission interface forwards the erase command to the non-volatile memory, and the non-volatile memory erases the second target ciphertext data based on the erase command.

[0071] For example, the main processor can read an erase command from memory, which may include the starting address of the target erase block, the erase range, and the erase mode; the coprocessor can receive a third coprocessor program containing the erase command through the internal bus and send the erase command to the data transmission interface.

[0072] In one exemplary embodiment, such as Figure 6 As shown, step S102 above may include:

[0073] Step S1021: Based on the target address, retrieve the target plaintext data from the memory via the system-on-a-chip bus.

[0074] For example, the coprocessor can parse the first coprocessor program and extract data access parameters, which may include the target data address, data length, and access mode, etc. The coprocessor can then initiate a bus read request based on these data access parameters to read the target plaintext data from the internal memory.

[0075] In an exemplary embodiment, the main processor is configured to determine the type of non-volatile memory when the system-on-a-chip is electrically connected to the non-volatile memory; the main processor is also configured to send a coprocessor matching the type to the coprocessor.

[0076] For example, the main processor can determine the type of non-volatile memory by reading its ID. The memory can store programs that match the type of each non-volatile memory. Non-volatile memories of the same type can be matched with the same set of commands. Each type of non-volatile memory can include multiple models of non-volatile memory.

[0077] In one exemplary embodiment, the coprocessor includes a central processing unit, and the area occupied by the coprocessor in the system-on-a-chip is smaller than the area occupied by the main processor in the system-on-a-chip.

[0078] The coprocessor can retain only essential functions, supporting basic CPU instructions. It can be a small CPU. For example, the area occupied by the coprocessor in the system-on-a-chip (SoC) can be as small as that of the main processor. .

[0079] In summary, the above-described data processing method for non-volatile memory, by using a coprocessor to replace the hardware state machine in the data processing of the external non-volatile memory, eliminates the need to fix the control logic for specific non-volatile memory models during the system-on-a-chip (SoC) design phase. Later, when adapting to different non-volatile memory models, only the coprocessor program needs to be updated. When data needs to be encrypted and stored in non-volatile memory, a matching coprocessor program is dynamically injected into the coprocessor to achieve encrypted storage, thus improving the compatibility of the SoC with non-volatile memory. Furthermore, data in non-volatile memory can be decrypted using the coprocessor. Furthermore, data in non-volatile memory can also be erased using the coprocessor.

[0080] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0081] Based on the same inventive concept, this application also provides a data processing apparatus for non-volatile memory for implementing the data processing method for non-volatile memory described above. The solution provided by this apparatus is similar to the implementation described in the above method. Therefore, the specific limitations in one or more embodiments of the data processing apparatus for non-volatile memory provided below can be found in the limitations of the data processing method for non-volatile memory described above, and will not be repeated here.

[0082] In one exemplary embodiment, such as Figure 7 As shown, a data processing device 300 for non-volatile memory is provided, including: a receiving module 301, an acquisition module 302, and a transmitting module 303, wherein:

[0083] The receiving module 301 is used to receive a first coprocessor program sent by the main processor. The first coprocessor program contains programming commands that match the non-volatile memory, and the programming commands contain a target address.

[0084] The acquisition module 302 acquires the target plaintext data from the memory based on the target address.

[0085] The sending module 303 sends the target plaintext data to the encryption component and obtains the ciphertext data corresponding to the target plaintext data.

[0086] The aforementioned sending module 303 is also used to send the encrypted data and programming commands to the data transmission interface, so that the data transmission interface forwards the encrypted data and programming commands to the non-volatile memory, and the non-volatile memory writes the encrypted data based on the programming commands.

[0087] In one embodiment, the system-on-a-chip further includes a decryption component, and the receiving module 301 is further configured to:

[0088] Receives a second coprocessor program sent by the main processor, the second coprocessor program containing read commands that match the non-volatile memory.

[0089] The aforementioned sending module 303 is further configured to send a read command to the data transmission interface, so that the data transmission interface forwards the read command to the non-volatile memory, and the non-volatile memory reads the first target ciphertext data based on the read command and returns the first target ciphertext data to the data transmission interface.

[0090] The aforementioned sending module 303 is also used to send the first target ciphertext data to the decryption component to obtain the plaintext data corresponding to the first target ciphertext data.

[0091] The aforementioned sending module 303 is also used to send plaintext data to the main processor.

[0092] In one embodiment, the receiving module 301 is further configured to:

[0093] Receives a third coprocessor program sent by the main processor, which contains erase commands that match the non-volatile memory.

[0094] The aforementioned sending module 303 is further configured to send an erase command to the data transmission interface, so that the data transmission interface forwards the erase command to the non-volatile memory, and the non-volatile memory erases the second target ciphertext data based on the erase command.

[0095] In one embodiment, the acquisition module 302 is further configured to:

[0096] Based on the target address, the target plaintext data is retrieved from the memory via the system-on-a-chip bus.

[0097] In one embodiment, the main processor is configured to determine the type of non-volatile memory when the system-on-a-chip is electrically connected to the non-volatile memory; the main processor is also configured to send a coprocessor matching the type to the coprocessor.

[0098] In one embodiment, the coprocessor includes a central processing unit, and the area occupied by the coprocessor in the system-on-a-chip is smaller than the area occupied by the main processor in the system-on-a-chip.

[0099] All modules in the aforementioned non-volatile memory data processing device can be implemented entirely in software. These modules can be stored in software form in the system-on-a-chip memory, allowing the coprocessor to call and execute the corresponding operations.

[0100] In one exemplary embodiment, a system-on-a-chip (SoC) is provided, the internal structure of which can be as follows: Figure 8 As shown, this system-on-a-chip (SoC) includes a main processor, coprocessor, memory, input / output (I / O) interfaces, and a communication interface. The main processor, coprocessor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The main processor provides computational and control capabilities. The coprocessor interprets input coprocessor programs, translating them into various read / write operations. The memory includes non-volatile storage media and internal memory. The I / O interfaces facilitate information exchange between the processor and external devices. The communication interface enables communication with external terminals via a network connection. When the computer program is executed by the coprocessor, it implements a data processing method using non-volatile memory.

[0101] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the solution of this application and does not constitute a limitation on the system-on-a-chip to which the solution of this application is applied. The specific system-on-a-chip may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0102] In one exemplary embodiment, a system-on-a-chip is provided, including a memory, a main processor, and a coprocessor. The memory stores a computer program, and the coprocessor executes the computer program to implement the steps in the above-described method embodiments.

[0103] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0104] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0105] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0107] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data processing method using a non-volatile memory, characterized in that, A coprocessor applied to a system-on-a-chip (SoC), the SoC further comprising a main processor, memory, encryption components, and a data transmission interface, the SoC being electrically connected to non-volatile memory, the main processor determining the type of the non-volatile memory and sending a coprocessor program matching the type to the coprocessor, the method comprising: The system receives a first coprocessor program sent by the main processor. The first coprocessor program contains programming commands and encryption parameters that match the non-volatile memory. The programming commands contain a target address. Based on the target address, retrieve the target plaintext data from the memory; The encryption component is configured based on the encryption parameters, and the target plaintext data is sent to the encryption component so that the encryption component processes the target plaintext data according to the encryption logic corresponding to the encryption parameters to obtain the ciphertext data corresponding to the target plaintext data. The encrypted data and the programming command are sent to the data transmission interface, so that the data transmission interface forwards the encrypted data and the programming command to the non-volatile memory, and the non-volatile memory writes the encrypted data based on the programming command.

2. The method according to claim 1, characterized in that, The system-on-a-chip also includes a decryption component, and the method further includes: Receive a second coprocessor program sent by the main processor, the second coprocessor program containing read commands that match the non-volatile memory; The read command is sent to the data transmission interface, so that the data transmission interface forwards the read command to the non-volatile memory, and the non-volatile memory reads the first target ciphertext data based on the read command and returns the first target ciphertext data to the data transmission interface; The first target ciphertext data is sent to the decryption component to obtain the plaintext data corresponding to the first target ciphertext data; The plaintext data is sent to the main processor.

3. The method according to claim 1, characterized in that, The method further includes: Receive a third coprocessor program sent by the main processor, the third coprocessor program containing an erase command that matches the non-volatile memory; The erase command is sent to the data transmission interface, so that the data transmission interface forwards the erase command to the non-volatile memory, and the non-volatile memory erases the second target ciphertext data based on the erase command.

4. The method according to claim 1, characterized in that, The step of retrieving target plaintext data from the memory based on the target address includes: Based on the target address, the target plaintext data is retrieved from the memory via the bus of the system-on-a-chip.

5. The method according to claim 1, characterized in that, The coprocessor includes a central processing unit, and the area occupied by the coprocessor in the system-on-a-chip is smaller than the area occupied by the main processor in the system-on-a-chip.

6. A data processing apparatus for a non-volatile memory, characterized in that, A coprocessor for a system-on-a-chip (SoC), the SoC further comprising a main processor, memory, encryption components, and a data transmission interface, the SoC being electrically connected to non-volatile memory, the main processor determining the type of the non-volatile memory and sending a coprocessor program matching the type to the coprocessor, the apparatus comprising: A receiving module is configured to receive a first coprocessor program sent by the main processor. The first coprocessor program contains programming commands and encryption parameters that match the non-volatile memory. The programming commands contain a target address. The acquisition module is used to acquire target plaintext data from the memory based on the target address; The sending module is configured to configure the encryption component based on the encryption parameters and send the target plaintext data to the encryption component, so that the encryption component processes the target plaintext data according to the encryption logic corresponding to the encryption parameters to obtain ciphertext data corresponding to the target plaintext data. The sending module is further configured to send the encrypted data and the programming command to the data transmission interface, so that the data transmission interface forwards the encrypted data and the programming command to the non-volatile memory, and the non-volatile memory writes the encrypted data based on the programming command.

7. A system-on-a-chip (SoC) comprising a memory, a main processor, and a coprocessor, wherein the memory stores a computer program, characterized in that, When the coprocessor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the coprocessor, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the coprocessor, it implements the steps of the method according to any one of claims 1 to 5.

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