Configuration method of stacked chips

Abstract

The invention provides a configuration method of stacked chips, which comprises the following steps of: defining any bare chip as a master chip and other chips as slave chips; linked list circuits used for chip configuration are arranged on the master chip and the slave chip and comprise a freezing and unfreezing chain used for freezing and unfreezing all IO interfaces of the chips, a zero clearing chain used for clearing all data in the chips; selecting a chip address to write an address chain and a data chain of configuration data; a clock signal interface and a data signal interface of the slave chip linked list circuit are connected with a clock signal interface and a data signal interface of the master chip linked list circuit; the master chip receives configuration data, controls the linked list circuit of the master chip based on the received configuration data to realize configuration of the master chip, or sends the received configuration data to the slave chip through the clock signal interface and the data signal interface of the master chip, and controls the linked list circuit of the slave chip to realize configuration of the slave chip. The scheme of the invention has the advantages of simple structure and efficient configuration.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and in particular relates to a configuration method for stacked chips. Background Art

[0002] SSI (Stacked Silicon Interconnect) is a 2.5D integrated circuit packaging technology that aims to break through the size limitations of traditional single chips and achieve the design of FPGA chips with higher integration and performance.

[0003] As a large-scale programmable device, FPGA chips solve the problem of insufficient customized circuits. Users can describe the required functions through hardware language, then compile the description language into a bit stream file (also known as a configuration file) through software, and finally configure the FPGA software. The programmable and configurable features of FPGA chips make them widely used in various fields.

[0004] In the existing technology, after using SSI packaging for FPGA chips, multiple FPGA dies can be packaged together, thereby further expanding the capacity of the FPGA.

[0005] The stacking process of not only FPGA chips but other chips can greatly improve the performance of a single chip. However, configuring a single chip in a stacked chip becomes a major challenge. After packaging, the stacked chip ultimately appears to the user as a single chip, but it is actually a combination of multiple chips. Each chip must be independently powered on and started up. In active mode, it must actively send a clock to read the code stream file from an external storage device, while in passive mode, it passively receives the external configuration code stream file. If the configuration pins of multiple chips are connected to an external device together, the number of configuration pins will be relatively large, and the configuration method will be relatively complex, which is not conducive to users' rapid configuration of the stacked chips.

[0006] Therefore, it is necessary to design a stacked chip configuration method that can reduce the number of configuration pins in the stacked chip and reduce the complexity of the configuration. Summary of the Invention

[0007] The present invention provides a configuration method for stacked chips, which configures each chip through a matching table circuit connected between a master chip and slave chips, and has the advantages of simple structure and efficient configuration.

[0008] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] In order to achieve one or part or all of the above-mentioned purposes or other purposes, a technical solution of the present invention provides a configuration method for stacked chips, wherein the stacked chip includes multiple bare chips, any bare chip is defined as the master chip, and the remaining chips are slave chips; the master chip and the slave chip are provided with a linked list circuit for chip configuration, including a freeze-thaw chain for freezing and thawing all IO interfaces of the chip: a clear chain for clearing all data in the chip; an address chain and a data chain for selecting a chip address to write configuration data; the clock signal interface and data signal interface of the slave chip linked list circuit are connected to the clock signal interface and data signal interface of the master chip linked list circuit; the master chip receives the configuration data, controls the linked list circuit of the master chip based on the received configuration data to realize the configuration of the master chip, or sends the received configuration data to the slave chip via the clock signal interface and data signal interface of the master chip, and controls the linked list circuit of the slave chip to realize the configuration of the slave chip.

[0010] The chip configuration implemented by the linked list circuit includes: after the chip is powered on, the freeze-thaw chain freezes all IO interfaces; after the freeze operation is completed, the clear chain clears the data configuration module of the chip; after the clear operation is completed, the address chain selects each configuration address in the chip in turn under the control of the clock signal, and for each selected chip configuration address, writes configuration data to the selected configuration address through the data chain; after all data configuration is completed, the freeze-thaw chain issues a thaw instruction to indicate that the chip configuration is complete.

[0011] The freeze-thaw chain circuit, the reset chain circuit, the address chain circuit and the data chain circuit are all provided with a clock signal input terminal and a data signal input terminal; The master chip and the slave chip are provided with clock signal interfaces and data signal interfaces of each linked list circuit; the clock signal interfaces and data signal interfaces of each linked list circuit on the slave chip are respectively connected to the clock signal interfaces and data signal interfaces of each corresponding linked list circuit on the master chip.

[0012] The freeze-thaw chain includes multiple cascaded D flip-flops, where the Q output of the previous D flip-flop in the cascade is input into the D input of the next D flip-flop; the freeze-thaw chain clock signal is input into the clock signal input of each D flip-flop, and the freeze-thaw chain data signal is input into the D input of the first D flip-flop; the output signal of the Q output of each D flip-flop is used for the freezing and thawing operations of the chip core.

[0013] The clear chain includes multiple cascaded D flip-flops, where the Q output of the previous D flip-flop in the cascaded D flip-flops is input into the D input of the next D flip-flop; the clear chain clock signal is input into the clock signal input of each D flip-flop, and the clear chain data signal is input into the D input of the first D flip-flop; the first clear control signal and the second clear control signal are respectively input into a NAND gate circuit with the output of each D flip-flop, the output of the NAND gate circuit is output into an inverter, and the inverter output signal is used to control the clearing of the core in the chip.

[0014] The clear chain data signal is set to 1 in one sampling period of the clear chain clock signal; when the clear chain data signal is set to 1, the first clear control signal and the second clear control signal are synchronously set to 1 and maintained.

[0015] The address chain includes multiple cascaded D flip-flops, where the Q output of the previous D flip-flop in the cascaded D flip-flops is input into the D input of the next D flip-flop; the address chain clock signal is input into the clock signal input of each D flip-flop, and the address chain data signal is input into the D input of the first D flip-flop; the address chain data signal is set to 1 in one sampling cycle of the address chain clock signal; and also includes an address control signal, which is set to 1 after the D flip-flop is reset; the address control signal and the output of each D flip-flop are input into a NAND gate circuit, the output of the NAND gate circuit is output into an inverter, and the inverter output signal is used to select the target address.

[0016] The data chain includes: two cascaded D flip-flops; a multiplexer, the output end of the data chain is input to the 0 input end of the multiplexer, and the data chain data signal is input to the 1 input end of the multiplexer; after the address chain selects the address, the selection signal of the multiplexer is set to 1; the output result of the multiplexer is input to the D input end of the first D flip-flop; the data chain clock signal is input to the clock signal input end of the first D flip-flop, and the clock signal input to the second D flip-flop is pulled high for one clock cycle after the data of the first D flip-flop is updated; the output of the Q output end of the second D flip-flop is saved in the MOSFET; a three-state gate circuit is set between the Q output end of the second D flip-flop and the MOSFET, and the excitation signal of the three-state gate circuit and the clock signal of the second D flip-flop are simultaneously pulled high for one clock cycle.

[0017] An enable signal port is set on the master chip and the slave chip, and the enable signal port on the master chip is connected to the enable signal port of the slave chip; after the master chip receives the configuration data, it sends an enable signal to the corresponding chip according to the chip pointed to by the configuration data, and controls the corresponding chip to be configured.

[0018] The master chip and the slave chip are arranged on the interconnection layer of the stacked chips; the connection between the clock signal interface and the data signal interface of each linked list circuit on the slave chip and the clock signal interface and the data signal interface of each corresponding linked list circuit on the master chip is realized through the interconnection layer.

[0019] Compared with the existing technology, the present invention has the following advantages: 1. It utilizes the configuration resources of each chip for configuration. When stacking chips for packaging, it does not require the introduction of additional components, which can reduce the use of configuration pins and improve chip area utilization. 2. It uses the linked list circuit within the chip for configuration, which can match the maximum configuration bandwidth of each chip without affecting configuration efficiency.

[0020] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 FIG. 4 is a schematic diagram showing the connection between the chips in the stacked chip of the present invention.

[0023] Figure 2 This is a circuit diagram of the freeze-thaw chain of the present invention.

[0024] Figure 3 This is a circuit diagram of the zero-clearing chain of the present invention.

[0025] Figure 4 This is the address chain circuit diagram of the present invention.

[0026] Figure 5 This is the data link circuit diagram of the present invention. DETAILED DESCRIPTION

[0027] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0028] Example 1 Embodiment 1 provides a configuration method for stacked chips, which includes multiple bare chips, and any bare chip is defined as a master chip, and the remaining chips are slave chips; a linked list circuit for chip configuration is provided on the master chip and the slave chip, including a freeze-thaw chain for freezing and thawing all IO interfaces of the chip: a clear chain for clearing all data in the chip; an address chain and a data chain for selecting a chip address to write configuration data; the clock signal interface and the data signal interface of the linked list circuit of the slave chip are connected to the clock signal interface and the data signal interface of the linked list circuit of the master chip; the master chip receives the configuration data, and controls the linked list circuit of the master chip based on the received configuration data to realize the configuration of the master chip, or sends the received configuration data to the slave chip via the clock signal interface and the data signal interface of the master chip, and controls the linked list circuit of the slave chip to realize the configuration of the slave chip.

[0029] The present invention connects the clock signal interfaces and data signal interfaces of the linked list circuits on the master and slave chips, forming a cascaded chip for packaged chip configuration. The master chip acts as the receiver of external configuration data. After receiving the configuration data, it uses the received configuration data for specific chip configuration (either master chip configuration or slave chip configuration), and then sends clock signals and data signals to the linked list circuits of the chips to be configured, controlling the configuration of the corresponding chips. Because the present invention uses pre-set linked list circuits on each chip for configuration, it does not require the introduction of additional configuration pins, significantly conserving chip configuration pin resources and reducing chip area overhead. Furthermore, the use of linked list circuits for configuration can adapt to the chip's configuration bandwidth, improving configuration efficiency.

[0030] The present invention can be used for the configuration of stacked chips formed by chips such as FPGA chips, DSP chips, and MCU chips.

[0031] See also Figure 1 The following embodiment 1 takes the sealing of three FPGA chips as an example to explain in detail the configuration of stacked chips implemented by the present invention.

[0032] One of the three FPGA chips of the present invention is a main chip ( Figure 1 FPGA Die1 in the FPGA) and two slave chips ( Figure 1 FPGA Die2 and FPGA Die3 in the chip), a linked list circuit is set on both the master chip and the slave chip. The linked list circuit includes a freeze-thaw chain for freezing and thawing all IO interfaces of the chip; a clear chain for clearing all data in the chip; an address chain for selecting the chip address to write configuration data, and a data chain.

[0033] In the above-mentioned linked list circuits, each linked list circuit needs to input a clock signal and a data signal, and each chip is provided with a clock signal interface and a data signal interface used by each linked list circuit configuration. Figure 1 The clock signal interface and data signal interface for connecting the master chip to each slave chip are: data link data signal interface ( Figure 1 Interface for signal Data_chain_dat[31:0] transmission), clock signal interface of data chain ( Figure 1 Interface for signal Data_chain_clk transmission), address chain data signal interface ( Figure 1 Interface for signal Addr_chain_dat transmission), address chain clock signal interface ( Figure 1 Interface for signal Addr_chain_clk transmission), freeze and thaw chain data signal interface ( Figure 1 Interface for signal Freeze_chain_dat transmission), freeze and thaw chain clock signal interface ( Figure 1 Interface for signal Freeze_chain_clk transmission), clear chain data signal interface ( Figure 1 Interface for signal Clr_chain_dat transmission), clear chain clock signal interface ( Figure 1 Interface for signal Clr_chain_clk transmission in ).

[0034] The master chip is also equipped with the same number of enable signal interfaces (Cfg_en0 and Cfg_en1) as the slave chips. After receiving the configuration data, the master chip uses the configuration data to configure the corresponding chip and controls the configuration of the corresponding chip. For example, when the configuration data is used to configure the master chip, the master chip inputs the received configuration data into the master chip's linked list circuit to implement the master chip configuration. When the configuration data is used to configure the slave chip, based on the specific chip being configured, the master chip sends the corresponding enable signal to the configured slave chip. The configuration data is then transmitted to the slave chip via the clock signal interface and data signal interface mentioned above, controlling the linked list circuit on the slave chip to implement the configuration of the corresponding slave chip.

[0035] For example, when the chip to be configured is the slave chip (FPGA Die2), the master chip sends an enable signal to the interface Cfg_en of the slave chip (FPGA Die2) through the enable signal interface Cfg_en0. After the slave chip (FPGA Die2) receives the enable signal, the master chip sends the configuration data to the slave chip (FPGA Die2) through the clock signal interface and the data signal interface, and controls the linked list circuit on the slave chip (FPGA Die2) to configure the chip.

[0036] The master chip and the slave chip are arranged on the interconnection layer of the stacked chips; the clock signal interface and data signal interface of each linked list circuit on the slave chip are connected with the clock signal interface and data signal interface of each corresponding linked list circuit on the master chip, and the connection between the enable signal port of the master chip and the slave chip is realized through the interconnection layer.

[0037] Using a linked list circuit to implement chip configuration includes the following steps: after the chip is powered on, the freeze-thaw chain freezes all IO interfaces; after the freeze operation is completed, the clear chain clears the data configuration module of the chip; after the clear operation is completed, the address chain selects each configuration address in the chip in turn under the control of the clock signal, and for each selected chip configuration address, writes configuration data to the selected configuration address through the data chain; after all data configuration is completed, the freeze-thaw chain issues a thaw instruction, indicating that the chip configuration is complete.

[0038] The following is combined with the attached Figure 2-5 , the working principle of each linked list circuit is explained in detail.

[0039] like Figure 2 The freeze-thaw chain shown includes multiple cascaded D flip-flops, where the Q output of the upper D flip-flop of two adjacent D flip-flops in the cascade is input to the D input of the next D flip-flop; the freeze-thaw chain clock signal Freeze_chain_clk is input to the clock signal input of each D flip-flop respectively, and the freeze-thaw chain data signal Freeze_chain_dat is input to the D input of the first D flip-flop; the Q output of each D flip-flop is inverted through an inverter and then outputs a signal Freeze_bus[x] for freezing and thawing operations of the chip core. The D flip-flop of the freeze-thaw chain of the present invention also has a reset signal aclr. After power-on, the reset signal aclr will first generate a pulse to set the Q output terminals of all D flip-flops to 0, and then the freeze-thaw chain data signal Freeze_chain_dat will be pulled high, and the freeze-thaw chain clock signal Freeze_chain_clk will be input and periodically jump, and multiple output signals Freeze_bus[0], Freeze_bus[1], Freeze_bus[2]...Freeze_bus[n] will be set to 0 in sequence, thereby realizing the freezing of the cores of all FPGA chips.

[0040] When unfreezing all cores in the FPGA chip, it is the opposite of freezing the cores. After all data configuration is completed, the freeze-unfreeze chain data signal Freeze_chain_dat is set low, the freeze-unfreeze chain clock signal Freeze_chain_clk is input and periodically jumps, and multiple output signals Freeze_bus[0], Freeze_bus[1], Freeze_bus[2]...Freeze_bus[n] are set to 1 in sequence. When all output signals Freeze_bus[x] are 0, all cores are unfrozen.

[0041] like Figure 3 The clear chain circuit shown includes multiple cascaded D flip-flops, where the Q output of the previous D flip-flop of two adjacent D flip-flops in the cascade is input to the D input of the next D flip-flop; the clear chain clock signal Clr_chain_clk is input to the clock signal input of each D flip-flop respectively, and the clear chain data signal Clr_chain_dat is input to the D input of the first D flip-flop; the first clear control signal clrsramen and the second clear control signal clrbaren are respectively input to a NAND gate circuit with the output of each D flip-flop, and the output of the NAND gate circuit is output to the inverter, which outputs two signals clrsram[x] and clrbar[x]. The two signals clrsram[0], clrbar[0]; clrsram[1], clrbar[1]; clrsram[2], clrbar[2]..., clrsram[n], clrbar[n] output by the clear chain will be set to 1 in sequence. When all the signals clrsram[x] and clrbar[x] have been 1, they will be changed to 0 to realize a clear operation of all the cores of the FPGA.

[0042] The reset input of the clear chain D flip-flop receives the reset signal creset. After power-up, a pulse of the reset signal creset appears, setting the Q outputs of all D flip-flops in the clear chain to 0. The clear chain data signal Clr_chain_dat is set to 1 during one sampling cycle of the clear chain clock signal and remains 0 the rest of the time. Therefore, within a single sampling cycle, the clear chain data signal Clr_chain_dat can be collected and output through the Q terminal (D flip-flops are triggered on rising edges to collect input data). The first clear control signal clrsramen and the second clear control signal clrbaren are set to 1 when the clear chain data signal Clr_chain_dat is set to 1 and remain 1 until the clear operation is complete.

[0043] See also Figure 4The circuit structure diagram of the address chain shows that the address chain circuit includes multiple cascaded D flip-flops. In the cascaded D flip-flops, the Q output of the previous D flip-flop of two adjacent D flip-flops is input to the D input of the next D flip-flop; the address chain clock signal Addr_chain_clk is input to the clock signal input of each D flip-flop respectively, and the address chain data signal Addr_chain_dat is input to the D input of the first D flip-flop; the address chain data signal Addr_chain_dat is set to 1 in one sampling cycle of the address chain clock signal; it also includes the address control signal aden, which is set to 1 after the D flip-flop is reset (the reset signal aclr of the address chain D flip-flop has a pulse after power-on, setting the Q output of the address chain D flip-flop to 0); the address control signal aden and the output of each D flip-flop are input into a NAND gate circuit, the output of the NAND gate circuit is output to the inverter, and the inverter output signal adrbus[x] is used to select the target address.

[0044] Specifically, after the D flip-flop is reset, all output signals adrbus[x] are 0. At this time, the address control signal aden is pulled high by 1, and the address chain data signal Addr_chain_dat is built-in to 1 in one sampling cycle of the address chain clock signal Addr_chain_clk, and is set to 0 at other times. Therefore, when the address chain clock signal Addr_chain_clk continuously jumps, the 1 of the address chain data signal Addr_chain_dat is continuously passed down. First, adrbus[0] is 1 and adrbus[1] is 0. With the arrival of the next Addr_chain_clk, adrbus[0] is 0 and adrbus[1] is 1. Therefore, the address chain of this application can select the configuration addresses in the FPGA chip one by one to write configuration data to the selected address.

[0045] like Figure 5 The data chain of the first embodiment includes: two cascaded D flip-flops, wherein the Q output terminal of the preceding D flip-flop is input to the Q input terminal of the succeeding D flip-flop; and a multiplexer having 0 / 1 input terminals, wherein the 1 input terminal receives a data chain data signal, Data_chain_dat. The output signal of the data chain is input to the 0 input terminal of the multiplexer.

[0046] After the address chain selects the address, the selection signal dcsm of the multiplexer is 1 (at this time, the signal at the 1 input terminal is output, that is, the data chain data signal Data_chain_dat is selected for output in the first embodiment); the output result of the multiplexer is input to the D input terminal of the first D flip-flop; the data chain clock signal Data_chain_clk is input to the clock signal input terminal of the first D flip-flop, and within the sampling period, the data chain data signal Data_chain_dat is input into the first D flip-flop. The clock signal dcbc input of the second D flip-flop is pulled high for one clock cycle after the data of the first D flip-flop is updated (the D flip-flop is sampled on the rising edge, and the data signal Data_chain_dat can be input into the second D flip-flop at this time); the data output by the Q output of the second D flip-flop is saved in the MOS tube; a three-state gate circuit is set between the Q output of the second D flip-flop and the MOS tube, and the excitation signal dcwr of the three-state gate circuit and the clock signal dcbc of the second D flip-flop are pulled high for one clock cycle at the same time. At this time, the second three-state gate circuit is turned on (the excitation signal of the three-state gate circuit is pulled high to the on state and data can be transmitted. The excitation signal of the three-state gate circuit is low, which is a high-impedance state and data cannot pass through). The data can enter the MOS tube through the three-state gate circuit for storage.

[0047] Among them, when the address chain selects the address, the MOS tube acts as a storage unit, its gate control signal hdbus is pulled low, and enters the data saving state. At this time, the data output by the data chain can be written into the storage unit.

[0048] The above describes in detail the stacked chip configuration method provided by the present invention. This article uses specific examples to illustrate the structure and operating principles of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for configuring stacked chips, characterized in that: The stacked chip includes multiple bare chips, and any bare chip is defined as a master chip, and the remaining chips are defined as slave chips; The master chip and the slave chip are provided with a linked list circuit for chip configuration, including a freeze-thaw chain for freezing and thawing all IO interfaces of the chip: A clear chain that clears all data in the chip; Select the chip address to write the address chain and data chain of the configuration data; The clock signal interface and the data signal interface of the slave chip link list circuit are connected to the clock signal interface and the data signal interface of the master chip link list circuit; The master chip receives configuration data, and based on the received configuration data, controls the linked list circuit of the master chip to implement the configuration of the master chip, or sends the received configuration data to the slave chip via the clock signal interface and data signal interface of the master chip, and controls the linked list circuit of the slave chip to implement the configuration of the slave chip.

2. The method for configuring stacked chips according to claim 1, wherein: The configuration of the chip implemented by the linked list circuit includes freezing all IO interfaces of the freeze-thaw chain after the chip is powered on; After completing the freeze operation, the clear chain clears the data configuration module of the chip; After completing the clear operation, the address chain selects each configuration address in the chip in turn under the control of the clock signal, and for each selected chip configuration address, writes the configuration data to the selected configuration address through the data chain; After all data configuration is completed, the freeze-thaw chain sends a thaw instruction, indicating that the chip configuration is complete.

3. The method for configuring stacked chips according to claim 2, wherein: The freeze-thaw chain circuit, the reset chain circuit, the address chain circuit and the data chain circuit are all provided with a clock signal input terminal and a data signal input terminal; The master chip and the slave chip are provided with clock signal interfaces and data signal interfaces of the linked list circuits; The clock signal interface and the data signal interface of each linked list circuit on the slave chip are respectively connected to the clock signal interface and the data signal interface of each corresponding linked list circuit on the master chip.

4. The method for configuring stacked chips according to claim 2, wherein: The freeze-thaw chain includes a plurality of cascaded D flip-flops, wherein the Q output terminal of the previous D flip-flop in the cascaded D flip-flops is input into the D input terminal of the next D flip-flop; The freeze-thaw chain clock signal is input into the clock signal input terminal of each D flip-flop respectively, and the freeze-thaw chain data signal is input into the D input terminal of the first D flip-flop; The output signal of the Q output terminal of each D flip-flop is used for freezing and unfreezing operations of the chip core.

5. The method for configuring stacked chips according to claim 2, wherein: The zeroing chain includes a plurality of cascaded D flip-flops, wherein the Q output terminal of the previous D flip-flop in the cascaded D flip-flops is input into the D input terminal of the next D flip-flop; The clear chain clock signal is input into the clock signal input terminal of each D flip-flop respectively, and the clear chain data signal is input into the D input terminal of the first D flip-flop; The first clear control signal and the second clear control signal are respectively input into a NAND gate circuit with the output end of each D trigger, and the output end of the NAND gate circuit is output into the inverter, and the inverter output signal is used to control the clearing of the core in the chip.

6. The method for configuring stacked chips according to claim 5, wherein: The clear chain data signal has a built-in 1 in one sampling period of the clear chain clock signal; When the clear chain data signal is set to 1, the first clear control signal and the second clear control signal are synchronously set to 1 and maintained.

7. The method for configuring stacked chips according to claim 2, wherein: The address chain includes a plurality of cascaded D flip-flops, wherein the Q output terminal of the previous D flip-flop in the cascaded D flip-flops is input into the D input terminal of the next D flip-flop; The address chain clock signal is input into the clock signal input terminal of each D flip-flop respectively, and the address chain data signal is input into the D input terminal of the first D flip-flop; The address chain data signal is built-in as 1 in one sampling period of the address chain clock signal; Also included is an address control signal, wherein the address control signal is set to 1 after the D flip-flop is reset; The address control signal and the output end of each D flip-flop are input into a NAND gate circuit, the output end of the NAND gate circuit is output into an inverter, and the inverter output signal is used to select the target address.

8. The method for configuring stacked chips according to claim 2, wherein: The data chain includes: two cascaded D flip-flops; A multiplexer, wherein the output end of the data link is input to the 0 input end of the multiplexer, and the data link data signal is input to the 1 input end of the multiplexer; After the address chain selects the address, the selection signal of the multiplexer is set to 1; The output result of the multiplexer is input to the D input terminal of the first D flip-flop; The data chain clock signal is input to the clock signal input terminal of the first D flip-flop, and the clock signal input to the second D flip-flop is pulled high for one clock cycle after the data of the first D flip-flop is updated; The output of the Q output terminal of the second D flip-flop is stored in the MOS tube; A tri-state gate circuit is provided between the Q output terminal of the second D flip-flop and the MOSFET, and the excitation signal of the tri-state gate circuit and the clock signal of the second D flip-flop are simultaneously pulled high for one clock cycle.

9. The method for configuring stacked chips according to claim 3, wherein: The master chip and the slave chip are provided with an enable signal port, and the enable signal port on the master chip is connected to the enable signal port on the slave chip; After receiving the configuration data, the master chip sends an enable signal to the corresponding chip according to the chip pointed to by the configuration data, and controls the corresponding chip to perform configuration.

10. The method for configuring stacked chips according to claim 9, wherein: The master chip and the slave chip are arranged on the interconnection layer of the stacked chips; The connection between the clock signal interface and the data signal interface of each linked list circuit on the slave chip and the clock signal interface and the data signal interface of each corresponding linked list circuit on the master chip is achieved through an interconnection layer.

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