A configuration method of stacked chips

Abstract

The application provides a chip stacking configuration method, any die is defined as a master chip, and the rest of the chips are slave chips; the master chip and the slave chips are provided with a linked list circuit for chip configuration, including a freeze and unfreeze linked list for freezing and unfreezing all IO interfaces of the chip; a clear linked list for clearing all data in the chip; an address linked list and a data linked list for selecting a chip address to write configuration data; a clock signal interface and a data signal interface of the linked list circuit of the slave chip are connected with a clock signal interface and a data signal interface of the linked list circuit of the master chip; the master chip receives configuration data, controls the linked list circuit of the master chip to realize the configuration of the master chip based on the received configuration data, or sends the received configuration data to the slave chip through the clock signal interface and the data signal interface of the master chip, and controls the linked list circuit of the slave chip to realize the configuration of the slave chip, and the application has the advantages of simple structure and efficient configuration.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip testing, and particularly relates to a configuration method of stacked chips. BACKGROUND

[0002] SSI (Stacked Silicon Interconnect) is a 2.5D integrated circuit packaging technology, aiming to break through the size limit of traditional single-chip and realize the design of FPGA chips with higher integration and performance.

[0003] As a large-scale programmable device, FPGA chips solve the problem of insufficient custom circuits. Users can describe the required functions through hardware language, and then compile the description language into a code stream file (i.e., a configuration file) through software. Finally, the FPGA software is configured. The programmable and configurable features of FPGA chips make them widely used in various fields.

[0004] In the prior art, after using SSI packaging for FPGA chips, multiple FPGA dies can be combined together to further expand the capacity of FPGA.

[0005] Not only for the stacking of FPGA chips, but also for the stacking of other chips, the performance of a single chip can be greatly improved. However, the configuration of a single chip of a stacked chip has become a big problem. For a packaged stacked chip, it is finally presented to the user in the form of a chip, but it is actually a combination of multiple chips. Each chip needs to be independently powered on after power-on. In active mode, it needs to actively send a clock to read the code stream file from the external storage device. In passive mode, it passively receives the external configuration code stream file. If the configuration pins of multiple chips are connected together, the number of configuration pins will be more, and the configuration method will be more complex, which is not conducive to the user to realize the rapid configuration of the stacked chip.

[0006] Therefore, it is necessary to design a configuration method of stacked chips, which can reduce the number of configuration pins in the stacked chips and reduce the complexity of configuration. SUMMARY

[0007] The present application provides a configuration method of stacked chips, which configures each chip through the configuration chain circuit connected between the master chip and the slave chip, and has the advantages of simple structure and efficient configuration.

[0008] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0009] To achieve one or some or all of the above purposes or other purposes, one technical scheme of the present application provides a configuration method of stacked chips, the stacked chips comprising a plurality of dies, any die being defined as a master chip and the rest being defined as slave chips; the master chip and the slave chips are provided with chain table circuits for chip configuration, including a freeze-thaw chain for freezing and thawing all IO interfaces of the chips, a clear chain for clearing all data in the chips, an address chain for selecting chip addresses to write configuration data, and a data chain; the clock signal interface and the data signal interface of the chain table circuits of the slave chips are connected to the clock signal interface and the data signal interface of the chain table circuits of the master chip; the master chip receives configuration data, controls the chain table circuits of the master chip to realize configuration of the master chip based on the received configuration data, or sends the received configuration data to the slave chips through the clock signal interface and the data signal interface of the master chip, and controls the chain table circuits of the slave chips to realize configuration of the slave chips.

[0010] The chain table circuits realize configuration of the chips, including freezing all IO interfaces by the freeze-thaw chain after the chips are powered on; clearing the data configuration module of the chips by the clear chain after the freezing operation is completed; selecting each configuration address in the chips in turn by the address chain under the control of the clock signal, and writing configuration data to the selected configuration address through the data chain for each selected configuration address; and issuing a thaw instruction by the freeze-thaw chain to indicate that the chip configuration is completed after all data configuration is completed.

[0011] The freeze-thaw chain circuit, the clear chain circuit, the address chain circuit, and the data chain circuit are each provided with a clock signal input end and a data signal input end;

[0012] The master chip and the slave chips are provided with the clock signal interface and the data signal interface of each chain table circuit; the clock signal interface and the data signal interface of each chain table circuit on the slave chips are connected to the clock signal interface and the data signal interface of the corresponding chain table circuit on the master chip, respectively.

[0013] The freeze-thaw chain comprises a plurality of cascaded D flip-flops, the Q output end of a previous D flip-flop being connected to the D input end of a next D flip-flop; the freeze-thaw chain clock signal is input to the clock signal input end of each D flip-flop, and the freeze-thaw chain data signal is input to the D input end of the first D flip-flop; the output signal of the Q output end of each D flip-flop is used for freezing and thawing operation of the chip core.

[0014] The clear chain comprises a plurality of cascaded D flip-flops, a Q output of a previous D flip-flop being input to a D input of a next D flip-flop; a clear chain clock signal is input to a clock signal input of each D flip-flop, and a clear chain data signal is input to a D input of a first D flip-flop; the first clear control signal and the second clear control signal are input to a NAND gate circuit from an output of each D flip-flop, an output of the NAND gate circuit is input to an inverter, and an output signal of the inverter is used to control the clear of a core in the chip.

[0015] The clear chain data signal is set to 1 in a sampling period of the clear chain clock signal; the first clear control signal and the second clear control signal are set to 1 synchronously and kept at 1 when the clear chain data signal is set to 1.

[0016] The address chain comprises a plurality of cascaded D flip-flops, a Q output of a previous D flip-flop being input to a D input of a next D flip-flop; an address chain clock signal is input to a clock signal input of each D flip-flop, and an address chain data signal is input to a D input of a first D flip-flop; the address chain data signal is set to 1 in a sampling period of the address chain clock signal; an address control signal is further provided, the address control signal being set to 1 after the D flip-flop is reset; the address control signal is input to a NAND gate circuit from an output of each D flip-flop, an output of the NAND gate circuit is input to an inverter, and an output signal of the inverter is used to select a target address.

[0017] The data chain comprises two cascaded D flip-flops; a multiplexer, an output of the data chain being input to a 0 input of the multiplexer, and a data chain data signal being input to a 1 input of the multiplexer; a selection signal of the multiplexer is set to 1 after the address chain selects an address; an output result of the multiplexer is input to a D input of a first D flip-flop; a data chain clock signal is input to a clock signal input of the first D flip-flop, and a clock signal input of a second D flip-flop is pulled high for one clock period after the data of the first D flip-flop is updated; an output of a Q output of the second D flip-flop is saved to a mos transistor; a tri-state gate circuit is arranged between the Q output of the second D flip-flop and the mos transistor, and an excitation signal of the tri-state gate circuit is pulled high for one clock period simultaneously with the clock signal of the second D flip-flop.

[0018] An enable signal port is arranged on the master chip and the slave chip, the enable signal port on the master chip is connected to the enable signal port on the slave chip; after the master chip receives configuration data, the master chip sends an enable signal to a corresponding chip according to a chip pointed by the configuration data, so as to control the corresponding chip to perform configuration.

[0019] The main chip and the slave chip are arranged on the interconnection layer of the stacked chip; and the connection between the clock signal interface and the data signal interface of each linked list circuit on the slave chip and the clock signal interface and the data signal interface of the corresponding linked list circuit on the main chip is realized through the interconnection layer.

[0020] Compared with the prior art, the beneficial effects of the present application mainly include: 1. The present application uses the configuration resources of each chip for configuration, and when the stacked chip is packaged, more devices do not need to be introduced, the use of configuration pins can be reduced, and the utilization rate of chip area is improved. 2. The present application configures through the linked list circuit in the chip, which can match the maximum configuration bandwidth of each chip, and does not affect the efficiency of configuration.

[0021] In order to make the above and other objects, features and advantages of the present application more apparent, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0023] Figure 1 The connection diagram of each chip in the stacked chip of the present application.

[0024] Figure 2 The frozen and unfrozen linked circuit diagram of the present application.

[0025] Figure 3 The clear zero linked circuit diagram of the present application.

[0026] Figure 4 The address linked circuit diagram of the present application.

[0027] Figure 5 The data linked circuit diagram of the present application. DETAILED DESCRIPTION

[0028] The foregoing and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment in cooperation with the drawings. The directions mentioned in the following embodiments, such as up, down, left, right, front or back, are only the directions of the drawings. Therefore, the directions used are used for illustration, not for limitation of the present application.

[0029] Embodiment one

[0030] Embodiment 1 provides a configuration method for stacked chips, which includes multiple bare chips, and any bare chip is defined as a master chip, and the remaining chips are slave chips; a linked list circuit for chip configuration is provided on the master chip and the slave chip, including a freeze-thaw chain for freezing and thawing all IO interfaces of the chip: a clear chain for clearing all data in the chip; an address chain and a data chain for selecting a chip address to write configuration data; the clock signal interface and the data signal interface of the linked list circuit of the slave chip are connected to the clock signal interface and the data signal interface of the linked list circuit of the master chip; the master chip receives the configuration data, and controls the linked list circuit of the master chip based on the received configuration data to realize the configuration of the master chip, or sends the received configuration data to the slave chip via the clock signal interface and the data signal interface of the master chip, and controls the linked list circuit of the slave chip to realize the configuration of the slave chip.

[0031] The present invention connects the clock signal interfaces and data signal interfaces of the linked list circuits on the master and slave chips, forming a cascaded chip for packaged chip configuration. The master chip acts as the receiver of external configuration data. After receiving the configuration data, it uses the received configuration data for specific chip configuration (either master chip configuration or slave chip configuration), and then sends clock signals and data signals to the linked list circuits of the chips to be configured, controlling the configuration of the corresponding chips. Because the present invention uses pre-set linked list circuits on each chip for configuration, it does not require the introduction of additional configuration pins, significantly conserving chip configuration pin resources and reducing chip area overhead. Furthermore, the use of linked list circuits for configuration can adapt to the chip's configuration bandwidth, improving configuration efficiency.

[0032] The present invention can be used for the configuration of stacked chips formed by chips such as FPGA chips, DSP chips, and MCU chips.

[0033] See also Figure 1 The following embodiment 1 takes the sealing of three FPGA chips as an example to explain in detail the configuration of stacked chips implemented by the present invention.

[0034] One of the three FPGA chips of the present invention is a main chip ( Figure 1 FPGA Die1 in the FPGA) and two slave chips ( Figure 1 FPGA Die2 and FPGA Die3 in the chip), a linked list circuit is set on both the master chip and the slave chip. The linked list circuit includes a freeze-thaw chain for freezing and thawing all IO interfaces of the chip; a clear chain for clearing all data in the chip; an address chain for selecting the chip address to write configuration data, and a data chain.

[0035] In the above-mentioned linked list circuits, each linked list circuit needs to input a clock signal and a data signal, and each chip is provided with a clock signal interface and a data signal interface used by each linked list circuit configuration.Figure 1 The clock signal interface and the data signal interface through which the main chip connects with each slave chip include: a data signal interface (Data_chain_dat[31:0] in the data chain) for signal transmission, Figure 1 a clock signal interface (Data_chain_clk in the data chain) for signal transmission, an address chain data signal interface (Addr_chain_dat in the address chain) for signal transmission, Figure 1 an address chain clock signal interface (Addr_chain_clk in the address chain) for signal transmission, a freeze-thaw chain data signal interface (Freeze_chain_dat in the freeze-thaw chain) for signal transmission, Figure 1 a freeze-thaw chain clock signal interface (Freeze_chain_clk in the freeze-thaw chain) for signal transmission, a clear chain data signal interface (Clr_chain_dat in the clear chain) for signal transmission, Figure 1 a clear chain clock signal interface (Clr_chain_clk in the clear chain) for signal transmission. Figure 1 Figure 1 The main chip is further provided with the same number of enable signal interfaces (Cfg_en0 and Cfg_en1) as the slave chips. After the main chip receives the configuration data, the main chip controls the configuration of the corresponding chip according to the configuration data for the corresponding chip. For example, when the configuration data is used for the configuration of the main chip, the main chip inputs the received configuration data into the chain table circuit of the main chip to realize the configuration of the main chip. When the configuration data is used for the configuration of the slave chip, the main chip sends the corresponding enable signal to the slave chip with the configuration according to the specific chip with the configuration, and then transmits the configuration data to the slave chip through the clock signal interface and the data signal interface mentioned above, so as to control the chain table circuit on the slave chip to realize the configuration of the corresponding slave chip. Figure 1 Figure 1 For example, when the chip to be configured is a slave chip (FPGA Die2), the main chip sends an enable signal to the interface Cfg_en of the slave chip (FPGA Die2) through the enable signal interface Cfg_en0. After the slave chip (FPGA Die2) receives the enable signal, the main chip sends the configuration data to the slave chip (FPGA Die2) through the clock signal interface and the data signal interface, so as to control the chain table circuit on the slave chip (FPGA Die2) to configure the chip.

[0036] For example, when the chip to be configured is a slave chip (FPGA Die2), the main chip sends an enable signal to the interface Cfg_en of the slave chip (FPGA Die2) through the enable signal interface Cfg_en0. After the slave chip (FPGA Die2) receives the enable signal, the main chip sends the configuration data to the slave chip (FPGA Die2) through the clock signal interface and the data signal interface, so as to control the chain table circuit on the slave chip (FPGA Die2) to configure the chip.

[0037] For example, when the chip to be configured is a slave chip (FPGA Die2), the main chip sends an enable signal to the interface Cfg_en of the slave chip (FPGA Die2) through the enable signal interface Cfg_en0. After the slave chip (FPGA Die2) receives the enable signal, the main chip sends the configuration data to the slave chip (FPGA Die2) through the clock signal interface and the data signal interface, so as to control the chain table circuit on the slave chip (FPGA Die2) to configure the chip.

[0038] ​​The master chip and the slave chip are arranged on the interconnection layer of the stacked chips; the clock signal interface and data signal interface of each linked list circuit on the slave chip are connected with the clock signal interface and data signal interface of each corresponding linked list circuit on the master chip, and the connection between the enable signal port of the master chip and the slave chip is realized through the interconnection layer.

[0039] Using a linked list circuit to implement chip configuration includes the following steps: after the chip is powered on, the freeze-thaw chain freezes all IO interfaces; after the freeze operation is completed, the clear chain clears the data configuration module of the chip; after the clear operation is completed, the address chain selects each configuration address in the chip in turn under the control of the clock signal, and for each selected chip configuration address, writes configuration data to the selected configuration address through the data chain; after all data configuration is completed, the freeze-thaw chain issues a thaw instruction, indicating that the chip configuration is complete.

[0040] The following is combined with the attached Figure 2-5 , the working principle of each linked list circuit is explained in detail.

[0041] like Figure 2 The freeze-thaw chain shown includes multiple cascaded D flip-flops, where the Q output of the upper D flip-flop of two adjacent D flip-flops in the cascade is input to the D input of the next D flip-flop; the freeze-thaw chain clock signal Freeze_chain_clk is input to the clock signal input of each D flip-flop respectively, and the freeze-thaw chain data signal Freeze_chain_dat is input to the D input of the first D flip-flop; the Q output of each D flip-flop is inverted through an inverter and then outputs a signal Freeze_bus[x] for freezing and thawing operations of the chip core. The D flip-flop of the freeze-thaw chain of the present invention also has a reset signal aclr. After power-on, the reset signal aclr will first generate a pulse to set the Q output terminals of all D flip-flops to 0, and then the freeze-thaw chain data signal Freeze_chain_dat will be pulled high, and the freeze-thaw chain clock signal Freeze_chain_clk will be input and periodically jump, and multiple output signals Freeze_bus[0], Freeze_bus[1], Freeze_bus[2]...Freeze_bus[n] will be set to 0 in sequence, thereby realizing the freezing of the cores of all FPGA chips.

[0042] When unfreezing all cores in the FPGA chip, it is the opposite of freezing the cores. After all data configuration is completed, the freeze-unfreeze chain data signal Freeze_chain_dat is set low, the freeze-unfreeze chain clock signal Freeze_chain_clk is input and periodically jumps, and multiple output signals Freeze_bus[0], Freeze_bus[1], Freeze_bus[2]...Freeze_bus[n] are set to 1 in sequence. When all output signals Freeze_bus[x] are 0, all cores are unfrozen.

[0043] like Figure 3 The clear chain circuit shown includes multiple cascaded D flip-flops, where the Q output of the previous D flip-flop of two adjacent D flip-flops in the cascade is input to the D input of the next D flip-flop; the clear chain clock signal Clr_chain_clk is input to the clock signal input of each D flip-flop respectively, and the clear chain data signal Clr_chain_dat is input to the D input of the first D flip-flop; the first clear control signal clrsramen and the second clear control signal clrbaren are respectively input to a NAND gate circuit with the output of each D flip-flop, and the output of the NAND gate circuit is output to the inverter, which outputs two signals clrsram[x] and clrbar[x]. The two signals clrsram[0], clrbar[0]; clrsram[1], clrbar[1]; clrsram[2], clrbar[2]..., clrsram[n], clrbar[n] output by the clear chain will be set to 1 in sequence. When all the signals clrsram[x] and clrbar[x] have been 1, they will be changed to 0 to realize a clear operation of all the cores of the FPGA.

[0044] The reset input of the clear chain D flip-flop receives the reset signal creset. After power-up, a pulse of the reset signal creset appears, setting the Q outputs of all D flip-flops in the clear chain to 0. The clear chain data signal Clr_chain_dat is set to 1 during one sampling cycle of the clear chain clock signal and remains 0 the rest of the time. Therefore, within a single sampling cycle, the clear chain data signal Clr_chain_dat can be collected and output through the Q terminal (D flip-flops are triggered on rising edges to collect input data). The first clear control signal clrsramen and the second clear control signal clrbaren are set to 1 when the clear chain data signal Clr_chain_dat is set to 1 and remain 1 until the clear operation is complete.

[0045] See also Figure 4The circuit structure diagram of the address chain can be seen that the address chain circuit includes a plurality of cascaded D flip-flops, in which the Q output terminal of the previous D flip-flop of two adjacent D flip-flops is input to the D input terminal of the next D flip-flop; the address chain clock signal Addr_chain_clk is input to the clock signal input terminal of each D flip-flop; the address chain data signal Addr_chain_dat is input to the D input terminal of the first D flip-flop; the address chain data signal Addr_chain_dat is set to 1 in one sampling period of the address chain clock signal; the address chain circuit further includes an address control signal aden, which is set to 1 after the D flip-flop is reset (the reset signal aclr of the address chain D flip-flop generates a pulse after power-on, and the Q output terminals of the address chain D flip-flop are all set to 0); the address control signal aden and the output terminal of each D flip-flop are input to a NAND gate circuit together, the output terminal of the NAND gate circuit is output to an inverter, and the output signal adrbus[x] of the inverter is used to select the target address.

[0046] Specifically, after the D flip-flop is reset, all output signals adrbus[x] are 0, at this time, the address control signal aden is pulled up to 1, the address chain data signal Addr_chain_dat is set to 1 in one sampling period of the address chain clock signal Addr_chain_clk, and is set to 0 at other times, so that the 1 of the address chain data signal Addr_chain_dat is continuously transmitted downward when the address chain clock signal Addr_chain_clk continuously changes. First, adrbus[0] is 1 and adrbus[1] is 0, with the arrival of the next Addr_chain_clk, adrbus[0] is 0 and adrbus[1] is 1, therefore, the address chain of the application can select the configuration addresses in the FPGA chip one by one to write configuration data into the selected addresses.

[0047] As Figure 5 , the data chain of embodiment one includes: two cascaded D flip-flops, the Q output terminal of the previous D flip-flop is input to the Q input terminal of the next D flip-flop; a multiplexer, the multiplexer has 0 / 1 input terminals, wherein the 1 input terminal inputs the data chain data signal Data_chain_dat. The output signal of the data chain is input to the 0 input terminal of the multiplexer.

[0048] After the address chain selects the address, the selection signal dcsm of the multiplexer is 1 (at this time, the signal at the input end of 1 is output, which is selecting the data chain data signal Data_chain_dat to output in the first embodiment) ; the output result of the multiplexer is input to the D input end of the first D flip-flop; the data chain clock signal Data_chain_clk is input to the clock signal input end of the first D flip-flop, and in the sampling period, the data chain data signal Data_chain_dat is punched into the first D flip-flop. The clock signal dcbc input end of the second D flip-flop is pulled high for one clock cycle after the data of the first D flip-flop is updated (the D flip-flop is rising edge sampling, at this time, the data chain data signal Data_chain_dat can be punched into the second D flip-flop) ; the data output from the Q output end of the second D flip-flop is saved to the mos tube; the three-state gate circuit is arranged between the Q output end of the second D flip-flop and the mos tube, the excitation signal dcwr of the three-state gate circuit is pulled high for one clock cycle at the same time as the clock signal dcbc of the second D flip-flop, at this time, the second three-state gate circuit is turned on (the excitation signal of the three-state gate circuit is pulled high for the on state of the data transmission, the excitation signal of the three-state gate circuit is low, then it is high resistance state, and the data cannot pass through), and the data can enter the MOS tube through the three-state gate circuit and be saved.

[0049] When the address chain selects the address, the MOS tube serves as a storage unit, the gate control signal hdbus thereof is pulled low to enter the data saving state, at this time, the data output by the data chain can be written into the storage unit.

[0050] The configuration method of the stacked chip provided by the present application is described in detail above, and the structure and working principle of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that for ordinary skilled persons in the technical field, without departing from the principle of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method of configuring a stacked chip, comprising: The stacked chip comprises a plurality of dies, any die is defined as a master chip, and the rest are slave chips; The master chip and the slave chips are provided with chain table circuits for chip configuration, including a freeze-thaw chain for freezing and thawing all IO interfaces of the chip; A clear chain for clearing all data in the chip; An address chain for selecting a chip address to write configuration data; The clock signal interface and the data signal interface of the slave chip chain table circuit are connected to the clock signal interface and the data signal interface of the master chip chain table circuit; The master chip receives configuration data, controls the chain table circuit of the master chip to realize the configuration of the master chip based on the received configuration data, or sends the received configuration data to the slave chip through the clock signal interface and the data signal interface of the master chip, and controls the chain table circuit of the slave chip to realize the configuration of the slave chip; The chain table circuit realizes the configuration of the chip, including freezing all IO interfaces by the freeze-thaw chain after the chip is powered on; clearing the data configuration module of the chip by the clear chain after the freezing operation is completed; selecting each configuration address in the chip in turn by the address chain under the control of the clock signal, and writing configuration data to the selected configuration address through the data chain for each selected chip configuration address; and issuing a thaw instruction by the freeze-thaw chain to indicate that the chip configuration is completed after all data configuration is completed.

2. The method of claim 1, wherein The freeze-thaw chain circuit, the clear chain circuit, the address chain circuit, and the data chain circuit are each provided with a clock signal input end and a data signal input end; The master chip and the slave chips are provided with clock signal interfaces and data signal interfaces of the chain table circuits; The clock signal interfaces and the data signal interfaces of the chain table circuits on the slave chip are respectively connected to the clock signal interfaces and the data signal interfaces of the corresponding chain table circuits on the master chip.

3. The method of claim 1, wherein The freeze-thaw chain comprises a plurality of cascaded D flip-flops, and the Q output end of a previous D flip-flop inputs the D input end of a next D flip-flop in the cascaded D flip-flops; The freeze-thaw chain clock signal is input to the clock signal input end of each D flip-flop, and the freeze-thaw chain data signal is input to the D input end of the first D flip-flop; The output signal of the Q output end of each D flip-flop is used for freezing and thawing operations of the chip core.

4. The method of claim 1, wherein The clear chain comprises a plurality of cascaded D flip-flops, and the Q output end of a previous D flip-flop inputs the D input end of a next D flip-flop in the cascaded D flip-flops; The clear chain clock signal is input to the clock signal input end of each D flip-flop, and the clear chain data signal is input to the D input end of the first D flip-flop; The first clear control signal and the second clear control signal are respectively input to a NAND gate circuit from the output end of each D flip-flop, the output end of the NAND gate circuit is output to an inverter, and the output signal of the inverter is used for controlling the clearing of the chip core.

5. The method of claim 4, wherein, The clear chain data signal is set to 1 in a sampling period of the clear chain clock signal; The first clear control signal and the second clear control signal are synchronously set to 1 and remain unchanged when the clear chain data signal is set to 1.

6. The method of claim 1, wherein The address chain comprises a plurality of cascaded D flip-flops, and a Q output of a previous D flip-flop is input to a D input of a next D flip-flop; An address chain clock signal is input to a clock signal input of each D flip-flop, and an address chain data signal is input to a D input of a first D flip-flop; The address chain data signal is set to 1 in a sampling period of the address chain clock signal; An address control signal is further provided, and the address control signal is set to 1 after the D flip-flop is reset; The address control signal is input to an AND NOT gate circuit together with an output of each D flip-flop, and an output of the AND NOT gate circuit is input to an inverter, and an output signal of the inverter is used to select a target address.

7. The method of claim 1, wherein The data chain comprises two cascaded D flip-flops; A multiplexer, a 0 input of the multiplexer is connected to an output of the data chain, and a 1 input of the multiplexer is connected to a data signal of the data chain; After the selected address of the address chain is selected, a selection signal of the multiplexer is set to 1; An output result of the multiplexer is input to a D input of a first D flip-flop; A data chain clock signal is input to a clock signal input of the first D flip-flop, and a clock signal input of a second D flip-flop is pulled high for one clock period after a data of the first D flip-flop is updated; An output of a Q output of the second D flip-flop is saved to a mos transistor; A tri-state gate circuit is arranged between the Q output of the second D flip-flop and the mos transistor, and an excitation signal of the tri-state gate circuit is pulled high for one clock period at the same time as a clock signal of the second D flip-flop.

8. The method of claim 2, wherein: An enable signal port is arranged on the master chip and the slave chip, and the enable signal port on the master chip is connected to the enable signal port on the slave chip; After the master chip receives configuration data, the master chip sends an enable signal to a corresponding chip according to a chip pointed by the configuration data, so as to control the corresponding chip to perform configuration.

9. The method of claim 8, wherein, The master chip and the slave chip are arranged on an interconnection layer of a stacked chip. Clock signal interfaces and data signal interfaces of each linked list circuit on the slave chip are connected to corresponding clock signal interfaces and data signal interfaces of each linked list circuit on the master chip through the interconnection layer.

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