Simulator model based on second-order local active memristor

Abstract

The invention discloses an emulator model based on a second-order local active memristor, the emulator model is constructed based on a mathematical model of the second-order local active memristor, the constructed emulator model comprises integrated operational amplifiers U1, U2 and U3, multipliers U4, U5, U6, U7 and U8, a resistor and a capacitor, and the U1 is used for integral operation and inverse amplification operation and outputting a state variable x in the memristor; the U2 is used for realizing inverting amplification operation and integral operation to obtain a state variable y in the memristor; the U3 is used for realizing inverting addition operation and inverting amplification operation, and the memristor output current i is obtained by connecting an external resistor in series; the multiplier U4, the multiplier U5, the multiplier U6, the multiplier U7 and the multiplier U8 are used for achieving multiplication of signals. The simulator model can replace an actual second-order local active memristor for experiment and application research.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, relates to a second-order local active memristor, and particularly relates to a simulator model based on the second-order local active memristor. Background Art

[0002] The memristor, the fourth fundamental circuit element after resistors, capacitors, and inductors, was first predicted in 1971 by Chinese-American scientist Shao-Tang Tsai based on theoretical mathematical symmetry. Its core characteristic is that its resistance value can dynamically change based on the amount of charge flowing through it and retain its state after power failure, enabling non-volatile storage. The memristor's "storage-computation-in-one" feature (i.e., performing computation directly within the memory cell) offers new insights into overcoming the bottlenecks of the traditional von Neumann architecture, demonstrating significant potential in fields such as artificial intelligence, neuromorphic computing, and big data processing.

[0003] Second-order locally active memristors are a key branch of memristor research in recent years. Their core characteristic is the presence of two internal state variables, which exhibit local activity under specific operating conditions. This allows them to generate energy gain (similar to "negative differential resistance") under small-signal excitation, thereby supporting more complex nonlinear dynamics. Second-order locally active memristors represent a significant trend in memristor research, moving from simple models to complex systems. They offer a new path for building artificial intelligence hardware that more closely resembles biological neural systems.

[0004] Compared to passive memristors, research on second-order local active memristors is relatively limited, and practical mathematical and circuit models are lacking. Therefore, this paper designs a mathematical model and simulator based on second-order local active memristors. The mathematical model provides a theoretical model for the physical implementation of second-order local active memristors, and the simulator can replace actual second-order local active memristors for experiments and applied research. This has important implications for the implementation and research of second-order local active memristors. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention proposes a simulator model based on a second-order local active memristor. The simulator model is constructed based on the mathematical model of the second-order local active memristor. The mathematical model can provide a theoretical model for the physical realization of the second-order local active memristor. The simulator model is used to simulate the volt-ampere characteristics of the memristor and replace the actual memristor for circuit design and application.

[0006] To achieve the above object, the technical solution adopted by the present invention is that t is the corresponding time point;

[0007] A simulator model based on a second-order local active memristor is constructed based on the mathematical model of the second-order local active memristor.

[0008] The mathematical model based on the second-order local active memristor is as follows:

[0009] ;

[0010] Where i and u are the current and voltage of the memristor, x and y are the state variables of the memristor,

[0011] The simulator model includes integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3, multipliers U4, U5, U6, U7, U8 and components resistors and capacitors.

[0012] The integrated operational amplifier U1 is used to implement inverting addition operation, inverting amplification operation and integration operation, which includes a first control chip, resistors R1-R11, and a capacitor C1. Pins 1, 2, and 3 of the first control chip and resistors R1 and R2 constitute a first inverting amplifier. Pins 12, 13, and 14 of the first control chip and resistors R3, R4, and R5 and capacitor C1 constitute a first integrator. Pins 5, 6, and 7 of the first control chip and resistors R6 and R7 constitute a second inverting amplifier. Pins 8, 9, and 10 of the first control chip and resistors R8 and R9 constitute a third inverting amplifier. Pin 1 outputs voltage -u, pin 7 outputs -X1, pin 8 outputs X1, and pin 14 outputs the internal state variable x of the memristor.

[0013] The integrated operational amplifier U2 is used to implement inverting addition, inverting amplification, and integration operations. It includes a second control chip, resistors R10-13, and a capacitor C2. Pins 1, 2, and 3 of the second control chip, resistors R10, R11, and capacitor C2 form a second integrator. Pins 5, 6, and 7 of the second control chip, and resistors R12 and R13 form a fourth inverting amplifier. Pin 1 outputs the internal state variable y of the memristor, and pin 7 outputs -Y1.

[0014] The integrated operational amplifier U3 is used to implement inverting addition and inverting amplification operations. It includes a third control chip and resistors R14-R20. Pins 5, 6, and 7 of the third control chip and resistors R14 and R15 constitute a fifth inverting amplifier. Pins 8, 9, and 10 of the third control chip and resistors R16 and R17 constitute a sixth inverting amplifier. Pins 1, 2, and 3 of the third control chip and resistors R18, R19, and R20 constitute an inverting adder. Pin 7 outputs -X2 2 , Pin 8 Output - Y2 2 , pin 1 outputs current i;

[0015] The multipliers U4, U5, U6, U7 and U8 are used to implement signal multiplication operations.

[0016] The multiplier U4 is used to realize the voltage u at pin 9 of U1 1-9 and U2 pin 7 voltage u 2-7 The voltage at the output terminal W of the multiplier U4 is:

[0017] ;

[0018] The multiplier U5 is used to realize the voltage u1 pin 7 1-7 The voltage at the output terminal W of the multiplier U5 is:

[0019] ;

[0020] The multiplier U6 is used to realize the voltage u at pin 7 of U2 2-7 The voltage at the output terminal W of the multiplier U6 is:

[0021] ;

[0022] The multiplier U7 is used to realize the input voltage u and the voltage u of U3 pin 7 3-7 The voltage at the output terminal W of the multiplier U7 is:

[0023] ;

[0024] The multiplier U8 is used to realize the input voltage u and the voltage u at pin 8 of U3. 3-8 The voltage at the output terminal W of the multiplier U7 is:

[0025] .

[0026] As a preferred technical solution of the present invention: the first control chip in the integrated operational amplifier U1 adopts TL084, pin 1 is connected to pin 2 through resistor R2; pin 2 is connected to the memristor voltage u through resistor R1, pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 14 through resistor R6; pin 7 is connected to pin 6 through resistor R7; pin 8 is connected to pin 9 through resistor R9; pin 9 is connected to pin 7 through resistor R8; pin 10 is grounded; pin 12 is grounded; pin 13 is connected to pin 14 and multiplier U4 output -X1Y1 / 10 through resistor R3, resistor R4, and resistor R5 respectively. 4 , pin 1; pin 14 is connected to pin 13 through capacitor C1; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0027] As a preferred technical solution of the present invention: the second control chip in the integrated operational amplifier U2 adopts TL084, pin 1 is connected to pin 2 through capacitor C2; pin 2 is connected to pin 1 and the first control chip pin 1 output -u through resistors R10 and R11 respectively; pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 1 through resistor R12; pin 7 is connected to pin 6 through resistor R13; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0028] As a preferred technical solution of the present invention: the third control chip in the integrated operational amplifier U3 adopts TL084, and pin 6 is connected to the multiplier U5 output X1 through the resistor R14. 2 / 10 4 Pin 7 is connected to pin 6 through resistor R15; Pin 9 is connected to multiplier U6 output Y1 through resistor R16 2 / 10 4 Pin 8 is connected to pin 9 through resistor R17; Pin 2 is connected to multiplier U7 output -X2 through resistors R18 and R19 respectively 2 u / 10 4 and multiplier U8 output - Y2 2 u / 10 4 ; Also includes a resistor R21, pin 1 is connected to pin 2 and the memristor current i through resistors R20 and R21 respectively; pin 3 and pin 5 are grounded; pin 4 is connected to the power supply VCC; pin 11 is connected to the power supply VEE.

[0029] As a preferred technical solution of the present invention: the multiplier U4 is controlled by an AD633 chip, the multiplier U4 pin 1 is connected to the pin 8 of the first control chip to output X1; pin 3 is connected to the pin 7 of the second control chip to output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; pin 7 outputs -X1Y1 / 10 4 .

[0030] As a preferred technical solution of the present invention: the multiplier U5 is controlled by the AD633 chip, the multiplier U5 pin 1 is connected to the pin 8 of the first control chip to output X1; pin 3 is connected to the pin 8 of the first control chip to output X1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; pin 7 outputs X1 2 / 10 4 .

[0031] As a preferred technical solution of the present invention: the multiplier U6 is controlled by the AD633 chip, the multiplier U6 pin 1 is connected to the pin 7 output of the second control chip -Y1; pin 3 is connected to the pin 7 output of the second control chip -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; pin 7 output is Y1 2 / 10 4 .

[0032] As a preferred technical solution of the present invention: the multiplier U7 is controlled by an AD633 chip, and the pin 1 of the multiplier U7 is connected to the pin 7 output of the third control chip -X2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -X2 2 u / 10 4 .

[0033] As a preferred technical solution of the present invention: the multiplier U8 is controlled by an AD633 chip, and the pin 1 of the multiplier U8 is connected to the pin 8 of the third control chip output -Y2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -Y2 2 u / 10 4 .

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] This paper designs a mathematical model based on a second-order locally active memristor and establishes a simulator model based on the mathematical model. The simulator model contains three integrated operational amplifiers (U1, U2, and U3), five multipliers (U4, U5, U6, U7, and U8), and resistors and capacitors for connecting components. The simulator model is used to simulate the volt-ampere characteristics of the second-order locally active memristor. When actual memristor devices are unavailable, this method can be used to replace actual memristors for memristor-related circuit design, experiments, and applications, thus having important practical significance for research on the characteristics and applications of memristors.

[0036] The present invention utilizes an integrated operational circuit and an analog multiplier to implement the corresponding operations in the memristor's characteristics. The integrated operational amplifier is primarily used to implement voltage inversion and addition operations, integration operations, and inverting amplifiers, while the analog multiplier is used to implement voltage product operations. The memristor's voltage u passes through the second and third inverting amplifiers of integrated operational amplifier U1, and the first integrator to obtain the memristor's internal state variable x. After passing through U1's first inverting amplifier, voltage u passes through the fourth inverting amplifier and second integrator of integrated operational amplifier U2 to obtain the memristor's internal state variable y. The internal state variables x and y, after respectively using the inverting amplifiers of integrated operational amplifiers U1 and U2, are then multiplied by the multiplier and the fifth and sixth inverting amplifiers and inverting adder of integrated operational amplifier U3 to obtain the memristor's current i. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is an equivalent circuit block diagram of the simulator model in the present invention;

[0038] Figure 2 is a schematic diagram of an analog equivalent circuit of a simulator model in the present invention;

[0039] Figure 3 This is the output waveform of the memristor when f=1000Hz;

[0040] Figure 4 is the hysteresis curve of the memristor when f=1000Hz;

[0041] Figure 5 This is the hysteresis curve of the memristor when f=3000Hz. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0043] The present invention designs a mathematical model based on a second-order local active memristor. The designed mathematical model can provide a theoretical model for the physical realization of the second-order local active memristor. A simulator model is constructed based on the designed mathematical model. The simulator model can replace the actual second-order local active memristor for experiments and application research. This is of great significance for the realization and research of new second-order local active memristors.

[0044] The mathematical model based on the second-order local active memristor proposed in the present invention is as follows:

[0045] ;

[0046] Where i and u are the current and voltage of the memristor, and x and y are the state variables of the memristor.

[0047] like Figure 1 As shown, a simulator model is constructed based on the mathematical model of the second-order local active memristor. The simulator model includes an integrated operational amplifier U1, an integrated operational amplifier U2, an integrated operational amplifier U3, multipliers U4, U5, U6, U7, U8 and components such as resistors and capacitors.

[0048] The integrated operational amplifier U1 is used for integration and inverting amplification operations, and outputs the state variable x inside the memristor;

[0049] The integrated operational amplifier U2 is used to implement inverting amplification and integration operations to obtain the state variable y inside the memristor;

[0050] The integrated operational amplifier U3 is used to implement inverting addition and inverting amplification operations, and obtains the memristor output current i by connecting an external resistor in series;

[0051] The first control chip, the second control chip and the third control chip in the integrated operational amplifiers U1 , U2 and U3 of the present invention are all TL084 chips.

[0052] Multipliers U4, U5, U6, U7, and U8 are used to implement signal multiplication operations.

[0053] The multipliers U4, U5, U7 and U8 in the present invention all adopt the chip AD633.

[0054] like Figure 2 As shown, pins 1, 2, and 3 of the first control chip in the integrated operational amplifier U1 and resistors R1 and R2 form a first inverting amplifier. The external voltage u is connected to pin 2 through resistor R1. According to the calculation formula of the inverting amplifier, the voltage at the output pin 1 can be obtained as:

[0055] ;

[0056] Since R1 = 10kΩ, R2 = 10kΩ, the voltage at pin 1 is:

[0057] ;

[0058] Pins 12, 13, 14 of the first control chip and resistors R3, R4, R5 and capacitor C1 form a first integrator. The input end of pin 13 is respectively connected to the internal state variable x of the memristor and the output end -X1Y1 / 10 of the multiplier U4 through resistors R3, R4, R5. 4 And the output voltage -u of pin 1 is connected to get the current i of pin 13 1-13 for:

[0059] ;

[0060] The current on pin 14 is:

[0061] ;

[0062] According to the amplifier's operational characteristics, the current i at pin 14 is 1-14 The current i at pin 13 1-13 The same, so we can get:

[0063] ;

[0064] Since R3 = 10kΩ, R4 = 20kΩ, R5 = 10kΩ, and capacitor C1 = 10μF, the output voltage at pin 14 is:

[0065] ;

[0066] Pins 5, 6, and 7 of the first control chip and resistors R6 and R7 form a second inverting amplifier circuit. Pin 5 is directly grounded. The memristor state variable x is connected to pin 6 via resistor R6, and pin 7 is connected to pin 6 via resistor R7. Given R6 = 1KΩ and R7 = 100KΩ, the output voltage can be calculated as:

[0067] ;

[0068] Pins 8, 9, and 10 of the first control chip and resistors R8 and R9 form a third inverting amplifier. Pin 10 is directly grounded. The output -X1 of pin 7 is connected to pin 9 through resistor R8, and pin 8 is connected to pin 8 through resistor R9. Since R8 = 10KΩ and R9 = 10KΩ, the output voltage can be obtained as follows:

[0069] ;

[0070] Pins 1, 2, and 3 of the second control chip in the integrated operational amplifier U2, along with resistors R10, R11, and capacitor C2, form a second integrator. Pin 3 is directly grounded. The internal state variable y of the memristor is connected to pin 2 via resistor R10, and the output -u of pin 1 of the first control chip is connected to pin 1 via resistor R11. The current at pin 2 is:

[0071] ;

[0072] The corresponding current on pin 1 is:

[0073] ;

[0074] Since R10 = 10kΩ, R11 = 20kΩ, and the current on pin 2 is equal to the current on pin 1, the output voltage on pin 1 is:

[0075] ;

[0076] Pins 5, 6, and 7 of the second control chip and resistors R12 and R13 form a fourth inverting amplifier. Pin 5 is directly grounded, pin 6 is connected to the internal variable y of the memristor through resistor R12, and pin 7 is connected to pin 6 through resistor R13. Since R12 = 1 kΩ and R13 = 100 kΩ, the output voltage of pin 7 can be obtained as:

[0077] .

[0078] Pins 5, 6, and 7 of the third control chip in the integrated operational amplifier U3 and resistors R14 and R15 form a fifth inverting amplifier. Pin 5 is directly grounded, and the multiplier U5 outputs a voltage of X1. 2 / 10 4 Connected to pin 6 through resistor R14, pin 7 is the output terminal and is connected to pin 6 through resistor R15. The output voltage is:

[0079] ;

[0080] Pins 8, 9, and 10 of the third control chip and resistors R16 and R17 form a sixth inverting amplifier. Pin 10 is directly grounded. The multiplier U6 outputs a voltage Y1. 2 / 10 4 Pin 8 is connected to pin 9 through resistor R16. Pin 8 is the output terminal and is connected to pin 9 through resistor R17. The output voltage is:

[0081] ;

[0082] Pins 1, 2, and 3 of the third control chip and resistors R18, R19, and R20 form an inverting adder. Pin 3 is directly grounded, and the multiplier U7 outputs a voltage of -X2. 2 u / 10 4 Connected to pin 2 through resistor R18, the multiplier U8 outputs voltage -Y2 2 u / 10 4 Connected to pin 2 through resistor R19, pin 1 is connected to pin 2 through resistor R20. The output voltage of pin 1 is:

[0083] ;

[0084] Since the resistors R18 = 10kΩ, R19 = 10kΩ, and R20 = 10kΩ, the output voltage of pin 1 can be changed to:

[0085] ;

[0086] The output current i of pin 1 through the series resistor R21 is:

[0087] ;

[0088] Because R21=10Ω, u=1V is converted to u=10 3 mV, combined with the relationship between X2, Y2 and X1, Y1 as well as x and y, we can get the current i as:

[0089] .

[0090] Multiplier U4 is used to realize the voltage u at pin 9 of U1 1-9 and U2 pin 7 voltage u 2-7 The multiplication operation, because the multiplier has its own voltage 10V (10 4 mV) cannot be ignored, so the voltage at the output W of the multiplier U4 is:

[0091] ;

[0092] Multiplier U5 is used to realize the voltage u at pin 7 of U1 1-7 The square operation, the multiplier has a voltage of 10V (10 4 mV) cannot be ignored, so the voltage at the output W of the multiplier U5 is:

[0093] ;

[0094] Multiplier U6 is used to realize the voltage u at pin 7 of U2 2-7 Square operation, because the multiplier has its own voltage 10V (10 4 mV) cannot be ignored, so the voltage at the output W of the multiplier U6 is:

[0095] ;

[0096] Multiplier U7 is used to realize the input voltage u and the voltage u at pin 7 of U3 3-7 The multiplication operation, because the multiplier has its own voltage 10V (10 4 mV) cannot be ignored, so the voltage at the output W of the multiplier U7 is:

[0097] ;

[0098] Multiplier U8 is used to realize the input voltage u and the voltage u at pin 8 of U3 3-8 The multiplication operation, because the multiplier has its own voltage 10V (10 4 mV) cannot be ignored, so the voltage at the output W of the multiplier U7 is:

[0099] .

[0100] The specific connection method of the three integrated operational amplifiers U1, U2 and U3 is as follows:

[0101] like Figure 2 As shown, the first control chip in the integrated operational amplifier U1 adopts TL084, pin 1 is connected to pin 2 through resistor R2; pin 2 is connected to the memristor voltage u through resistor R1, and pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 14 through resistor R6; pin 7 is connected to pin 6 through resistor R7; pin 8 is connected to pin 9 through resistor R9; pin 9 is connected to pin 7 through resistor R8; pin 10 is grounded; pin 12 is grounded; pin 13 is connected to pin 14 and multiplier U4 output -X1Y1 / 10 through resistor R3, resistor R4, and resistor R5 respectively. 4 , pin 1; pin 14 is connected to pin 13 through capacitor C1; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0102] like Figure 2 As shown, the second control chip in the integrated operational amplifier U2 adopts TL084, pin 1 is connected to pin 2 through capacitor C2; pin 2 is connected to pin 1 and -u respectively through resistors R10 and R11; pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 1 through resistor R12; pin 7 is connected to pin 6 through resistor R13; pin 4 is connected to power supply VCC; and pin 11 is connected to power supply VEE.

[0103] like Figure 2 As shown, the third control chip in the integrated operational amplifier U3 adopts TL084, and pin 6 is connected to the multiplier U5 output X1 through resistor R14. 2 / 10 4 Pin 7 is connected to pin 6 through resistor R15; Pin 9 is connected to multiplier U6 output Y1 through resistor R16 2 / 10 4 Pin 8 is connected to pin 9 through resistor R17; Pin 2 is connected to multiplier U7 output -X2 through resistors R18 and R19 respectively 2 u / 10 4 and multiplier U8 output - Y2 2 u / 10 4 ; Pin 1 is connected to pin 2 and memristor current i through resistor R20 and resistor R21 respectively; Pin 3 and pin 5 are grounded; Pin 4 is connected to power supply VCC; Pin 11 is connected to power supply VEE.

[0104] like Figure 2 As shown, multipliers U4, U5, U6, U7, and U8 all use AD633.

[0105] Pin 1 of multiplier U4 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 7 of the second control chip to output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to power supply VCC; pin 5 is connected to power supply VEE; pin 7 outputs -X1Y1 / 10 4 .

[0106] Pin 1 of multiplier U5 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 8 of the first control chip to output X1; pins 2, 4, and 6 are grounded; pin 8 is connected to power supply VCC; pin 5 is connected to power supply VEE; pin 7 output is X1 2 / 10 4 .

[0107] Pin 1 of multiplier U6 is connected to pin 7 of the second control chip, output -Y1; pin 3 is connected to pin 7 of the second control chip, output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to power supply VCC; pin 5 is connected to power supply VEE; pin 7 output is Y1 2 / 10 4 .

[0108] Multiplier U7 pin 1 is connected to the third control chip pin 7 output - X2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -X2 2 u / 10 4 .

[0109] Multiplier U8 pin 1 is connected to the third control chip pin 8 output - Y2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -Y2 2 u / 10 4 .

[0110] The actual simulation test using Multisim is as follows:

[0111] Assume that the input voltage is u=Msin(2πft), M=1mV, f=1000Hz, the waveform and hysteresis curve of the memristor output are as follows: Figure 3-5 As shown, Figure 3 In the figure, the blue curve corresponds to the current i of the memristor. According to the oscilloscope's unit conversion of 1V / mA, the current i of the memristor is 0.01mA at this time.

[0112] like Figure 4 As shown, the present invention meets the basic properties of a locally active memristor, has an 8-shaped hysteresis curve and a local active domain, can produce complex dynamic behaviors, and can be applied to the research and design of neuron circuits.

[0113] like Figure 5 As shown in Figure 1, when the input voltage frequency of the memristor is increased to f = 3000 Hz, it can be observed that the hysteresis area of ​​the memristor hysteresis curve is significantly reduced. If the frequency is further increased, the hysteresis curve of the memristor will shrink to a straight line.

[0114] This paper designs a mathematical model based on a second-order locally active memristor and establishes a simulator model based on the mathematical model. The simulator model contains three integrated operational amplifiers (U1, U2, and U3), five multipliers (U4, U5, U6, U7, and U8), and resistors and capacitors for connecting components. The simulator model is used to simulate the volt-ampere characteristics of the second-order locally active memristor. When actual memristor devices are unavailable, this method can be used to replace actual memristors for memristor-related circuit design, experiments, and applications, thus having important practical significance for research on the characteristics and applications of memristors.

[0115] The present invention utilizes an integrated operational circuit and an analog multiplier to implement the corresponding operations in the memristor's characteristics. The integrated operational amplifier is primarily used to implement voltage inversion and addition operations, integration operations, and inverting amplifiers, while the analog multiplier is used to implement voltage product operations. The memristor's voltage u passes through the second and third inverting amplifiers of integrated operational amplifier U1, and the first integrator to obtain the memristor's internal state variable x. After passing through U1's first inverting amplifier, voltage u passes through the fourth inverting amplifier and second integrator of integrated operational amplifier U2 to obtain the memristor's internal state variable y. The internal state variables x and y, after respectively using the inverting amplifiers of integrated operational amplifiers U1 and U2, are then multiplied by the multiplier and the fifth and sixth inverting amplifiers and inverting adder of integrated operational amplifier U3 to obtain the memristor's current i.

[0116] Those skilled in the art should recognize that the above embodiments are only used to verify the present invention and are not intended to limit the present invention. As long as they are within the scope of the present invention, any changes or modifications to the above embodiments will fall within the scope of protection of the present invention.

Claims

1. A simulator model based on a second-order locally active memristor, characterized by: Based on the mathematical model of the second-order local active memristor, a simulator model is constructed. The mathematical model based on the second-order local active memristor is as follows: ； Where i and u are the current and voltage of the memristor, x and y are the state variables of the memristor, and t is the corresponding time point; The simulator model includes integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3, multipliers U4, U5, U6, U7, U8 and components resistors and capacitors. The integrated operational amplifier U1 is used to implement inverting addition operation, inverting amplification operation and integration operation, which includes a first control chip, resistors R1-R9, and a capacitor C1. Pins 1, 2, and 3 of the first control chip and resistors R1 and R2 constitute a first inverting amplifier, pins 12, 13, and 14 of the first control chip and resistors R3, R4, and R5 and capacitor C1 constitute a first integrator, pins 5, 6, and 7 of the first control chip and resistors R6 and R7 constitute a second inverting amplifier, and pins 8, 9, and 10 of the first control chip and resistors R8 and R9 constitute a third inverting amplifier, wherein pin 1 outputs voltage -u, pin 7 outputs -X1, pin 8 outputs X1, and pin 14 outputs the internal state variable x of the memristor; The integrated operational amplifier U2 is used to implement inverting addition, inverting amplification, and integration operations. It includes a second control chip, resistors R10-13, and a capacitor C2. Pins 1, 2, and 3 of the second control chip, resistors R10, R11, and capacitor C2 form a second integrator. Pins 5, 6, and 7 of the second control chip, and resistors R12 and R13 form a fourth inverting amplifier. Pin 1 outputs the internal state variable y of the memristor, and pin 7 outputs -Y1. The integrated operational amplifier U3 is used to implement inverting addition and inverting amplification operations. It includes a third control chip and resistors R14-R20. Pins 5, 6, and 7 of the third control chip and resistors R14 and R15 constitute a fifth inverting amplifier. Pins 8, 9, and 10 of the third control chip and resistors R16 and R17 constitute a sixth inverting amplifier. Pins 1, 2, and 3 of the third control chip and resistors R18, R19, and R20 constitute an inverting adder. Pin 7 outputs -X2 2 , Pin 8 Output - Y2 2 , pin 1 output is the memristor current i; The multipliers U4, U5, U6, U7 and U8 are used to implement signal multiplication operations. The multiplier U4 is used to realize the voltage u1 pin 9 1-9 and U2 pin 7 voltage u 2-7 The voltage at the output terminal W of the multiplier U4 is: ； The multiplier U5 is used to realize the voltage u1 pin 7 1-7 The voltage at the output terminal W of the multiplier U5 is: ； The multiplier U6 is used to realize the voltage u at pin 7 of U2 2-7 The voltage at the output terminal W of the multiplier U6 is: ； The multiplier U7 is used to realize the input voltage u and the voltage u of U3 pin 7 3-7 The voltage at the output terminal W of the multiplier U7 is: ； The multiplier U8 is used to realize the input voltage u and the voltage u at pin 8 of U3. 3-8 The voltage at the output terminal W of the multiplier U7 is: 。 2. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The first control chip in the integrated operational amplifier U1 adopts TL084, pin 1 is connected to pin 2 through resistor R2; pin 2 is connected to the memristor voltage u through resistor R1, pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 14 through resistor R6; pin 7 is connected to pin 6 through resistor R7; pin 8 is connected to pin 9 through resistor R9; pin 9 is connected to pin 7 through resistor R8; pin 10 is grounded; pin 12 is grounded; pin 13 is connected to pin 14 and multiplier U4 output -X1Y1 / 10 through resistor R3, resistor R4 and resistor R5 respectively. 4 , pin 1; pin 14 is connected to pin 13 through capacitor C1; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

3. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The second control chip in the integrated operational amplifier U2 adopts TL084, pin 1 is connected to pin 2 through capacitor C2; pin 2 is connected to pin 1 and the first control chip pin 1 output -u through resistors R10 and R11 respectively; pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 1 through resistor R12; pin 7 is connected to pin 6 through resistor R13; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

4. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The third control chip in the integrated operational amplifier U3 adopts TL084, and pin 6 is connected to the output X1 of the multiplier U5 through the resistor R14. 2 / 10 4 Pin 7 is connected to pin 6 through resistor R15; Pin 9 is connected to multiplier U6 output Y1 through resistor R16 2 / 10 4 Pin 8 is connected to pin 9 through resistor R17; Pin 2 is connected to multiplier U7 output -X2 through resistors R18 and R19 respectively 2 u / 10 4 and multiplier U8 output - Y2 2 u / 10 4 Also includes a resistor R21, pin 1 is connected to pin 2 and the memristor current i through resistors R20 and R21 respectively; pin 3 and pin 5 are grounded; pin 4 is connected to the power supply VCC; pin 11 is connected to the power supply VEE.

5. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U4 is controlled by an AD633 chip. Pin 1 of the multiplier U4 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 7 of the second control chip to output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; and pin 7 outputs -X1Y1 / 10. 4 .

6. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U5 is controlled by the AD633 chip. Pin 1 of the multiplier U5 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 8 of the first control chip to output X1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; and pin 7 outputs X1. 2 / 10 4 .

7. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U6 is controlled by the AD633 chip. Pin 1 of the multiplier U6 is connected to the pin 7 output of the second control chip -Y1; pin 3 is connected to the pin 7 output of the second control chip -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; and pin 7 output is Y1 2 / 10 4 .

8. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U7 is controlled by the AD633 chip, and the pin 1 of the multiplier U7 is connected to the pin 7 output of the third control chip -X2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -X2 2 u / 10 4 .

9. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U8 is controlled by an AD633 chip, and the pin 1 of the multiplier U8 is connected to the pin 8 output of the third control chip -Y2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -Y2 2 u / 10 4 .

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