Method, tool, computer device, medium and program for concurrent clock optimization and data optimization

Abstract

The present application relates to the technical field of electronic design automation, in particular to a concurrent clock optimization and data optimization method, tool, computer device, medium and program. The concurrent clock optimization and data optimization method comprises providing a clock optimizer and constructing a clock tree; obtaining an initial skew on the clock tree, and the clock optimizer performs balancing processing on the clock tree based on the initial skew, so that the clock tree obtains a useful skew; integrating the clock optimizer and a data optimizer to obtain a concurrent optimizer; using the concurrent optimizer to simultaneously perform data optimization on the balanced clock tree, and clock optimization on the balanced clock tree based on the useful skew. The existing optimization tool has poor efficiency for clock tree optimization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to a concurrent clock optimization and data optimization method, tool, computer device, medium and program. BACKGROUND

[0002] In the field of integrated circuits, clock tree optimization is an optimization based on the clock tree result after layout optimization. The existing clock tree optimization method usually has two kinds, clock path optimization and data path optimization. Clock tree synthesis is a key part connecting the layout stage and the routing stage, and the quality of the clock tree will greatly affect the timing convergence and power consumption of the entire design.

[0003] Generally, after layout optimization is completed, a zero-skew clock tree is first constructed, and the expected result quality is consistent with the result quality after layout optimization. After the clock tree is completed, the skew is not completely zero, and there is an influence of on-chip differences, so the timing result after the clock tree is constructed is often worse than after layout optimization, so the tool needs to optimize the data path according to the current clock skew.

[0004] For a register, its capture clock path is also the trigger clock path of the next level register, so sometimes the zero-skew clock tree is not necessarily the most friendly to timing convergence. Therefore, the clock skew that will help timing convergence is called useful skew. Using useful skew can reduce the complexity of data path optimization, effectively utilize design resources, avoid a large number of buffers introduced by data path optimization, and thus achieve the purpose of reducing power consumption.

[0005] The existing method is to separately perform clock path optimization and data path optimization, and the consideration in clock optimization is the optimization of clock delay and clock skew, and the direct influence of the change of the clock tree on timing convergence cannot be seen. Moreover, the optimization of the clock tree cannot consider on-chip differences, clock gating, clock pessimistic elimination and other information, and there is a large gap between the actual optimization target and the purpose optimization target. In many cases, the influence of optimization on timing convergence is unpredictable, causing the problem of poor optimization efficiency. SUMMARY

[0006] In order to solve the problem of poor optimization efficiency of the existing optimization tool for the clock tree, the present application provides a concurrent clock optimization and data optimization method, tool, computer device, medium and program.

[0007] The application provides a concurrent clock optimization and data optimization method, which comprises the following steps: providing a clock optimizer and constructing a clock tree; providing a concurrent optimizer; obtaining initial skew of each path on the clock tree, performing balance processing on the clock tree based on the initial skew, so that part of the clock tree paths obtain useful skew and part of the clock tree paths obtain zero skew; performing data optimization on the balanced clock tree by using the concurrent optimizer, and simultaneously performing clock optimization on the balanced clock tree based on the useful skew; or, performing data optimization on the balanced clock tree by using the concurrent optimizer, and simultaneously performing clock optimization on the balanced clock tree.

[0008] Preferably, the balance processing on the clock tree based on the initial skew comprises: providing a preset design condition, judging whether the constructed clock tree meets the preset design condition; if not, the clock optimizer directly performs balance processing on the clock tree based on the initial skew; if yes, performing data optimization on the clock tree by using the concurrent optimizer, providing a timing updater, obtaining an offset based on the initial skew by the timing updater combined with the concurrent optimizer after the data optimization, performing clock optimization on the clock tree based on the offset, and performing balance processing on the clock tree after the data optimization and the clock optimization.

[0009] Preferably, the balance processing on the clock tree after the data optimization and the clock optimization further comprises: obtaining initial delay variation of each node in the constructed clock tree; obtaining updated delay variation of each node in the clock tree based on the offset after the offset is obtained; and re-clustering each node in the constructed clock tree based on the updated delay variation.

[0010] Preferably, the obtaining of the offset by the timing updater combined with the concurrent optimizer after the data optimization comprises: obtaining worst slack of a fan-in path and worst slack of a fan-out path based on the timing updater after the data optimization; and obtaining the offset based on the worst slack of the fan-in path and the worst slack of the fan-out path; wherein the offset comprises effective skew of clock advance and effective skew of clock delay; the effective skew of the clock advance is calculated as:

[0011] Formula 1:

[0012] When d_slack<0, if q_slack>0, the effective skew is the smaller one of q_slack and negative d_slack, and if q_slack<0, the effective skew is (q_slack-d_slack) / 2;

[0013] The effective skew calculation of clock delay is: formula two: q_slack<0 is used, if d_slack>0, the effective skew is the smaller one of d_slack and negative q_slack, if d_slack<0, the effective skew is (d_slack-q_slack) / 2;

[0014] Wherein, d_slack in formula one and formula two is the worst timing slack of the fan-in path, and q_slack is the worst timing slack of the fan-out path.

[0015] Preferably, the concurrent optimizer comprises: providing a buffer, a register and a data optimizer, configuring an interface available for the register and the buffer to be connected in the data optimizer, the register being the start point and the end point of the timing path, and the buffer being the resource of the timing path available for optimization; and integrating the clock optimization function in the data optimizer.

[0016] Preferably, the integration of the clock optimization function in the data optimizer comprises: performing reverse traversal on the clock ports on the start point and end point registers to find the clock path; traversing the elements on the clock path, obtaining the load driven by the elements on the clock path and whether there is a timing poor end point in the driven load; judging whether the end point can be optimized; if yes, adjusting the clock path; updating the timing information of the clock path and the associated timing path by the timing updater to perceive the result of timing convergence after the optimization of the end point; judging whether to cancel the adjusting operation of the clock path based on the result of timing convergence; if yes, finding the next adjustable end point until the timing converges or the clock path traversal ends.

[0017] The present application provides another technical solution to solve the above technical problems, and the tool comprises:

[0018] The clock optimizer is used for constructing the clock tree and performing balancing processing on the clock tree;

[0019] The concurrent optimizer comprises a concurrent clock data optimizer and an optimization processor.

[0020] The concurrent clock data optimizer is used for performing data optimization on the balanced clock tree and scheduling the clock optimization of the balanced clock tree based on the useful skew.

[0021] The optimization processor is used for performing the operation of data optimization or clock optimization.

[0022] Preferably, the tool further comprises:

[0023] The library element processor is connected with the optimization processor and is used for processing the elements on the time path and the data path respectively and directly acting on the optimization processor.

[0024] Timing updater: used to update the result obtained after each optimization, used to determine whether the timing path converges and obtain the timing margin.

[0025] Offset converter: used to transmit the offset obtained by the concurrent clock data optimizer calculation.

[0026] To solve the above technical problems, the present application provides another technical solution as follows: a computer readable storage medium, wherein the computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the concurrent clock optimization and data optimization method according to the above.

[0027] To solve the above technical problems, the present application provides another technical solution as follows: a computer device applied to the concurrent clock optimization and data optimization method, comprising a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to realize the concurrent clock optimization and data optimization method.

[0028] To solve the above technical problems, the present application provides another technical solution as follows: a computer program product comprising a computer program or instructions, which, when executed by a processor, realizes the concurrent clock optimization and data optimization method.

[0029] Compared with the prior art, the concurrent clock optimization and data optimization method, tool, computer device, medium and program provided by the present application have the following beneficial effects:

[0030] 1. The concurrent clock optimization and data optimization method provided by the embodiment of the present application comprises the following steps: providing a clock optimizer and constructing a clock tree.

[0031] A concurrent optimizer is provided; the initial skew of each path on the clock tree is obtained, the clock tree is balanced based on the initial skew, part of the clock tree paths obtain useful skew, and the other part of the clock tree paths obtain zero skew; the data of the balanced clock tree is optimized using the concurrent optimizer, and the clock of the balanced clock tree is optimized based on the useful skew; or, the data of the balanced clock tree is optimized using the concurrent optimizer, and the clock of the balanced clock tree is optimized. In this embodiment, the clock optimization and data optimization are performed simultaneously by providing the concurrent optimizer, which greatly saves the optimization time of the clock tree, reduces the operation resources required in the optimization process, and further reduces the waste of resources in the optimization process by selectively optimizing different paths of the clock tree.

[0032] 2. The embodiment of the present application balances the clock tree based on the initial skew, and comprises the following steps: providing a preset design condition, judging whether the constructed clock tree meets the preset design condition; if not, a clock optimizer directly balances the clock tree based on the initial skew; if yes, using a concurrent optimizer to optimize data of the clock tree, providing a timing updater, the timing updater combines the concurrent optimizer to calculate an offset based on the initial skew after the data optimization, optimizing the clock based on the offset, and balancing the clock tree after the data optimization and the clock optimization. In the embodiment, two operation modes are set based on the preset design condition, so as to reasonably cope with different scenarios. In addition, in the limit mode, the data optimization is performed by the concurrent optimizer; the timing updater combines the initial skew to calculate the offset; after the clock optimization based on the offset, the balancing is performed. The embodiment solves the inefficiency problem caused by repeated adjustment of the clock tree on the zero skew clock tree.

[0033] 3. The embodiment of the present application further provides a concurrent clock optimization and data optimization tool, which has the same beneficial effects as the concurrent clock optimization and data optimization method, and details are not described herein.

[0034] 4. The embodiment of the present application further provides a computer readable storage medium, which has the same beneficial effects as the concurrent clock optimization and data optimization method, and details are not described herein.

[0035] 5. The embodiment of the present application further provides a computer device, which has the same beneficial effects as the concurrent clock optimization and data optimization method, and details are not described herein.

[0036] 6. The embodiment of the present application provides a computer program product, comprising a computer program or instructions, which are executed by a processor to realize the concurrent clock optimization and data optimization method. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 FIG. 1 is a flowchart of a concurrent clock optimization and data optimization method provided by a first embodiment of the present application.

[0038] Figure 2 FIG. 2 is a flowchart of integrating a clock optimization function into a data optimizer in the concurrent clock optimization and data optimization method provided by the first embodiment of the present application.

[0039] Figure 3 FIG. 3 is a structural diagram of a concurrent clock optimization and data optimization tool provided by a second embodiment of the present application.

[0040] Figure 4 FIG. 4 is a structural diagram of a computer readable storage medium provided by a third embodiment of the present application.

[0041] Figure 5 is a structural schematic diagram of a computer device provided by a fourth embodiment of the present application.

[0042] Figure 6 is a structural schematic diagram of a computer program product provided by a fifth embodiment of the present application. DETAILED DESCRIPTION

[0043] For the purpose of the present application, the technical solutions and advantages are more clear and obvious, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and do not limit the present application.

[0044] In the embodiments provided by the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0045] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0046] In various embodiments of the present application, it should be understood that the size of the serial number of the above processes does not mean the inevitable sequence of execution, and the execution sequence of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0047] The computer program product of the present application can be a computer program product that, when executed by one or more computer, causes the one or more computer to perform a method of the present application. The computer program product can be a storage medium or memory media storing the computer instructions, e.g., a floppy disk, a DVD, a CD, a USB drive, a ROM, a RAM, etc. The computer program product can be implemented as a downloadable software program transmitted over the Internet or over a network. The computer program product can be implemented as software that is stored in a memory and executed by a processor.

[0048] In the field of integrated circuits, clock tree optimization is a kind of optimization based on clock tree results after layout optimization. The existing clock tree optimization method usually has two kinds, clock path optimization and data path optimization. Clock tree synthesis is a key part of connecting the layout stage and the routing stage, and the quality of the clock tree will greatly affect the timing convergence and power consumption of the entire design.

[0049] Generally, after layout optimization is completed, a zero skew clock tree is first constructed, and the expected result quality is consistent with the result quality after layout optimization. After the clock tree is completed, the skew is generally not completely zero, and there is an influence of on-chip differences, so the timing result after the clock tree is constructed is often worse than after layout optimization, so the tool needs to optimize the data path according to the current clock skew.

[0050] For a register, its capture clock path is also the trigger clock path of the next stage register, so sometimes the zero skew clock tree is not necessarily the most friendly to timing convergence. Therefore, the clock skew that will help timing convergence is called useful skew. Using useful skew can reduce the complexity of data path optimization, effectively utilize design resources, avoid a large number of buffers introduced by data path optimization, and thus achieve the purpose of reducing power consumption.

[0051] The existing method is to separately perform clock path optimization and data path optimization. In clock optimization, clock delay and clock skew optimization are considered, and the direct influence of clock tree change on timing convergence cannot be seen. Moreover, the optimization of the clock tree cannot consider on-chip differences, clock gating, clock pessimism elimination and other information, and there is a large gap between the actual optimization target and the purpose optimization target. In many cases, the influence of the optimization on timing convergence is unpredictable, causing poor optimization efficiency.

[0052] For ease of understanding, first explain some definitions in clock tree optimization:

[0053] Clock path optimization: referred to as clock optimization, refers to the optimization of the path of the clock signal from the clock source to the clock input end of each register. The purpose is to reduce clock skew and delay, and ensure that the clock signal is synchronized to all registers.

[0054] Data path optimization: referred to as data optimization, refers to the optimization of the path of the data signal from the register output to the next stage register input. The purpose is to meet the timing constraints (such as setup time and hold time).

[0055] Trigger clock path: refers to the path of the clock signal from the clock source to the clock input end of the current register. The delay of this path affects when the register starts sampling data.

[0056] Capture clock path: refers to the path of the clock signal from the clock source to the clock input end of the next stage register. The difference between the delay of this path and the delay of the trigger clock path is called clock skew, which directly affects the result of timing check.

[0057] Data path: refers to the path of the data signal from the output end of the current register to the input end of the next stage register. Its delay needs to meet the requirements of setup time and hold time.

[0058] Timing setup time: refers to the shortest time that the data signal must remain stable before the active edge of the clock signal arrives. If the data path delay is too long, it may cause a setup time violation.

[0059] Clock period: refers to the length of time of one complete cycle of the clock signal, which determines the highest working frequency of the circuit. Timing constraints are usually based on the clock period.

[0060] On-chip difference: refers to the uncertainty of the actual delay of the same path on the same chip due to local differences in manufacturing process, temperature or voltage. Such differences will affect the accuracy of timing analysis.

[0061] Gated clock: A low power technique that controls the switching of the clock signal by a logic gate, providing the clock signal to a register only when needed, to reduce dynamic power consumption.

[0062] Clock Pessimism Removal (CPR): Refers to the removal of excessive pessimistic estimates due to on-chip differences in timing analysis. For example, the delay difference of the common clock path may be repeatedly calculated in the trigger and capture path, and CPR will eliminate this repeated pessimistic amount.

[0063] Setup Check: Used to verify whether the data signal can be stabilized to the next stage register before the clock capture edge. The formula is: trigger clock path delay + data path delay ≤ capture clock path delay + setup time + clock period.

[0064] Hold Check: Used to verify that the data signal will not change too early after the clock capture edge. The formula is: trigger clock path delay + data path delay ≥ capture clock path delay + hold time.

[0065] Skew: The difference between the timing delay of the capture clock path and the timing delay of the trigger clock path is called clock skew, which is in nanoseconds or picoseconds, and the skew directly affects the margin of setup time and hold time.

[0066] The impact of clock tree on timing convergence mainly manifests as follows: Usually, a timing path is divided into three parts: trigger clock path, capture clock path and data path. The difference between the timing delay of the capture clock path and the timing delay of the trigger clock path is called clock skew, which is in nanoseconds or picoseconds, and the skew directly affects the margin of setup time and hold time.

[0067] The existing optimization method of clock tree is to separately perform clock path optimization and data path optimization, which obviously does not take into account the impact of useful skew on optimization. In addition, separate clock path optimization and data path optimization not only causes structural redundancy and poor optimization effect, but also causes great waste of computing resources.

[0068] In order to solve the problem of poor optimization efficiency of the existing optimization tool for clock tree optimization, please refer toFigure 1 The first embodiment of the present application provides a concurrent clock optimization and data optimization method, which comprises the following steps:

[0069] S1, providing a clock optimizer and constructing a clock tree;

[0070] S2, providing a concurrent optimizer;

[0071] S3, obtaining an initial skew of each path on the clock tree, and performing a balancing process on the clock tree based on the initial skew, so that part of the clock tree paths obtain useful skew and the other part of the clock tree paths obtain zero skew;

[0072] S4, using the concurrent optimizer to perform data optimization on the balanced clock tree, and simultaneously performing clock optimization on the balanced clock tree based on the useful skew;

[0073] S5, or, using the concurrent optimizer to perform data optimization on the balanced clock tree, and simultaneously performing clock optimization on the balanced clock tree.

[0074] It can be understood that first, the embodiment adopts a conventional clock optimizer to construct a clock tree. It should be noted that the constructed clock tree has multiple paths, also known as timing paths, and the length and skew of each path in the constructed clock tree have randomness and uncertainty. Skew is a natural result of clock signal transmission, which cannot be directly adjusted, but can only be indirectly changed by optimizing the clock tree. Further, the clock tree is balanced, and during the balancing process, part of the paths obtain useful skew, and the other part of the paths obtain zero skew. It should be understood that balancing the clock tree is also a process of optimizing the clock tree, which can be performed using a conventional clock optimizer or a concurrent optimizer. In the embodiment, the part of the paths of the clock tree obtain useful skew during the balancing process, and then the influence of skew on part of the paths in the clock tree is reasonably utilized during subsequent optimization of the clock tree. It should be noted that the concurrent optimizer of the embodiment is different from the conventional clock optimizer and data optimizer, and its specific structure is that the function of clock optimization is integrated into the data optimizer, so that the data optimizer obtains part of the function of the clock optimizer. The concurrent optimizer does not need to separate the clock optimization and the data optimization as in the prior art. The concurrent optimizer in the embodiment can simultaneously perform clock optimization and data optimization, thereby greatly saving the optimization time and reducing the operation resources required in the optimization process.

[0075] Specifically, for the part of the paths obtaining useful skew, after the balancing processing, the concurrent optimizer will perform data optimization on the balanced clock tree, and at the same time, clock optimization on the balanced clock tree based on the useful skew. It should be understood that using the useful skew when performing clock optimization at the same time can reduce the complexity of data path optimization, effectively utilize design resources, avoid the introduction of a large number of buffers on the data path due to optimization, and thus achieve the purpose of reducing power consumption. For the other part of the paths obtaining zero skew, which are the timing paths that do not need useful skew to help convergence, the concurrent optimizer is directly used to simultaneously perform data optimization and clock optimization on the clock tree paths of this part.

[0076] It should be understood that in the embodiment, by providing the concurrent optimizer to simultaneously perform clock optimization and data optimization, the optimization time of the clock tree is greatly saved, and the calculation resources required in the optimization process are also reduced. In addition, the influence of the useful skew on the clock tree is considered, and the waste of resources in the optimization process is further reduced by selectively optimizing different paths of the clock tree.

[0077] Further, in the step S3, the balancing processing on the clock tree based on the initial skew comprises:

[0078] providing a preset design condition to determine whether the constructed clock tree meets the preset design condition;

[0079] If not, the clock optimizer directly performs balancing processing on the clock tree based on the initial skew;

[0080] If yes, the concurrent optimizer is used to perform data optimization on the clock tree, a timing updater is provided, the offset is obtained by the timing updater in combination with the concurrent optimizer based on the initial skew after the data optimization, the clock optimization is performed on the clock tree based on the offset, and the balancing processing is performed on the clock tree after the data optimization and the clock optimization.

[0081] It should be noted that in the step S3, the preset design condition can be freely defined according to the user's demand. For example, the preset design condition can be determined according to the design complexity of the clock tree. For example, if the design of the constructed clock tree is complex, it is automatically determined that the constructed clock tree meets the preset design condition. If the design of the constructed clock tree is simple, it is automatically determined that the constructed clock tree does not meet the preset design condition. The design complexity of the clock tree can be determined according to the design process node, the design size and the register size, which will not be described in detail.

[0082] It should be understood that whether the constructed clock tree meets the preset design condition can be regarded as two modes in clock tree optimization. One is a simple mode: for example, the clock tree is relatively simple and does not meet the preset design condition, and the existing clock optimizer can be directly used to balance the clock tree. The operation is simple. The clock optimizer in this mode needs to perform two-step operations. The first step is to balance the clock tree. Because the paths of the initially constructed clock tree are long or short, if the clock tree is not balanced and directly optimized, the subsequent optimization workflow will be more complex. Therefore, the simplest method is to make the length of each path of the clock tree about the same. This step is called balancing. However, after balancing, all paths of the clock tree will have about the same length. If the subsequent optimization is directly performed, all paths of the clock tree will be in a zero skew state, which will cause waste of computing resources. Therefore, the clock optimizer in the simple mode needs to perform a second-step operation. The purpose of the second-step operation is to readjust part of the balanced clock tree paths to obtain useful skew, that is, to make part of the paths longer and part of the paths shorter, so as to obtain useful skew again and facilitate the subsequent optimization work. However, this balancing of the clock tree to make the clock tree balanced and then making part of the clock tree shorter based on useful skew is a quite inefficient processing method. If a slightly more complex clock tree is to be dealt with, this method will waste a lot of time. Therefore, the other mode of the two modes is an extreme mode: in the extreme mode, the existing clock optimizer is not used for balancing, but a timing updater is provided. The timing updater is used to update the optimization result obtained each time the optimization is completed, and can also be used to judge whether the timing path converges and obtain the timing margin. Specifically, the concurrent optimizer can be used to perform data optimization on the clock tree. After data optimization, the timing margin can be obtained based on the timing updater. Then, the timing margin and the initial skew of the clock tree path can be used to calculate the offset. It should be noted that the offset is a design parameter, which is used to realize useful skew, that is, the clock tree is optimized by the offset to balance the clock tree after data optimization and clock optimization. It should be understood that in the extreme mode, the calculation of the offset is a calculation process and does not involve operation on the clock tree. The clock optimization based on the offset involves operation on the clock tree. That is, the extreme mode is different from the simple mode. Only one operation is performed, and the paths of part of the clock tree will directly obtain useful skew after balancing. Unlike the simple mode, the paths are first balanced and then made longer or shorter.

[0083] It can be understood that two operation modes are set based on preset design conditions in the embodiment, which reasonably cope with different scenarios. In addition, in the extreme mode, data optimization is performed by the concurrent optimizer; the timing updater calculates the offset in combination with the initial skew; after clock optimization based on the offset, balance processing is performed. The inefficiency problem caused by repeated adjustment of the clock tree on the zero skew clock tree is solved. In addition, the user can also design a button to start the simple mode or the extreme mode, so as to facilitate the user to switch between the two modes.

[0084] Further, before the balance processing of the clock tree after data optimization and clock optimization, it further includes:

[0085] Obtaining the initial delay variation of each node in the constructed clock tree;

[0086] After obtaining the offset, obtaining the updated delay variation of each node in the clock tree based on the offset;

[0087] Based on the updated delay variation, re-clustering each node in the constructed clock tree.

[0088] It should be understood that after adjusting the clock path based on the offset, the delay distribution of each node in the clock tree changes non-uniformly: for example, part of the nodes are shortened due to positive offset requirements; part of the nodes are lengthened due to negative offset requirements. If the original delay of the unadjusted node is maintained, direct clock tree balancing will cause

[0089] Nodes with large delay differences will be forced to be clustered and grouped, which will increase power consumption and computing resources.

[0090] Therefore, by obtaining the updated delay variation of each node in the clock tree, the nodes of the clock tree are re-clustered. Specifically, nodes with similar updated delay values are grouped into the same cluster, for example, 80-85ps is the first group, and 95-105ps is the second group. In this way, the grouping mode of the original physical position or logical level is replaced. The difficulty of clock tree balancing can be reduced, and the power consumption in the balancing process can be reduced.

[0091] Further, in step S4, the data optimization and the timing updater in combination with the concurrent optimizer based on the initial skew to obtain the offset include:

[0092] After data optimization, obtaining the worst timing margin of the fan-in path and the worst timing margin of the fan-out path based on the timing updater;

[0093] Obtaining the offset based on the worst timing margin of the fan-in path and the worst timing margin of the fan-out path;

[0094] The offset includes the effective skew of clock advance and the effective skew of clock delay;

[0095] The effective skew calculation of clock advance is:

[0096] Formula one:

[0097] When d_slack<0, if q_slack>0, the effective skew is the smaller one of q_slack and negative d_slack, if q_slack<0, the effective skew is (q_slack-d_slack) / 2;

[0098] The effective skew calculation of clock delay is: Formula two: q_slack<0 is used, if d_slack>0, the effective skew is the smaller one of d_slack and negative q_slack, if d_slack<0, the effective skew is (d_slack-q_slack) / 2;

[0099] In formula one and formula two, d_slack is the worst slack of the fan-in path, and q_slack is the worst slack of the fan-out path.

[0100] It should be understood that the embodiment converts the pessimistic quantity elimination into a skew redistribution problem under mathematical constraints, and dynamically calculates the offset by using the worst slack of the real-time fan-in path and the worst slack of the fan-out path of the fan-in / fan-out path.

[0101] Further, please refer to Figure 1 , which provides a concurrent optimizer including:

[0102] A buffer, a register and a data optimizer are provided, an interface is configured in the data optimizer for the register and the buffer to be connected, the register is the start point and the end point of the timing path, and the buffer is the resource of the timing path which can be optimized;

[0103] The clock optimization function is integrated in the data optimizer.

[0104] It should be understood that the traditional clock optimization and data optimization based on effective skew, the data optimizer and the clock optimizer are separate, when the clock optimization is selected, the clock path is considered, the optimization of clock delay and clock skew, and the change of the clock tree cannot be directly affected for timing convergence, and the optimization of the clock tree cannot consider the on-chip difference, the gated clock, the clock pessimistic elimination and other timing convergence related information, which leads to a large gap between the actual optimization target and the purpose optimization target. The data optimization is considered for timing margin, and the worst timing path is optimized, which can directly see the effect of optimization on timing convergence. The concurrent clock data optimizer of the embodiment is a program module, which is responsible for the scheduling of the data optimizer and the scheduling of the timing updater. By selecting the worst timing path, finding the optimization element, performing the optimization operation, and updating the timing, the purpose of timing convergence is achieved. Registers and buffers are program processing elements in electronic design. Registers are the starting point and the end point of the timing path, and buffers are elements that can be processed by the program to add optimized timing paths in the design. Registers are generally fixed before the design front end, and their data paths are implemented by various combinational logic elements to achieve complex functions. Buffers do not change the state of the signal and can be inserted by the program.

[0105] In particular, further in combination with Figure 2 Integrating the clock optimization function into the data optimizer includes:

[0106] s221, performing reverse traversal on the clock port of the starting and ending register to find the clock path;

[0107] s222, traversing the elements on the clock path to obtain the load driven by the elements and whether there will be a poor timing end point in the driven load through the clock path;

[0108] s223, judging whether the end point can be optimized;

[0109] s224, if yes, adjusting the clock path;

[0110] s225, updating the clock path and the timing information of the associated timing path through the timing updater to perceive the timing convergence result after the end point optimization;

[0111] s226, judging whether to cancel the adjusting operation of the clock path based on the timing convergence result;

[0112] s227, if yes, finding the next adjustable end point until the timing converges or the clock path traversal ends.

[0113] It should be understood that a common data optimizer selects a timing slack negative timing path endpoint, which is usually a data port of a register, obtains the worst data path from the port, and then optimizes the data path. The concurrent clock data optimizer of the embodiment integrates the clock optimization part into the data optimizer, which optimizes the timing poor path after the path optimization, finds the clock path by traversing the clock ports of the start and end registers in reverse, traverses the elements of the clock path, and determines whether the endpoint can be optimized by the load driven by the current element of the clock path and whether the load driven by the current element of the clock path will have a timing poor endpoint. If it can be optimized, the clock optimization will call the optimization processing module to adjust the clock path by inserting buffers and replacing elements on the clock path. After the clock path is adjusted, the timing information of the clock path and the associated timing path can be updated by the timing update module, and the effect of the clock optimization on the timing convergence can be directly perceived to obtain the timing convergence result. If the endpoint modification results in timing deterioration, the step is cancelled, and the next executable endpoint position is found until the timing converges or the clock path traversal ends. It should be understood that the concurrent clock path optimization provided in the embodiment can more accurately optimize the clock path, and the next round of optimization can directly perceive the change of the timing convergence result, and can obtain better optimization effect than the separate data optimization and clock optimization in the prior art.

[0114] To show the effect of the concurrent clock optimization and data optimization method in the embodiment, the following is the experimental data in the first embodiment:

[0115] Experiment 1: The test case set in Table 1 was tested by using the method without using concurrent clock data optimization, using the concurrent clock data optimization method, and using the concurrent clock data optimization method based on offset.

[0116] Table 1: Test case set:

[0117]

[0118] Table 2: Test results

[0119]

[0120] Table 1 is a test case set, and Table 2 is a test result of the test case set in Table 1 under three methods in the first experimental example. In Table 2, the worst negative slack (WNS) is the most serious timing violation value in all timing paths. The total negative slack (TNS) is the sum of negative slacks of all paths that violate timing constraints (paths with negative slack). It should be noted that the concurrent clock data optimization corresponds to the simple mode in the first embodiment, and the concurrent clock data optimization based on offset corresponds to the extreme mode in the first embodiment. It can be seen that, compared with the conventional data optimization using effective skew, both the simple mode and the extreme mode have great optimization in terms of timing convergence degree and running time. Specifically, the simple mode can achieve good optimization effect and has very short running time. Although the running time of the extreme mode is increased, it is still faster than the conventional mode, and is mainly used to cope with complex design scenarios.

[0121] Please refer to Figure 1 and Figure 3 , the second embodiment of the present application further provides a concurrent clock optimization and data optimization tool, which applies the concurrent clock optimization and data optimization method described above, and the tool comprises:

[0122] a clock optimizer, which is used to construct a clock tree and balance the clock tree;

[0123] a concurrent optimizer, which comprises a concurrent clock data optimizer and an optimization processor;

[0124] the concurrent clock data optimizer, which is used to perform data optimization on the balanced clock tree and perform clock optimization on the balanced clock tree based on useful skew for scheduling;

[0125] the optimization processor, which is used to perform data optimization or clock optimization operation.

[0126] It can be understood that the tool provided in the embodiment greatly saves the optimization time of the clock tree, reduces the operation resources required by the optimization process, and further reduces the waste of resources in the optimization process by considering the influence of the useful skew on the clock tree and selectively optimizing different paths of the clock tree. The concurrent clock data optimizer and the clock optimizer both serve as a scheduler. Specifically, the concurrent clock data optimizer can coordinate the data path optimization and the clock path optimization in real time, such as concurrent optimization based on skew or concurrent optimization based on offset. It should be noted that the clock optimization using offset and the clock optimization using effective skew can both complete the joint optimization of the clock path and the data path, and the main difference is in the clock path optimization part. The optimization processor serves as an executor and performs the optimization operation.

[0127] Further, the tool further comprises:

[0128] The library element processor is connected with the optimization processor and is used for processing the elements on the time path and the data path respectively and directly acting on the optimization processor. It should be understood that the optimization processor can selectively call the clock / data path elements in the library element processor. For example, if the clock path only uses low-power buffers, the clock path elements can be preferentially called.

[0129] The offset converter is used for transmitting the offset obtained by the concurrent clock data optimizer. Specifically, the offset converter is used for transmitting the offset obtained by the concurrent clock data optimizer to other modules after the offset is calculated.

[0130] The timing updater is used for updating the obtained optimization result after each optimization is completed, and is used for judging whether the timing path converges and obtaining the timing margin. It should be understood that the timing updater can update the data path timing and the clock path timing. The data path timing update has the characteristics of large update range and slow speed. The clock path update has the characteristics of small update range and fast speed.

[0131] Please refer to Figure 1 and Figure 4 The third embodiment of the present application further provides a computer readable storage medium, wherein the computer readable storage medium stores computer instructions, and the computer instructions are used for making the computer execute the concurrent clock optimization and data optimization method.

[0132] The computer readable storage medium provided by the embodiment of the present application has the same beneficial effects as the concurrent clock optimization and data optimization method, which will not be described here.

[0133] Please refer to Figure 1 and Figure 5The fourth embodiment of the present embodiment also provides a computer device applied to the concurrent clock optimization and data optimization method, which comprises a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to realize the concurrent clock optimization and data optimization method.

[0134] The computer device provided by the embodiments of the present application has the same beneficial effects as the concurrent clock optimization and data optimization method, which will not be repeated here.

[0135] Please refer to Figure 1 and Figure 6 The fifth embodiment of the present embodiment also provides a computer program product comprising a computer program or instructions, which is executed by the processor to realize the concurrent clock optimization and data optimization method.

[0136] The computer program product provided by the embodiments of the present application has the same beneficial effects as the concurrent clock optimization and data optimization method, which will not be repeated here.

[0137] The concurrent clock optimization and data optimization method, tool, computer device, medium and program disclosed by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above embodiment is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description should not be understood as a limitation of the present application. Any modification, equivalent replacement and improvement within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A method of concurrent clock optimization and data optimization, characterized by: The method comprises the following steps: providing a clock optimizer and constructing a clock tree; providing a concurrent optimizer; obtaining initial skew of each path on the clock tree, providing preset design conditions, and judging whether the constructed clock tree meets the preset design conditions; if not, the clock optimizer directly balances the clock tree based on the initial skew; if yes, the concurrent optimizer is used to optimize data of the clock tree, a timing updater is provided, the data is optimized, the timing updater combines the concurrent optimizer to calculate an offset based on the initial skew, the clock is optimized based on the offset, and the balanced clock tree after data optimization and clock optimization is balanced; part of the clock tree paths obtains useful skew, and the other part of the clock tree paths obtains zero skew; the data of the balanced clock tree is optimized by using the concurrent optimizer, and the clock of the balanced clock tree is optimized based on the useful skew; or, the data of the balanced clock tree is optimized by using the concurrent optimizer, and the clock of the balanced clock tree is optimized.

2. The method for concurrent clock optimization and data optimization of claim 1, wherein: Before the balanced clock tree after data optimization and clock optimization is balanced, the following steps are further included: obtaining initial delay variation of each node in the constructed clock tree; after the offset is calculated, obtaining updated delay variation of each node in the clock tree based on the offset; re-clustering each node in the constructed clock tree based on the updated delay variation.

3. The method for concurrent clock optimization and data optimization of claim 1, wherein: The data-optimized timing updater combines the concurrent optimizer to calculate the offset based on the initial skew, which comprises the following steps: after data optimization, obtaining worst slack of fan-in paths and worst slack of fan-out paths based on the timing updater; obtaining the offset based on the worst slack of fan-in paths and the worst slack of fan-out paths; wherein the offset comprises effective skew of clock advance and effective skew of clock delay; the effective skew of clock advance is calculated as: Formula One: when d_slack<0, if q_slack>0, the effective skew is the smaller one of q_slack and negative d_slack, and if q_slack<0, the effective skew is (q_slack-d_slack) / 2; the effective skew of clock delay is calculated as: Formula Two: q_slack<0 is used, if d_slack>0, the effective skew is the smaller one of d_slack and negative q_slack, and if d_slack<0, the effective skew is (d_slack-q_slack) / 2; wherein d_slack in Formula One and Formula Two is the worst slack of fan-in paths, and q_slack is the worst slack of fan-out paths.

4. The method for concurrent clock optimization and data optimization of claim 1, wherein: The concurrent optimizer is provided, which comprises the following steps: providing a buffer, a register and a data optimizer, configuring an interface in the data optimizer for connection of the register and the buffer, the register being a starting point and an ending point of a timing path, and the buffer being a resource of an optimizable timing path; the clock optimization function is integrated in the data optimizer.

5. The method for concurrent clock optimization and data optimization of claim 4, wherein: The clock optimization function is integrated in the data optimizer, which comprises the following steps: performing reverse traversal on clock ports on the starting point and the ending point register to find a clock path; traversing elements on the clock path, obtaining the load driven by the elements on the clock path and whether there is a terminal point with poor timing in the driven load; determining whether the terminal point can be optimized; if yes, adjusting the clock path; updating the timing information of the clock path and the associated timing path by the timing updater to perceive the result of timing convergence after the terminal point is optimized; determining whether to cancel the operation of adjusting the clock path based on the result of timing convergence; if yes, finding the next adjustable terminal point until timing convergence or the end of the clock path traversal.

6. A concurrent clock optimization and data optimization tool applying the method of concurrent clock optimization and data optimization of any of claims 1-5, characterized in that: The tool comprises: a clock optimizer for constructing a clock tree and performing balancing processing on the clock tree; a concurrent optimizer comprising a concurrent clock data optimizer and an optimization processor; the concurrent clock data optimizer is configured to perform data optimization on the balanced clock tree and schedule clock optimization on the balanced clock tree based on useful skew; the optimization processor is configured to perform the operation of data optimization or clock optimization.

7. The concurrent clock optimization and data optimization tool of claim 6, characterized in that the tool further comprises: a library element processor connected to the optimization processor and configured to process the elements on the time path and the data path respectively and directly act on the optimization processor; a timing updater configured to update the obtained optimization result after each optimization is completed, determine whether the timing path converges and obtain timing slack; a skew converter configured to transmit the skew calculated by the concurrent clock data optimizer.

8. A computer-readable storage medium, characterized in that: The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the concurrent clock optimization and data optimization method according to any one of claims 1-5.

9. A computer device for concurrently clock optimization and data optimization according to any one of claims 1-5. The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the concurrent clock optimization and data optimization method according to any one of claims 1-5.

10. A computer program product, characterised in that: The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the concurrent clock optimization and data optimization method according to any one of claims 1-5.

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