Power-on response and instruction processing method and device, equipment and storage medium

Abstract

The embodiment of the invention relates to a power-on response and instruction processing method and device, equipment and a storage medium, and the method comprises the steps: responding to a reset signal transmitted by card reading equipment under the condition that a safety chip obtains the power provided by the card reading equipment, initializing an eSIM hardware interface, and transmitting a receiving response signal to the card reading equipment through the eSIM hardware interface, the receiving response signal is used for representing that the reset signal is received; scanning and identifying valid data based on the context information, and storing the valid data in a memory; dirty page marking is conducted on the memory, and dirty pages are cleared away in the garbage collection process and / or cleared away in the process of responding to the contact type instruction; and sending the ATR to the card reading equipment. According to the embodiment of the invention, the speed of responding to the reset signal can be improved, and power failure recovery and the response speed of the first instruction can be taken into account.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of security chip technology, and more particularly to a power-on response and instruction processing method, apparatus, device, and storage medium. Background Art

[0002] Currently, security chips usually do not have a power supply and are powered by the card reader during communication. Therefore, the security chip needs to perform power-off recovery after powering on to restore the state before power off. In addition, the security chip needs to return a feedback signal to the card reader after receiving the reset signal sent by the card reader.

[0003] Both power-off recovery and responding to reset signals have high time requirements. Responding to reset signals, in particular, generally requires the security chip to respond within 4ms. However, in reality, the security chip takes 12 to 800ms to recover from a power-off after powering on, far exceeding the 4ms requirement of the card reader. Therefore, the current mainstream solution is to postpone power-off recovery after receiving the first command after powering on. While this approach allows for a fast response to reset signals, it slows down the response to the first command. Therefore, a solution that can quickly respond to reset signals while also ensuring both fast power-off recovery and a fast response to the first command is urgently needed. Summary of the Invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the embodiments of the present disclosure provide a power-on response and instruction processing method, apparatus, device and storage medium.

[0005] A first aspect of an embodiment of the present disclosure provides a power-on response and instruction processing method, which is applied to a security chip, the security chip including an eSIM hardware interface, wherein the method includes:

[0006] When the security chip obtains power provided by the card reader device, in response to a reset signal sent by the card reader device, initializing the eSIM hardware interface, and sending a reception response signal to the card reader device through the eSIM hardware interface, wherein the reception response signal is used to indicate that the reset signal has been received;

[0007] Scan and identify valid data based on context information, and store the valid data in a memory;

[0008] Marking dirty pages of the memory, wherein the dirty pages are cleared during garbage collection and / or in response to contact instructions;

[0009] Sending the ATR to the card reader.

[0010] A second aspect of an embodiment of the present disclosure provides a power-on response and instruction processing device, which is applied to a security chip, wherein the security chip includes an eSIM hardware interface, wherein the device includes:

[0011] a first sending module, configured to, when the security chip obtains power provided by the card reader device, initialize the eSIM hardware interface in response to a reset signal sent by the card reader device, and send a reception response signal to the card reader device through the eSIM hardware interface, wherein the reception response signal is used to indicate that the reset signal has been received;

[0012] A scanning and rolling back module, configured to scan and identify valid data based on context information, and store the valid data in a memory;

[0013] a dirty page marking module, configured to mark dirty pages of the memory, wherein the dirty pages are cleared during garbage collection and / or in response to contact instructions;

[0014] The second sending module is used to send the ATR to the card reading device.

[0015] A third aspect of an embodiment of the present disclosure provides an electronic device, comprising: a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the method of the first aspect above.

[0016] A fourth aspect of an embodiment of the present disclosure provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of the first aspect described above can be implemented.

[0017] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0018] In an embodiment of the present disclosure, when a security chip receives power from a card reader, it can, in response to a reset signal sent by the card reader, initialize an eSIM hardware interface and send a receive response signal to the card reader via the eSIM hardware interface, wherein the receive response signal indicates receipt of the reset signal; scan and identify valid data based on context information and store the valid data in memory; mark dirty pages in the memory, wherein the dirty pages are cleared during garbage collection and / or in response to contact commands; and send an automatic time-record (ATR) to the card reader. By adopting the above technical solution, after the security chip is powered on, it can first send a receive response signal back to the card reader via the eSIM hardware interface, thereby achieving a rapid response to the reset signal. Furthermore, after returning the receive response signal to the card reader, it can first perform power-on scanning and dirty page marking, but not immediately clear the dirty pages. Instead, it can place the dirty page clearing during garbage collection and / or in response to contact commands. This means that unlike related technologies, the entire power-off recovery process is not placed in the response to the first command, thereby achieving both power-off recovery and a rapid response to the first command. It can be seen that the embodiment of the present disclosure can not only improve the speed of responding to the reset signal, but also take into account the power-off recovery and the response speed of the first instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 This is a flow chart of a power-on response and instruction processing method provided by an embodiment of the present disclosure;

[0022] Figure 2 This is a flowchart of an example of power-on response and instruction processing provided by an embodiment of the present disclosure;

[0023] Figure 3 This is a flowchart of power-on initialization provided by an embodiment of the present disclosure;

[0024] Figure 4 This is a flowchart of power-on scanning and marking dirty pages provided by an embodiment of the present disclosure;

[0025] Figure 5 This is a flowchart of clearing dirty pages provided by an embodiment of the present disclosure;

[0026] Figure 6 This is a flow chart of executing a contactless instruction provided by an embodiment of the present disclosure;

[0027] Figure 7 1 is a structural diagram of a power-on response and instruction processing device provided by an embodiment of the present disclosure;

[0028] Figure 8 It is a structural diagram of an electronic device in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0031] Currently, security chips usually do not have a power supply and are powered by the card reader during communication. Therefore, the security chip needs to perform power-off recovery after powering on to restore the state before power off. In addition, the security chip needs to return a feedback signal to the card reader after receiving the reset signal sent by the card reader.

[0032] Both power-off recovery and responding to reset signals have high time requirements. Responding to a reset signal generally requires the security chip to respond within 4ms. However, in reality, this recovery time after power-on is often longer, especially with the increasing integration of chips, such as the trend toward integrating the embedded Secure Element (eSE) and embedded Subscriber Identity (eSIM) into the same security chip. The more functions a security chip integrates, the more data must be recovered after power-on, and the longer the power-off recovery time. For example, a security chip integrating both an eSE and an eSIM can take anywhere from 12 to 800ms to recover after power-on, far exceeding the 4ms required by the card reader. Therefore, the current mainstream solution is to delay power-off recovery after receiving the first command after power-on, performing it during the processing of the first command. While this approach allows for a fast response to the reset signal, it also results in a slower response to the first command. Therefore, there is an urgent need for a solution that can quickly respond to reset signals while also balancing power-off recovery and a fast response to the first command. At the same time, as a security chip integrating eSE and eSIM, it also needs to be compatible with concurrent services with performance requirements, such as contactless card swiping (that is, the process of using contactless technology for payment or identity authentication, which utilizes near-field communication (NFC) or other wireless communication technologies to achieve it). The contactless instructions in the contactless card swiping process (such as read and write instructions, etc.) have high performance requirements. When the card reader sends a write instruction, it is generally required that the security chip can execute it successfully and respond with the 0x9000 status word within 4 to 5ms. However, the erasing and writing of the flash already takes nearly 4ms. Although the ordinary write cache method can respond to the 0x9000 status word within 1ms, there is a risk of data loss due to power failure. If the power fails in the middle, the final erasing and writing will take even longer. Therefore, a more reasonable and fast writing mechanism that supports power failure is urgently needed.

[0033] Figure 1 This is a flow chart of a power-on response and instruction processing method provided by an embodiment of the present disclosure, which can be executed by a security chip. The security chip can be exemplarily understood as a security chip that only includes an eSIM, or a security chip that integrates eSE and eSIM. The security chip includes an eSIM hardware interface, wherein the eSIM hardware interface is the communication interface used by the eSIM. Figure 1 As shown, the method provided in this embodiment includes the following steps:

[0034] S110. When the security chip obtains power provided by the card reader device, in response to a reset signal sent by the card reader device, the security chip initializes the eSIM hardware interface and sends a receive response signal to the card reader device through the eSIM hardware interface, where the receive response signal is used to indicate that the reset signal has been received.

[0035] In an embodiment of the present disclosure, a card reader device provides power to the security chip. Once the security chip receives power, the card reader device sends a reset signal (i.e., rst_requst) to the security chip. The reset signal notifies the security chip that a reset operation is required to prepare for normal operation. This reset operation prepares the security chip for communication with the card reader device and provides the necessary information for the card reader device to understand how to effectively interact with the security chip. In response to receiving the reset signal, the security chip first initializes the eSIM hardware interface. Of course, if the security chip also integrates an eSE, the eSE hardware interface (i.e., the communication interface used by the eSE) can also be initialized. It then sends a receive response signal to the card reader device via the eSIM hardware interface. The receive response signal serves as a feedback signal to the reset signal, notifying the card reader device that the reset signal has been successfully received and the reset operation has begun, preventing the card reader device from assuming a response timeout after a prolonged period of no feedback signal. In this embodiment, sending a receive response signal to the card reader device via the eSIM hardware interface immediately after the eSIM hardware interface is initialized allows for a faster response to the reset signal.

[0036] Specifically, the eSIM hardware interface may include a 7816 hardware interface, etc., but is not limited thereto.

[0037] Specifically, the reception response signal may include 0x3b, but is not limited thereto.

[0038] For example, after testing, after the security chip integrating eSE and eSIM is powered on, after receiving the reset signal sent by the card reader device, the 7816 hardware interface is initialized, and the 7816 hardware interface outputs 0x3b, which is completed within 1ms, meeting the card reader device's requirement to respond to the reset signal within 4ms.

[0039] S120 . Scan and identify valid data based on the context information, and store the valid data in a memory.

[0040] In the embodiment of the present disclosure, in order to prepare for communication with the card reader device, the security chip needs to perform power-off recovery, wherein the power-off recovery usually includes power-on scanning and data rollback (including marking dirty pages and clearing dirty pages). Considering that clearing dirty pages has little or even no effect on "the security chip is ready to communicate with the card reader device", the embodiment of the present disclosure first performs power-on scanning and dirty page marking, but does not clear the dirty pages immediately. Instead, the dirty page clearing is placed in the garbage collection process and / or the process of responding to contact instructions. That is, unlike the related art, the entire power-off recovery is not placed in the process of responding to the first instruction, thereby achieving the purpose of taking into account both power-off recovery and fast response to the first instruction.

[0041] Specifically, valid data refers to data that is logically meaningful to users or applications.

[0042] Specifically, the memory may include Flash, etc., but is not limited thereto.

[0043] Optionally, for a security chip integrating eSE and eSIM, the context information includes eSE context information for eSE and eSIM context information for eSIM. In this case, S120 includes: S121, scanning and identifying eSE valid data based on the eSE context information, and storing the eSE valid data in an eSE area used by the eSE in the memory; S122, scanning and identifying eSIM valid data based on the eSIM context information, and storing the eSIM valid data in an eSIM area used by the eSIM in the memory, wherein the eSE area and the eSIM area are isolated from each other. For a security chip integrating only an eSIM, S120 includes S122.

[0044] S130: Mark dirty pages in the memory, wherein the dirty pages are cleared during garbage collection and / or in response to contact instructions.

[0045] Optionally, marking dirty pages of the memory includes: for each storage page in the memory, if the storage page is a valid page, adding the storage page to a context mapping table; if the storage page is an invalid page, adding the storage page to a dirty page table.

[0046] Specifically, a valid page refers to a storage page containing valid data that is currently being used or may be used in the future. In other words, a valid page refers to a storage unit that stores data that is considered useful and correct by an application or system.

[0047] Specifically, an invalid page refers to a storage page that is considered invalid, unavailable, or has been marked as deleted. In other words, a valid page refers to a storage unit that is no longer considered valid due to some reason (such as data corruption, logical error, deletion, etc.).

[0048] Specifically, the context mapping table records a table of all valid pages and their locations, helping the system to quickly locate the required data.

[0049] Specifically, the dirty page table is used to efficiently record which storage pages are dirty, facilitating subsequent cleanup operations. Marked dirty pages are locked and cannot be accessed or modified by users. Dirty pages are considered free pages in space statistics and can be written to but not read from.

[0050] Further optionally, for a security chip that integrates both eSE and eSIM, S130 includes: S131. For an eSE storage page in the eSE area, if the eSE storage page is a valid page, adding the eSE storage page to the eSE context mapping table; if the eSE storage page is an invalid page, adding the eSE storage page to the eSE dirty page table; S132. For an eSIM storage page in the eSIM area, if the eSIM storage page is a valid page, adding the eSIM storage page to the eSIM context mapping table; if the eSIM storage page is an invalid page, adding the eSIM storage page to the eSIM dirty page table. For a security chip that integrates only an eSIM, S130 includes S132.

[0051] Specifically, the instructions received by the security chip include contact instructions and contactless instructions, wherein the contact instructions refer to instructions for exchanging data with the security chip through a physical connection, and the contactless instructions refer to instructions for exchanging data with the security chip through NFC.

[0052] In some embodiments, the process of clearing dirty pages includes: clearing all dirty pages during garbage collection. Optionally, the triggering condition for garbage collection includes at least one of the following: the current available space of the memory is less than a preset threshold, and the time since the last garbage collection reaches a preset time.

[0053] Specifically, the specific values ​​of the preset threshold and the preset time duration can be set by those skilled in the art according to actual conditions and are not limited here.

[0054] In yet other embodiments, the process of clearing dirty pages includes: clearing a preset number of dirty pages in response to a contact instruction. Further optionally, clearing a preset number of dirty pages in response to a contact instruction includes: clearing a preset number of dirty pages in response to a "contact unexpected non-urgent instruction," wherein the contact unexpected non-urgent instruction refers to a contact instruction that does not immediately affect the core functions of the system and can be delayed without affecting the user experience, such as some background maintenance tasks, logging, status checks, etc.

[0055] Specifically, the specific value of the preset number of pages can be set by those skilled in the art according to actual conditions and is not limited here.

[0056] For example, after receiving each contact instruction, the security chip erases a dirty page. If garbage collection occurs during the service process, all dirty pages are cleared in the garbage collection service.

[0057] S140: Send ATR to the card reader.

[0058] Specifically, ATR stands for Answer To Reset. ATR contains some basic information about the security chip, such as the supported protocol types, maximum clock frequency, programming voltage, etc., to help the card reader understand how to communicate effectively with the card reader.

[0059] It is understandable that the time required for a security chip to recover from a power failure after powering on is usually longer, especially for security chips that integrate eSE and eSIM. Because they are dual systems, the power-on process needs to process more data than a single system, and the time required for power failure recovery is also longer. The length of the power failure recovery time is related to the state before the power failure. If the transaction before the power failure is relatively long but not completed, the rollback time will be longer, and vice versa. For security chips that integrate eSE and eSIM, the shortest power failure recovery time is at the level of 15ms. When a card reader device accesses the service after powering on, a quick response is required after receiving the reset signal of the card reader device, and the response needs to be completed within 4 to 8ms. In view of this, the embodiment of the present disclosure uses hardware means to quickly initialize the hardware interface. After receiving the reset signal of the card reader device, 0x3B is first sent through the eSIM hardware interface. After testing, the security chip can send 0x3B within 1.5ms. After 0x3B is sent out through the eSIM hardware interface, power-on scanning and data rollback are performed, and the embodiment of the present disclosure optimizes data rollback by first marking dirty pages and then gradually erasing dirty pages instead of clearing all dirty pages immediately. After completing a series of power-on scans, marking dirty pages and replying to ATR, dirty pages are gradually cleared and released in subsequent services. After testing, the technical solution provided by the implementation of the present disclosure can respond to ATR within 3ms after receiving the reset signal at power-on. For related technologies, placing dirty page marking and dirty page clearing in the first instruction will cause the response of the instruction to be particularly slow, while the embodiment of the present disclosure spreads the time for clearing dirty pages to the idle time, which can improve the response speed of the first instruction.

[0060] The disclosed embodiment can, after the security chip is powered on, first feed back a reception response signal to the card reader through the eSIM hardware interface, thereby achieving the purpose of quickly responding to the reset signal. Furthermore, after returning the reception response signal to the card reader, it can first perform power-on scanning, data rollback, and dirty page marking, but does not immediately clear the dirty pages. Instead, dirty page clearing is placed during the garbage collection process and / or during the response to contact instructions. That is, unlike related technologies, the entire power-off recovery is not placed during the response to the first instruction, thereby achieving the purpose of both power-off recovery and a quick response to the first instruction. It can be seen that the disclosed embodiment can not only improve the speed of responding to the reset signal, but also take into account the speed of power-off recovery and the response to the first instruction.

[0061] In another embodiment of the present disclosure, the security chip integrates an eSE system and an eSIM system, and the method further includes: when the security chip turns on a radio frequency field, in response to a contactless instruction, if old data exists at a write address corresponding to the contactless instruction in a memory, writing the data to be written to an idle page in the memory;

[0062] Mark the storage page where the old data is located;

[0063] When the data to be written is completed, a write completion signal is sent to the card reading device.

[0064] In an embodiment of the present disclosure, after sending an ATR signal to a card reader, when the security chip turns on the radio frequency field (i.e., contactless field), in response to a contactless instruction, it is detected whether data (referred to as old data) already exists in the write address corresponding to the contactless instruction. If old data already exists, an idle page is searched in the memory (the idle page here refers to a brand new erased storage page), the data to be written is written into the idle page, and the storage page where the old data is located is marked as a dirty page. After all the data to be written is written, a write completion signal is sent to the card reader.

[0065] Optionally, after sending the write completion signal to the card reading device, the method further includes: clearing the storage page where the old data is located when the security chip turns off the radio frequency field.

[0066] In the disclosed embodiment, when the security chip turns off the RF field (i.e., not in the contact-off state), the memory page where the old data is located is immediately cleared. Of course, the memory page where the old data is located can also be cleared during the garbage collection process and / or in response to a contact instruction.

[0067] It is understandable that the security chip integrating eSE and eSIM, as a composite product, needs to be compatible with the concurrency of contactless card swiping. The response to contactless commands has high performance requirements. For certain contactless commands with real-time response requirements, the time from the issuance of the contactless command to the receipt of the response must be within 4ms. This process generally involves erasing and writing flash data. A single erase and write of ordinary flash takes about 4ms, which cannot meet the response requirements. Improving hardware performance means requiring higher chip costs. The ordinary write cache method, although it can respond within 1ms, has the risk of data loss due to power failure. In view of this, the embodiment of the present disclosure optimizes the read and write timing. When a contactless command is received to write data to be written, the data to be written is written to a new, erased flash page. Before the data to be written is completed, the storage page containing the old data is used as a backup page. After the data to be written is completed, the storage page containing the old data is marked as a dirty page, and a confirmation status word of the contactless command is returned. After the data to be written is completed, the dirty page is erased and deleted during the subsequent processing of the contact command or garbage collection process. This can reduce the time required to erase once before a contactless instruction completes its response (usually 2ms), thereby reducing the time required to respond to contactless instructions and helping to meet the need for fast contactless response. Furthermore, during the process of writing the data to be written, the data to be written is directly written to the flash to ensure the integrity of the data to be written, greatly improving the transaction performance of the security chip and the integrity of data read and write. At the same time, an amortization scheme is added, as the write instruction of the contactless instruction is completed by two instructions. The first instruction, cmd+addr, performs preprocessing first, and the second instruction, data+crc, performs the write operation to the flash. After all contactless card transactions are completed, the backup page is erased after leaving the site. This way, the first instruction can respond in 2ms and the second instruction in 3ms, achieving the ultimate performance. It also ensures that data is not lost. If the write is not completed midway, power-off rollback is supported.

[0068] The following describes in detail the power-on response and instruction processing method provided by the embodiment of the present disclosure with reference to a specific example. Figure 2-Figure 6As shown in the figure, when the security chip is powered by the card reader (i.e., power_on), the card reader sends an rst_request (i.e., reset signal) and waits for 4ms. The security chip boots the code from the flash and then initializes the apdu_7816 hardware interface. After the initialization is complete, it quickly responds to 0x3b (i.e., send0x3b), then performs a preliminary power-on scan (i.e., power_on_scan) and data rollback. The data rollback is divided into marking dirty pages (i.e., mark_dirty_page) and clearing dirty pages. The first stage only marks dirty pages to ensure that user data is correct. The second stage of clearing dirty pages is placed in the internal clearing sequence (i.e., clear_in_apdu_and_garbage collection) when garbage collection or processing instructions with low response performance requirements. It is not noticeable to the user. When processing instructions with low response performance requirements, each instruction clears some invalid data until the data is completely cleared. In other words, the time spent clearing dirty pages is evenly distributed among garbage collection and instructions with low response performance requirements. After completing the power-on scan and marking dirty pages, an ATR (i.e., sendatr) is sent to the card reader, completing power-on initialization (i.e., power_on_init_end). More specifically, after the security chip is powered on, it receives a reset signal from the card reader. Within 4ms, the security chip outputs 0x3b through the C7 pin of the 7816 interface, indicating that it is ready for power-off recovery. It then enters the power-on scan and dirty page marking phases: The eSE context information (i.e., se_context) and eSIM context information (esim_context) are present, respectively. The scanned valid data is stored in the eSE area according to the eSE context information, and in the eSIM area according to the eSIM context information. Then, the flash pages in the flash are traversed, and the validity of the flash pages is determined by data such as the page header and version number, that is, whether the data in the flash page is valid data (i.e., flash_page_check and judgment page_is_valid). If it is a valid page, it is added to the corresponding context mapping table (i.e., add_to_maptable). If it is an invalid page, it is marked as a dirty page (i.e., mark as dirty) and the corresponding dirty page table is updated. Then, the next flash page is traversed until all flash pages are traversed (i.e., judging is_end_page and scan_end if yes, check_next_page if no). The difference from traditional traversal of flash pages is that only traversal query is performed, and flash erasure (i.e., dirty page clearing) is not involved. Therefore, the overall scanning time can reach 2ms. Traditional scanning and erasing of flash takes at least 15ms to 1000ms, depending on the amount of data to be recovered.The method for clearing dirty pages is as follows: when an APDU processing business is received (i.e., apdu_come), if the business process triggers garbage collection (i.e., trigger garbage collection), all dirty pages will be cleared in the garbage collection (i.e., clear_all_dirty_page); if it is a contact instruction (i.e., is_contact_irq_apdu), one page of dirty pages will be cleared (i.e., clear_one_dirty_page). The combination of these two methods will evenly distribute the time for clearing dirty pages instead of concentrating it in a certain business, resulting in a decrease in response time. After power-on initialization is completed, the eSE performs eSE operations (i.e., se_process) and the eSIM performs eSIM operations (i.e., esim_process). When the eSIM receives the command (i.e., apdu_coming), the eSIM executes the corresponding service (i.e., do_task). At this time, if the eSE interrupt (i.e., se_irq) is received, it is ready to respond to and process the contactless command (i.e., se_contact_less_irq) and contactless entry (i.e., field_on). The security chip receives the contactless command (i.e., contact_less_cmd) and requests to write data to the security chip (i.e., request_write_data_to_flash). Since the current write address already has old data, if data is continued to be written at the write address, it needs to be erased before writing. Here, a new free page is found to write data (i.e., find_free_page and write_to_free). After confirming that the write is complete, the flash page where the old data is located is marked as a dirty page (i.e., mark_old_page_as_dirty), and then the command reply is 0x9000 (i.e., response). 0x9000), a contactless instruction is completed (i.e., isend_cmd). This approach not only saves 2-3ms of page erase time within the instruction cycle, but also ensures that data can be written to the flash memory without being lost during power outages, unlike write caches (some traditional solutions use write caches to speed up contactless instructions, which carries the risk of power outages). This speeds up instruction response and solves the power outage issue. The next contactless instruction (i.e., next_cmd) is then executed using the same processing method. Finally, after all contactless processing is completed, the contactless device is detected to have left the field. After the contactless device leaves the field (i.e., field_off), dirty pages are cleared (i.e., clear_dirty_page). These dirty pages are gradually released during subsequent instructions and garbage collection processes that require less responsiveness, ensuring time amortization and user-impactless processing. Testing has shown that the response to write instructions in contactless card transactions can be within 3ms, far exceeding the 6-15ms of traditional solutions.

[0069] Figure 7This is a schematic diagram of the structure of a power-on response and instruction processing device provided by an embodiment of the present disclosure. The power-on response and instruction processing device can be understood as the above-mentioned electronic device or a part of the functional modules in the above-mentioned electronic device. Figure 7 As shown, the power-on response and instruction processing device includes:

[0070] a first sending module 710, configured to initialize the eSIM hardware interface in response to a reset signal sent by the card reader when the security chip obtains power provided by the card reader, and to send a reception response signal to the card reader through the eSIM hardware interface, wherein the reception response signal indicates that the reset signal has been received;

[0071] A scanning and rolling back module 720 is configured to scan and identify valid data based on context information, and store the valid data in a memory;

[0072] a dirty page marking module 730 for marking dirty pages of the memory, wherein dirty pages are cleared during garbage collection and / or in response to contact instructions;

[0073] The second sending module 740 is configured to send the ATR to the card reading device.

[0074] Optionally, the dirty page marking module 730 is specifically configured to add each storage page in the memory to a context mapping table if the storage page is a valid page, and to add the storage page to a dirty page table if the storage page is an invalid page.

[0075] Optionally, the device further includes: a dirty page clearing module, configured to clear all the dirty pages during the garbage collection process.

[0076] Optionally, the triggering condition for garbage collection includes at least one of the following: the current available space of the memory is less than a preset threshold, and the time since the last garbage collection reaches a preset time.

[0077] Optionally, the device further includes: a dirty page clearing module, configured to clear a preset number of dirty pages in response to a contact instruction.

[0078] Optionally, the security chip integrates an eSE and an eSIM, and the device further includes: a writing module, configured to, when the radio frequency field of the security chip is turned on, respond to a contactless instruction and, if old data exists at a write address corresponding to the contactless instruction in the memory, write the data to be written to an idle page in the memory;

[0079] Marking the storage page where the old data is located;

[0080] When the writing of the data to be written is completed, a write completion signal is sent to the card reading device.

[0081] Optionally, the apparatus further includes: a clearing module configured to clear the storage page where the old data is located after the write completion signal is sent to the card reader device; and further includes: when the security chip turns off the radio frequency field.

[0082] The device provided in this embodiment can execute the method of any of the above embodiments, and its execution method and beneficial effects are similar, which will not be repeated here.

[0083] An embodiment of the present disclosure further provides an electronic device, comprising: a memory storing a computer program; and a processor for executing the computer program. When the computer program is executed by the processor, the method of any of the above embodiments can be implemented.

[0084] For example, Figure 8 This is a schematic diagram of the structure of an electronic device in the embodiment of the present disclosure. Figure 8 , which shows a schematic structural diagram of an electronic device 800 suitable for implementing the embodiments of the present disclosure. The electronic device 800 in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0085] like Figure 8 As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage device 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the electronic device 800 are also stored in the RAM 803. The processing device 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0086] Typically, the following devices may be connected to the I / O interface 805: an input device 806 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 807 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 808 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 809. The communication device 809 may allow the electronic device 800 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 800 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed instead.

[0087] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 809, or installed from the storage device 808, or installed from the ROM 802. When the computer program is executed by the processing device 801, the above-mentioned functions defined in the method of the embodiment of the present disclosure are performed.

[0088] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0089] In some embodiments, the client and server can communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol), and can be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0090] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0091] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes any of the methods described above.

[0092] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including, but not limited to, object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0094] The units involved in the embodiments described in this disclosure may be implemented in software or hardware, wherein the name of a unit does not necessarily limit the unit itself.

[0095] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0096] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0097] The embodiments of the present disclosure further provide a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of any of the above embodiments can be implemented. The execution method and beneficial effects are similar and will not be repeated here.

[0098] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0099] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A power-on response and instruction processing method, characterized in that: Applied to a security chip, the security chip including an eSIM hardware interface, wherein the method includes: When the security chip obtains power provided by the card reader device, in response to a reset signal sent by the card reader device, initializing the eSIM hardware interface, and sending a reception response signal to the card reader device through the eSIM hardware interface, wherein the reception response signal is used to indicate that the reset signal has been received; Scan and identify valid data based on context information, and store the valid data in a memory; Marking dirty pages of the memory, wherein the dirty pages are cleared during garbage collection and / or in response to contact instructions; Sending the ATR to the card reader.

2. The method according to claim 1, characterized in that The dirty page marking of the memory includes: For each storage page in the memory, if the storage page is a valid page, the storage page is added to a context mapping table; if the storage page is an invalid page, the storage page is added to a dirty page table.

3. The method according to claim 1, characterized in that The process of clearing the dirty pages includes: All said dirty pages are cleared during garbage collection.

4. The method according to claim 3, characterized in that The triggering condition for garbage collection includes at least one of the following: the current available space of the memory is less than a preset threshold, and the time since the last garbage collection reaches a preset time.

5. The method according to claim 1, wherein the process of clearing dirty pages comprises: In the process of responding to the contact instruction, a preset number of dirty pages are cleared.

6. The method according to claim 1, characterized in that The security chip integrates an eSE and an eSIM, and the method further includes: In a case where the radio frequency field is turned on by the security chip, in response to a contactless instruction, if old data exists at a write address corresponding to the contactless instruction in the memory, writing the data to be written into an idle page in the memory; Marking the storage page where the old data is located; When the writing of the data to be written is completed, a write completion signal is sent to the card reading device.

7. The method according to claim 6, characterized in that After sending the write completion signal to the card reading device, the method further includes: When the radio frequency field is turned off by the security chip, the storage page where the old data is located is cleared.

8. A power-on response and instruction processing device, characterized in that: Applied to a security chip, the security chip including an eSIM hardware interface, wherein the device includes: a first sending module, configured to, when the security chip obtains power provided by the card reader device, initialize the eSIM hardware interface in response to a reset signal sent by the card reader device, and send a reception response signal to the card reader device through the eSIM hardware interface, wherein the reception response signal is used to indicate that the reset signal has been received; A scanning and rolling back module, configured to scan and identify valid data based on context information, and store the valid data in a memory; a dirty page marking module, configured to mark dirty pages of the memory, wherein the dirty pages are cleared during garbage collection and / or in response to contact instructions; The second sending module is used to send the ATR to the card reading device.

9. An electronic device, characterized in that: include: A processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor performs the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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