A semiconductor cross-section structure detection method and system based on etching technology

Abstract

The application belongs to the technical field of semiconductors, and discloses a semiconductor cross-section structure detection method and system based on etching technology, which comprises the following steps: different-angle etching treatment is performed on a semiconductor sample by using ion beam swing cutting technology to form preset target structure characteristics, and etching process data is synchronously collected; the semiconductor sample after etching treatment is subjected to layer-by-layer slicing by using a focused ion beam, an image sequence of each layer cross-section is collected, and the image sequence is converted into a three-dimensional structure model of the semiconductor sample by using a three-dimensional reconstruction algorithm; a heterogeneous graph is constructed by fusing the three-dimensional model and the etching process data, a graph attention mechanism is used to capture the space-time correlation features between heterogeneous nodes in the heterogeneous graph, and topology analysis is performed by establishing a heterogeneous circulation mechanism to optimize hyperedge weights to generate a defect space distribution map. The three-dimensional reconstruction algorithm is combined to restore the structural integrity, and high-precision three-dimensional model support is provided for subsequent defect analysis.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and system for detecting semiconductor cross-sectional structures based on etching technology. Background Technology

[0002] With the continuous advancement of integrated circuit manufacturing technology, semiconductor devices are shrinking in size, becoming increasingly complex in structure, and requiring more refined manufacturing processes. As a critical step in the semiconductor manufacturing process, the precision of the etching process directly determines device performance and production yield. Especially in advanced process nodes, etching not only requires precise material removal between multilayer structures, but also strict control over the contours and thicknesses of each material interface to ensure the smooth progress of subsequent processes.

[0003] However, current semiconductor cross-sectional structure inspection mainly relies on techniques such as mechanical polishing and focused ion beam (FIB) cutting. Mechanical polishing exposes the internal cross-section of the device through physical means, but this method is prone to introducing mechanical stress damage and makes it difficult to maintain consistent polishing flatness, which can lead to distorted inspection results. On the other hand, although FIB cutting can achieve nanoscale precision cross-section fabrication, its problems such as ion implantation damage, slow operation speed, high cost, and potential contamination of the ion source due to long-term use cannot be ignored. Furthermore, when dealing with complex multilayer structures, traditional image processing methods often struggle to accurately extract the boundary features of the etched micro / nano structures, and are susceptible to image noise, alignment errors, and deformation, thus affecting the accuracy and stability of the inspection results.

[0004] Therefore, how to provide a method and system for detecting semiconductor cross-sectional structures based on etching technology is an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a method and system for detecting semiconductor cross-sectional structures based on etching technology, in order to solve the aforementioned technical problems existing in the prior art.

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or to describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0007] According to a first aspect of the present invention, a method for detecting semiconductor cross-sectional structures based on etching technology is provided.

[0008] In one embodiment, a semiconductor cross-sectional structure detection method based on etching technology includes:

[0009] The semiconductor sample is etched at different angles using ion beam swing cutting technology to form the preset target structural features, and the etching process data is collected simultaneously.

[0010] The semiconductor sample after etching is sliced ​​layer by layer using a focused ion beam, and image sequences of each cross-section are acquired. The image sequences are then converted into a three-dimensional structural model of the semiconductor sample using a three-dimensional reconstruction algorithm.

[0011] By integrating 3D models and etching process data, a heterogeneous graph is constructed. The graph attention mechanism is used to capture the spatiotemporal correlation features between heterogeneous nodes in the graph. A heterogeneous loop mechanism is established to optimize the hyperedge weights and perform topology analysis to generate a defect spatial distribution map.

[0012] In one embodiment, the step of slicing the etched semiconductor sample layer by layer using a focused ion beam, acquiring image sequences of each cross-section, and converting the image sequences into a three-dimensional structural model of the semiconductor sample using a three-dimensional reconstruction algorithm includes:

[0013] Based on the etched semiconductor sample, the slice thickness is set, and a focused ion beam is used to perform a layer-by-layer slicing operation on the semiconductor sample. During the slicing process, images of each cross-section are acquired simultaneously to generate an image sequence with spatial order.

[0014] The image sequence is denoised, and the denoised image sequence is spatially aligned using an image registration algorithm;

[0015] The spatially aligned image sequences are stacked and reassembled in spatial order, and a 3D reconstruction algorithm is used to process the stacked and reassembled image sequences to construct a 3D structural model.

[0016] In one embodiment, stacking and reassembling the spatially aligned image sequence according to spatial order, and processing the stacked and reassembled image sequence using a 3D reconstruction algorithm to construct a 3D structural model includes:

[0017] The spatially aligned image sequence is processed using a generative model based on a deep neural network, and the processed image sequence is stacked and recombined according to spatial order to construct the initial discrete voxel structure.

[0018] Based on the initial discrete voxel structure, a symbolic distance function network is established to convert the initial discrete voxel structure into a continuous scalar field representation. The implicit surface equation is then learned through a multilayer perceptron to obtain the surface geometric data of the semiconductor sample.

[0019] Based on the acquired surface geometry data, a three-dimensional structural model is constructed using a graph neural network.

[0020] In one embodiment, the process of fusing 3D model and etching process data to construct a heterogeneous graph, using a graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in the heterogeneous graph, and optimizing hyperedge weights through a heterogeneous loop mechanism to perform topology analysis to generate a defect spatial distribution map includes:

[0021] The three-dimensional structural model is processed using a deep learning framework to extract geometric features, and the etching process data is spatiotemporally hierarchically encoded to obtain process parameters.

[0022] Using geometric features and process parameters as heterogeneous nodes, a hyperedge connection mechanism is designed, and a time decay function is combined to assign weights to the hyperedges to construct a heterogeneous graph.

[0023] The graph attention mechanism is used to capture the spatiotemporal correlation features between heterogeneous nodes in a heterogeneous graph, and the hyperedge weights are optimized by establishing a heterogeneous recurrence mechanism.

[0024] Based on the optimized hyperedge weights, a subgraph isomorphism detection algorithm is used to match predefined defect templates, and the matching results are filtered to identify defect regions.

[0025] The defect area is mapped onto a three-dimensional structural model, and the spatial coordinate cluster of each defect area is calculated using a voxel localization algorithm to generate a spatial distribution map of the defects.

[0026] In one embodiment, the step of using geometric features and process parameters as heterogeneous nodes, designing a hyperedge connection mechanism, and assigning weights to hyperedges using a time decay function to construct a heterogeneous graph includes:

[0027] The extracted geometric features and the acquired process parameters are used as heterogeneous nodes to establish a heterogeneous node set.

[0028] The process flow is divided into stages according to the preset processing procedure file. Based on the division results, a hyperedge connection mechanism is designed to aggregate heterogeneous nodes belonging to the same process stage into hyperedges.

[0029] A time decay function is introduced for each hyperedge, and weights are assigned to the hyperedges based on the time interval between heterogeneous nodes within the hyperedge;

[0030] By combining a heterogeneous set of nodes with weighted hyperedges, a heterogeneous graph is constructed using a graph transformer.

[0031] In one embodiment, the step of using a graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in a heterogeneous graph and optimizing the hyperedge weights by establishing a heterogeneous recurrence mechanism includes:

[0032] By utilizing the graph attention mechanism, a heterogeneous node encoder is constructed to encode the features of heterogeneous nodes in a heterogeneous graph, and combined with timestamp information, the spatiotemporal correlation features between heterogeneous nodes are captured.

[0033] Design a dual-channel recurrent network framework, using spatiotemporal correlation features as temporal state inputs, and establish a heterogeneous recurrent mechanism across time steps;

[0034] Based on each time step, the state representation of heterogeneous nodes is iterated cyclically, and the hyperedge weights are optimized according to the current spatiotemporal correlation characteristics.

[0035] In one embodiment, the design of the dual-channel recurrent network framework, which uses spatiotemporal correlation features as temporal state inputs to establish a heterogeneous recurrent mechanism across time steps, includes:

[0036] Modeling the temporal features of heterogeneous graphs based on long short-term memory networks, and constructing temporal channels to extract sequence dependencies by capturing the dynamic patterns of heterogeneous node evolution over time.

[0037] The spatial features of neighboring heterogeneous nodes in a heterogeneous graph are aggregated using a multi-head attention mechanism. Spatial relationships between heterogeneous nodes are obtained through attention weight allocation, and spatial channels are constructed to obtain local structural features.

[0038] By employing a cross-attention mechanism to integrate features from the temporal and spatial channels, and by learning the interactive weights of spatiotemporal related features, a dual-channel recurrent network framework is constructed.

[0039] The spatiotemporal correlation features are used as temporal state inputs into a dual-channel recurrent network framework, and the contribution of the hyperedge is calculated at each time step.

[0040] Based on the contribution of the superedge, the temporal state of the current time step is heterogeneously cyclically interacted with the historical temporal state, and updated through the time channel and the spatial channel to realize the heterogeneous node transmission and state iteration across time steps.

[0041] Based on the heterogeneous recurrent process across time steps, the parameters of the dual-channel recurrent network framework are adjusted to establish a heterogeneous recurrent mechanism.

[0042] In one embodiment, the step of matching a predefined defect template using a subgraph isomorphism detection algorithm based on the optimized hyperedge weights, and filtering the matching results to identify defect regions includes:

[0043] Based on the optimized hyperedge weights, local structural features are extracted from the heterogeneous graph to establish a candidate subgraph set;

[0044] Using a subgraph isomorphism detection algorithm, the candidate subgraph set is matched with a predefined defect template for structural pattern matching. By comparing the mapping of heterogeneous node types with the hyperedge relationship, a candidate set of defect regions is generated.

[0045] Calculate the structural matching similarity between each candidate set of defect regions and the corresponding defect template, generate a confidence score based on the structural matching similarity, and filter the candidate set of defect regions by statistical analysis of the confidence score distribution and a preset threshold to identify the defect regions.

[0046] In one embodiment, the confidence score is calculated using the following formula:

[0047] ;

[0048] In the formula, C This represents the confidence score. α Represents the weight coefficients for heterogeneous node matching and hyperedge matching; N m This represents the number of heterogeneous nodes in the candidate subgraph set that match the heterogeneous node type of the defect template; N t Indicates the total number of heterogeneous nodes in the defect template; θ m This represents the sum of optimized weights for the hyperedges in the candidate subgraph set that match the defect template. θ t This represents the sum of the optimized weights of all hyperedges in the defect template.

[0049] According to a second aspect of the present invention, a semiconductor cross-sectional structure inspection system based on etching technology is provided.

[0050] In one embodiment, the semiconductor cross-sectional structure inspection system based on etching technology includes:

[0051] The etching and acquisition module is used to etch semiconductor samples at different angles using ion beam swing cutting technology to form preset target structural features, and to simultaneously acquire etching process data.

[0052] The 3D structure conversion module is used to slice the etched semiconductor sample layer by layer using a focused ion beam, acquire image sequences of each cross-section, and convert the image sequences into a 3D structural model of the semiconductor sample through a 3D reconstruction algorithm.

[0053] The defect spatial distribution module is used to fuse 3D model and etching process data to construct a heterogeneous graph. It uses graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in the heterogeneous graph, and optimizes the hyperedge weights by establishing a heterogeneous loop mechanism to perform topology analysis in order to generate a defect spatial distribution graph.

[0054] According to a third aspect of the present invention, a computer device is provided.

[0055] In some embodiments, the computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method described above.

[0056] According to a fourth aspect of the present invention, a computer-readable storage medium is provided.

[0057] In one embodiment, a computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the steps of the above method.

[0058] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0059] 1. This invention achieves precise cutting and image acquisition of semiconductor samples from multiple angles through ion beam swing etching and focused ion beam slicing. Combined with a three-dimensional reconstruction algorithm, it restores the structural integrity and provides high-precision three-dimensional model support for subsequent defect analysis.

[0060] 2. This invention constructs a heterogeneous graph through a graph attention mechanism, using geometric structures and process parameters as heterogeneous nodes, integrating temporal features to capture complex spatiotemporal dependencies between nodes; and dynamically optimizes hyperedge weights by combining a heterogeneous loop mechanism to enhance the representational ability of the graph structure.

[0061] 3. This invention generates a defect spatial distribution map by performing topological analysis on heterogeneous graphs, enabling accurate identification and location of defects. It supports the evaluation of defect characteristics from both structural and process dimensions, and helps optimize process parameters and improve semiconductor manufacturing quality.

[0062] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0063] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0064] Figure 1 This is a flowchart illustrating a semiconductor cross-sectional structure detection method based on etching technology, according to an exemplary embodiment.

[0065] Figure 2 This is a schematic block diagram illustrating a semiconductor cross-sectional structure inspection system based on etching technology, according to an exemplary embodiment.

[0066] Figure 3 This is a schematic diagram of the structure of a computer device according to an exemplary embodiment. Detailed Implementation

[0067] The following description and accompanying drawings fully illustrate specific embodiments described herein to enable those skilled in the art to practice them. Some embodiments may include or substitute parts and features of other embodiments. The scope of the embodiments herein encompasses the entire scope of the claims and all available equivalents thereof. Throughout this document, the terms “first,” “second,” etc., are used only to distinguish one element from another without requiring or implying any actual relationship or order between the elements. Indeed, a first element can also be referred to as a second element, and vice versa. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a structure, apparatus, or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the structure, apparatus, or device that includes said element. The various embodiments described herein are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0068] The terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" used in this document to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. They are used solely for the convenience of describing the document and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description herein, unless otherwise specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two elements; they can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0069] In this document, unless otherwise stated, the term "multiple" means two or more.

[0070] In this article, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0071] In this article, the term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0072] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0073] The modules in the apparatus or system of this application can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0074] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0075] Figure 1 An embodiment of a semiconductor cross-sectional structure detection method based on etching technology according to the present invention is shown.

[0076] In this optional embodiment, the semiconductor cross-sectional structure detection method based on etching technology includes:

[0077] In step S101, the semiconductor sample is etched at different angles using ion beam swing cutting technology to form the preset target structural features, and the etching process data is collected simultaneously.

[0078] It should be further noted that the following is a specific embodiment of using ion beam swaying cutting technology to etch semiconductor samples at different angles to form preset target structural features, and simultaneously acquiring etching process data:

[0079] In the etching of flip-chip copper pillar structures, PFIB (Xe+) technology was used with 30keV energy and 2.3μA beam current for multi-angle milling. Through two-stage processing of rough milling (55° tilt angle) and fine polishing (10° tilt angle), the etching time of 200μm silicon chips was shortened from 8-10 hours using traditional methods to 1.2-1.5 hours. In the fabrication of convex blazed gratings, a three-dimensional stage was used to dynamically adjust the ion beam incident angle (30-60° for main etching and 15° for supplementary etching), combined with a circular arc fitting algorithm to achieve oscillating etching. A grating with a radius of curvature of 156.88mm and a blaze angle of 2.2° was successfully fabricated, with a peak diffraction efficiency of 90%. For synchronous data acquisition, an aluminum-coated quartz crystal oscillator was used to monitor frequency changes in real time. When the aluminum film etching depth reached 245nm, the corresponding target etching depth error on the silicon wafer was only 5.7%. This technology is also applied to MEMS cavity defect analysis. By etching at a 50° angle to create windows in a 100μm thick silicon cover plate, combined with XeF2 chemically enhanced etching, efficiency is increased by 12 times, completing defect exposure in one hour that would take 12 hours using traditional methods. In the case of bond line crack detection, multi-angle ion beams (a combination of high-current rough milling and low-current polishing) reduce analysis time from 10 hours to 15 minutes and eliminate the curtain effect.

[0080] Step S102: The semiconductor sample after etching is sliced ​​layer by layer using a focused ion beam, image sequences of each cross section are acquired, and the image sequences are converted into a three-dimensional structural model of the semiconductor sample using a three-dimensional reconstruction algorithm.

[0081] Step S103: Integrate the 3D model and etching process data to construct a heterogeneous graph. Use graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in the heterogeneous graph. Optimize the hyperedge weights by establishing a heterogeneous loop mechanism to perform topology analysis and generate a defect spatial distribution map.

[0082] In this optional embodiment, the step of slicing the etched semiconductor sample layer by layer using a focused ion beam, acquiring image sequences of each cross-section, and converting the image sequences into a three-dimensional structural model of the semiconductor sample using a three-dimensional reconstruction algorithm includes:

[0083] Based on the etched semiconductor sample, the slice thickness is set, and a focused ion beam is used to perform a layer-by-layer slicing operation on the semiconductor sample. During the slicing process, images of each cross-section are acquired simultaneously to generate an image sequence with spatial order.

[0084] The image sequence is denoised, and the denoised image sequence is spatially aligned using an image registration algorithm;

[0085] The spatially aligned image sequences are stacked and reassembled in spatial order, and a 3D reconstruction algorithm is used to process the stacked and reassembled image sequences to construct a 3D structural model.

[0086] In this optional embodiment, the step of stacking and reassembling the spatially aligned image sequences according to spatial order, and then processing the stacked and reassembled image sequences using a 3D reconstruction algorithm to construct a 3D structural model includes:

[0087] The spatially aligned image sequence is processed using a generative model based on a deep neural network, and the processed image sequence is stacked and recombined according to spatial order to construct the initial discrete voxel structure.

[0088] Based on the initial discrete voxel structure, a symbolic distance function network is established to convert the initial discrete voxel structure into a continuous scalar field representation. The implicit surface equation is then learned through a multilayer perceptron to obtain the surface geometric data of the semiconductor sample.

[0089] Based on the acquired surface geometry data, a three-dimensional structural model is constructed using a graph neural network.

[0090] In this optional embodiment, the process of fusing the 3D model and etching process data to construct a heterogeneous graph, using a graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in the heterogeneous graph, and optimizing the hyperedge weights through a heterogeneous loop mechanism to perform topology analysis to generate a defect spatial distribution map includes:

[0091] The three-dimensional structural model is processed using a deep learning framework to extract geometric features, and the etching process data is spatiotemporally hierarchically encoded to obtain process parameters.

[0092] Using geometric features and process parameters as heterogeneous nodes, a hyperedge connection mechanism is designed, and a time decay function is combined to assign weights to the hyperedges to construct a heterogeneous graph.

[0093] The graph attention mechanism is used to capture the spatiotemporal correlation features between heterogeneous nodes in a heterogeneous graph, and the hyperedge weights are optimized by establishing a heterogeneous recurrence mechanism.

[0094] Based on the optimized hyperedge weights, a subgraph isomorphism detection algorithm is used to match predefined defect templates, and the matching results are filtered to identify defect regions.

[0095] The defect area is mapped onto a three-dimensional structural model, and the spatial coordinate cluster of each defect area is calculated using a voxel localization algorithm to generate a spatial distribution map of the defects.

[0096] In this optional embodiment, the step of using geometric features and process parameters as heterogeneous nodes, designing a hyperedge connection mechanism, and assigning weights to hyperedges using a time decay function to construct a heterogeneous graph includes:

[0097] The extracted geometric features and the acquired process parameters are used as heterogeneous nodes to establish a heterogeneous node set.

[0098] The process flow is divided into stages according to the preset processing procedure file. Based on the division results, a hyperedge connection mechanism is designed to aggregate heterogeneous nodes belonging to the same process stage into hyperedges.

[0099] A time decay function is introduced for each hyperedge, and weights are assigned to the hyperedges based on the time interval between heterogeneous nodes within the hyperedge;

[0100] By combining a heterogeneous set of nodes with weighted hyperedges, a heterogeneous graph is constructed using a graph transformer.

[0101] In this optional embodiment, the step of using a graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in a heterogeneous graph and optimizing the hyperedge weights by establishing a heterogeneous recurrence mechanism includes:

[0102] By utilizing the graph attention mechanism, a heterogeneous node encoder is constructed to encode the features of heterogeneous nodes in a heterogeneous graph, and combined with timestamp information, the spatiotemporal correlation features between heterogeneous nodes are captured.

[0103] Design a dual-channel recurrent network framework, using spatiotemporal correlation features as temporal state inputs, and establish a heterogeneous recurrent mechanism across time steps;

[0104] Based on each time step, the state representation of heterogeneous nodes is iterated cyclically, and the hyperedge weights are optimized according to the current spatiotemporal correlation characteristics.

[0105] In this optional embodiment, the design of the dual-channel recurrent network framework, which uses spatiotemporal correlation features as temporal state inputs to establish a heterogeneous recurrent mechanism across time steps, includes:

[0106] Modeling the temporal features of heterogeneous graphs based on long short-term memory networks, and constructing temporal channels to extract sequence dependencies by capturing the dynamic patterns of heterogeneous node evolution over time.

[0107] The spatial features of neighboring heterogeneous nodes in a heterogeneous graph are aggregated using a multi-head attention mechanism. Spatial relationships between heterogeneous nodes are obtained through attention weight allocation, and spatial channels are constructed to obtain local structural features.

[0108] By employing a cross-attention mechanism to integrate features from the temporal and spatial channels, and by learning the interactive weights of spatiotemporal related features, a dual-channel recurrent network framework is constructed.

[0109] The spatiotemporal correlation features are used as temporal state inputs into a dual-channel recurrent network framework, and the contribution of the hyperedge is calculated at each time step.

[0110] Based on the contribution of the superedge, the temporal state of the current time step is heterogeneously cyclically interacted with the historical temporal state, and updated through the time channel and the spatial channel to realize the heterogeneous node transmission and state iteration across time steps.

[0111] Based on the heterogeneous recurrent process across time steps, the parameters of the dual-channel recurrent network framework are adjusted to establish a heterogeneous recurrent mechanism.

[0112] In this optional embodiment, the step of matching a predefined defect template using a subgraph isomorphism detection algorithm based on the optimized hyperedge weights, and then filtering the matching results to identify defect regions includes:

[0113] Based on the optimized hyperedge weights, local structural features are extracted from the heterogeneous graph to establish a candidate subgraph set;

[0114] Using a subgraph isomorphism detection algorithm, the candidate subgraph set is matched with a predefined defect template for structural pattern matching. By comparing the mapping of heterogeneous node types with the hyperedge relationship, a candidate set of defect regions is generated.

[0115] Calculate the structural matching similarity between each candidate set of defect regions and the corresponding defect template, generate a confidence score based on the structural matching similarity, and filter the candidate set of defect regions by statistical analysis of the confidence score distribution and a preset threshold to identify the defect regions.

[0116] In this optional embodiment, the confidence score is calculated using the following formula:

[0117] ;

[0118] In the formula, C This represents the confidence score. α Represents the weight coefficients for heterogeneous node matching and hyperedge matching; N m This represents the number of heterogeneous nodes in the candidate subgraph set that match the heterogeneous node type of the defect template; N t This represents the total number of heterogeneous nodes in the defect template. θ m This represents the sum of optimized weights for the hyperedges in the candidate subgraph set that match the defect template. θ t This represents the sum of the optimized weights of all hyperedges in the defect template.

[0119] Figure 2 An embodiment of a semiconductor cross-sectional structure inspection system based on etching technology according to the present invention is shown.

[0120] In this optional embodiment, the semiconductor cross-sectional structure inspection system based on etching technology includes:

[0121] The etching and acquisition module 201 is used to perform etching processing on semiconductor samples at different angles using ion beam swing cutting technology to form preset target structural features, and to simultaneously acquire etching process data.

[0122] The three-dimensional structure conversion module 202 is used to slice the etched semiconductor sample layer by layer using a focused ion beam, acquire image sequences of each cross section, and convert the image sequences into a three-dimensional structural model of the semiconductor sample through a three-dimensional reconstruction algorithm.

[0123] The defect spatial distribution module 203 is used to fuse the 3D model and etching process data to construct a heterogeneous graph. It uses a graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in the heterogeneous graph and optimizes the hyperedge weights by establishing a heterogeneous loop mechanism to perform topology analysis in order to generate a defect spatial distribution graph.

[0124] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 3 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores static and dynamic information data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the steps in the above method embodiments.

[0125] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0126] In addition, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0127] In addition, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0128] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0129] This invention is not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this invention is limited only by the appended claims.

Claims

1. A method for detecting semiconductor cross-sectional structures based on etching technology, characterized in that, include: The semiconductor sample is etched at different angles using ion beam swing cutting technology to form the preset target structural features, and the etching process data is collected simultaneously. The semiconductor sample after etching is sliced ​​layer by layer using a focused ion beam, and image sequences of each cross-section are acquired. The image sequences are then converted into a three-dimensional structural model of the semiconductor sample using a three-dimensional reconstruction algorithm. The three-dimensional structural model is processed using a deep learning framework to extract geometric features, and the etching process data is spatiotemporally hierarchically encoded to obtain process parameters. The extracted geometric features and the acquired process parameters are used as heterogeneous nodes to establish a heterogeneous node set. The process flow is divided into stages according to the preset processing procedure file. Based on the division results, a hyperedge connection mechanism is designed to aggregate heterogeneous nodes belonging to the same process stage into hyperedges. A time decay function is introduced for each hyperedge, and weights are assigned to the hyperedges based on the time intervals between heterogeneous nodes within the hyperedges; combining the set of heterogeneous nodes and the weighted hyperedges, a heterogeneous graph is constructed using a graph transformer. The graph attention mechanism is used to capture the spatiotemporal correlation features between heterogeneous nodes in a heterogeneous graph, and the hyperedge weights are optimized by establishing a heterogeneous recurrence mechanism. Based on the optimized hyperedge weights, a subgraph isomorphism detection algorithm is used to match predefined defect templates, and the matching results are filtered to identify defect regions. The defect area is mapped onto a three-dimensional structural model, and the spatial coordinate cluster of each defect area is calculated using a voxel localization algorithm to generate a spatial distribution map of the defects.

2. The semiconductor cross-sectional structure detection method based on etching technology according to claim 1, characterized in that, The process of slicing the etched semiconductor sample layer by layer using a focused ion beam, acquiring image sequences of each cross-section, and converting the image sequences into a three-dimensional structural model of the semiconductor sample using a three-dimensional reconstruction algorithm includes: Based on the etched semiconductor sample, the slice thickness is set, and a focused ion beam is used to perform a layer-by-layer slicing operation on the semiconductor sample. During the slicing process, images of each cross-section are acquired simultaneously to generate an image sequence with spatial order. The image sequence is denoised, and the denoised image sequence is spatially aligned using an image registration algorithm; The spatially aligned image sequences are stacked and reassembled in spatial order, and a 3D reconstruction algorithm is used to process the stacked and reassembled image sequences to construct a 3D structural model.

3. The semiconductor cross-sectional structure detection method based on etching technology according to claim 2, characterized in that, The process of stacking and reassembling spatially aligned image sequences according to spatial order, and then processing the stacked and reassembled image sequences using a 3D reconstruction algorithm to construct a 3D structural model includes: The spatially aligned image sequence is processed using a generative model based on a deep neural network, and the processed image sequence is stacked and recombined according to spatial order to construct the initial discrete voxel structure. Based on the initial discrete voxel structure, a symbolic distance function network is established to convert the initial discrete voxel structure into a continuous scalar field representation. The implicit surface equation is then learned through a multilayer perceptron to obtain the surface geometric data of the semiconductor sample. Based on the acquired surface geometry data, a three-dimensional structural model is constructed using a graph neural network.

4. The semiconductor cross-sectional structure detection method based on etching technology according to claim 1, characterized in that, The method of using graph attention mechanism to capture the spatiotemporal correlation features between heterogeneous nodes in a heterogeneous graph, and optimizing the hyperedge weights by establishing a heterogeneous recurrent mechanism, includes: By utilizing the graph attention mechanism, a heterogeneous node encoder is constructed to encode the features of heterogeneous nodes in a heterogeneous graph, and combined with timestamp information, the spatiotemporal correlation features between heterogeneous nodes are captured. Design a dual-channel recurrent network framework, using spatiotemporal correlation features as temporal state inputs, and establish a heterogeneous recurrent mechanism across time steps; Based on each time step, the state representation of heterogeneous nodes is iterated cyclically, and the hyperedge weights are optimized according to the current spatiotemporal correlation characteristics.

5. The semiconductor cross-sectional structure detection method based on etching technology according to claim 4, characterized in that, The proposed dual-channel recurrent network framework uses spatiotemporal correlation features as temporal state inputs to establish a heterogeneous recurrent mechanism across time steps, including: Modeling the temporal features of heterogeneous graphs based on long short-term memory networks, and constructing temporal channels to extract sequence dependencies by capturing the dynamic patterns of heterogeneous node evolution over time. The spatial features of neighboring heterogeneous nodes in a heterogeneous graph are aggregated using a multi-head attention mechanism. Spatial relationships between heterogeneous nodes are obtained through attention weight allocation, and spatial channels are constructed to obtain local structural features. By employing a cross-attention mechanism to integrate features from the temporal and spatial channels, and by learning the interactive weights of spatiotemporal related features, a dual-channel recurrent network framework is constructed. The spatiotemporal correlation features are used as temporal state inputs into a dual-channel recurrent network framework, and the contribution of the hyperedge is calculated at each time step. Based on the contribution of the superedge, the temporal state of the current time step is heterogeneously cyclically interacted with the historical temporal state, and updated through the time channel and the spatial channel to realize the heterogeneous node transmission and state iteration across time steps. Based on the heterogeneous recurrent process across time steps, the parameters of the dual-channel recurrent network framework are adjusted to establish a heterogeneous recurrent mechanism.

6. The semiconductor cross-sectional structure detection method based on etching technology according to claim 5, characterized in that, Based on the optimized hyperedge weights, a subgraph isomorphism detection algorithm is used to match predefined defect templates, and the matching results are filtered to identify defect regions, including: Based on the optimized hyperedge weights, local structural features are extracted from the heterogeneous graph to establish a candidate subgraph set; Using a subgraph isomorphism detection algorithm, the candidate subgraph set is matched with a predefined defect template for structural pattern matching. By comparing the mapping of heterogeneous node types with the hyperedge relationship, a candidate set of defect regions is generated. Calculate the structural matching similarity between each candidate set of defect regions and the corresponding defect template, generate a confidence score based on the structural matching similarity, and filter the candidate set of defect regions by statistical analysis of the confidence score distribution and a preset threshold to identify the defect regions.

7. The semiconductor cross-sectional structure detection method based on etching technology according to claim 6, characterized in that, The formula for calculating the confidence score is: ； In the formula, C This represents the confidence score. α Represents the weight coefficients for heterogeneous node matching and hyperedge matching; N m This represents the number of heterogeneous nodes in the candidate subgraph set that match the heterogeneous node type of the defect template; N t This represents the total number of heterogeneous nodes in the defect template. θ m This represents the sum of optimized weights for the hyperedges in the candidate subgraph set that match the defect template. θ t This represents the sum of the optimized weights of all hyperedges in the defect template.

8. A semiconductor cross-sectional structure inspection system based on etching technology, characterized in that, include: The etching and acquisition module is used to etch semiconductor samples at different angles using ion beam swing cutting technology to form preset target structural features, and to simultaneously acquire etching process data. The 3D structure conversion module is used to slice the etched semiconductor sample layer by layer using a focused ion beam, acquire image sequences of each cross-section, and convert the image sequences into a 3D structural model of the semiconductor sample through a 3D reconstruction algorithm. The defect spatial distribution module is used to process 3D structural models based on a deep learning framework to extract geometric features and to perform spatiotemporal hierarchical encoding on etching process data to obtain process parameters. The extracted geometric features and the acquired process parameters are used as heterogeneous nodes to establish a heterogeneous node set. The process flow is divided into stages according to the preset processing procedure file. Based on the division results, a hyperedge connection mechanism is designed to aggregate heterogeneous nodes belonging to the same process stage into hyperedges. A time decay function is introduced for each hyperedge, and weights are assigned to the hyperedges based on the time intervals between heterogeneous nodes within the hyperedges; combining the set of heterogeneous nodes and the weighted hyperedges, a heterogeneous graph is constructed using a graph transformer. The graph attention mechanism is used to capture the spatiotemporal correlation features between heterogeneous nodes in a heterogeneous graph, and the hyperedge weights are optimized by establishing a heterogeneous recurrence mechanism. Based on the optimized hyperedge weights, a subgraph isomorphism detection algorithm is used to match predefined defect templates, and the matching results are filtered to identify defect regions. The defect area is mapped onto a three-dimensional structural model, and the spatial coordinate cluster of each defect area is calculated using a voxel localization algorithm to generate a spatial distribution map of the defects.

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