Display panel and display device

Abstract

The invention relates to the technical field of display, and provides a display panel and a display device. The display panel comprises a plurality of pixel units, a plurality of data lines, a source electrode driving chip and a plurality of gating circuits, a plurality of sub-pixels in the same pixel unit comprise a first sub-pixel and a second sub-pixel, and the first sub-pixel is a peep-proof sub-pixel; the plurality of data lines comprise a first data line and a second data line, the first data line is used for providing data signals for a plurality of first sub-pixels distributed in a second direction, and the second data line is used for providing data signals for a plurality of second sub-pixels distributed in the second direction; the source electrode driving chip comprises a plurality of data output ends, and the data output ends are used for providing data signals; the gating circuit is connected with the corresponding data output end, the first data line and the second data line, and the gating circuit is configured to select one of data signals output by the data output end to be transmitted to the first data line or the second data line. According to the display panel, the size of the peep-proof area can be adjusted.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, in some display panels, anti-peeping display is required in a local area of ​​the display panel. The related art usually sets anti-peeping sub-pixels in the local area to enable anti-peeping display in this area. However, the anti-peeping area in the related art cannot be adjusted in size according to actual needs.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes:

[0005] A plurality of pixel units, wherein the plurality of pixel units are arrayed along a first direction and a second direction, the first direction and the second direction intersecting, the pixel unit including a plurality of sub-pixels distributed along the first direction, the plurality of sub-pixels in the same pixel unit including a first sub-pixel and a second sub-pixel, the first sub-pixel being an anti-peeping sub-pixel;

[0006] a plurality of data lines extending along the second direction, the plurality of data lines comprising a first data line and a second data line, the first data line being configured to provide data signals to a plurality of first sub-pixels distributed in the second direction, and the second data line being configured to provide data signals to a plurality of second sub-pixels distributed in the second direction;

[0007] A source driver chip comprising a plurality of data output terminals, wherein the data output terminals are used to provide the data signals;

[0008] A plurality of gating circuits are provided, wherein the gating circuits are provided corresponding to the data output terminals, and the gating circuits are provided corresponding to a group of first data lines and second data lines in the same pixel unit, the gating circuits are connected to the corresponding data output terminals, the first data lines, and the second data lines, and the gating circuits are configured to selectively transmit the data signals output from the data output terminals to either the first data lines or the second data lines.

[0009] In an exemplary embodiment of the present disclosure, the source driver chip is configured to output the first reference voltage or the second reference voltage through the data output terminal during a blank period between frames, and output the data signal through the data output terminal during a frame period;

[0010] The gating circuit comprises:

[0011] a first gating circuit connected to the data output terminal, the first node, and the second node, wherein the first gating circuit is configured to transmit the first reference voltage or the second reference voltage output by the data output terminal to the first node during the blank period, and to transmit the data signal output by the data output terminal to the second node during the frame period;

[0012] a second gating circuit connected to the second node, the third node, the first data line, and the second data line, wherein the second gating circuit is configured to selectively connect the second node to the first data line or the second data line according to a voltage of the third node;

[0013] A voltage conversion circuit is connected to the first node and the third node, and the voltage conversion circuit is configured to convert a first reference voltage on the first node into a first power supply voltage and transmit the first power supply voltage to the third node, or convert a second reference voltage on the first node into a second power supply voltage and transmit the second power supply voltage to the third node.

[0014] In an exemplary embodiment of the present disclosure, the first gating circuit is also connected to a first gate drive signal terminal and a second gate drive signal terminal, and the first gating circuit is configured to respond to a signal of the first gate drive signal terminal during the blank period to transmit the first reference voltage or the second reference voltage output by the data output terminal to the first node, and respond to a signal of the second gate drive signal terminal during the frame period to transmit the data signal output by the data output terminal to the second node.

[0015] In an exemplary embodiment of the present disclosure, the first gating circuit includes:

[0016] a first transistor, having a first electrode connected to the data output terminal, a second electrode connected to the first node, and a gate connected to the first gate drive signal terminal;

[0017] The second transistor has a first electrode connected to the data output terminal, a second electrode connected to the second node, and a gate connected to the second gate drive signal terminal.

[0018] In an exemplary embodiment of the present disclosure, the second gating circuit includes:

[0019] a third transistor, having a first electrode connected to the second node, a second electrode connected to the first data line, and a gate connected to the third node;

[0020] a fourth transistor, having a first electrode connected to the second node, a second electrode connected to the second data line, and a gate connected to the third node;

[0021] The conduction level polarities of the third transistor and the fourth transistor are opposite.

[0022] In an exemplary embodiment of the present disclosure, the voltage conversion circuit includes:

[0023] a communication circuit connecting the first power terminal and the fourth node, wherein the communication circuit is configured to transmit a signal from the first power terminal to the fourth node in response to a control signal;

[0024] a reset circuit connected to the second power supply terminal, the fifth node, and the sixth node, wherein the reset circuit is configured to transmit a signal from the second power supply terminal to the fifth node and the sixth node in response to a control signal;

[0025] A sensitive amplifier circuit is connected to the first node, the initial signal terminal, the fourth node, the second power supply terminal, the fifth node, and the sixth node. The sensitive amplifier circuit is configured to transmit the voltage of the fourth node to the fifth node or transmit the signal of the second power supply terminal to the fifth node based on the magnitude relationship between the voltages on the first node and the initial signal terminal. The fifth node is connected to the third node.

[0026] In an exemplary embodiment of the present disclosure, the communication circuit is further connected to a third gate drive signal terminal, and the communication circuit is configured to respond to a signal of the third gate drive signal terminal to transmit a signal of the first power supply terminal to the fourth node;

[0027] The reset circuit is further connected to the third gate drive signal terminal, and is configured to respond to the signal of the third gate drive signal terminal to transmit the signal of the second power supply terminal to the fifth node and the sixth node, and the conduction level polarity of the reset circuit and the connection circuit is opposite;

[0028] The sensitive amplifier circuit is configured to: when the voltage of the first node is greater than the voltage of the initial signal terminal, transmit the voltage of the fourth node to the fifth node; when the voltage of the first node is less than the voltage of the initial signal terminal, transmit the signal of the second power supply terminal to the fifth node.

[0029] In an exemplary embodiment of the present disclosure, the voltage conversion circuit further includes:

[0030] a first inverter, an input end of which is connected to the fifth node, and an output end of which is connected to the seventh node;

[0031] a second inverter, an input end of which is connected to the seventh node, and an output end of which is connected to the third node;

[0032] The high-level power supply terminal of the first inverter is connected to the first power supply terminal, and the low-level power supply terminal is connected to the second power supply terminal; the high-level power supply terminal of the second inverter is connected to the first power supply terminal, and the low-level power supply terminal is connected to the second power supply terminal; the voltage of the first power supply terminal is the first power supply voltage, and the voltage of the second power supply terminal is the second power supply voltage.

[0033] In an exemplary embodiment of the present disclosure, the voltage conversion circuit further includes:

[0034] The capacitor has a first electrode connected to the first node and a second electrode connected to a stable voltage terminal.

[0035] In an exemplary embodiment of the present disclosure, the communication circuit includes:

[0036] a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth node, and a gate connected to the third gate drive signal terminal;

[0037] The reset circuit comprises:

[0038] a sixth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the sixth node, and a gate connected to the third gate drive signal terminal;

[0039] a seventh transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fifth node, and a gate connected to the third gate drive signal terminal;

[0040] The sensitive amplifier circuit comprises:

[0041] an eighth transistor, having a first electrode connected to the fourth node and a gate connected to the first node;

[0042] a ninth transistor, wherein a first electrode is connected to the fourth node, a gate is connected to the initial signal terminal, and the eighth and ninth transistors have the same conduction level polarity;

[0043] a tenth P-type transistor, having a first electrode connected to the second electrode of the eighth transistor, a second electrode connected to the sixth node, and a gate connected to the fifth node;

[0044] an eleventh P-type transistor, having a first electrode connected to the second electrode of the ninth transistor, a second electrode connected to the fifth node, and a gate connected to the sixth node;

[0045] a twelfth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the sixth node, and a gate connected to the fifth node;

[0046] a thirteenth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fifth node, and a gate connected to the sixth node;

[0047] The voltage conversion circuit further includes: a first inverter and a second inverter, wherein the first inverter includes:

[0048] a fourteenth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the seventh node, and a gate connected to the fifth node;

[0049] a fifteenth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the seventh node, and a gate connected to the fifth node;

[0050] The second inverter comprises:

[0051] a sixteenth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the seventh node;

[0052] The seventeenth N-type transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the third node, and a gate connected to the seventh node.

[0053] In an exemplary embodiment of the present disclosure, the second sub-pixel is a shared sub-pixel;

[0054] Alternatively, the second sub-pixel is an anti-peeping sub-pixel, and the anti-peeping orientations of the first sub-pixel and the second sub-pixel are different.

[0055] In an exemplary embodiment of the present disclosure, the pixel unit includes sub-pixels of multiple colors, there are multiple sub-pixels of each color, and the multiple sub-pixels of the same color all include the first sub-pixel and the second sub-pixel.

[0056] In an exemplary embodiment of the present disclosure, in the same pixel unit, sub-pixels of different colors are alternately and cyclically distributed along the first direction;

[0057] Alternatively, in the same pixel unit, sub-pixels of the same color are adjacently arranged in the first direction.

[0058] In an exemplary embodiment of the present disclosure, the first data line and the second data line connected to the same gating circuit are used to provide data signals to sub-pixels of the same color;

[0059] Alternatively, the first data line and the second data line connected to the same gating circuit are respectively used to provide data signals to sub-pixels of different colors.

[0060] In an exemplary embodiment of the present disclosure, the display panel includes a display area and a frame area located on one side of the display area in the second direction, and the gating circuit is located in the frame area.

[0061] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0062] In an exemplary embodiment of the present disclosure, the display device is a vehicle-mounted display screen.

[0063] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0065] Figure 1 This is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0066] Figure 2 Schematic diagram of the structure of the gating circuit in the display panel of the present disclosure;

[0067] Figure 3 for Figure 2 A timing diagram of each node in a driving method of the gating circuit shown;

[0068] Figure 4 This is a schematic structural diagram of another exemplary embodiment of the display panel disclosed herein;

[0069] Figure 5 This is a schematic structural diagram of another exemplary embodiment of the display panel disclosed herein;

[0070] Figure 6 This is a schematic structural diagram of another exemplary embodiment of the display panel disclosed herein;

[0071] Figure 7 A partial cross-sectional view of an exemplary embodiment of a display panel of the present disclosure. DETAILED DESCRIPTION

[0072] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0073] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0074] like Figure 1 The figure shows a schematic diagram of the structure of an exemplary embodiment of the display panel of the present invention. The display panel may include: a plurality of pixel units Pix, a plurality of data lines Da, a source driver chip SDIC, and a plurality of gating circuits SPOA. The plurality of pixel units Pix are arrayed along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction. The pixel unit Pix includes a plurality of sub-pixels Pz distributed along the first direction X, and the plurality of sub-pixels Pz in the same pixel unit Pix include a first sub-pixel Pz1 and a second sub-pixel Pz2, and the first sub-pixel Pz1 is an anti-peep sub-pixel; the data line Da extends along the second direction Y, and the plurality of data lines Da include a first data line Da1 and a second data line Da2, the first data line Da1 is used to provide data signals to a plurality of first sub-pixels Pz1 distributed in the second direction Y, and the second data line Da2 is used to provide data signals to a plurality of second sub-pixels Pz2 distributed in the second direction Y. No.; the source driver chip SDIC includes multiple data output terminals Dt, which are used to provide data signals; the selection circuit SPOA is corresponding to the data output terminal Dt, and the selection circuit SPOA is corresponding to a group of first data lines Da1 and second data lines Da2 in the same pixel unit Pix, and the selection circuit SPOA is connected to the corresponding data output terminal Dt, the first data line Da1, and the second data line Da2, and the selection circuit SPOA is configured to selectively transmit the data signal output by the data output terminal Dt to the first data line Da1 or the second data line Da2.

[0075] In this exemplary embodiment, the second sub-pixel Pz2 can be a shared sub-pixel. The display panel provided in this exemplary embodiment can select, through a gating circuit SPOA, whether the data output terminal Dt provides a data signal to the anti-peeping sub-pixel or the shared sub-pixel, thereby achieving light emission in the anti-peeping sub-pixel or the shared sub-pixel. Furthermore, the display panel can control the size of the anti-peeping display area in the first direction X. In other words, the display panel can dynamically change the position and width of the anti-peeping area of ​​a long screen. For example, if the display panel uses multiple gating circuits SPOA to select data signals for the anti-peeping sub-pixels in the first through fiftieth columns of pixel units, and simultaneously uses multiple gating circuits SPOA to select data signals for the shared sub-pixels in the fifty-first through one-hundredth columns of pixel units, then the area of ​​the first through fiftieth columns of pixel units forms the anti-peeping display area, and the area of ​​the fifty-first through one-hundredth columns of pixel units forms the shared display area.

[0076] In this exemplary embodiment, the sub-pixel Pz includes a pixel driving circuit and a light-emitting unit. It should be noted that the anti-peeping sub-pixel is a sub-pixel including an anti-peeping light-emitting unit, and the anti-peeping light-emitting unit has an anti-peeping effect, that is, when viewing the display panel at a certain tilt angle, the user cannot see the light emitted by the anti-peeping light-emitting unit in a certain or arbitrary direction; the shared sub-pixel is a sub-pixel including a shared light-emitting unit. Compared with the anti-peeping light-emitting unit, the shared light-emitting unit does not have an anti-peeping effect, that is, when viewing the display panel at a certain tilt angle, the user can see the light emitted by the shared light-emitting unit in any direction.

[0077] It should be understood that in other exemplary embodiments, the second sub-pixel Pz2 may also be an anti-peeping sub-pixel, and the anti-peeping orientations of the first sub-pixel Pz1 and the second sub-pixel Pz2 are different. For example, the anti-peeping orientation of the first sub-pixel Pz1 is on the right, that is, the light emitted by the first sub-pixel Pz1 cannot be seen from the right side of the display panel, and the anti-peeping orientation of the second sub-pixel Pz2 is on the left, that is, the light emitted by the second sub-pixel Pz2 cannot be seen from the left side of the display panel, so that the user can see different display images from the left and right sides of the display panel, that is, the display panel can achieve a dual display effect, and the display panel can use the selection circuit SPOA to control the size of the two display areas in the first direction.

[0078] In this exemplary embodiment, Figure 1 As shown, the display panel may include a display area AA and a frame area BB located on one side of the display area AA in the second direction Y, and the gate circuit SPOA may be located in the frame area BB.

[0079] In this exemplary embodiment, Figure 1As shown, the display panel may further include a chip-on-film (COF) and a printed circuit board (PCB). The source driver chip (SDIC) may be bonded to the COF, which is bonded between the panel and the PCB. The source driver chip (SDIC) may be connected to the gate circuit (SPOA) via traces on the COF. A timing controller (TCON) may be integrated on the PCB, and the timing controller (TCON) may provide a clock signal to the source driver chip (SDIC) via the PCB and the COF. In other exemplary embodiments, the gate circuit (SPOA) may also be bonded to the COF or the PCB.

[0080] In this exemplary embodiment, Figure 2 FIG2 is a schematic diagram of the structure of the gating circuit in the display panel of the present disclosure. The source driver chip SDIC can be configured to output a first reference voltage or a second reference voltage through the data output terminal Dt during the blank period between frames, and to output a data signal through the data output terminal Dt during the frame period. The gating circuit may include: a first gating circuit 11, a second gating circuit 12, and a voltage conversion circuit 13. The first gating circuit 11 is connected to the data output terminal Dt, the first node N1, and the second node N2. The first gating circuit 11 is configured to transmit the first reference voltage or the second reference voltage output by the data output terminal Dt to the first node N1 during the blank period, and to transmit the data signal output by the data output terminal Dt to the second node N2 during the frame period; the second gating circuit 12 is connected to the second node N2, the third node N3, the first data line Da1, and the second data line Da2. The second gating circuit 12 is configured to selectively connect the second node N2 to the first data line Da1 or the second data line Da2 according to the voltage of the third node N3; the voltage conversion circuit 13 is connected to the first node N1 and the third node N3. The voltage conversion circuit 13 is configured to convert the first reference voltage on the first node N1 into a first power supply voltage and transmit the first power supply voltage to the third node N3, or convert the second reference voltage on the first node N1 into a second power supply voltage and transmit the second power supply voltage to the third node N3.

[0081] In this exemplary embodiment, Figure 2 As shown, the first gating circuit 11 can also be connected to the first gate drive signal terminal G1 and the second gate drive signal terminal G2. The first gating circuit 11 is configured to respond to the signal of the first gate drive signal terminal G1 during the blank period to transmit the first reference voltage or the second reference voltage output by the data output terminal Dt to the first node N1, and respond to the signal of the second gate drive signal terminal G2 during the frame period to transmit the data signal output by the data output terminal Dt to the second node N2.

[0082] In this exemplary embodiment, Figure 2As shown, the first gating circuit 11 may include: a first transistor T1 and a second transistor T2. The first electrode of the first transistor T1 is connected to the data output terminal Dt, the second electrode is connected to the first node N1, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the second transistor T2 is connected to the data output terminal Dt, the second electrode is connected to the second node N2, and the gate is connected to the second gate drive signal terminal G2. In this exemplary embodiment, the first transistor T1 may be an N-type transistor, the second transistor T2 may be a P-type transistor, and the first gate drive signal terminal G1 may also be multiplexed as the second gate drive signal terminal. It should be understood that in other exemplary embodiments, the first transistor T1 may also be a P-type transistor, and the second transistor T2 may also be an N-type transistor. In addition, the first transistor T1 and the second transistor T2 may also be both N-type transistors or both P-type transistors.

[0083] In this exemplary embodiment, Figure 2 As shown, the second selection circuit 12 includes: a third transistor T3 and a fourth transistor T4, the first electrode of the third transistor T3 is connected to the second node N2, the second electrode is connected to the first data line Da1, and the gate is connected to the third node N3; the first electrode of the fourth transistor T4 is connected to the second node N2, the second electrode is connected to the second data line Da2, and the gate is connected to the third node N3; wherein, the conduction level polarities of the third transistor T3 and the fourth transistor T4 are opposite.

[0084] In this exemplary embodiment, Figure 2 As shown, the third transistor T3 is an N-type transistor and the fourth transistor T4 is a P-type transistor. It should be understood that in other exemplary embodiments, the third transistor T3 may also be a P-type transistor and the fourth transistor T4 may also be an N-type transistor.

[0085] In this exemplary embodiment, Figure 2As shown, the voltage conversion circuit 13 includes: a connection circuit 131, a reset circuit 132, and a sensitive amplifier circuit 133. The connection circuit 131 is connected to the first power supply terminal VGH and the fourth node N4. The connection circuit 131 is configured to transmit the signal of the first power supply terminal VGH to the fourth node N4 in response to a control signal. The reset circuit 132 is connected to the second power supply terminal VGL, the fifth node N5, and the sixth node N6. The reset circuit 132 is configured to transmit the signal of the second power supply terminal VGL to the fifth node N5 and the sixth node N6 in response to a control signal. The sensitive amplifier circuit 133 is connected to the first node N1, the initial signal terminal Vinit, the fourth node N4, the second power supply terminal VGL, the fifth node N5, and the sixth node N6. The sensitive amplifier circuit 133 is configured to transmit the voltage of the fourth node N4 to the fifth node N5 or the signal of the second power supply terminal VGL to the fifth node N5 based on the magnitude relationship between the voltages on the first node N1 and the initial signal terminal Vinit. The fifth node N5 is connected to the third node N3.

[0086] In this exemplary embodiment, Figure 2 As shown, the connection circuit 131 can also be connected to the third gate drive signal terminal G3. The connection circuit 131 is configured to respond to the signal of the third gate drive signal terminal G3 to transmit the signal of the first power supply terminal VGH to the fourth node N4. The reset circuit 132 can also be connected to the third gate drive signal terminal G3. The reset circuit 132 is configured to respond to the signal of the third gate drive signal terminal G3 to transmit the signal of the second power supply terminal VGL to the fifth node N5 and the sixth node N6. The conduction level polarity of the reset circuit 132 and the connection circuit 131 are opposite. The sensitive amplifier circuit 133 can be configured to: transmit the voltage of the fourth node N4 to the fifth node N5 when the voltage of the first node N1 is greater than the voltage of the initial signal terminal; and transmit the signal of the second power supply terminal VGL to the fifth node N5 when the voltage of the first node N1 is less than the voltage of the initial signal terminal.

[0087] It should be understood that in other exemplary embodiments, the connection circuit 131 and the reset circuit 132 may also be connected to different gate drive signal terminals. Accordingly, the conduction level polarities of the reset circuit 132 and the connection circuit 131 may also be the same.

[0088] In this exemplary embodiment, Figure 2As shown, the voltage conversion circuit 13 may further include: a first inverter 134 and a second inverter 135, wherein the input end of the first inverter 134 is connected to the fifth node N5, and the output end is connected to the seventh node N7; the input end of the second inverter 135 is connected to the seventh node N7, and the output end is connected to the third node N3; wherein, the high-level power supply end of the first inverter 134 is connected to the first power supply end VGH, and the low-level power supply end is connected to the second power supply end VGL, the high-level power supply end of the second inverter 135 is connected to the first power supply end VGH, and the low-level power supply end is connected to the second power supply end VGL, the voltage of the first power supply end VGH is the first power supply voltage, and the voltage of the second power supply end VGL is the second power supply voltage.

[0089] In this exemplary embodiment, Figure 2 As shown, the voltage conversion circuit 13 further includes: a capacitor C, a first electrode of the capacitor C is connected to the first node N1, and a second electrode is connected to a stable voltage terminal. For example, the second electrode of the capacitor C can be connected to the second power supply terminal VGL.

[0090] In this exemplary embodiment, Figure 2As shown, the connection circuit 131 includes: a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is connected to the first power supply terminal VGH, a second electrode is connected to the fourth node N4, and a gate is connected to the third gate drive signal terminal G3. The fifth transistor T5 can be a P-type transistor. The reset circuit 132 includes: a sixth transistor T6 and a seventh transistor T7, wherein a first electrode of the sixth transistor T6 is connected to the second power supply terminal VGL, a second electrode is connected to the sixth node N6, and a gate is connected to the third gate drive signal terminal G3; and a first electrode of the seventh transistor T7 is connected to the second power supply terminal VGL, a second electrode is connected to the fifth node N5, and a gate is connected to the third gate drive signal terminal G3. The sixth transistor T6 and the seventh transistor T7 can be N-type transistors. The sensitive amplifier circuit 133 includes: an eighth transistor T8, a ninth transistor T9, a tenth P-type transistor T10, an eleventh P-type transistor T11, a twelfth N-type transistor T12, and a thirteenth N-type transistor T13. The first electrode of the eighth transistor T8 is connected to the fourth node N4, and the gate is connected to the first node N1; the first electrode of the ninth transistor T9 is connected to the fourth node N4, and the gate is connected to the initial signal terminal Vinit; the first electrode of the tenth P-type transistor T10 is connected to the second electrode of the eighth transistor T8, the second electrode is connected to the sixth node N6, and the gate is connected to the fifth node N5; the first electrode of the eleventh P-type transistor T11 is connected to the second electrode of the ninth transistor T9, The second electrode is connected to the fifth node N5, and the gate is connected to the sixth node N6; the first electrode of the twelfth N-type transistor T12 is connected to the second power supply terminal VGL, the second electrode is connected to the sixth node N6, and the gate is connected to the fifth node N5; the first electrode of the thirteenth N-type transistor T13 is connected to the second power supply terminal VGL, the second electrode is connected to the fifth node N5, and the gate is connected to the sixth node N6; in this exemplary embodiment, the conduction level polarity of the eighth transistor T8 and the ninth transistor is the same. For example, the eighth transistor T8 and the ninth transistor can be P-type transistors. It should be understood that in other exemplary embodiments, the eighth transistor T8 and the ninth transistor T9 can also be N-type transistors. The first inverter 134 may include: a fourteenth P-type transistor T14 and a fifteenth N-type transistor T15, wherein a first electrode of the fourteenth P-type transistor T14 is connected to the first power supply terminal VGH, a second electrode is connected to the seventh node N7, and a gate is connected to the fifth node N5; a first electrode of the fifteenth N-type transistor T15 is connected to the second power supply terminal VGL, a second electrode is connected to the seventh node N7, and a gate is connected to the fifth node N5; the second inverter 135 includes: a sixteenth P-type transistor T16 and a seventeenth N-type transistor T17, wherein a first electrode of the sixteenth P-type transistor T16 is connected to the first power supply terminal VGH, a second electrode is connected to the third node N3, and a gate is connected to the seventh node N7; and a first electrode of the seventeenth N-type transistor T17 is connected to the second power supply terminal VGL, a second electrode is connected to the third node N3, and a gate is connected to the seventh node N7.

[0091] The first power supply terminal VGH may be a high-level power supply terminal, and the second power supply terminal VGL may be a low-level power supply terminal.

[0092] like Figure 3 As shown, Figure 2 The timing diagram of each node in a driving method of the gating circuit shown in the figure. Among them, G1 is the timing diagram of the signal on the first gate drive signal terminal, G2 is the timing diagram of the signal on the second gate drive signal terminal, G3 is the timing diagram of the signal on the third gate drive signal terminal, Dt is the timing diagram of the signal on the data output terminal, and N3 is the timing diagram of the signal on the third node.

[0093] The display panel includes a blank period between frames during the driving process, for example, Figure 3 As shown, the display panel includes a blank period tb2 between the frame period tz1 and the frame period tz2, and a blank period tb1 between the frame period tz1 and the previous frame. The blank period includes a reset phase and a voltage conversion phase. For example, the blank period tb1 includes a reset phase t11 and a voltage conversion phase t12, and the blank period tb2 includes a reset phase t21 and a voltage conversion phase t22.

[0094] like Figure 3 As shown, in the reset phase t11: the third gate drive signal terminal G3 outputs a high level, the sixteenth N-type transistor T16 and the seventeenth N-type transistor T17 are turned on, and the fifth transistor T5 is turned off. The second power supply terminal VGL inputs a low level signal to the fifth node N5 and the sixth node N6.

[0095] During voltage conversion phase t12: the first gate drive signal terminal G1 and the second gate drive signal terminal G2 output a high level, the first transistor T1 is turned on, and the second transistor T2 is turned off. Simultaneously, the data output terminal Dt outputs a first reference voltage. The first reference voltage can be the data signal voltage corresponding to the maximum grayscale of the display panel. The first reference voltage can be greater than the voltage at the initial signal terminal. The data output terminal Dt can input the first reference voltage to the first node N1 via the first transistor T1, and the capacitor C can store the voltage at the first node N1. Furthermore, the third gate drive signal terminal G3 outputs a low level, the fifth transistor T5 is turned on, and the sixteenth N-type transistor T16 and the seventeenth N-type transistor T17 are turned off. Because the first reference voltage is greater than the voltage at the initial signal terminal, the ninth transistor T9 conducts faster than the eighth transistor T8, causing the fifth node N5 to be pulled high first. Simultaneously, the tenth P-type transistor T10 is turned off by the action of the fifth node N5, and the twelfth N-type transistor T12 is turned on by the action of the fifth node N5. The second power supply terminal VGL inputs a low level to the sixth node N6 via the twelfth N-type transistor T12, turning off the thirteenth N-type transistor T13 and turning on the eleventh P-type transistor T11. The high level at the fifth node N5 enters the first inverter 134, causing the first power supply terminal VGH to write the first power supply voltage to the third node N3, turning on the third transistor T3.

[0096] In the frame period tz1: the first gate drive signal terminal G1 and the second gate drive signal terminal G2 output low level, the first transistor T1 is turned off, the second transistor T2 is turned on, and the data output terminal Dt outputs the data signal, so that the data output terminal Dt can provide the data signal to the first data line Da1 through the third transistor T3.

[0097] like Figure 3 As shown, in the reset phase t21, the third gate drive signal terminal G3 outputs a high level, the sixteenth N-type transistor T16 and the seventeenth N-type transistor T17 are turned on, and the fifth transistor T5 is turned off. The second power supply terminal VGL inputs a low level signal to the fifth node N5 and the sixth node N6.

[0098] During voltage conversion phase t22: the first gate drive signal terminal G1 and the second gate drive signal terminal G2 output a high level, the first transistor T1 is turned on, and the second transistor T2 is turned off. Simultaneously, the data output terminal Dt outputs a second reference voltage. The second reference voltage can be the data signal voltage corresponding to the minimum grayscale of the display panel. The second reference voltage can be lower than the voltage at the initial signal terminal. The data output terminal Dt can input the second reference voltage to the first node N1 via the first transistor T1, and the capacitor C can store the voltage at the first node N1. Furthermore, the third gate drive signal terminal G3 outputs a low level, the fifth transistor T5 is turned on, and the sixteenth N-type transistor T16 and the seventeenth N-type transistor T17 are turned off. Because the second reference voltage is lower than the voltage at the initial signal terminal, the conduction speed of the ninth transistor T9 is lower than the conduction speed of the eighth transistor T8. The sixth node N6 is first pulled high, the eleventh P-type transistor T11 is turned off under the influence of the sixth node N6, and the thirteenth N-type transistor T13 is turned on under the influence of the sixth node N6. The second power supply terminal VGL inputs a low level to the fifth node N5 through the thirteenth N-type transistor T13, the twelfth N-type transistor T12 is turned off, and the tenth P-type transistor T10 is turned on. The low level of the fifth node N5 enters the first inverter 134, causing the second power supply terminal VGL to write the second power supply voltage to the third node N3, turning on the fourth transistor T4.

[0099] In the frame period tz2: the first gate drive signal terminal G1 and the second gate drive signal terminal G2 output a low level, the first transistor T1 is turned off, the second transistor T2 is turned on, and the data output terminal Dt outputs a data signal, so that the data output terminal Dt can provide a data signal to the second data line Da2 through the fourth transistor T4.

[0100] In this exemplary embodiment, since the ninth transistor is in a half-on state, in the voltage conversion stage t12, the voltage of the fifth node N5 will be lower than the voltage of the first power supply terminal VGH. Therefore, the first inverter 134 and the second inverter 135 are required to pull the voltage of the third node N3 up to the first power supply voltage.

[0101] It should be understood that in other exemplary embodiments, the voltage conversion circuit 13 may not include the first inverter 134 and the second inverter 135, and the fifth node N5 may be directly connected to the third node N3. Alternatively, the voltage conversion circuit 13 may include only one inverter, with the input of the inverter connected to the fifth node N5 and the output connected to the third node N3. Accordingly, when the data output terminal Dt outputs the first reference voltage during the blank period, the third node N3 outputs a low level, the fourth transistor T4 turns on, and during the frame period, the data output terminal Dt inputs a data signal to the second data line Da2. When the data output terminal Dt outputs the second reference voltage during the blank period, the third node N3 outputs a high level, the third transistor T3 turns on, and during the frame period, the data output terminal Dt inputs a data signal to the first data line Da1.

[0102] like Figure 4 FIG2 is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed herein. A pixel unit Pix may include sub-pixels of multiple colors, with multiple sub-pixels of each color. Multiple sub-pixels of the same color each include a first sub-pixel Pz1 and a second sub-pixel Pz2. For example, a pixel unit Pix may include a first red sub-pixel Pzr1, a second red sub-pixel Pzr2, a first green sub-pixel Pzg1, a second green sub-pixel Pzg2, a first blue sub-pixel Pzb1, and a second blue sub-pixel Pzb2. Accordingly, the pixel unit Pix requires three corresponding gating circuits SPOA.

[0103] like Figure 4 As shown, in the same pixel unit Pix, sub-pixels of different colors are alternately and cyclically distributed along the first direction X. It should be understood that in other exemplary embodiments, the sub-pixels in the pixel unit Pix may also be distributed in other ways.

[0104] For example, Figure 5 FIG2 is a schematic diagram of the structure of another exemplary embodiment of a display panel of the present disclosure. In the same pixel unit Pix, sub-pixels of the same color are adjacently arranged in a first direction.

[0105] like Figure 4 、 Figure 5 As shown, the first data line Da1 and the second data line Da2 connected to the same gating circuit SPOA are used to provide data signals to sub-pixels of the same color. It should be understood that in other exemplary embodiments, the first data line Da1 and the second data line Da2 connected to the same gating circuit SPOA may also have different connection methods. For example, Figure 6FIG2 is a schematic diagram of another exemplary embodiment of a display panel of the present disclosure. The first data line Da1 and the second data line Da2 connected to the same gating circuit SPOA can also be used to provide data signals to sub-pixels of different colors.

[0106] In this exemplary embodiment, Figure 4-Figure 6 The relative position relationship of each sub-pixel unit is shown. In an actual display panel, the projections of the light-emitting unit in a sub-pixel unit and the pixel driving circuit in an adjacent sub-pixel unit along the direction perpendicular to the display panel may partially overlap.

[0107] In this exemplary embodiment, the light emitting units may be arranged in RealRGB, diamond, GGRB or other arrangements.

[0108] like Figure 7 Figure 2 shows a partial cross-sectional view of an exemplary embodiment of a display panel disclosed herein. The display panel may include a base substrate 10 and a shielding layer 22. The shielding layer 22 is located on the side of the pixel unit facing away from the base substrate 10. The orthographic projection of the shielding layer 22 on the base substrate is located on at least one side of the orthographic projection of the pixel opening of the privacy-prevention light-emitting unit on the base substrate. The shielding layer 22 can block light emitted by the privacy-prevention light-emitting unit in a certain direction, thereby achieving an anti-peeping effect. Figure 7 An example of a double-sided anti-peeping structure is given. It should be understood that in other exemplary embodiments, the anti-peeping light-emitting unit can also be a single-sided anti-peeping light-emitting unit. Accordingly, the orthographic projection of the shielding layer 22 on the base substrate is only located on one side of the orthographic projection of the pixel opening of the anti-peeping light-emitting unit on the base substrate. In addition, the anti-peeping effect can also be achieved by other optical devices, which is not limited in this exemplary embodiment.

[0109] like Figure 7 As shown, the display panel may further include a circuit layer 21 . The circuit layer 21 is located between the base substrate 10 and the light emitting unit. The circuit layer 21 may include the above-mentioned pixel driving circuit and gating circuit.

[0110] like Figure 7 As shown, the light emitting unit may include a first electrode 101, a light emitting layer 102, and a common electrode layer 103. The common electrode layer 103 forms the second electrode of the light emitting unit. The light emitting layer 102 is located in a pixel opening formed by a pixel definition layer PDL.

[0111] It should be noted that, in this exemplary embodiment, the first electrode and the second electrode of the transistor serve as its source and drain.

[0112] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, a car display screen, or other display device.

[0113] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0114] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes: A plurality of pixel units, wherein the plurality of pixel units are arrayed along a first direction and a second direction, the first direction and the second direction intersecting, the pixel unit including a plurality of sub-pixels distributed along the first direction, the plurality of sub-pixels in the same pixel unit including a first sub-pixel and a second sub-pixel, the first sub-pixel being an anti-peeping sub-pixel; a plurality of data lines extending along the second direction, the plurality of data lines comprising a first data line and a second data line, the first data line being configured to provide data signals to a plurality of first sub-pixels distributed in the second direction, and the second data line being configured to provide data signals to a plurality of second sub-pixels distributed in the second direction; A source driver chip comprising a plurality of data output terminals, wherein the data output terminals are used to provide the data signals; A plurality of gating circuits are provided, wherein the gating circuits are provided corresponding to the data output terminals, and the gating circuits are provided corresponding to a group of first data lines and second data lines in the same pixel unit, the gating circuits are connected to the corresponding data output terminals, the first data lines, and the second data lines, and the gating circuits are configured to selectively transmit the data signals output from the data output terminals to either the first data lines or the second data lines.

2. The display panel according to claim 1, wherein The source driver chip is configured to output the first reference voltage or the second reference voltage through the data output terminal during a blank period between frames, and output the data signal through the data output terminal during a frame period; The gating circuit comprises: a first gating circuit connected to the data output terminal, the first node, and the second node, wherein the first gating circuit is configured to transmit the first reference voltage or the second reference voltage output by the data output terminal to the first node during the blank period, and to transmit the data signal output by the data output terminal to the second node during the frame period; a second gating circuit connected to the second node, the third node, the first data line, and the second data line, wherein the second gating circuit is configured to selectively connect the second node to the first data line or the second data line according to a voltage of the third node; A voltage conversion circuit is connected to the first node and the third node, and the voltage conversion circuit is configured to convert a first reference voltage on the first node into a first power supply voltage and transmit the first power supply voltage to the third node, or convert a second reference voltage on the first node into a second power supply voltage and transmit the second power supply voltage to the third node.

3. The display panel according to claim 2, wherein: The first gating circuit is also connected to a first gate drive signal terminal and a second gate drive signal terminal. The first gating circuit is configured to respond to a signal at the first gate drive signal terminal during the blank period to transmit the first reference voltage or the second reference voltage output by the data output terminal to the first node, and to respond to a signal at the second gate drive signal terminal during the frame period to transmit the data signal output by the data output terminal to the second node.

4. The display panel according to claim 3, wherein: The first gating circuit includes: a first transistor, having a first electrode connected to the data output terminal, a second electrode connected to the first node, and a gate connected to the first gate drive signal terminal; The second transistor has a first electrode connected to the data output terminal, a second electrode connected to the second node, and a gate connected to the second gate drive signal terminal.

5. The display panel according to claim 2, wherein: The second gating circuit includes: a third transistor, having a first electrode connected to the second node, a second electrode connected to the first data line, and a gate connected to the third node; a fourth transistor, having a first electrode connected to the second node, a second electrode connected to the second data line, and a gate connected to the third node; The conduction level polarities of the third transistor and the fourth transistor are opposite. The display panel according to claim 2 , wherein: The voltage conversion circuit comprises: a communication circuit connecting the first power terminal and the fourth node, wherein the communication circuit is configured to transmit a signal from the first power terminal to the fourth node in response to a control signal; a reset circuit connected to the second power supply terminal, the fifth node, and the sixth node, wherein the reset circuit is configured to transmit a signal from the second power supply terminal to the fifth node and the sixth node in response to a control signal; A sensitive amplifier circuit is connected to the first node, the initial signal terminal, the fourth node, the second power supply terminal, the fifth node, and the sixth node. The sensitive amplifier circuit is configured to transmit the voltage of the fourth node to the fifth node or transmit the signal of the second power supply terminal to the fifth node based on the magnitude relationship between the voltages on the first node and the initial signal terminal. The fifth node is connected to the third node.

7. The display panel according to claim 6, wherein: The communication circuit is further connected to a third gate driving signal terminal, and the communication circuit is configured to transmit the signal of the first power supply terminal to the fourth node in response to the signal of the third gate driving signal terminal; The reset circuit is further connected to the third gate drive signal terminal, and is configured to respond to the signal of the third gate drive signal terminal to transmit the signal of the second power supply terminal to the fifth node and the sixth node, and the conduction level polarity of the reset circuit and the connection circuit is opposite; The sensitive amplifier circuit is configured to: when the voltage of the first node is greater than the voltage of the initial signal terminal, transmit the voltage of the fourth node to the fifth node; when the voltage of the first node is less than the voltage of the initial signal terminal, transmit the signal of the second power supply terminal to the fifth node.

8. The display panel according to claim 6 or 7, wherein: The voltage conversion circuit also includes: a first inverter, an input end of which is connected to the fifth node, and an output end of which is connected to the seventh node; a second inverter, an input end of which is connected to the seventh node, and an output end of which is connected to the third node; The high-level power supply terminal of the first inverter is connected to the first power supply terminal, and the low-level power supply terminal is connected to the second power supply terminal; the high-level power supply terminal of the second inverter is connected to the first power supply terminal, and the low-level power supply terminal is connected to the second power supply terminal; the voltage of the first power supply terminal is the first power supply voltage, and the voltage of the second power supply terminal is the second power supply voltage.

9. The display panel according to claim 6, wherein: The voltage conversion circuit further includes: The capacitor has a first electrode connected to the first node and a second electrode connected to a stable voltage terminal.

10. The display panel according to claim 7, wherein: The communication circuit includes: a fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth node, and a gate connected to the third gate drive signal terminal; The reset circuit comprises: a sixth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the sixth node, and a gate connected to the third gate drive signal terminal; a seventh transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fifth node, and a gate connected to the third gate drive signal terminal; The sensitive amplifier circuit comprises: an eighth transistor, having a first electrode connected to the fourth node and a gate connected to the first node; a ninth transistor, wherein a first electrode is connected to the fourth node, a gate is connected to the initial signal terminal, and the eighth and ninth transistors have the same conduction level polarity; a tenth P-type transistor, having a first electrode connected to the second electrode of the eighth transistor, a second electrode connected to the sixth node, and a gate connected to the fifth node; an eleventh P-type transistor, having a first electrode connected to the second electrode of the ninth transistor, a second electrode connected to the fifth node, and a gate connected to the sixth node; a twelfth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the sixth node, and a gate connected to the fifth node; a thirteenth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fifth node, and a gate connected to the sixth node; The voltage conversion circuit further includes: a first inverter and a second inverter, wherein the first inverter includes: a fourteenth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the seventh node, and a gate connected to the fifth node; a fifteenth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the seventh node, and a gate connected to the fifth node; The second inverter comprises: a sixteenth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the seventh node; The seventeenth N-type transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the third node, and a gate connected to the seventh node.

11. The display panel according to any one of claims 1 to 10, wherein: The second sub-pixel is a shared sub-pixel; Alternatively, the second sub-pixel is an anti-peeping sub-pixel, and the anti-peeping orientations of the first sub-pixel and the second sub-pixel are different.

12. The display panel according to any one of claims 1 to 10, wherein: The pixel unit includes sub-pixels of multiple colors, each color has multiple sub-pixels, and the multiple sub-pixels of the same color all include the first sub-pixel and the second sub-pixel.

13. The display panel according to claim 12, wherein: In the same pixel unit, sub-pixels of different colors are alternately and cyclically distributed along the first direction; Alternatively, in the same pixel unit, sub-pixels of the same color are adjacently arranged in the first direction.

14. The display panel according to any one of claims 1 to 10, wherein: The first data line and the second data line connected to the same gating circuit are used to provide data signals to sub-pixels of the same color; Alternatively, the first data line and the second data line connected to the same gating circuit are respectively used to provide data signals to sub-pixels of different colors.

15. A display device, wherein: The display device comprises a plurality of display panels according to any one of claims 1 to 14.

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