Method for detecting crosstalk among multiple rows of memory

Abstract

The invention provides a method for detecting crosstalk among multiple rows of a memory, which comprises the following steps of: providing the memory, and performing erasing operation on all memory units in a memory unit array. Performing read operation on all the erased storage units; in the reading operation, external sink current is provided to serve as reference current of the storage unit; the read operation obtains a read current of the memory cell. If the ratio of the read current to the reference current is larger than the selected ratio gear, it is judged that crosstalk failure exists in the storage unit, and the storage unit is removed. The external sink current is used for supplying power, the external sink current is not influenced by crosstalk among multiple rows of the memory, and the external sink current can also provide stable current when crosstalk exists; and through a mode of screening large gears, namely, judging that the ratio of the read current to the external input reference current is greater than the selected ratio gear, the storage unit with the crosstalk defect is screened out. Under the requirement of low PPM pursuing of automobile specification products and white electricity, the product quality can be better improved by applying the test mode, and the product competitiveness is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for detecting crosstalk between multiple rows of a memory. Background Art

[0002] With the development of the electronics market, memory has been widely used in products such as mobile phones and digital cameras, and the market size is continuously expanding. Data crosstalk is one of the main failure factors of all non-volatile memories. Practical testing solutions for split-gate flash memory screen for row crosstalk, column crosstalk, and read crosstalk, but there is no effective test solution for failures caused by crosstalk between multiple rows. In actual applications, non-volatile memories in automotive and white goods applications experience crosstalk failures between multiple rows at the ppm (parts per million) level, necessitating effective testing methods to detect memories at risk of failure. Summary of the Invention

[0003] The present invention aims to provide a method for detecting crosstalk between multiple rows of memory. The method utilizes an external current supply, which is unaffected by crosstalk between rows and provides a stable current even when crosstalk is present. By ensuring that the ratio of the read current to the reference current is greater than a selected ratio level, memory cells with crosstalk defects are screened out. This method can significantly improve product quality and enhance product competitiveness, as automotive and consumer electronics pursue low PPM requirements.

[0004] The present invention provides a method for detecting crosstalk between multiple rows of a memory, comprising:

[0005] Step S1, providing a memory, wherein the memory includes a memory cell array, wherein the memory cell array includes a plurality of memory cells arranged in an array; performing an erasing operation on all memory cells in the memory cell array, wherein after erasing, the storage bits of all the memory cells are all 1;

[0006] Step S2, performing a read operation on all the erased memory cells; in the read operation, providing an external input current Iout as a reference current Iref of the memory cell; and obtaining a read current Icell of the memory cell through the read operation;

[0007] Step S3: If the ratio of the read current Icell to the reference current Iref is greater than the selected ratio level, it is determined that the memory cell has a crosstalk failure, and the memory cell is removed.

[0008] Furthermore, in step S2, the read current obtained by the read operation is a drain read current of the memory cell after programming or erasing at a certain voltage.

[0009] Furthermore, in step S2, the read operation uses a read circuit to apply a certain read voltage to the memory cell, compares the read current with the reference current through a sense amplifier, and then outputs the comparison result at the output terminal.

[0010] Furthermore, in step S2, the external injection current is N times the normal read current of the memory cell; 1≤N≤2.

[0011] Furthermore, in step S3, the selected ratio gear can be any percentage value between 50% and 100%.

[0012] Furthermore, in step S3, the selected ratio gear is set to 100%.

[0013] Furthermore, in step S3, the selected ratio gear is set to 90% or 95%.

[0014] Furthermore, the memory includes: non-volatile memory flash memory.

[0015] Furthermore, the crosstalk includes at least one of read crosstalk, write crosstalk and erase crosstalk between multiple rows.

[0016] Furthermore, in step S3, if the ratio of the read current to the reference current is less than or equal to the selected ratio level, it is determined that the crosstalk test of the memory cell is qualified.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention provides a method for detecting crosstalk between multiple rows of a memory, comprising: S1, providing a memory, performing an erasing operation on all memory cells in a memory cell array, and after erasing, the storage bits of all memory cells are all 1; S2, performing a read operation on all erased memory cells; in the read operation, providing an external injection current as a reference current for the memory cell; the read operation obtains the read current of the memory cell; S3, if the ratio of the read current to the reference current is greater than a selected ratio gear, then it is determined that the memory cell has a crosstalk failure, and the memory cell is removed. The present invention adopts an external injection current for power supply, and the external injection current is not affected by the crosstalk between multiple rows of the memory. When crosstalk exists in the memory, the external injection current can also provide a stable current; and by screening a large gear, that is, judging that the ratio of the read current to the external injection reference current is greater than the selected ratio gear, the memory cell with crosstalk defects is screened out. Under the demand for low PPM for automotive products and white goods, the use of this test method can better improve product quality and enhance product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of memory failure.

[0020] Figure 2 A schematic diagram of a memory having read crosstalk.

[0021] Figure 3 A schematic diagram of write crosstalk in a memory.

[0022] Figure 4 2 is a flow chart of a method for detecting crosstalk between multiple rows of a memory according to an embodiment of the present invention.

[0023] Figure 5 Schematic diagram of memory reading principle in a method for detecting crosstalk between multiple rows of a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] As described in the background art, it is found in actual applications that non-volatile memories suffer from crosstalk failures between multiple rows at the ppm (parts per million) level.

[0025] Specifically, such as Figure 1 As shown in Figure 1, after erasing, the mth row (X=593, rows 592 to 607) is invalid. The first red row indicates that the read current Ir1 of the mth row is obviously abnormal, and the second red row indicates that the reference current Iref of the mth row is obviously abnormal. After erasing, the nth row (X=721, rows 720 to 735) is invalid. Figure 1 The first green row indicates normal read current Ir1 in row n, and the second green row indicates normal reference current Iref in row n. Regardless of row m or row n, the ratio of read current to reference current is approximately 100%. Existing methods that use ratios below a certain level cannot detect abnormalities in, for example, row m.

[0026] like Figure 2 As shown, only the even-numbered column bytes in row n (X=721, rows 720-735) were programmed. The read current Ir1 for the corresponding even-numbered column bytes in row m (X=593, rows 592-607) was found to be halved, returning to normal. Therefore, the approximately 66 μA read current Ir1 in row m is due to read crosstalk from the corresponding columns in row n.

[0027] like Figure 3 As shown, after the chips of row n (X=721, rows 720-735) and row m (X=593, rows 592-607) are erased, only the even columns of row 593 are programmed to write 0, and it is found that the even columns corresponding to row n are also programmed to write 0 at the same time; thus, it can be judged that row 593 also generates write crosstalk to row n.

[0028] In-depth research and analysis revealed that when both the first-stage and second-stage driver circuits of a memory device are at 1, the logic of the selected word line in row n (X=721, rows 720-735) is always 1. This indicates that the corresponding driver transistor has a process defect, causing it to be normally open. Therefore, effective testing methods are needed to detect memory devices at risk of failure.

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0030] For ease of description, some embodiments of the present application may use spatially relative terms such as "above," "below," "top," "below," etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that, in addition to the orientations described in the figures, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the figures is turned over, the elements or components described as being "below" or "beneath" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first," "second," etc., hereinafter, are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It is to be understood that, where appropriate, these terms used in this manner are interchangeable.

[0031] The embodiment of the present invention provides a method for detecting crosstalk between multiple rows of a memory, such as Figure 4 Shown, including:

[0032] Step S1, providing a memory, the memory including a memory cell array, the memory cell array including a plurality of memory cells arranged in an array; performing an erasing operation on all memory cells in the memory cell array, so that after erasing, the storage bits of all memory cells are all 1;

[0033] Step S2, performing a read operation on all erased memory cells; in the read operation, providing an external input current Iout as a reference current Iref of the memory cell; and obtaining a read current Icell of the memory cell by the read operation;

[0034] Step S3: If the ratio of the read current Icell to the reference current Iref is greater than the selected ratio level, it is determined that the memory cell has a crosstalk failure and the memory cell is removed.

[0035] The following describes in detail the steps of the method for detecting crosstalk between multiple rows of a memory according to an embodiment of the present invention.

[0036] Step S1, providing a memory, the memory including a memory cell array, the memory cell array including a plurality of memory cells arranged in an array; performing an erase operation on all memory cells in the memory cell array, and after erasing, the storage bits of all memory cells are all 1. The memory cell of the memory is, for example, a MOS transistor with a floating gate structure, and the working principle is to store or release data by injecting or releasing charge into the floating gate to change the threshold voltage of the memory cell. The erasing process is to apply a reverse voltage to the control gate and the substrate, and pull the charge out of the floating gate through the tunnel effect. Programming "0" is to inject charge into the floating gate through the channel effect by applying a voltage to the control gate and the bit line. By applying different working voltages to the word line, control gate, source line and bit line, each memory cell can be read, programmed (written) and erased.

[0037] Step S2: Perform a read operation on all erased memory cells. During the read operation, an external current Iout is provided as a reference current Iref for the memory cell. The read operation obtains a read current Icell of the memory cell. For example, the read current Icell of memory cells in memory cell arrays on the same platform is substantially the same, approximately 35 μA.

[0038] Specifically, such as Figure 5 As shown, the read operation obtains the read current Icell corresponding to each of the memory cells to be tested. The read current Icell can be understood as the drain read current of the memory cell after programming or erasing at a certain voltage. The read operation can use a read circuit to apply a certain read voltage V to the memory cell M0, compare the read current Icell of the memory cell M0 with the reference current Iref through the sense amplifier, and then output the comparison result at the output terminal Do. In the erase mode, an external current Iout is provided as the reference current Iref of the memory cell. The external current Iout is N times the normal read current I of a normal memory cell; 1≤N≤2, Iout=I*N.

[0039] In memory design, read current, reference current, and external current are three interrelated and important concepts that collectively determine the memory's read reliability, speed, and power consumption characteristics. Read current refers to the current flowing out of a memory cell during a read operation and is used to determine the data state (0 or 1) stored in the cell. Reference current is a baseline current used for comparison with the read current and is typically set to a value midway between the two storage state currents. External current is a bias current applied externally to the memory cell to establish read conditions or assist in state determination. Key functions of external current include: providing read bias (powering the memory cell), enhancing sensitivity (increasing the read current signal), and providing a stable power supply to prevent read interference current sources. The external current must be sufficiently stable to minimize the effects of noise.

[0040] Typically, a built-in original reference current is used as the reference current. However, actual testing reveals that when crosstalk occurs between multiple rows of memory, the built-in original reference current is also disturbed and changes. Therefore, due to the interference, the built-in original reference current can no longer be used as the reference current. The present invention uses an external current supply, which is not affected by crosstalk between multiple rows of memory. Even when crosstalk occurs in the memory, the external current can still provide a stable current. The present invention provides an external current Iout as the reference current Iref (reference current) of the memory cell.

[0041] Step S3: If the ratio of the read current Icell to the reference current Iref is greater than the selected ratio level, it is determined that the memory cell has a crosstalk failure and the memory cell is removed. Specifically, the selected ratio level can be any percentage value between 50% and 100%. In one example, the selected ratio level is set to 100%. In another example, the selected ratio level is set to 90% or 95%. If the ratio of the read current to the reference current is less than or equal to the selected ratio level, it is determined that the crosstalk item test of the memory cell is qualified. Crosstalk includes at least one of read crosstalk, write crosstalk and erase crosstalk between multiple rows.

[0042] Currently, when memories are screened against an all-1 background after erasure, they primarily screen for bits with low current. Crosstalk occurs across multiple rows of addresses, causing abnormally high read currents in the read current Icell. Using the ratio of the read current Icell to the built-in original reference current as previously improved will not work. For example, the normal read current Icell is 35μA, and the abnormal read current Icell of the row with crosstalk is 66μA, but the built-in original reference current of that row is also changed to 66μA by crosstalk. The ratio of the abnormal read current Icell to the built-in original reference current = 66 / 66, which is still 100%. Since the Icell / Iref corresponding to many normal bits is also around 100%, screening with a ratio less than or greater than 100% is also not possible.

[0043] The present invention innovates a test scheme for the failure of crosstalk between multiple rows caused by defects in row driving of non-volatile flash memory. The reference current does not use the built-in original reference current. The reference current uses an external injection current, that is, the external injection current Iout as the reference current Iref. This is equivalent to fixing the reference current Iref of all rows. The read current Icell satisfies the normal distribution. In order to avoid mistakenly killing a bit that is too large, the external injection current is set to a certain multiple of the read current I of the normal bit. The external injection current Iout is N times the normal read current I of a normal storage cell, Iout = I*N. For example, Iout = I*1.5 = 35*1.5 = 52.5μA, the reference current Iref is about 52.5μA, and I is the read current of a normal storage cell, that is, a normal bit. The read current of the abnormal bit in the row where crosstalk occurs is approximately 66μA. The ratio of read current to reference current = 66μA / 52.5μA = 126%. By adopting a large-scale screening method, bits with a ratio greater than 100% can be screened out. If the ratio of read current Icell to reference current Iref is greater than the selected ratio level (e.g., 100%), the memory cell is determined to have a crosstalk failure and is removed.

[0044] In summary, the present invention provides a method for detecting crosstalk between multiple rows of a memory, including: S1, providing a memory, performing an erase operation on all memory cells in a memory cell array, and after erasing, the storage bits of all memory cells are all 1; S2, performing a read operation on all erased memory cells; in the read operation, providing an external injection current as a reference current for the memory cell; the read operation obtains the read current of the memory cell; S3, if the ratio of the read current to the reference current is greater than the selected ratio gear, it is determined that the memory cell has a crosstalk failure, and the memory cell is removed. The present invention adopts an external injection current for power supply, and the external injection current is not affected by the crosstalk between multiple rows of the memory. When crosstalk exists in the memory, the external injection current can also provide a stable current; and by screening a large gear, that is, judging that the ratio of the read current to the external injection reference current is greater than the selected ratio gear, the memory cell with crosstalk defects is screened out. Under the demand for low PPM for automotive products and white goods, the use of this test method can better improve product quality and enhance product competitiveness.

[0045] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The methods disclosed in the embodiments are described briefly because they correspond to the devices disclosed in the embodiments. For relevant details, refer to the method description.

[0046] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for detecting crosstalk between multiple rows of a memory, characterized in that: include: Step S1, providing a memory, wherein the memory includes a memory cell array, and the memory cell array includes a plurality of memory cells arranged in an array; Performing an erasing operation on all the memory cells in the memory cell array, so that after erasing, the storage bits of all the memory cells are all 1; Step S2, performing a read operation on all the erased memory cells; in the read operation, providing an external input current Iout as a reference current Iref of the memory cell; and obtaining a read current Icell of the memory cell through the read operation; Step S3: If the ratio of the read current Icell to the reference current Iref is greater than the selected ratio level, it is determined that the memory cell has a crosstalk failure, and the memory cell is removed.

2. The method for detecting crosstalk between multiple rows of a memory according to claim 1, wherein: In step S2, the read current obtained by the read operation is a drain read current of the memory cell after programming or erasing at a certain voltage.

3. The method for detecting crosstalk between multiple rows of a memory according to claim 1, wherein: In step S2 , the read operation uses a read circuit to apply a certain read voltage to the memory cell, compares the read current with the reference current through a sense amplifier, and then outputs the comparison result at the output terminal.

4. The method for detecting crosstalk between multiple rows of a memory according to claim 1, wherein: In step S2, the external injection current is N times the normal read current of the memory cell; 1 <N≤2。 5. The method for detecting crosstalk between multiple rows of a memory according to claim 1, wherein: In step S3, the selected ratio gear can be any percentage value between 50% and 100%.

6. The method for detecting crosstalk between multiple rows of a memory according to claim 5, wherein: In step S3, the selected ratio gear is set to 100%.

7. The method for detecting crosstalk between multiple rows of a memory according to claim 5, wherein: In step S3, the selected ratio gear is set to 90% or 95%.

8. The method for detecting crosstalk between multiple rows of a memory according to claim 1, wherein: The memory includes: a non-volatile memory flash memory.

9. The method for detecting crosstalk between multiple rows of a memory according to claim 1, wherein: The crosstalk includes at least one of read crosstalk, write crosstalk and erase crosstalk between multiple rows.

10. The method for detecting crosstalk between multiple rows of a memory according to claim 1, wherein: In step S3, if the ratio of the read current to the reference current is less than or equal to the selected ratio level, it is determined that the crosstalk test of the memory cell is qualified.

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