Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of suppressing the occurrence of interfacial peeling while suppressing a decrease in capacitance even in a multilayer ceramic capacitor of a high withstand voltage specification. In a multilayer ceramic capacitor (1), a plurality of internal electrode layers include a first internal electrode layer (31), a second internal electrode layer (32), and an intermediate electrode layer (33), and the coverage rate of the intermediate electrode layer (33) is higher than the coverage rate of the first internal electrode layer (31) and the coverage rate of the second internal electrode layer (32).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, as a multilayer ceramic capacitor having a high withstand voltage, a multilayer ceramic capacitor having a structure in which a plurality of capacitor portions are connected in series (so-called series structure) is known (see Patent Document 1).

[0003] Regarding stacked ceramic capacitors with a series structure, the voltage resistance is improved because a series connection capacitor is formed. On the other hand, there is a tendency for the capacitance to decrease. Therefore, as a countermeasure to maintain the capacitance, measures such as increasing the number of stacked internal electrode layers and dielectric layers can be taken.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2012-209495

[0007] However, increasing the number of stacked internal electrode layers and dielectric layers increases the internal stress caused by the difference in shrinkage between the dielectric layers and the internal electrode layers, which may result in delamination at the interface between the internal electrode layers and the dielectric layers. Summary of the Invention

[0008] Problems to be solved by the invention

[0009] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing a decrease in electrostatic capacitance and preventing the occurrence of interface delamination even in a multilayer ceramic capacitor with a high withstand voltage specification.

[0010] Technical solutions to solve problems

[0011] The multilayer ceramic capacitor of the present invention comprises: a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode arranged on the first end surface; and a second external electrode arranged on the second end surface, the plurality of internal electrode layers including a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer, the first internal electrode layer having a first lead portion having one end portion extending to the first end surface and connected to the first external electrode; and a first opposing portion connected to the first lead portion and opposed to the internal electrode layer arranged adjacent to the stacking direction, the second internal electrode layer having: a second lead portion, one end of which is led to the second end face and connected to the second external electrode; and a second opposing portion connected to the second lead portion and opposed to the internal electrode layer arranged adjacent to the stacking direction, the intermediate electrode layer is an internal electrode layer that is neither connected to the first external electrode nor to the second external electrode and forms a capacitor element connected in series with the first internal electrode layer and the second internal electrode layer, and the coverage of the intermediate electrode layer is higher than the coverage of the first internal electrode layer and the coverage of the second internal electrode layer.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing a decrease in electrostatic capacitance and preventing the occurrence of interface delamination even in a multilayer ceramic capacitor with a high withstand voltage specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a perspective view of the external appearance of a double-structured multilayer ceramic capacitor according to the first embodiment.

[0015] Figure 2 yes Figure 1 The II-II cross-sectional view is a diagram for explaining the schematic structure of the double-structured stacked body according to the first embodiment.

[0016] Figure 3 yes Figure 2 Sectional view III-III.

[0017] Figure 4A yes Figure 2 The IVA-IVA cross-sectional view is a cross-sectional view taken along the first internal electrode layer and the second internal electrode layer.

[0018] Figure 4B yes Figure 2The IVB-IVB cross-sectional view is a cross-sectional view along the middle electrode layer.

[0019] Figure 5 This is a schematic cross-sectional view for explaining a structure in which the coverage of the internal electrode layers of the multilayer ceramic capacitor according to the first embodiment is improved by the intermediate electrode layer.

[0020] Figure 6 This is a schematic cross-sectional view for explaining a structure in which the coverage of the internal electrode layers of the multilayer ceramic capacitor according to the second embodiment is improved by the intermediate electrode layer.

[0021] Figure 7 This is a schematic cross-sectional view for explaining a structure in which the coverage of the internal electrode layers of the multilayer ceramic capacitor according to the third embodiment is improved by the intermediate electrode layer.

[0022] Description of Reference Numerals

[0023] 1: Multilayer ceramic capacitor;

[0024] 10: laminate;

[0025] 20: dielectric layer;

[0026] 30: internal electrode layer;

[0027] 31: first internal electrode layer;

[0028] 32: second internal electrode layer;

[0029] 33: middle electrode layer;

[0030] 40A: 1st external electrode;

[0031] 40B: second external electrode;

[0032] D1: first lead;

[0033] D2: second lead;

[0034] EA: 1st opposing part;

[0035] EB: second opposing part;

[0036] L: length direction;

[0037] LS1: 1st end face;

[0038] LS2: 2nd end face;

[0039] T: stacking direction;

[0040] TS1: 1st main surface;

[0041] TS2: 2nd main surface;

[0042] W: width direction;

[0043] WS1: side 1;

[0044] WS2: Side 2. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto.

[0046] <First embodiment>

[0047] A multilayer ceramic capacitor 1, a dual-structured multilayer ceramic electronic component according to a first embodiment of the present disclosure, will be described with reference to the accompanying drawings. Multilayer ceramic capacitor 1 of this embodiment is a capacitor for temperature compensation, having a low rate of change in capacitance due to temperature changes, and is used for matching filters and high-frequency circuits. However, multilayer ceramic capacitor 1 of the present disclosure is not limited to this embodiment. Figure 1 1 is a perspective view of the external appearance of a double-structured multilayer ceramic capacitor 1 according to the first embodiment. Figure 2 yes Figure 1 The II-II cross-sectional view is a diagram for explaining the schematic structure of the double-structured stacked body according to the first embodiment. Figure 3 yes Figure 2 Sectional view III-III. Figure 4A yes Figure 2 The IVA-IVA cross-sectional view is a cross-sectional view taken along the first internal electrode layer and the second internal electrode layer. Figure 4B yes Figure 2 The IVB-IVB cross-sectional view is a cross-sectional view along the middle electrode layer.

[0048] In addition, in order to illustrate the content of the invention, the drawings are sometimes simplified and drawn schematically, and sometimes the ratios of the dimensions of the drawn components or the dimensions between the components are inconsistent with the ratios of these dimensions described in the specification. In addition, there are cases where the components described in the specification are omitted in the drawings, or the number of components is omitted in the drawings. For example, for the convenience of explanation, Figure 2 、 Figure 3 The number of internal electrode layers described in FIG is 7, but this does not indicate the actual number of internal electrode layers 30. Figures 5 to 7 Furthermore, the shapes, geometric conditions, terms that define their degree (e.g., terms such as “parallel,” “orthogonal,” and “same”), lengths, angle values, etc. used in the present invention are not to be construed in a strict sense, but are to be interpreted within a range that encompasses the degree to which the same function can be expected.

[0049] like Figure 1 As shown, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape and includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 so as to be spaced apart from each other.

[0050] exist Figure 1 In FIG. 1 , arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the multilayer body 10. The stacking direction T is also the thickness direction and height direction of the multilayer ceramic capacitor 1 and the multilayer body 10. Figure 1 In FIG. 1 , arrow L indicates the longitudinal direction of the multilayer ceramic capacitor 1 and the multilayer body 10 perpendicular to the stacking direction T. Figure 1 In FIG, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10 , which is perpendicular to the lamination direction T and the longitudinal direction L. The pair of external electrodes 40 are respectively arranged at one end and the other end of the laminate 10 in the longitudinal direction L.

[0051] exist Figures 1 to 4B In FIG, an XYZ orthogonal coordinate system is shown. The length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3 The cross section shown is also referred to as the WT cross section. Figure 4A as well as Figure 4B The cross section shown is also referred to as the LW cross section.

[0052] like Figures 1 to 4B As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W perpendicular to the stacking direction T and the length direction L.

[0053] like Figure 1 As shown, the laminate 10 has a generally rectangular parallelepiped shape. Furthermore, the dimension of the laminate 10 in the longitudinal direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is where three surfaces of the laminate intersect, and a ridge is where two surfaces of the laminate intersect. Furthermore, concavities and convexities may be formed on part or all of the surface constituting the laminate 10.

[0054] The dimensions of the laminate 10 are not particularly limited. However, if the dimension in the longitudinal direction L of the laminate 10 is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. Furthermore, if the dimension in the stacking direction T of the laminate 10 is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. Furthermore, if the dimension in the width direction W of the laminate 10 is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0055] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the lamination direction T so as to sandwich the inner layer portion 11 .

[0056] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in a stacking direction T. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 and the internal electrode layer 30 located closest to the second main surface TS2 in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0057] The plurality of dielectric layers 20 are composed of a dielectric material. As described above, the multilayer ceramic capacitor 1 according to this embodiment is a temperature-compensating capacitor, and the dielectric material is a CaZrO3-based (hereinafter sometimes referred to as CZ-based) or Ca(Sr,Zr)O3-based (hereinafter sometimes referred to as CSZ-based) dielectric material. CZ-based and CSZ-based dielectric materials contain perovskite-type compounds containing at least Ca and Zr. CZ-based dielectric materials contain not only CaZrO3 but also a CaZrO3 solid solution in which a portion of Ca, a portion of Zr, or a portion of Ca and Zr are replaced with appropriate elements. The dielectric material contains at least one of Ca (calcium), Zr (zirconium), and Ti (titanium). As an example, the dielectric layer 20 contains a perovskite-type compound containing Ca, Zr, and optionally Sr and Ti. Specifically, dielectric layer 20 contains CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), titanium oxide (TiO2), and other materials. While multilayer ceramic capacitors 1 typically generate oxygen vacancies due to firing in a reducing atmosphere, CaZrO3, in particular, suppresses the generation of oxygen vacancies due to its high band gap. This results in high reliability. Alternatively, the dielectric material may be a material containing additives such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0058] The dielectric layer 20 of this embodiment uses a material containing at least one of Ca (calcium), Zr (zirconium), and Ti (titanium). This results in a relative dielectric constant of approximately 20 to 300, resulting in lower capacitance than high-dielectric-constant materials. Furthermore, the dielectric layer 20 of this embodiment exhibits a characteristic in which the relative dielectric constant changes approximately linearly with temperature, resulting in excellent heat resistance and high-frequency characteristics. Furthermore, the capacitance value of the dielectric layer 20 of this embodiment exhibits negligible temporal variation, resulting in minimal capacitor loss even at high temperatures, high power, and high frequencies, resulting in excellent stability. Furthermore, the dielectric constant of the dielectric layer 20 exhibits minimal temporal variation and variation due to applied voltage. Furthermore, the dielectric material is not limited to this; for example, high-dielectric-constant ceramics such as BaTiO3 (BT) can also be used.

[0059] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The thickness of the dielectric layer 20 is particularly preferably 3 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in each of the first main surface-side outer layer portion 12 and the second main surface-side outer layer portion 13.

[0060] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31, a plurality of second internal electrode layers 32, and an intermediate electrode layer 33. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other in a spaced-apart manner in the longitudinal direction L, and the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layers 33 are alternately arranged in the stacking direction T with the dielectric layer 20 interposed therebetween.

[0061] The first internal electrode layer 31 extends to the first end surface LS1 and is connected to the first external electrode 40A, described later. The second internal electrode layer 32 extends to the second end surface LS2 and is connected to the second external electrode 40B, described later. The intermediate electrode layer 33 extends neither to the first end surface LS1 nor to the second end surface LS2, and is neither connected to the first external electrode 40A nor to the second external electrode 40B, described later. The first internal electrode layer 31, the intermediate electrode layer 33, and the second internal electrode layer 32 included in the plurality of internal electrode layers 30 form a capacitor element connected in series. In the following description, when it is unnecessary to distinguish between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be collectively referred to as the internal electrode layer 30.

[0062] like Figure 2 、 Figure 4AAs shown, the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1. The first opposing portion EA is a region that faces the intermediate electrode layer 33 adjacently arranged in the stacking direction T, sandwiching the dielectric layer 20 therebetween. It is located within the stacked body 10. The first internal electrode layer 31 has a first opposing portion EA that is connected to the first lead portion D1 and faces the internal electrode layer 30 adjacently arranged in the stacking direction T. The first lead portion D1 is a portion that extends from the first opposing portion EA toward the first end surface LS1 and is exposed at the first end surface LS1. The first internal electrode layer 31 has a first lead portion D1, one end of which is extended to the first end surface LS1 and connected to the first external electrode 40A.

[0063] like Figure 2 、 Figure 4A As shown, the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2. The second opposing portion EB is a region that faces the intermediate electrode layer 33 disposed adjacent in the stacking direction T, sandwiching the dielectric layer 20 therebetween. It is located within the stacked body 10. The second internal electrode layer 32 has a second opposing portion EB that is connected to the second lead portion D2 and faces the internal electrode layer 30 disposed adjacent in the stacking direction T. The second lead portion D2 extends from the second opposing portion EB toward the second end surface LS2 and is exposed at the second end surface LS2. The second internal electrode layer 32 has a second lead portion D2, one end of which is extended to the second end surface LS2 and connected to the second external electrode 40B.

[0064] like Figure 2 、 Figure 4B As shown, the intermediate electrode layer 33 includes a first electrode layer side opposing portion ECA, a second electrode layer side opposing portion ECB, and a connecting portion E0. The first electrode layer side opposing portion ECA is a region that faces the first internal electrode layer 31, which is adjacently arranged in the stacking direction T, with the dielectric layer 20 interposed therebetween, and is located within the laminate 10. The second electrode layer side opposing portion ECB is a region that faces the second internal electrode layer 32, which is adjacently arranged in the stacking direction T, with the dielectric layer 20 interposed therebetween, and is located within the laminate 10. The connecting portion E0 connects the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and is located between the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB.

[0065] In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the first end face LS1 side is disposed apart from the first end face LS1. In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the first end face LS1 side is disposed closer to the first end face LS1 than the end portion 40AE of the first external electrode 40A. However, this is not limiting; the end portion of the intermediate electrode layer 33 on the first end face LS1 side may also be disposed closer to the second end face LS2 than the end portion 40AE of the first external electrode 40A.

[0066] The end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed apart from the second end face LS2. In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed closer to the second end face LS2 than the end portion 40BE of the second external electrode 40B. However, this is not limiting; the end portion of the intermediate electrode layer 33 on the second end face LS2 side may also be disposed closer to the first end face LS1 than the end portion 40BE of the second external electrode 40B.

[0067] like Figure 2 As shown, in the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other in the longitudinal direction L. In the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layers 33 are stacked so as to overlap alternately with the dielectric layers 20 interposed therebetween.

[0068] In this embodiment, the first opposing portion EA and the first electrode layer-side opposing portion ECA oppose each other via the dielectric layer 20, thereby forming capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33, including the first electrode layer-side opposing portion ECA, oppose each other via the dielectric layer 20, thereby forming capacitance CAP2 (second capacitor portion CAP2). The connecting portion E0 connects capacitance CAP1 and capacitance CAP2 in series. The multilayer ceramic capacitor 1 of this embodiment has a so-called two-combination structure, a serial structure in which two capacitor portions are connected in series.

[0069] The shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion ECA, and the second electrode layer side opposing portion ECB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion D1 and the second lead portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shape of the connecting portion E0 is not particularly limited, but is preferably rectangular.

[0070] The dimension in the width direction W of the first opposing portion EA and the dimension in the width direction W of the first lead portion D1 can be the same, or either dimension can be smaller. The dimension in the width direction W of the second opposing portion EB and the dimension in the width direction W of the second lead portion D2 can be the same, or either dimension can be narrower. The dimension in the width direction W of the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and the dimension in the width direction W of the connecting portion E0 can be the same, or either dimension can be smaller.

[0071] The first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are formed of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be formed of, for example, an Ag-Pd alloy.

[0072] The thickness of each of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is preferably 0.2 μm to 2.0 μm, for example. The total number of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is preferably 15 to 1000.

[0073] like Figure 2 as well as Figure 3 As shown, the first principal surface-side outer layer portion 12 is located on the first principal surface TS1 side of the laminate 10. The first principal surface-side outer layer portion 12 is a collection of multiple dielectric layers 20 located between the first principal surface TS1 and the internal electrode layer 30 closest to the first principal surface TS1. On the other hand, the second principal surface-side outer layer portion 13 is located on the second principal surface TS2 side of the laminate 10. The second principal surface-side outer layer portion 13 is a collection of multiple dielectric layers 20 located between the second principal surface TS2 and the internal electrode layer 30 closest to the second principal surface TS2. The dielectric layers 20 used in the first principal surface-side outer layer portion 12 and the second principal surface-side outer layer portion 13 may be the same as the dielectric layers 20 used in the internal layer portion 11.

[0074] In addition, the stacked body 10 has a series capacitor forming portion 11E. The series capacitor forming portion 11E includes a portion where the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33 oppose each other (a portion forming the electrostatic capacitor CAP1), a portion where the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 oppose each other (a portion forming the electrostatic capacitor CAP2), and a portion connecting the electrostatic capacitor CAP1 and the electrostatic capacitor CAP2 in series. The series capacitor forming portion 11E is configured as a portion of the inner layer portion 11. Figure 4A as well as Figure 4B , the range of the series capacitor forming portion 11E in the width direction W and the length direction L is shown. The portion forming the electrostatic capacitance CAP1 (first capacitor portion CAP1) and the portion forming the electrostatic capacitance CAP2 (second capacitor portion CAP2) in the series capacitor forming portion 11E are also referred to as capacitor effective portions.

[0075] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion includes a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the series capacitor forming portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the series capacitor forming portion 11E and the second side WS2. Figure 3 、 Figure 4A as well as Figure 4B , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the side outer layer portion is also called a W interval or a side interval.

[0076] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2. The first end face side outer layer portion LG1 is a portion located between the series capacitor forming portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion D1. That is, the first end face side outer layer portion LG1 is a collection of portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions D1. The second end face side outer layer portion LG2 is a portion located between the series capacitor forming portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion D2. That is, the second end face side outer layer portion LG2 is a collection of portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions D2. In Figure 2 、 Figure 4A as well as Figure 4B, the ranges of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the longitudinal direction L are shown. In addition, the end surface side outer layer portion is also referred to as an L interval or an end interval.

[0077] The series capacitor forming portion 11E of the laminate 10 also includes a series connection region. This region is located between the portion forming the electrostatic capacitance CAP1 and the portion forming the electrostatic capacitance CAP2, and includes the dielectric layer 20 and the connecting portion E0. Specifically, the series connection region is the aggregate of the central portions of the multiple dielectric layers 20 in the longitudinal direction L and the multiple connecting portions E0. The series connection region is also referred to as the intermediate space.

[0078] like Figure 1 as well as Figure 2 As shown, the external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side of the stacked body 10 and a second external electrode 40B arranged on the second end surface LS2 side of the stacked body 10 .

[0079] The first external electrode 40A and the second external electrode 40B have the same basic structure. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are substantially plane-symmetrical with respect to a WT cross-section taken at the center in the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following description, when there is no need to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0080] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A contacts the first lead portion D1 of each of the plurality of first internal electrode layers 31 exposed on the first end surface LS1. Thus, the first external electrode 40A is electrically connected to the plurality of first internal electrode layers 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0081] The second external electrode 40B is disposed on the second end surface LS2. The second external electrode 40B contacts the second lead portion D2 of each of the plurality of second internal electrode layers 32 exposed on the second end surface LS2. Thus, the second external electrode 40B is electrically connected to the plurality of second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0082] As described above, within the laminate 10, the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33 oppose each other via the dielectric layer 20, thereby forming capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB of the second internal electrode layer 32 and the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 oppose each other via the dielectric layer 20, thereby forming capacitance CAP2 (second capacitor portion CAP2).

[0083] The connection portion E0 connects the capacitance CAP1 and the capacitance CAP2 in series. Therefore, a capacitor characteristic formed by series-connected capacitance is exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0084] like Figure 2 As shown, the first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A. The second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B.

[0085] The first foundation electrode layer 50A is disposed on the first end surface LS1. The first foundation electrode layer 50A is connected to the first lead portion D1 of each of the plurality of first internal electrode layers 31 exposed on the first end surface LS1. In the present embodiment, the first foundation electrode layer 50A is formed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0086] The second foundation electrode layer 50B is disposed on the second end surface LS2. The second foundation electrode layer 50B contacts the second lead portion D2 of each of the plurality of second internal electrode layers 32 exposed on the second end surface LS2. In the present embodiment, the second foundation electrode layer 50B is formed so as to extend from the second end surface LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0087] The first foundation electrode layer 50A and the second foundation electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0088] The first and second base electrode layers 50A and 50B of this embodiment are sintered layers. The sintered layers preferably contain either a metal component, a glass component, or a ceramic component, or both. The metal component, for example, includes at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like. The glass component, for example, includes at least one selected from B, Si, Ba, Mg, Al, Li, and the like. The ceramic component may be the same or a different type of ceramic material as the dielectric layer 20. For example, the ceramic component may include at least one selected from CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), titanium oxide (TiO2), and the like.

[0089] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the laminate 10 and sintering it. The sintered layer can be formed by simultaneously sintering a pre-sintered laminate chip (chip) having multiple internal electrode layers and a dielectric layer, which is the raw material of the laminate 10, and the conductive paste applied to the laminate chip. Alternatively, it can be formed by applying a conductive paste to the laminate 10 and sintering it after the laminate 10 is obtained by sintering the laminate chip. In addition, in the case of the above-mentioned structure, the sintered layer is preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. In this case, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20 as the added ceramic material. In addition, the sintered layer can also be a plurality of layers.

[0090] The thickness of the first foundation electrode layer 50A located on the first end surface LS1 in the longitudinal direction L is preferably about 3 μm or more and 200 μm or less in the central portion in the stacking direction T and the width direction W of the first foundation electrode layer 50A, for example.

[0091] The thickness of the second foundation electrode layer 50B located on the second end surface LS2 in the longitudinal direction L is preferably about 3 μm or more and 200 μm or less in the central portion in the stacking direction T and the width direction W of the second foundation electrode layer 50B, for example.

[0092] In the case where the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on the portion corresponding to the stacking direction T is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0093] In the case where the first base electrode layer 50A is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided on the portion corresponding to the width direction W is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the stacking direction T of the first base electrode layer 50A provided on the portion.

[0094] In the case where a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on the portion corresponding to the stacking direction T is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on the portion.

[0095] In the case where the second base electrode layer 50B is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided on the portion corresponding to the width direction W is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the longitudinal direction L and the stacking direction T of the second base electrode layer 50B provided on the portion.

[0096] In the present embodiment, the first foundation electrode layer 50A and the second foundation electrode layer 50B may be thin film layers. A thin film layer is a layer in which metal particles are deposited.

[0097] When the first foundation electrode layer 50A and the second foundation electrode layer 50B are formed of thin film layers, they are preferably formed by a thin film forming method such as sputtering or vapor deposition. Here, a sputtering electrode formed by sputtering will be described.

[0098] The first base electrode layer 50A of this embodiment may also be composed of a first thin film layer formed by a sputtering electrode. The second base electrode layer 50B may also be composed of a second thin film layer formed by a sputtering electrode. When the base electrode layer is formed by a sputtering electrode, the sputtering electrode is preferably formed directly on a portion of at least one of the first main surface TS1 and the second main surface TS2 of the stacked body 10. The first thin film layer formed by the sputtering electrode is arranged on a portion of the first side surface WS1 on the first main surface TS1. The second thin film layer formed by the sputtering electrode is arranged on a portion of the second side surface WS2 on the first main surface TS1.

[0099] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This can improve the adhesion of the external electrode 40 to the stacked body 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0100] The first plating layer 60A is arranged to cover the first foundation electrode layer 50A.

[0101] The second plating layer 60B is arranged to cover the second foundation electrode layer 50B.

[0102] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, and the like. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0103] In the present embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0104] In the present embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0105] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer improves solder wettability when mounting the multilayer ceramic capacitor 1. This facilitates mounting the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0106] Alternatively, the external electrode 40 of this embodiment may include, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may also be disposed so as to cover the sintered layer. When the conductive resin layer is disposed so as to cover the sintered layer, the conductive resin layer is disposed between the sintered layer and the plating layers (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the sintered layer or partially cover the sintered layer.

[0107] The conductive resin layer composed of a thermosetting resin is more flexible than conductive layers composed of, for example, a plated film or a fired product of a conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Consequently, the conductive resin layer prevents cracks from forming in the multilayer ceramic capacitor 1.

[0108] The metal constituting the conductive particles may also be Ag, Cu, Ni, Sn, Bi, or alloys thereof. The conductive particles preferably contain Ag. An example of the conductive particles is Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, making it resistant to oxidation and highly weatherable. Therefore, Ag metal powder is suitable as the conductive particles.

[0109] Alternatively, the conductive particles may be metal powder coated with Ag. When using Ag-coated metal powder, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy thereof. To maintain the properties of Ag while using an inexpensive base metal, Ag-coated metal powder is preferred.

[0110] Furthermore, the conductive particles may be Cu or Ni treated to prevent oxidation. Furthermore, the conductive particles may be metal powder coated with Sn, Ni, or Cu. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy thereof.

[0111] The shape of the conductive particles is not particularly limited. Spherical, flat, or other shapes can be used as the conductive particles, but a mixture of spherical metal powder and flat metal powder is preferably used.

[0112] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the conductivity of the conductive resin layer. Specifically, the conductive particles are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0113] The resin constituting the conductive resin layer may also include at least one selected from various well-known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is particularly suitable due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin of the conductive resin layer preferably includes a curing agent along with the thermosetting resin. When an epoxy resin is used as the base resin, the epoxy resin curing agent may also be various well-known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides.

[0114] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0115] Alternatively, a structure may be employed in which the first and second base electrode layers 50A and 50B are not provided, and the first and second plated layers 60A and 60B are disposed directly on the laminate 10. In other words, the laminated ceramic capacitor 1 may include a plated layer that is directly electrically connected to the first and second internal electrode layers 31 and 32. In such a case, the plated layer may be formed after a catalyst is disposed on the surface of the laminate 10 as a pretreatment.

[0116] Even in this case, the plating layer is preferably a plurality of layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder resistance. The upper plating layer is more preferably formed using Sn or Au, which has good solder wettability. For example, when Ni is used to form the first internal electrode layer 31 and the second internal electrode layer 32, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. In addition, the upper plating layer can be formed as needed, and the external electrode 40 can also be composed only of the lower plating layer. In addition, the plating layer can be formed with the upper plating layer as the outermost layer, or other plating layers can be further formed on the surface of the upper plating layer.

[0117] The thickness of each plating layer disposed without a base electrode layer is preferably 2 μm to 10 μm. Furthermore, the plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or greater.

[0118] Furthermore, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Consequently, the dimensions of the multilayer ceramic capacitor 1 in the stacking direction T can be reduced by the amount of the reduction in the thickness of the base electrode layer, thereby achieving a lower height of the multilayer ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 can be increased by the amount of the reduction in the thickness of the base electrode layer, thereby increasing the body thickness. In this way, by forming the plating layer directly on the laminate 10, the design freedom of the multilayer ceramic capacitor can be increased.

[0119] The above is the basic structure of the multilayer ceramic capacitor 1 according to the embodiment. Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the multilayer body 10 and the external electrodes 40, is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the multilayer body 10 and the external electrodes 40, is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1, is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0120] Below, use Figures 1 to 5 , this embodiment is described in detail. Figure 5 This is a schematic cross-sectional view for explaining a structure in which the coverage of the intermediate electrode layer 33 is improved in the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to the first embodiment.

[0121] In the multilayer ceramic capacitor 1 according to this embodiment, the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32. Furthermore, the internal electrode layer 30 includes not only metal material but also voids where no metal material is present. The coverage ratio is referred to as the coverage ratio of the internal electrode layer 30 to the dielectric layer 20. Furthermore, voids where no metal material is present may contain ceramic components such as dielectrics or glass components such as silicon dioxide. Alternatively, voids where no metal material is present may be voids.

[0122] For example, in the multilayer ceramic capacitor 1 according to this embodiment, the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 are preferably less than 85%, and more preferably 60% to 80%. The coverage of the intermediate electrode layer 33 is preferably 90% or more, and more preferably 95% or more. The coverage of the intermediate electrode layer 33 is preferably 10 percentage points higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32, and more preferably 15 percentage points higher.

[0123] In the multilayer ceramic capacitor 1 according to this embodiment, the first and second internal electrode layers 31 and 32 have a greater proportion of portions without cavities containing metal material than the intermediate electrode layer 33. In other words, the proportion of metal material in the first and second internal electrode layers 31 and 32 is smaller than the proportion of metal material in the intermediate electrode layer 33.

[0124] Ceramic pillar structures, connecting the two dielectric layers 20 sandwiched between the two surfaces of the internal electrode layer 30, are easily formed in the voids. Therefore, the lower the coverage, the more pillar structures are present in the voids. The more pillar structures there are, the more firmly the two dielectric layers 20 are connected. In this case, the internal electrode layer 30 sandwiched between the two dielectric layers 20 is firmly held together, thus suppressing interfacial delamination between the two dielectric layers 20 and the internal electrode layer 30 sandwiched between the two dielectric layers 20. Special care must be taken to prevent interfacial delamination at the first lead portion D1 and the second lead portion D2 (lead electrode portions), which serve as the starting point for the infiltration of moisture and the plating solution.

[0125] Therefore, in this embodiment, by reducing the coverage of the first and second internal electrode layers 31, 32, including the lead electrode portion, the interfacial adhesion between the internal electrode layer 30 and the dielectric layer 20 is improved. Furthermore, by increasing the coverage of the intermediate electrode layer 33, the capacitance is increased. In other words, the high-withstand-voltage dual-structure multilayer ceramic capacitor of this embodiment can suppress a decrease in capacitance and prevent interfacial delamination.

[0126] Here, the relationship among the coverage ratios of the first internal electrode layer 31 , the second internal electrode layer 32 , and the intermediate electrode layer 33 will be described in more detail.

[0127] As described above, in the multilayer ceramic capacitor 1 according to this embodiment, the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32. For example, the coverage of the first opposing portion EA and the coverage of the first lead portion D1 of the first internal electrode layer 31 are preferably lower than the coverage of the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33. The coverage of the second opposing portion EB and the coverage of the second lead portion D2 of the second internal electrode layer 32 are preferably lower than the coverage of the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33. For example, the coverage of the first opposing portion EA and the first lead portion D1 may be substantially the same, but lower than the coverage of the first electrode layer-side opposing portion ECA. Alternatively, the coverage of the second opposing portion EB and the second lead portion D2 may be substantially the same, and lower than the coverage of the second electrode layer-side opposing portion ECB. This prevents complication in the manufacturing process for forming the first internal electrode layer 31 and the second internal electrode layer 32. Alternatively, the coverage of the first opposing portion EA may be higher than the coverage of the first lead portion D1. The coverage of the second opposing portion EB may be higher than the coverage of the second lead portion D2. This suppresses interfacial delamination and improves capacitance. Alternatively, the coverage of the first opposing portion EA may be higher than the coverage of the first lead portion D1 and lower than the coverage of the first electrode layer-side opposing portion ECA. Alternatively, the coverage of the second opposing portion EB may be higher than the coverage of the second lead portion D2 and lower than the coverage of the second electrode layer-side opposing portion ECB.

[0128] The coverage of the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33 is higher than the coverage of the first opposing portion EA of the first internal electrode layer 31. The coverage of the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 is higher than the coverage of the second opposing portion EB of the second internal electrode layer 32. By increasing the coverage of at least one of the pair of opposing portions forming the capacitor-forming portion in this manner, a decrease in electrostatic capacitance can be suppressed.

[0129] The coverage of the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33 is higher than the coverage of the first lead portion D1 of the first internal electrode layer 31. The coverage of the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 is higher than the coverage of the first lead portion D2 of the second internal electrode layer 32. This can suppress a decrease in capacitance and prevent the occurrence of interfacial delamination.

[0130] The coverage of the connecting portion E0 of the intermediate electrode layer 33 is higher than the coverage of the first opposing portion EA of the first internal electrode layer 31 and the coverage of the second opposing portion EB of the second internal electrode layer 32. The coverage of the connecting portion E0 of the intermediate electrode layer 33 is also higher than the coverage of the first lead portion D1 of the first internal electrode layer 31 and the coverage of the second lead portion D2 of the second internal electrode layer 32. This allows for more stable series electrical connection of multiple capacitor-forming portions. Furthermore, it becomes easier to adopt a structure in which the intermediate electrode layer 33 is formed with a constant coverage and a constant thickness, thereby preventing complication in the manufacturing process. The coverage of the first electrode layer-side opposing portion ECA, the connecting portion E0, and the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 can also be substantially the same.

[0131] <Method for measuring coverage>

[0132] A method for measuring the coverage ratio, which is the coverage ratio of the internal electrode layer 30 to the dielectric layer 20, will be described. In this measurement method, the measurement of the coverage ratio is also referred to as the measurement of the line coverage ratio.

[0133] First, the multilayer ceramic capacitor 1 is polished from either the first side surface WS1 or the second side surface WS2 to expose the LT cross-section of the laminate 10, where the series capacitor forming portion 11E is exposed. If necessary, the exposed LT cross-section is etched to remove the internal electrode layer 30 stretched by the polishing. Measurement points M1 to M5, described later, are observed using a scanning electron microscope (SEM) at the center of the exposed LT cross-section in the width direction W.

[0134] Measurement points are set at the aforementioned L interval, the capacitor effective portion, and the intermediate interval. In this embodiment, measurement points M1 to M5 are set at the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2, which constitute the L interval; the first capacitor portion CAP1 and the second capacitor portion CAP2, which constitute the capacitor effective portion; and the intermediate interval including the connection portion E0. Measurement points M1 to M5 are set at the center of the exposed LT cross section in the stacking direction T.

[0135] The measurement point M1 is set in a region including the lead portion D1 of the first internal electrode layer 31. Specifically, the measurement point M1 is set at the center in the longitudinal direction L of the lead portion D1.

[0136] The measurement point M2 is set in a region of the first capacitor portion CAP1 that includes the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33. Specifically, the measurement point M2 is set at the center, in the longitudinal direction L, of the first opposing portion EA and the first electrode layer-side opposing portion ECA that form the first capacitor portion CAP1.

[0137] The measurement point M3 is set in a region of the connection portion E0 in the intermediate space including the intermediate electrode layer 33. Specifically, the measurement point M3 is set at the center in the longitudinal direction L of the connection portion E0.

[0138] The measurement point M4 is set in a region of the second capacitor portion CAP2 that includes the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33. Specifically, the measurement point M4 is set at the center, in the longitudinal direction L, of the second opposing portion EB and the second electrode layer-side opposing portion ECB that form the second capacitor portion CAP2.

[0139] The measurement point M5 is set in the region of the second end surface side outer layer portion LG2 including the lead portion D2 of the second internal electrode layer 32. Specifically, the measurement point M5 is set at the center in the longitudinal direction L of the lead portion D2.

[0140] In addition, in the case of a stacked ceramic capacitor with three or more components as shown in the embodiment described later, the measurement points are preferably set in areas corresponding to the structure, but as in this embodiment, they are preferably set in the L interval, the capacitor effective part, and the intermediate interval.

[0141] The line coverage of the exposed LT cross section was measured using an optical microscope. The line coverage was measured at the aforementioned measurement points M1 to M5. The observation magnification for each measurement point was set to 1000x.

[0142] The internal electrode layer 30 has regions where the conductive component exists and regions where the conductive component is absent, such as voids. In the optical microscope image, the ratio of the length in the longitudinal direction L of the region actually comprising the conductive component to the length of the internal electrode layer 30 in the longitudinal direction L without considering the presence of the conductive component (i.e., the ratio of the length in the longitudinal direction L excluding the region where the conductive component is absent to the length in the longitudinal direction L of the internal electrode layer 30 without considering the presence of the conductive component) is calculated as the line coverage. The coverage of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 at each measurement point is then measured. The average value for each of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is then taken as the coverage of each of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in this embodiment.

[0143] For example, when measuring the coverage of the first internal electrode layer 31, the coverage of the first internal electrode layer 31 is measured at measurement points M1 and M2, and the average value thereof is used as the coverage of the first internal electrode layer 31 in this embodiment. Furthermore, when measuring the coverage of the second internal electrode layer 32, the coverage of the second internal electrode layer 32 is measured at measurement points M4 and M5, and the average value thereof is used as the coverage of the second internal electrode layer 32 in this embodiment. Furthermore, when measuring the coverage of the intermediate electrode layer 33, the coverage of the intermediate electrode layer 33 is measured at measurement points M2, M3, and M4, respectively, and the average value thereof is used as the coverage of the intermediate electrode layer 33 in this embodiment.

[0144] <Manufacturing method>

[0145] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the aforementioned requirements are met. However, a preferred manufacturing method includes the following steps. Each step is described in detail below.

[0146] A dielectric sheet for dielectric layer 20 and a conductive paste for internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for internal electrode contain a binder and a solvent. The binder and solvent may be known binders and solvents.

[0147] For example, a conductive paste for the internal electrode layer 30 is printed in a predetermined pattern on a dielectric sheet using screen printing, gravure printing, or the like. Thus, a dielectric sheet having patterns for the first internal electrode layer 31 and the second internal electrode layer 32, and a dielectric sheet having a pattern for the intermediate electrode layer 33, are prepared. The coverage of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is adjusted by stacking dielectric sheets of varying coating thicknesses. For example, the conductive paste for the intermediate electrode layer 33, where coverage is desired to be higher, is applied thicker than the conductive paste for the first internal electrode layer 31 and the second internal electrode layer 32. Printing methods are not limited to screen printing or the like.

[0148] Alternatively, the conductive paste forming the intermediate electrode layer 33 may be applied at a substantially constant thickness, so that the intermediate electrode layer 33 has a substantially constant thickness and a substantially constant coverage ratio. Alternatively, the conductive paste forming the first internal electrode layer 31 may be applied at a substantially constant thickness, so that the first internal electrode layer 31 has a substantially constant thickness and a substantially constant coverage ratio. Alternatively, the conductive paste forming the second internal electrode layer 32 may be applied at a substantially constant thickness, so that the second internal electrode layer 32 has a substantially constant thickness and a substantially constant coverage ratio. This can prevent complication of the manufacturing process. Alternatively, the conductive paste forming the first internal electrode layer 31 and the conductive paste forming the second internal electrode layer 32 may be applied at substantially the same thickness, so that the first internal electrode layer 31 and the second internal electrode layer 32 have substantially the same coverage ratio. This can prevent complication of the manufacturing process. However, this is not limiting.

[0149] The laminated sheets are pressed in the height direction by isostatic pressing or the like to produce a laminated block.

[0150] The laminated block is cut into a given size, thereby cutting out laminated chips.

[0151] At this time, the corners and ridges of the stacked small pieces may be rounded by barrel polishing or the like.

[0152] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0153] A conductive paste serving as a base electrode layer is applied to both end surfaces of the laminate 10 .

[0154] In this embodiment, the base electrode layer is a sintered layer. For example, a conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A sintering process is then performed to form the base electrode layer. The sintering process temperature is preferably between 700°C and 900°C.

[0155] Furthermore, when the pre-fired laminated pieces and the conductive paste applied to the laminated pieces are fired simultaneously, the sintered layer is preferably formed by sintering a paste to which a ceramic material has been added in place of the glass component. In this case, the added ceramic material is particularly preferably the same type of ceramic material as that used in dielectric layer 20. In this case, the conductive paste is applied to the pre-fired laminated pieces, and the laminated pieces and the conductive paste applied to the laminated pieces are sintered simultaneously to form laminate 10, which has the sintered layer formed thereon.

[0156] Next, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. The plating process can be performed using either electrolytic plating or electroless plating.

[0157] However, electroless plating requires pretreatment with a catalyst or the like to increase the deposition rate of the coating, which has the disadvantage of complicating the process. Therefore, electrolytic plating is generally preferred. The Ni plating layer and the Sn plating layer are sequentially formed, for example, by barrel plating.

[0158] Furthermore, when a conductive resin layer is provided as the base electrode layer, the conductive resin layer can also be arranged to cover the sintered layer. When providing a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the sintered layer and then heat-treated at a temperature of 250 to 550°C or higher. This heat cures the thermosetting resin, forming the conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent scattering of the resin and oxidation of the various metal components, the oxygen concentration is preferably 100 ppm or less.

[0159] Through such manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0160] The present invention is not limited to the multilayer ceramic capacitor 1 having a dual structure, but can be widely used in multilayer ceramic capacitors having a serial structure.

[0161] <Second embodiment>

[0162] The multilayer ceramic capacitor 1 according to the second embodiment is a triple structure multilayer ceramic capacitor. Figure 6 A multilayer ceramic capacitor 1 according to a second embodiment will be described. In the following description, detailed descriptions of the same configurations as those of the first embodiment may be omitted. Figure 6 This is a schematic cross-sectional view for explaining a structure in which the coverage of the intermediate electrode layer 33 is improved in the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to the second embodiment. The manufacturing method of the second embodiment is the same as that of the first embodiment, and its description is omitted.

[0163] In the multilayer ceramic capacitor 1 of this embodiment, the configuration of the internal electrode layers 30 within the laminate 10 differs from that of the first embodiment. Specifically, whereas the multilayer ceramic capacitor 1 according to the first embodiment has a two-element structure, the multilayer ceramic capacitor 1 according to the second embodiment has a three-element structure, and the configuration of the internal electrode layers 30 within the laminate 10 differs from that of the first embodiment.

[0164] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductive layers, a plurality of second internal electrode layers 32 as a plurality of second internal conductive layers, and an intermediate electrode layer 33 .

[0165] like Figure 6 As shown, the intermediate electrode layer 33 according to the second embodiment includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332 .

[0166] The first intermediate electrode layer 331 includes a first electrode layer side opposing portion EC1A, a first intermediate electrode layer opposing portion EC1B, and a first connecting portion E10. The first electrode layer side opposing portion EC1A is a region opposing the first internal electrode layer 31 arranged adjacent to the stacking direction T and is located within the stack 10. The first intermediate electrode layer opposing portion EC1B is a region opposing the second intermediate electrode layer 332 arranged adjacent to the stacking direction T and is located within the stack 10. The first connecting portion E10 connects the first electrode layer side opposing portion EC1A and the first intermediate electrode layer opposing portion EC1B and is located between the first electrode layer side opposing portion EC1A and the first intermediate electrode layer opposing portion EC1B.

[0167] The second intermediate electrode layer 332 includes a second electrode layer side opposing portion EC2A, a second intermediate electrode layer opposing portion EC2B, and a second connecting portion E20. The second electrode layer side opposing portion EC2A opposes the second internal electrode layer 32, which is arranged adjacent to the stacking direction T. The second intermediate electrode layer opposing portion EC2B opposes the first intermediate electrode layer 331, which is arranged adjacent to the stacking direction T. The second connecting portion E20 connects the second electrode layer side opposing portion EC2A and the second intermediate electrode layer opposing portion EC2B and is arranged between the second electrode layer side opposing portion EC2A and the second intermediate electrode layer opposing portion EC2B.

[0168] like Figure 6 As shown, in the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layer 31 and the second intermediate electrode layer 332 are arranged adjacent to each other in the longitudinal direction L. In the multilayer ceramic capacitor 1 according to the second embodiment, the second internal electrode layer 32 and the first intermediate electrode layer 331 are arranged adjacent to each other in the longitudinal direction L.

[0169] In the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layers 31 and the second intermediate electrode layers 332 and the second internal electrode layers 32 and the first intermediate electrode layers 331 are stacked alternately with the dielectric layers 20 interposed therebetween.

[0170] In this embodiment, the first opposing portion EA and the first electrode layer-side opposing portion EC1A oppose each other via the dielectric layer 20, thereby forming capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer-side opposing portion EC2A oppose each other via the dielectric layer, thereby forming capacitance CAP2 (second capacitor portion CAP2). The first intermediate electrode layer opposing portion EC1B and the second intermediate electrode layer opposing portion EC2B oppose each other via the dielectric layer 20, thereby forming capacitance CAP3 (third capacitor portion CAP3). The first connecting portion E10 connects capacitance CAP1 and capacitance CAP3 in series. The second connecting portion E20 connects capacitance CAP2 and capacitance CAP3 in series. The multilayer ceramic capacitor 1 of this embodiment has a serial structure, a so-called triple structure, with three capacitor portions connected in series.

[0171] The laminate 10 also includes a series capacitor forming portion 11E. This portion includes a portion forming capacitance CAP1, a portion forming capacitance CAP2, a portion forming capacitance CAP3, a portion connecting capacitance CAP1 and capacitance CAP3 in series, and a portion connecting capacitance CAP2 and capacitance CAP3 in series. The series capacitor forming portion 11E forms part of the inner portion 11. The portion forming capacitance CAP1 (first capacitor portion CAP1), the portion forming capacitance CAP2 (second capacitor portion CAP2), and the portion forming capacitance CAP3 (third capacitor portion CAP3) within the series capacitor forming portion 11E are also referred to as capacitor effective portions.

[0172] Furthermore, the series capacitor forming portion 11E of the stacked body 10 includes a first series connection region and a second series connection region. The first series connection region is a portion located between the portion forming the electrostatic capacitance CAP1 and the portion forming the electrostatic capacitance CAP3, and includes the dielectric layer 20 and the first connecting portion E10. The second series connection region is a portion located between the portion forming the electrostatic capacitance CAP2 and the portion forming the electrostatic capacitance CAP3, and includes the dielectric layer 20 and the second connecting portion E20. In other words, the first series connection region is a collection of portions of the plurality of dielectric layers 20 that overlap with the first connecting portion E10 when viewed in the stacking direction T, and the plurality of first connecting portions E10. The second series connection region is a collection of portions of the plurality of dielectric layers 20 that overlap with the second connecting portion E20 when viewed in the stacking direction T, and the plurality of second connecting portions E20.

[0173] like Figure 6 As shown, the external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 side of the stacked body 10 and a second external electrode 40B disposed on the second end surface LS2 side of the stacked body 10 .

[0174] The first connecting portion E10 connects the capacitance CAP1 and the capacitance CAP3 in series. The second connecting portion E20 connects the capacitance CAP2 and the capacitance CAP3 in series. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit the characteristics of a capacitor formed by series-connected capacitance.

[0175] In the multilayer ceramic capacitor 1 according to the second embodiment, the coverage of the intermediate electrode layer 33 is also higher than the coverage of the first and second internal electrode layers 31 and 32. More specifically, the coverage of the first and second intermediate electrode layers 331 and 332 is higher than the coverage of the first and second internal electrode layers 31 and 32. For example, in the multilayer ceramic capacitor 1 according to the second embodiment, the coverage of the first and second internal electrode layers 31 and 32 is preferably less than 85%, more preferably 60% to 80%. The coverage of the first and second intermediate electrode layers 331 and 332 is preferably 90% or higher, more preferably 95% or higher. The coverage of the intermediate electrode layer 33 is preferably 10 percentage points higher than the coverage of the first and second internal electrode layers 31 and 32, more preferably 15 percentage points higher.

[0176] In the multilayer ceramic capacitor 1 according to this embodiment, the first intermediate electrode layer opposing portion EC1B of the first intermediate electrode layer 331 and the second intermediate electrode layer opposing portion EC2B of the second intermediate electrode layer 332 both have a higher coverage ratio than the first internal electrode layer 31 and the second internal electrode layer 32. Furthermore, the first intermediate electrode layer opposing portion EC1B of the first intermediate electrode layer 331 and the second intermediate electrode layer opposing portion EC2B of the second intermediate electrode layer 332 oppose each other, forming the third capacitor portion CAP3. Therefore, the coverage ratio of the internal electrode layers constituting the third capacitor portion CAP3 is higher than the coverage ratio of the first internal electrode layer 31 and the coverage ratio of the second internal electrode layer 32.

[0177] Thus, in the high-withstand-voltage triple-structured multilayer ceramic capacitor according to the second embodiment, it is possible to improve the capacitance and suppress the occurrence of interface delamination.

[0178] <Third embodiment>

[0179] In addition, the multilayer ceramic capacitor 1 is not limited to Figures 1 to 4B For example, the multilayer ceramic capacitor 1 may also be as shown in FIG. Figure 7 The quadruple-structured multilayer ceramic capacitor shown.

[0180] Below, use Figure 7 A multilayer ceramic capacitor 1 according to a third embodiment will be described. In the following description, detailed descriptions of the same structures as those in the first and second embodiments will be omitted. Furthermore, the method for manufacturing the multilayer ceramic capacitor according to the third embodiment is the same as that of the first embodiment, and therefore, the description thereof will be omitted. Figure 7 This is a schematic cross-sectional view for explaining a structure in which the coverage of the intermediate electrode layer 33 is improved in the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to the third embodiment.

[0181] In the multilayer ceramic capacitor 1 of this embodiment, the arrangement of the internal electrode layers 30 and the external electrodes 40 within the laminate 10 differs from that of the first embodiment. Specifically, whereas the internal electrode layers 30 of the multilayer ceramic capacitor 1 according to the first embodiment had a two-element structure, the multilayer ceramic capacitor 1 according to the third embodiment has a four-element structure, and the arrangement of the internal electrode layers 30 within the laminate 10 differs from that of the first embodiment.

[0182] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductive layers, a plurality of second internal electrode layers 32 as a plurality of second internal conductive layers, and an intermediate electrode layer 33 .

[0183] like Figure 7As shown, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 , a second intermediate electrode layer 332 , and a third intermediate electrode layer 333 .

[0184] The first intermediate electrode layer 331 includes a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacent in the stacking direction T, a first intermediate electrode layer opposing portion EC1B opposing the third intermediate electrode layer 333 arranged adjacent in the stacking direction T, and a first connecting portion E10.

[0185] The second intermediate electrode layer 332 includes a second electrode layer side opposing portion EC2A opposing the second internal electrode layer 32 arranged adjacent in the stacking direction T, a second intermediate electrode layer opposing portion EC2B opposing the third intermediate electrode layer 333 arranged adjacent in the stacking direction T, and a second connecting portion E20.

[0186] The third intermediate electrode layer 333 includes a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 adjacent to the stacking direction T, a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 adjacent to the stacking direction T, and a third connecting portion E30.

[0187] like Figure 7 As shown, in the multilayer ceramic capacitor 1 according to the third embodiment, the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32 are arranged adjacent to each other in the longitudinal direction L. In the multilayer ceramic capacitor 1 according to the third embodiment, the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are arranged adjacent to each other in the longitudinal direction L.

[0188] In the multilayer ceramic capacitor 1 according to the third embodiment, the first internal electrode layers 31 , the third intermediate electrode layers 333 , and the second internal electrode layers 32 are stacked alternately with the first intermediate electrode layers 331 and the second intermediate electrode layers 332 via the dielectric layers 20 .

[0189] In this embodiment, the first opposing portion EA and the first electrode layer-side opposing portion EC1A oppose each other via the dielectric layer 20, thereby forming capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer-side opposing portion EC2A oppose each other via the dielectric layer 20, thereby forming capacitance CAP2 (second capacitor portion CAP2). The first intermediate electrode layer opposing portion EC1B and the third intermediate electrode layer opposing portion EC3A oppose each other via the dielectric layer 20, thereby forming capacitance CAP3 (third capacitor portion CAP3). The second intermediate electrode layer opposing portion EC2B and the fourth intermediate electrode layer opposing portion EC3B oppose each other via the dielectric layer 20, thereby forming capacitance CAP4 (fourth capacitor portion CAP4). The first connecting portion E10 connects capacitance CAP1 and capacitance CAP3 in series. The second connecting portion E20 connects capacitance CAP2 and capacitance CAP4 in series. The third connecting portion E30 connects the electrostatic capacitance CAP3 and the electrostatic capacitance CAP4 in series. The multilayer ceramic capacitor 1 of the present embodiment is a multilayer ceramic capacitor 1 having a serial structure, a so-called quadruple structure, in which four capacitor portions are connected in series.

[0190] Furthermore, the laminate 10 includes a series capacitor forming portion 11E. The series capacitor forming portion 11E includes a portion forming capacitance CAP1, a portion forming capacitance CAP2, a portion forming capacitance CAP3, a portion forming capacitance CAP4, a portion connecting capacitance CAP1 and capacitance CAP3 in series, a portion connecting capacitance CAP2 and capacitance CAP4 in series, and a portion connecting capacitance CAP3 and capacitance CAP4 in series. The series capacitor forming portion 11E constitutes a portion of the inner layer portion 11. Furthermore, the portion forming capacitance CAP1 (first capacitor portion CAP1), the portion forming capacitance CAP2 (second capacitor portion CAP2), the portion forming capacitance CAP3 (third capacitor portion CAP3), and the portion forming capacitance CAP4 (fourth capacitor portion CAP4) in the series capacitor forming portion 11E are also referred to as capacitor effective portions.

[0191] Furthermore, the series capacitor forming portion 11E of the stacked body 10 includes a first series connection region, a second series connection region, and a third series connection region. The first series connection region is a portion located between the portion forming the electrostatic capacitor CAP1 and the portion forming the electrostatic capacitor CAP3, and includes the dielectric layer 20 and the first connecting portion E10. The second series connection region is a portion located between the portion forming the electrostatic capacitor CAP2 and the portion forming the electrostatic capacitor CAP4, and includes the dielectric layer 20 and the second connecting portion E20. The third series connection region is a portion located between the portion forming the electrostatic capacitor CAP3 and the portion forming the electrostatic capacitor CAP4, and includes the dielectric layer 20 and the third connecting portion E30. In other words, the first series connection region is a collection of portions of the plurality of dielectric layers 20 that overlap with the first connecting portion E10 when viewed in the stacking direction T, and the plurality of first connecting portions E10. The second series-connected region is a collection of portions of the plurality of dielectric layers 20 that overlap with the second connecting portion E20 when viewed in the stacking direction T, and the plurality of second connecting portions E20. The third series-connected region is a collection of portions of the plurality of dielectric layers 20 that overlap with the third connecting portion E30 when viewed in the stacking direction T, and the plurality of third connecting portions E30.

[0192] like Figure 7 As shown, the external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side of the stacked body 10 and a second external electrode 40B arranged on the second end surface LS2 side of the stacked body 10 .

[0193] The first connecting portion E10 connects the capacitance CAP1 and the capacitance CAP3 in series. The second connecting portion E20 connects the capacitance CAP2 and the capacitance CAP4 in series. The third connecting portion E30 connects the capacitance CAP3 and the capacitance CAP4 in series. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit the characteristics of a capacitor formed by series-connected capacitance.

[0194] In the multilayer ceramic capacitor 1 according to the third embodiment, the coverage of the intermediate electrode layer 33 is also higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32. More specifically, the coverage of the first intermediate electrode layer 331, the second intermediate electrode layer 332, and the third intermediate electrode layer 333 is higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32.

[0195] For example, in the multilayer ceramic capacitor 1 according to the third embodiment, the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 are preferably less than 85%, and more preferably 60% to 80%. The coverage of the first intermediate electrode layer 331, the second intermediate electrode layer 332, and the third intermediate electrode layer 333 is preferably 90% or more, and more preferably 95% or more. The coverage of the intermediate electrode layer 33 is preferably 10 percentage points higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32, and more preferably 15 percentage points higher.

[0196] In the multilayer ceramic capacitor 1 according to this embodiment, the first intermediate electrode layer opposing portion EC1B of the first intermediate electrode layer 331, the second intermediate electrode layer opposing portion EC2B of the second intermediate electrode layer 332, and the third and fourth intermediate electrode layer opposing portions EC3A and EC3B of the third intermediate electrode layer 333 all have higher coverage than the first and second internal electrode layers 31 and 32. Furthermore, the third intermediate electrode layer opposing portion EC3A of the third intermediate electrode layer 333 opposes the first intermediate electrode layer opposing portion EC1B of the first intermediate electrode layer 331, forming a third capacitor portion CAP3. The fourth intermediate electrode layer opposing portion EC3B of the third intermediate electrode layer 333 opposes the second intermediate electrode layer opposing portion EC2B of the second intermediate electrode layer 332, forming a fourth capacitor portion CAP4. Therefore, the coverage of the internal electrode layers constituting the third capacitor portion CAP3 and the fourth capacitor portion CAP4 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 .

[0197] Thus, in the high-withstand-voltage quadruple-structured multilayer ceramic capacitor according to the third embodiment, it is possible to improve the capacitance and suppress the occurrence of interface delamination.

[0198] <Experimental Example>

[0199] Next, an experimental example of the multilayer ceramic capacitor 1 according to the first embodiment, which represents the multilayer ceramic capacitor 1 disclosed in the present invention, is described. According to the manufacturing method described in the first embodiment, samples were manufactured in batches by adjusting the manufacturing conditions so that the coverage of each internal electrode layer was different, and these samples were used as samples of Experimental Examples 1 to 3 and Comparative Examples 1 to 3. The samples in each batch were manufactured under the same manufacturing conditions. According to each of the embodiments and comparative examples, n=5 samples for coverage measurement, n=10 samples for peeling test, and n=10 samples for electrostatic capacitance test were taken out from the same batch and prepared. In the coverage measurement and each test, the average value of the measurement results was used for evaluation. The specific coverage and evaluation results of each embodiment and comparative example are recorded in Table 1 described later.

[0200] First, according to the manufacturing method described in the first embodiment, a multilayer ceramic capacitor having the following specifications was produced as a sample of an example.

[0201] (Sample)

[0202] ・Dimensions of multilayer ceramic capacitors: 3.4mm (L) × 2.7mm (W) × 2.7mm (T)

[0203] Rated voltage: 1000V

[0204] Dielectric layer: CaZrO3 (thickness of dielectric layer: 3.96 μm)

[0205] Internal electrode layer: Ni (Internal electrode layer coverage: refer to Table 1)

[0206] ·Laminate structure: double structure

[0207] (Determination of coverage)

[0208] The coverage was measured by the aforementioned measurement method.

[0209] (Peel test)

[0210] Using an ultrasonic flaw detector, 20kHz ultrasonic waves were irradiated onto the sample, and cracks and peeling inside the small piece were detected based on the difference between the incident wave and the reflected wave.

[0211] Here, the interface peeling occurrence time and the interface entire surface peeling time between the dielectric layer and the internal electrode layer were evaluated by the following method.

[0212] Polish the small piece to expose the internal electrode layer. Clean the exposed surface of the internal electrode layer with a mixed solution mainly composed of ethanol.

[0213] Grasp the laminated piece with tweezers and secure them to the test bench. Connect the negative power cord of a DC power supply to the top of the tweezers. Furthermore, adjust the position of the test bench and immerse a portion of the laminated piece held by the tweezers in the sodium hydroxide solution in the test dish.

[0214] One end of a Pt wire connected to the power line on the positive electrode side of a DC power supply was immersed in the sodium hydroxide aqueous solution in a test dish.

[0215] Apply 5V to the power line using a DC power supply and use an ultrasonic flaw detector to check every minute for cracks.

[0216] The time from the start of application of a voltage of 5 V until the initial interface peeling was observed was defined as the interface peeling occurrence time. The time from the start of application of a voltage of 5 V until the entire interface peeling was observed was defined as the entire interface peeling time.

[0217] The evaluation criteria for the peeling test were: a peeling time of 40 minutes or longer across the entire interface was rated as 0 (pass), and a peeling time of less than 40 minutes across the entire interface was rated as x (fail).

[0218] (Electrostatic capacitance test)

[0219] Capacitance was measured using a capacitance meter (C-Meter) at a frequency of 120 Hz and an applied voltage of 0.5 Vrms. In Table 1, the acceptable range is defined as within ±5% of the capacitance of Comparative Example 1, with the capacitance falling within the acceptable range being considered acceptable (◯), and unacceptable (×).

[0220] Table 1 shows the measurement results and evaluation results of Examples 1 to 3 and Comparative Examples 1 to 3.

[0221] [Table 1]

[0222]

[0223] Table 1 lists the measurement results for the first and second internal electrode layer coverages, the intermediate electrode layer coverage, the interface peeling occurrence time, and the interface full-surface peeling time. Table 1 also lists the evaluation results for the interface peeling failure determination, the electrostatic capacitance determination, and the overall determination.

[0224] In Table 1, the comprehensive judgment is based on the results of the interface delamination failure judgment and the electrostatic capacitance judgment. For example, if the results of both the interface delamination failure judgment and the electrostatic capacitance judgment are acceptable (0), the comprehensive judgment is acceptable (0). If either the interface delamination failure judgment or the electrostatic capacitance judgment is unacceptable (×), the comprehensive judgment is unacceptable (×).

[0225] In Examples 1 to 3, the interface peeling failure determination and the electrostatic capacitance determination were acceptable, and the comprehensive determination was acceptable. In Examples 1 to 3, the coverage of the first and second internal electrode layers was lower than the coverage of the intermediate electrode layer.

[0226] In Comparative Examples 1 to 3, either the interface delamination failure or the capacitance failure was determined as unqualified, resulting in a comprehensive failure. More specifically, in Comparative Examples 1 and 2, although the capacitance was determined as acceptable, the interface delamination failure was determined as unqualified, resulting in a comprehensive failure. Furthermore, in Comparative Example 3, although the interface delamination failure was determined as acceptable, the capacitance failure was determined as unqualified, resulting in a comprehensive failure.

[0227] By making the coverage of the intermediate electrode layer 33 higher than the coverage of the first and second internal electrode layers 31, 32, the effects of the present disclosure can be expected. For example, by relatively increasing the coverage of the intermediate electrode layer 33 compared to a case where the coverage of the intermediate electrode layer 33 is the same as that of the first and second internal electrode layers 31, 32, the effects of suppressing interfacial delamination and increasing electrostatic capacitance can be expected. Furthermore, by relatively decreasing the coverage of the first and second internal electrode layers 31, 32 compared to a case where the coverage of the intermediate electrode layer 33 is the same as that of the first and second internal electrode layers 31, 32, the effects of suppressing a decrease in electrostatic capacitance and suppressing interfacial delamination can be expected.

[0228] The coverage of the first and second internal electrode layers 31, 32 is preferably less than 85%, more preferably 60% to 80%. The coverage of the intermediate electrode layer is preferably 90% or more, more preferably 95% or more. The coverage of the intermediate electrode layer 33 is preferably 10 percentage points higher than the coverage of the first and second internal electrode layers 31, 32, more preferably 15 percentage points higher.

[0229] The multilayer ceramic capacitor 1 according to the embodiment described above achieves the following effects. Multilayer ceramic capacitors 1 are sometimes required to have a higher withstand voltage. As a multilayer ceramic capacitor 1 that achieves a higher withstand voltage, a multilayer ceramic capacitor 1 having a structure in which multiple capacitor sections are connected in series (so-called a series structure) is known.

[0230] In a series-structured multilayer ceramic capacitor 1, series capacitance is formed, thereby improving withstand voltage, but this in turn reduces electrostatic capacitance. To increase electrostatic capacitance, the number of internal electrode layers 30 stacked must be increased. However, increasing the number of stacked layers increases internal stress within the stack 10, making interfacial delamination more likely to occur.

[0231] More specifically, the multilayer ceramic capacitor 1 structurally contains internal stress due to the difference in linear expansion coefficient between the internal electrode layer 30 and the dielectric layer 20. This stress may cause delamination at the interface between the internal electrode layer 30 and the dielectric layer 20. Furthermore, it is known that the internal stress increases as the number of stacked elements (i.e., the number of internal electrode layers 30) increases, thus becoming an obstacle to multilayering.

[0232] In particular, in medium and high voltage applications, multilayer ceramic capacitors 1 are sometimes arranged in a series structure to disperse the voltage applied to a single capacitor section (the portion that forms the electrostatic capacitance). However, in order to reduce the voltage applied to a single capacitor section while maintaining the electrostatic capacitance, the number of laminated sheets must be increased in proportion to the number of laminated sheets in the series. As a result, the increased number of laminated sheets increases the inherent stress and the risk of interface delamination.

[0233] Furthermore, the lead-out electrode portion, which serves as a starting point for the infiltration of moisture and the plating solution, requires special attention to prevent interfacial peeling.

[0234] Therefore, by making the coverage of the intermediate electrode layer 33 higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32, in other words, by making the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 lower than the coverage of the intermediate electrode layer 33, it is possible to suppress the decrease in electrostatic capacitance and the occurrence of interface delamination even in a multilayer ceramic capacitor 1 with a high withstand voltage specification.

[0235] The multilayer ceramic capacitor 1 according to the above-described embodiment comprises: a multilayer body 10 including a plurality of stacked dielectric layers 20 and a plurality of stacked internal electrode layers 30, and including a first main surface TS1 and a second main surface TS2 opposite to each other in a stacking direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction L perpendicular to the stacking direction T and the width direction W; a first external electrode 40A disposed on the first end surface LS1; and a second external electrode 40B disposed on the second end surface LS2; the plurality of internal electrode layers 30 including a first internal electrode layer 31, a second internal electrode layer 32, and an intermediate electrode layer 33; the first internal electrode layer 31 having a first lead portion D1, one end of which is led to the first end surface LS1, and is connected to the first external electrode 40A; and a first opposing portion EA, is connected to the first lead portion D1, and is opposite to the internal electrode layer 30 arranged adjacent to the stacking direction T, the second internal electrode layer 32 has: a second lead portion D2, one end of which is led to the second end face LS2 and is connected to the second external electrode 40B; and a second opposing portion EB, is connected to the second lead portion D2, and is opposite to the internal electrode layer 30 arranged adjacent to the stacking direction T, the intermediate electrode layer 33 is an internal electrode layer 30 that is connected to neither the first external electrode 40A nor the second external electrode 40B, and forms a series-connected capacitor element with the first internal electrode layer 31 and the second internal electrode layer 32, and the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32.

[0236] Thus, even in the multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to suppress a decrease in electrostatic capacitance and to inhibit the occurrence of interface peeling.

[0237] In the multilayer ceramic capacitor 1 according to the above-described embodiment, the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 are 60% or more and 80% or less.

[0238] Thus, even in the multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to suppress a decrease in electrostatic capacitance and more effectively suppress the occurrence of interface peeling.

[0239] Furthermore, in the multilayer ceramic capacitor 1 according to the above-described embodiment, the coverage of the intermediate electrode layer 33 is 90% or more.

[0240] Thus, even in the multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to suppress the occurrence of interface peeling and improve the electrostatic capacitance.

[0241] In the multilayer ceramic capacitor 1 according to the above-described embodiment, the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 by 10 percentage points or more.

[0242] Thus, even in the multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to more effectively suppress a decrease in electrostatic capacitance and to inhibit the occurrence of interface peeling.

[0243] In the multilayer ceramic capacitor 1 involved in the second embodiment, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332, and the first intermediate electrode layer 331 has: a first electrode layer side opposing portion EC1A, opposing to the first internal electrode layer 31 arranged adjacent to the stacking direction T; and a first intermediate electrode layer opposing portion EC1B, opposing to the second intermediate electrode layer 332 arranged adjacent to the stacking direction T, and the second intermediate electrode layer 332 has: a second electrode layer side opposing portion EC2A, opposing to the second internal electrode layer 32 arranged adjacent to the stacking direction T; and a second intermediate electrode layer opposing portion EC2B, opposing to the first intermediate electrode layer 331 arranged adjacent to the stacking direction T.

[0244] Even in such a triple-structured multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to suppress a decrease in electrostatic capacitance and to inhibit the occurrence of interface peeling.

[0245] In the multilayer ceramic capacitor 1 according to the third embodiment, the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333. The first intermediate electrode layer 331 has: a first electrode layer side opposing portion EC1A, which is opposed to the first internal electrode layer 31 arranged adjacent to the stacking direction T; and a first intermediate electrode layer opposing portion EC1B, which is opposed to the third intermediate electrode layer 333 arranged adjacent to the stacking direction T. The second intermediate electrode layer 332 has: a second electrode side opposing portion EC1A, which is opposed to the first internal electrode layer 31 arranged adjacent to the stacking direction T; and a first intermediate electrode layer opposing portion EC1B, which is opposed to the third intermediate electrode layer 333 arranged adjacent to the stacking direction T. The layer-side opposing portion EC2A is opposite to the second internal electrode layer 32 arranged adjacent to the stacking direction T; and the second intermediate electrode layer opposing portion EC2B is opposite to the third intermediate electrode layer 333 arranged adjacent to the stacking direction T. The third intermediate electrode layer 333 has: the third intermediate electrode layer opposing portion EC3A, opposite to the first intermediate electrode layer 331 arranged adjacent to the stacking direction T; and the fourth intermediate electrode layer opposing portion EC3B, opposite to the second intermediate electrode layer 332 arranged adjacent to the stacking direction T.

[0246] Even in such a quadruple-structured multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to suppress a decrease in electrostatic capacitance and to inhibit the occurrence of interface peeling.

[0247] In the multilayer ceramic capacitor 1 according to the present embodiment, the dielectric layer 20 contains a perovskite compound containing at least Ca and Zr.

[0248] Thus, even in the multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to improve heat resistance and high-frequency characteristics, suppress a decrease in electrostatic capacitance, and suppress the occurrence of interface delamination.

[0249] The present invention is not limited to the configuration of the above embodiment, and can be applied with appropriate modifications within the scope of the present invention. In addition, a combination of two or more configurations of the preferred configurations described in the above embodiment also constitutes the present invention.

[0250] In addition, the following various changes and modifications are possible.

[0251] <1>

[0252] A multilayer ceramic capacitor comprising:

[0253] A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction;

[0254] a first external electrode disposed on the first end surface; and

[0255] a second external electrode disposed on the second end surface;

[0256] The plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer.

[0257] The first internal electrode layer includes: a first lead portion, one end of which is led to the first end surface and connected to the first external electrode; and a first opposing portion connected to the first lead portion and opposed to the internal electrode layer arranged adjacent to the internal electrode layer in the stacking direction.

[0258] The second internal electrode layer includes: a second lead portion, one end of which is led to the second end surface and connected to the second external electrode; and a second opposing portion connected to the second lead portion and opposed to the internal electrode layer arranged adjacent to the stacking direction.

[0259] The intermediate electrode layer is an internal electrode layer that is not connected to either the first external electrode or the second external electrode and forms a capacitor element connected in series with the first internal electrode layer and the second internal electrode layer.

[0260] The coverage of the intermediate electrode layer is higher than the coverage of the first internal electrode layer and the coverage of the second internal electrode layer.

[0261] <2>

[0262] according to <1> The multilayer ceramic capacitor, wherein

[0263] The coverage rate of the first internal electrode layer and the coverage rate of the second internal electrode layer are 60% or more and 80% or less.

[0264] <3>

[0265] according to <1> or <2> The multilayer ceramic capacitor, wherein

[0266] The coverage of the intermediate electrode layer is greater than 90%.

[0267] <4>

[0268] according to <1> ~ <3> The multilayer ceramic capacitor according to any one of claims , wherein

[0269] The coverage of the intermediate electrode layer is higher than the coverage of the first internal electrode layer and the coverage of the second internal electrode layer by 10 percentage points or more.

[0270] <5>

[0271] according to <1> ~ <4> The multilayer ceramic capacitor according to any one of claims , wherein

[0272] The intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer.

[0273] The first intermediate electrode layer has:

[0274] a first electrode layer-side opposing portion facing the first internal electrode layer disposed adjacent to the first internal electrode layer in the stacking direction; and

[0275] The first intermediate electrode layer opposing portion is opposed to the second intermediate electrode layer disposed adjacent to the second intermediate electrode layer in the stacking direction.

[0276] The second intermediate electrode layer has:

[0277] a second electrode layer-side opposing portion facing the second internal electrode layer disposed adjacent to the second internal electrode layer in the stacking direction; and

[0278] The second intermediate electrode layer opposing portion faces the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction.

[0279] <6>

[0280] according to <1> ~ <4> The multilayer ceramic capacitor according to any one of claims , wherein

[0281] The intermediate electrode layer includes a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer.

[0282] The first intermediate electrode layer has:

[0283] a first electrode layer-side opposing portion facing the first internal electrode layer disposed adjacent to the first internal electrode layer in the stacking direction; and

[0284] The first intermediate electrode layer opposing portion is opposed to the third intermediate electrode layer disposed adjacent to the third intermediate electrode layer in the stacking direction.

[0285] The second intermediate electrode layer has:

[0286] a second electrode layer-side opposing portion facing the second internal electrode layer disposed adjacent to the second internal electrode layer in the stacking direction; and

[0287] The second intermediate electrode layer facing portion faces the third intermediate electrode layer disposed adjacent to the third intermediate electrode layer in the stacking direction.

[0288] The third intermediate electrode layer includes: a third intermediate electrode layer opposing portion opposing the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction; and

[0289] The fourth intermediate electrode layer opposing portion faces the second intermediate electrode layer disposed adjacent to the second intermediate electrode layer in the stacking direction.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface; The plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer. The first internal electrode layer has: a first lead portion, one end of which is led to the first end surface and connected to the first external electrode; and The first opposing portion is connected to the first lead portion and is opposed to the internal electrode layer arranged adjacent to the internal electrode layer in the stacking direction. The second internal electrode layer has: a second lead portion, one end of which is led to the second end surface and connected to the second external electrode; and The second opposing portion is connected to the second lead portion and is opposed to the internal electrode layer arranged adjacent to the internal electrode layer in the stacking direction. The intermediate electrode layer is an internal electrode layer that is not connected to either the first external electrode or the second external electrode and forms a capacitor element connected in series with the first internal electrode layer and the second internal electrode layer. The coverage of the intermediate electrode layer is higher than the coverage of the first internal electrode layer and the coverage of the second internal electrode layer.

2. The multilayer ceramic capacitor according to claim 1, wherein The coverage rate of the first internal electrode layer and the coverage rate of the second internal electrode layer are 60% or more and 80% or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein The coverage of the intermediate electrode layer is greater than 90%.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The coverage of the intermediate electrode layer is higher than the coverage of the first internal electrode layer and the coverage of the second internal electrode layer by 10 percentage points or more.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer. The first intermediate electrode layer has: a first electrode layer-side opposing portion facing the first internal electrode layer disposed adjacent to the first internal electrode layer in the stacking direction; and The first intermediate electrode layer opposing portion is opposed to the second intermediate electrode layer disposed adjacent to the second intermediate electrode layer in the stacking direction. The second intermediate electrode layer has: a second electrode layer-side opposing portion facing the second internal electrode layer disposed adjacent to the second internal electrode layer in the stacking direction; and The second intermediate electrode layer opposing portion faces the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction.

6. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The intermediate electrode layer includes a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer. The first intermediate electrode layer has: a first electrode layer-side opposing portion facing the first internal electrode layer disposed adjacent to the first internal electrode layer in the stacking direction; and The first intermediate electrode layer facing portion faces the third intermediate electrode layer disposed adjacent to the third intermediate electrode layer in the stacking direction. The second intermediate electrode layer has: a second electrode layer-side opposing portion facing the second internal electrode layer disposed adjacent to the second internal electrode layer in the stacking direction; and The second intermediate electrode layer facing portion faces the third intermediate electrode layer disposed adjacent to the third intermediate electrode layer in the stacking direction. The third intermediate electrode layer has: a third intermediate electrode layer opposing portion opposing the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the stacking direction; and The fourth intermediate electrode layer opposing portion faces the second intermediate electrode layer disposed adjacent to the second intermediate electrode layer in the stacking direction.

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