A power module packaging structure and a manufacturing method thereof

Abstract

The application provides a power module packaging structure and a manufacturing method, a thermistor is electrically connected by pressureless silver sintering and a copper surface, a chip is electrically connected by pressure silver sintering and a copper surface, the pressureless silver sintering of the thermistor and the pressure silver sintering of the chip are synchronously performed, so that the process is reduced and the cost is lowered; and the copper bridge is used to connect different regions and electrode leads, so that the size and volume of the power module are greatly reduced, the power density is improved, the stray inductance is reduced, the parasitic capacitance is reduced, and the power cycle reliability of the device is more than twice that of a traditional shell sealing module; in addition, a plurality of chips are connected in parallel on the copper surface of the third part, and a plurality of chips are connected in parallel on the copper surface of the fourth part, so that the overcurrent capacity is improved, the gate lines of the parallel chips are shared, the switching speed of the parallel chips is consistent, and the chip current sharing performance is good.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and relates to a power module packaging structure and a manufacturing method. BACKGROUND

[0002] With the increasing demand for power density, reliability, stray inductance, cost and installation flexibility and reliability of the power module, the traditional shell sealing module has been unable to meet the demand. Figure 1 The traditional shell sealing module is to weld a functional chip 01 to a double-sided copper clad ceramic substrate 02, then weld the double-sided copper clad ceramic substrate 02 to a copper bottom plate 03, bond the surface of the functional chip 01 with an aluminum wire 04, and finally mechanically protect the structure by a plastic sealing shell 05, while filling the inside with insulating silica gel. Due to the limitations of the shell and the bonding process, the volume of the power module is large, and the power density is low; and under the power cycle test condition, because the thermal expansion coefficients of the aluminum wire (thermal expansion coefficient: 23.5x10 -6 / K) and the chip (thermal expansion coefficient: 2.6~4.3x10 -6 / K) are quite different, the neck of the bonding point will crack after a certain number of power cycles, and the power cycle reliability is low; in addition, the stray inductance of the traditional shell sealing module is generally high, usually not less than 20nH, the size of the double-sided copper clad ceramic substrate is large, the parasitic capacitance is high, and in high frequency applications, the dv / dt increases, which will generate a high common mode current, causing serious interference to the driving circuit or causing driving failure and driving board damage.

[0003] Therefore, how to provide a power module packaging structure and a manufacturing method to reduce cost, reduce stray inductance, improve reliability and improve installation flexibility has become a technical problem to be solved by those skilled in the art. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a power module packaging structure and a manufacturing method to solve the problems of large volume, low power density, high cost and low reliability of the power module in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a manufacturing method of a power module packaging structure, comprising the following steps:

[0006] A copper clad ceramic substrate is provided, which comprises oppositely arranged upper and lower copper surfaces, and the upper copper surface comprises first, second, third and fourth part upper copper surfaces arranged at intervals;

[0007] Silver paste is printed on the first, second, third and fourth part upper copper surfaces.

[0008] The thermistor and a plurality of chips are provided, one end of the thermistor is attached to the silver paste on the copper surface of the first part, the other end of the thermistor is attached to the silver paste on the copper surface of the second part, the chip includes oppositely arranged first and second surfaces, the first surface of the chip is provided with a drain, the second surface of the chip is provided with a gate and a source, the first surface of at least two chips is attached to the silver paste on the copper surface of the third part, and the first surface of at least two chips is attached to the silver paste on the copper surface of the fourth part.

[0009] The structure attached with the thermistor and the chip is placed in a sintering furnace for sintering, wherein the chip is sintered by pressure silver sintering, and the thermistor is sintered by non-pressure silver sintering.

[0010] A solder layer is arranged at the soldering position of the copper surface of the first part, the copper surface of the second part, the copper surface of the third part, the copper surface of the fourth part and the chip.

[0011] A plurality of copper bridges are provided, all the copper bridges are placed at the corresponding soldering position for soldering, wherein the chips above the copper surface of the third part are connected in parallel, the chips above the copper surface of the fourth part are connected in parallel, and the chips above the copper surface of the third part and the chips above the copper surface of the fourth part are connected in series.

[0012] A packaging layer is formed, the upper surface of the packaging layer exposes the upper surface of the copper bridge at a preset position, and the lower surface of the packaging layer exposes the lower copper surface.

[0013] Optionally, when the structure attached with the thermistor and the chip is placed in a sintering furnace for sintering, an upper mold is used to press the second surface of the chip, and the upper mold does not contact the thermistor.

[0014] Optionally, the copper bridge includes a first copper bridge to a tenth copper bridge, wherein:

[0015] The first copper bridge electrically connects the gates of the chips above the copper surface of the third part, and the middle part of the first copper bridge is exposed on the upper surface of the packaging layer.

[0016] The second copper bridge electrically connects the sources of the chips above the copper surface of the third part, and the middle part of the second copper bridge is exposed on the upper surface of the packaging layer.

[0017] The third copper bridge electrically connects the gates of the chips above the copper surface of the fourth part, and the middle part of the third copper bridge is exposed on the upper surface of the packaging layer.

[0018] A fourth copper bridge electrically connects the source of the chip above the fourth upper copper surface, and the middle part of the fourth copper bridge is exposed on the upper surface of the packaging layer;

[0019] A fifth copper bridge electrically connects the source of the chip above the third upper copper surface and the fourth upper copper surface;

[0020] A bottom end of a sixth copper bridge is soldered to the first upper copper surface, and a top end of the sixth copper bridge is exposed on the upper surface of the packaging layer;

[0021] A bottom end of a seventh copper bridge is soldered to the second upper copper surface, and a top end of the seventh copper bridge is exposed on the upper surface of the packaging layer;

[0022] A bottom end of an eighth copper bridge is soldered to the third upper copper surface, and a top end of the eighth copper bridge is exposed on the upper surface of the packaging layer;

[0023] A bottom end of a ninth copper bridge is soldered to the fourth upper copper surface, and a top end of the ninth copper bridge is exposed on the upper surface of the packaging layer;

[0024] A bottom end of a tenth copper bridge is soldered to the source of the chip above the fourth upper copper surface, the top end of the tenth copper bridge approaches the eighth copper bridge across the fifth copper bridge, and the top end of the tenth copper bridge is exposed on the upper surface of the packaging layer.

[0025] Optionally, the second surface of the chip is further provided with a Kelvin source, and the copper bridge further includes an eleventh copper bridge and a twelfth copper bridge, wherein:

[0026] The eleventh copper bridge electrically connects the Kelvin source of the chip above the third upper copper surface, and the middle part of the eleventh copper bridge is exposed on the upper surface of the packaging layer;

[0027] The twelfth copper bridge electrically connects the Kelvin source of the chip above the fourth upper copper surface, and the middle part of the twelfth copper bridge is exposed on the upper surface of the packaging layer.

[0028] Optionally, before forming the packaging layer, the structure after the copper bridge is soldered is further subjected to a plasma surface treatment.

[0029] Optionally, the material of the packaging layer is epoxy resin.

[0030] The application further provides a power module packaging structure, comprising:

[0031] A copper-clad ceramic substrate includes oppositely arranged upper and lower copper surfaces, and the upper copper surface includes a first upper copper surface, a second upper copper surface, a third upper copper surface, and a fourth upper copper surface arranged at intervals;

[0032] a thermistor, one end of the thermistor is electrically connected with the copper surface of the first part by pressureless silver sintering, and the other end of the thermistor is electrically connected with the copper surface of the second part by pressureless silver sintering;

[0033] a plurality of chips, the chip comprising a first surface and a second surface arranged oppositely, the first surface of the chip being provided with a drain electrode, and the second surface of the chip being provided with a gate electrode and a source electrode, the first surfaces of at least two of the chips being electrically connected with the copper surface of the third part by pressure silver sintering, and the first surfaces of at least two of the chips being electrically connected with the copper surface of the fourth part by pressure silver sintering;

[0034] a solder layer, located at the soldering position of the copper surface of the first part, the copper surface of the second part, the copper surface of the third part, the copper surface of the fourth part and the chip;

[0035] a plurality of copper bridges, the copper bridges being soldered by the solder layer and the corresponding soldering position, wherein the chips above the copper surface of the third part are connected in parallel, the chips above the copper surface of the fourth part are connected in parallel, and the chips above the copper surface of the third part and the chips above the copper surface of the fourth part are connected in series;

[0036] a packaging layer, an upper surface of the packaging layer exposing an upper surface of the copper bridge at a preset position, and a lower surface of the packaging layer exposing the lower copper surface.

[0037] Optionally, the copper bridge comprises a first copper bridge to a tenth copper bridge, wherein:

[0038] the first copper bridge electrically connects the gate electrodes of the chips above the copper surface of the third part, and the middle part of the first copper bridge is exposed on the upper surface of the packaging layer;

[0039] the second copper bridge electrically connects the source electrodes of the chips above the copper surface of the third part, and the middle part of the second copper bridge is exposed on the upper surface of the packaging layer;

[0040] the third copper bridge electrically connects the gate electrodes of the chips above the copper surface of the fourth part, and the middle part of the third copper bridge is exposed on the upper surface of the packaging layer;

[0041] the fourth copper bridge electrically connects the source electrodes of the chips above the copper surface of the fourth part, and the middle part of the fourth copper bridge is exposed on the upper surface of the packaging layer;

[0042] the fifth copper bridge electrically connects the source electrodes of the chips above the copper surface of the third part and the copper surface of the fourth part;

[0043] the bottom end of the sixth copper bridge is soldered with the copper surface of the first part, and the top end of the sixth copper bridge is exposed on the upper surface of the packaging layer;

[0044] a bottom end of the seventh copper bridge is welded with the upper copper surface of the second part, and a top end of the seventh copper bridge is exposed on the upper surface of the packaging layer;

[0045] a bottom end of the eighth copper bridge is welded with the upper copper surface of the third part, and a top end of the eighth copper bridge is exposed on the upper surface of the packaging layer;

[0046] a bottom end of the ninth copper bridge is welded with the upper copper surface of the fourth part, and a top end of the ninth copper bridge is exposed on the upper surface of the packaging layer;

[0047] a bottom end of the tenth copper bridge is welded with the source electrode of the chip above the upper copper surface of the fourth part, a top end of the tenth copper bridge is close to the eighth copper bridge across the fifth copper bridge, and the top end of the tenth copper bridge is exposed on the upper surface of the packaging layer.

[0048] Optionally, the second surface of the chip is further provided with a Kelvin source electrode, and the copper bridge further comprises an eleventh copper bridge and a twelfth copper bridge, wherein:

[0049] the eleventh copper bridge electrically connects the Kelvin source electrode of the chip above the upper copper surface of the third part, and a middle part of the eleventh copper bridge is exposed on the upper surface of the packaging layer;

[0050] the twelfth copper bridge electrically connects the Kelvin source electrode of the chip above the upper copper surface of the fourth part, and a middle part of the twelfth copper bridge is exposed on the upper surface of the packaging layer.

[0051] Optionally, the material of the packaging layer is epoxy resin.

[0052] As described above, in the power module packaging structure and manufacturing method of the present application, the thermistor is electrically connected with the upper copper surface through pressureless silver sintering, and the chip is electrically connected with the upper copper surface through silver sintering under pressure, and the pressureless silver sintering of the thermistor and the silver sintering under pressure of the chip are performed synchronously, thereby reducing the process and cost; and the copper bridge is used to connect different regions and lead out electrodes, thereby greatly reducing the size and volume of the power module, improving the power density, reducing the stray inductance, reducing the parasitic capacitance, and the power cycle reliability of the device is more than twice that of the traditional shell sealing module; in addition, the third part of the upper copper surface is provided with a plurality of chips connected in parallel, and the fourth part of the upper copper surface is provided with a plurality of chips connected in parallel, thereby improving the overcurrent capacity, and the gate line is shared by the parallel chips, so that the switching speed of the parallel chips is consistent, and the chip current sharing performance is good. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 a schematic diagram of a traditional shell sealing module is shown.

[0054] Figure 2 a flow chart of the manufacturing method of the power module packaging structure in the embodiment of the present application is shown.

[0055] Figure 3 A schematic diagram of a copper clad ceramic substrate in an embodiment of the present application is shown.

[0056] Figure 4 A schematic diagram of printing silver paste in an embodiment of the present application is shown.

[0057] Figure 5 A schematic diagram of mounting a thermistor and a plurality of chips in an embodiment of the present application is shown.

[0058] Figure 6 A schematic diagram after soldering copper bridges in an embodiment of the present application is shown.

[0059] Figure 7 A sectional view after soldering copper bridges in an embodiment of the present application is shown.

[0060] Figure 8 A schematic diagram of forming a packaging layer in an embodiment of the present application is shown.

[0061] Figure 9 A circuit diagram of a power module in an embodiment of the present application is shown.

[0062] Figure 10 A schematic diagram of exposing a lower copper surface of a packaging layer in an embodiment of the present application is shown.

[0063] Element No. Explanation 01 - functional chip, 02 - double-sided copper clad ceramic substrate, 03 - copper bottom plate, 04 - aluminum wire, 05 - plastic package shell; 1 - copper clad ceramic substrate, 100 - upper copper surface, 1001 - first part of upper copper surface, 1002 - second part of upper copper surface, 1003 - third part of upper copper surface, 1004 - fourth part of upper copper surface, 101 - lower copper surface, 102 - ceramic layer; 2 - silver paste; 3 - thermistor; 4 - chip; 501 - first copper bridge, 502 - second copper bridge, 503 - third copper bridge, 504 - fourth copper bridge, 505 - fifth copper bridge, 506 - sixth copper bridge, 507 - seventh copper bridge, 508 - eighth copper bridge, 509 - ninth copper bridge, 510 - tenth copper bridge, 511 - eleventh copper bridge, 512 - twelfth copper bridge; 6 - packaging layer; S1-S7 - steps. DETAILED DESCRIPTION

[0064] The above embodiments of the present application are shown and described by specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description. The present application can be implemented or applied by other different embodiments, and the details in the description can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0065] Please refer to Figures 2 to 10It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout of the components can be more complex.

[0066] The embodiment provides a manufacturing method of a power module packaging structure. Figure 2 The manufacturing method of the power module packaging structure comprises the following steps.

[0067] S1: A copper-clad ceramic substrate is provided, the copper-clad ceramic substrate comprises oppositely arranged upper copper surfaces and lower copper surfaces, and the upper copper surfaces comprise first, second, third and fourth upper copper surfaces arranged at intervals.

[0068] S2: Silver paste is printed on the first, second, third and fourth upper copper surfaces.

[0069] S3: A thermistor and a plurality of chips are provided, one end of the thermistor is attached to the silver paste on the first upper copper surface, the other end of the thermistor is attached to the silver paste on the second upper copper surface, the chip comprises oppositely arranged first and second surfaces, the first surface of the chip is provided with a drain electrode, the second surface of the chip is provided with a gate electrode and a source electrode, and the first surfaces of at least two chips are attached to the silver paste on the third upper copper surface, and the first surfaces of at least two chips are attached to the silver paste on the fourth upper copper surface.

[0070] S4: The structure with the thermistor and the chips attached is placed in a sintering furnace for sintering, wherein the chips are sintered by pressure silver, and the thermistor is sintered by non-pressure silver.

[0071] S5: A solder layer is arranged at the soldering positions of the first, second, third and fourth upper copper surfaces and the chips.

[0072] S6: A plurality of copper bridges are provided, all the copper bridges are placed at corresponding soldering positions for soldering, wherein the chips above the third upper copper surface are connected in parallel, the chips above the fourth upper copper surface are connected in parallel, and the chips above the third upper copper surface and the chips above the fourth upper copper surface are connected in series.

[0073] S7: A packaging layer is formed, the upper surface of the packaging layer exposes the upper surfaces of the copper bridges at predetermined positions, and the lower surface of the packaging layer exposes the lower copper surfaces.

[0074] The manufacturing method of the power module packaging structure in the embodiment will be described in detail below with reference to the specific drawings.

[0075] First, refer to Figure 3 , step S1 is performed: a copper-clad ceramic substrate 1 is provided, which includes oppositely arranged upper and lower copper surfaces, and the upper copper surface includes a first partial upper copper surface 1001, a second partial upper copper surface 1002, a third partial upper copper surface 1003, and a fourth partial upper copper surface 1004 arranged at intervals.

[0076] As an example, the copper-clad ceramic substrate 1 adopts a double-sided copper-clad ceramic substrate, and the upper copper surface and the lower copper surface are separated by a ceramic layer 102. In the perspective of Figure 3 , only the upper copper surface and the ceramic layer 102 are exposed, and the cross-sectional view of the copper-clad ceramic substrate 1 is shown in the subsequent Figure 7 , the upper copper surface 100 and the lower copper surface 101 are arranged on both sides of the ceramic layer 102.

[0077] As an example, the size and position of the first partial upper copper surface 1001, the second partial upper copper surface 1002, the third partial upper copper surface 1003, and the fourth partial upper copper surface 1004 are set according to requirements. In this embodiment, the first partial upper copper surface 1001 and the second partial upper copper surface 1002 are used for soldering thermistors later, so the size of the first partial upper copper surface 1001 and the second partial upper copper surface 1002 is set to be smaller, and the third partial upper copper surface 1003 and the fourth partial upper copper surface 1004 are used for soldering chips later, so the size of the third partial upper copper surface 1003 and the fourth partial upper copper surface 1004 is set to be larger. The third partial upper copper surface 1003 and the fourth partial upper copper surface 1004 are separated by a predetermined distance, and the first partial upper copper surface 1001 and the second partial upper copper surface 1002 are located in the gap between the third partial upper copper surface 1003 and the fourth partial upper copper surface 1004.

[0078] Next, refer to Figure 4 , step S2 is performed: silver paste 2 is printed on the first partial upper copper surface 1001, the second partial upper copper surface 1002, the third partial upper copper surface 1003, and the fourth partial upper copper surface 1004.

[0079] As an example, the silver paste 2 is printed at the positions where the thermistors and chips will be attached later. After printing the silver paste 2, preliminary curing is performed to remove moisture and solvents in the silver paste 2. Specifically, in this embodiment, the temperature for preliminary curing is 100°C to 130°C.

[0080] Next, refer to Figure 5, execute step S3: provide the thermistor 3 and a plurality of chips 4, one end of the thermistor 3 is pasted on the silver paste of the copper surface 1001 of the first part, the other end of the thermistor 3 is pasted on the silver paste of the copper surface 1002 of the second part, the chip 4 includes a first surface and a second surface arranged oppositely, the first surface of the chip 4 is provided with a drain, the second surface of the chip 4 is provided with a gate and a source, and the first surface of at least two chips 4 is pasted on the silver paste of the copper surface 1003 of the third part. The first surface of at least two chips 4 is pasted on the silver paste of the copper surface 1004 of the fourth part.

[0081] As an example, the thermistor 3 is used to monitor the internal temperature of the power module, and in this embodiment, the thermistor 3 adopts a glass-encapsulated thermistor. The glass-encapsulated thermistor has the advantages of high temperature resistance, good air tightness, good chemical inertness, good insulation, etc., and can provide accurate, stable and long-term temperature monitoring for the power module.

[0082] As an example, the number of chips 4 in this embodiment is four, of which the number of chips pasted on the copper surface 1003 of the third part is two, and the drains (D) of the two chips on the copper surface 1003 of the third part are electrically connected through the copper surface 1003 of the third part. The number of chips pasted on the copper surface 1004 of the fourth part is two, and the drains (D) of the two chips on the copper surface 1004 of the fourth part are electrically connected through the copper surface 1004 of the fourth part.

[0083] Then, step S4 is executed, and the structure pasted with the thermistor 3 and the chip 4 is placed in a sintering furnace for sintering, wherein the chip 4 is sintered with pressure silver, and the thermistor 3 is sintered without pressure silver.

[0084] As an example, the structure pasted with the thermistor 3 and the chip 4 is placed in the lower die of the sintering furnace, and then the upper die is used to press the second surface of the chip 4, so that the chip 4 is sintered with pressure silver, wherein the upper die is designed so that when the upper die presses the chip 4, the upper die does not come into contact with the thermistor 3, and the thermistor 3 is sintered without pressure silver.

[0085] As an example, the thermistor 3 is glass-encapsulated, which has weak mechanical strength and may be damaged by pressure. In the prior art, the steps of connecting the thermistor and other devices include: tin paste, welding and cleaning, which increases three processes. In this application, the thermistor 3 is sintered without pressure silver, and the sintering of the chip 4 with pressure silver is synchronized, which can reduce the process, reduce the cost, and improve the production efficiency.

[0086] As an example, although the reliability of the no-pressure silver sintering is lower than that of the pressure silver sintering, it is completely sufficient to be used in the thermistor 3. Because the detection current is small when the thermistor 3 is applied, for example, in the electric vehicle application, the current of the thermistor is less than 10 mA, and the power loss is usually not more than 20 mV, the electrical connection requirement is low, and it is sufficient to be connected.

[0087] As an example, the chip 4 is sintered by the pressure silver, so that the high mechanical strength and the high reliability connection between the chip 4 and the upper copper surface are realized.

[0088] Then, step S5 is performed: the solder layer is arranged at the welding positions of the first part of the upper copper surface 1001, the second part of the upper copper surface 1002, the third part of the upper copper surface 1003, the fourth part of the upper copper surface 1004 and the chip 4.

[0089] As an example, the arrangement of the solder layer includes the tin paste and the pre-solder sheet, wherein the tin paste is arranged as the solder layer for the area with small welding position, and the pre-solder sheet is arranged as the solder layer for the area with large welding position.

[0090] Specifically, the tin paste is arranged as the solder layer on the first part of the upper copper surface 1001, the tin paste is arranged as the solder layer on the second part of the upper copper surface 1002, the pre-solder sheet is arranged as the solder layer on the third part of the upper copper surface 1003, and the pre-solder sheet is arranged as the solder layer on the fourth part of the upper copper surface.

[0091] Specifically, in the embodiment, the second surface of the chip 4 is also provided with the Kelvin source (KS), so as to eliminate the interference of the source parasitic inductance / resistance in the chip on the gate drive signal and improve the switching performance. Wherein, the tin paste is arranged as the solder layer on the gate (G) and the Kelvin source (KS) of the chip 4, and the pre-solder sheet is arranged as the solder layer on the source (S) of the chip 4.

[0092] Then, referring to Figure 6 and Figure 7 , step S6 is performed: a plurality of copper bridges are provided, all the copper bridges are placed at the corresponding welding positions and are welded, wherein the chip 4 above the third part of the upper copper surface 1003 is connected in parallel, the chip 4 above the fourth part of the upper copper surface 1004 is connected in parallel, and the chip 4 above the third part of the upper copper surface 1003 and the chip 4 above the fourth part of the upper copper surface 1004 are connected in series.

[0093] As an example, the copper bridge includes a first copper bridge 501 to a tenth copper bridge 510, wherein:

[0094] The first copper bridge 501 electrically connects the gate (G) of the chip 4 above the third part of the upper copper surface 1003;

[0095] The second copper bridge 502 electrically connects the source (S) of the chip 4 above the third copper surface 1003 of the third portion;

[0096] The third copper bridge 503 electrically connects the gate (G) of the chip 4 above the fourth copper surface 1004 of the fourth portion;

[0097] The fourth copper bridge 504 electrically connects the source (S) of the chip 4 above the fourth copper surface 1004 of the fourth portion;

[0098] The fifth copper bridge 505 electrically connects the source (S) of the chip 4 above the third copper surface 1003 of the third portion and the fourth copper surface 1004 of the fourth portion;

[0099] The bottom end of the sixth copper bridge 506 is welded with the first copper surface 1001 of the first portion;

[0100] The bottom end of the seventh copper bridge 507 is welded with the second copper surface 1002 of the second portion;

[0101] The bottom end of the eighth copper bridge 508 is welded with the third copper surface 1003 of the third portion;

[0102] The bottom end of the ninth copper bridge 509 is welded with the fourth copper surface 1004 of the fourth portion;

[0103] The bottom end of the tenth copper bridge 510 is welded with the source (S) of the chip 4 above the fourth copper surface 1004 of the fourth portion.

[0104] As an example, since the second surface of the chip 4 is also provided with a Kelvin source (KS), the copper bridge further comprises an eleventh copper bridge 511 and a twelfth copper bridge 512, wherein,

[0105] The eleventh copper bridge 511 electrically connects the Kelvin source (KS) of the chip 4 above the third copper surface 1003 of the third portion;

[0106] The twelfth copper bridge 512 electrically connects the Kelvin source (KS) of the chip 4 above the fourth copper surface 1004 of the fourth portion.

[0107] As an example, for the chip 4 on the third part of the upper copper surface 1003, the drain (D) of the chip is electrically connected through the third part of the upper copper surface 1003, the gate (G) of the chip is electrically connected through the first copper bridge 501, the source (S) of the chip is electrically connected through the second copper bridge 502, and the Kelvin source (KS) of the chip is electrically connected through the eleventh copper bridge 511, so that the chip 4 on the third part of the upper copper surface 1003 is connected in parallel, and the overcurrent capacity is increased, wherein the chip 4 on the third part of the upper copper surface 1003 shares the gate line (the first copper bridge 501), which can make the switching speed of the parallel chips consistent, the current sharing performance of the chips is good, and the different gate resistances caused by different gate line lengths or lines are reduced, thereby affecting the switching speed and current sharing performance of the parallel chips. If the switching speed of the parallel chips is not the same, the chips will not share the current, the chip with large current will heat up, and in extreme cases, product failure can be caused.

[0108] Similarly, for the chip 4 on the fourth part of the upper copper surface 1004, the drain (D) of the chip is electrically connected through the fourth part of the upper copper surface 1004, the gate (G) of the chip is electrically connected through the third copper bridge 503, the source (S) of the chip is electrically connected through the fourth copper bridge 504, and the Kelvin source (KS) of the chip is electrically connected through the twelfth copper bridge 512, so that the chip 4 on the fourth part of the upper copper surface 1004 is connected in parallel, and the overcurrent capacity is increased, wherein the chip 4 on the fourth part of the upper copper surface 1004 shares the gate line (the third copper bridge 503).

[0109] As an example, the chip 4 on the third part of the upper copper surface 1003 is recorded as the first group of parallel chips, the chip 4 on the fourth part of the upper copper surface 1004 is recorded as the second group of parallel chips, and the fifth copper bridge 505 electrically connects the source (D) of the chip 4 above the third part of the upper copper surface 1003 and the fourth part of the upper copper surface 1004, that is, the fifth copper bridge 505 electrically connects the source (S) of the first group of parallel chips and the drain (D) of the second group of parallel chips, so that the first group of parallel chips and the second group of parallel chips are connected in series.

[0110] As an example, the sixth copper bridge 506 and the seventh copper bridge 507 are respectively used as the lead terminals of the thermistor 3.

[0111] As an example, the eighth copper bridge 508 is used as a direct-current bus positive terminal (P).

[0112] As an example, the ninth copper bridge 509 is used as a three-phase alternating-current output terminal (U / V / W).

[0113] As an example, the tenth copper bridge 510 is used as a DC bus negative terminal (N), wherein the top end of the tenth copper bridge 510 is close to the eighth copper bridge 508 across the fifth copper bridge 505, that is, the DC bus positive terminal (P) and the DC bus negative terminal (N) are arranged in parallel and are close to each other, so that an ultra-low stray inductance can be achieved, and the stray inductance is less than 2 nH. Compared with the traditional 34MM / P1 shell sealing module (the stray inductance is about 30 nH), the 62MM / P2 shell sealing module and the Econodual3 / E3 shell sealing module (the stray inductance is about 20 nH), the stray inductance is greatly reduced, and the performance is improved.

[0114] As an example, in the prior art, different regions are connected by bonding with aluminum wires, the aluminum wires are prone to deformation, and in the industry, the curvature of the aluminum wires is usually required to be relatively high, so that the thickness of the power module is relatively thick; and usually, the aluminum wires of different electrodes are not staggered in space to avoid accidentally touching in production to change the spacing of the upper and lower aluminum wires, thereby affecting the reliability of the product. In the present application, different regions are connected and electrodes are led out by using copper bridges, the copper bridges are not prone to deformation, the height thereof does not need to be very high, the thickness of the power module can be reduced, and the copper bridges can be designed in a stacked manner (for example, the tenth copper bridge 510 is arranged above the fifth copper bridge 505), so that the volume of the power module can be reduced, the power density can be improved, and the parasitic capacitance can be reduced; in addition, the overcurrent capacity of the copper bridge is greater than that of the aluminum wire, so that the power cycle times of the power module can be improved, and the power cycle reliability can be improved by at least 2 times or more.

[0115] As an example, in the present embodiment, the copper bridges are welded by vacuum reflow soldering, including the following steps:

[0116] (1) Place a plurality of copper bridges on corresponding welding positions by suction / placement equipment or a mechanical hand, and fix the copper bridges with a clamp;

[0117] (2) Put the structure with the fixed copper bridges into a vacuum reflow furnace, and perform vacuum welding under the protection of 99.999% high-purity nitrogen to prevent oxidation and welding cavities of the product.

[0118] As an example, after the copper bridges are welded, a cleaning step is further included to remove the flux.

[0119] Next, referring to Figures 8 to 10 , a step S7 of forming an encapsulation layer 6 is performed, wherein an upper surface of the encapsulation layer 6 exposes an upper surface of the copper bridge at a preset position, and a lower surface of the encapsulation layer 6 exposes the lower copper surface 101.

[0120] As an example, before forming the encapsulation layer 6, a step of plasma surface treatment is further included after the structure with the copper bridges welded, and then the encapsulation layer 6 is formed, which can increase the bonding force between the encapsulation layer 6 and the surface of the substrate / chip, thereby enhancing the mechanical strength, moisture resistance and long-term reliability of the encapsulation.

[0121] Specifically, the structure after plasma surface treatment is put into an injection molding machine to perform injection molding to form the encapsulation layer 6, and the material of the encapsulation layer 6 is epoxy resin. The epoxy encapsulation layer enhances the mechanical strength, reliability and sealing performance of the module, and can be applied to a humid environment without the need for special sealing and moisture-proof protection like traditional shell encapsulation modules.

[0122] As an example, the middle part of the first copper bridge 501 is exposed on the upper surface of the encapsulation layer 6 to form the gate terminal of the first group of parallel chips, denoted as G1; the middle part of the second copper bridge 502 is exposed on the upper surface of the encapsulation layer 6 to form the source terminal of the first group of parallel chips, denoted as S1; the middle part of the third copper bridge 503 is exposed on the upper surface of the encapsulation layer 6 to form the gate terminal of the second group of parallel chips, denoted as G2; the middle part of the fourth copper bridge 504 is exposed on the upper surface of the encapsulation layer 6 to form the source terminal of the second group of parallel chips, denoted as S2; the top end of the sixth copper bridge 506 is exposed on the upper surface of the encapsulation layer 6, and the top end of the seventh copper bridge 507 is exposed on the upper surface of the encapsulation layer 6 to form the lead terminals of the thermistor 3; the top end of the eighth copper bridge 508 is exposed on the upper surface of the encapsulation layer 6 to form the positive terminal of the DC bus of the power module, denoted as P; the top end of the ninth copper bridge 509 is exposed on the upper surface of the encapsulation layer 6 to form the three-phase AC output terminal of the power module, denoted as U / V / W; the top end of the tenth copper bridge 510 is exposed on the upper surface of the encapsulation layer 6 to form the negative terminal of the DC bus of the power module, denoted as N; the middle part of the eleventh copper bridge 511 is exposed on the upper surface of the encapsulation layer 6 to form the Kelvin source terminal of the first group of parallel chips, denoted as KS1; and the middle part of the twelfth copper bridge 512 is exposed on the upper surface of the encapsulation layer 6 to form the Kelvin source terminal of the second group of parallel chips, denoted as KS2. The circuit diagram of the power module in this embodiment is shown in Figure 9

[0123] As an example, in the prior art, the signal terminals of the vehicle-mounted power module are led out from the upper surface, and the power terminals are led out from the side surface, which need to be manually installed and welded when connected with other devices, resulting in low installation efficiency and high cost. In this embodiment, all the terminals are led out from the upper surface of the power module, so that the power module can be applied to surface mount installation, and the power module and other devices can be connected and installed through automatic equipment, thereby improving the efficiency and reducing the cost.

[0124] ​As an example, in the bill of materials (BOM) of the traditional power module, about 15 kinds of materials are needed, and in the bill of materials (BOM) of the power module of the present application, about 11 kinds of materials are needed, the number of materials used is less, and the cost can be reduced.

[0125] As an example, as shown in Figure 10 The lower surface of the packaging layer 6 exposes the lower copper surface 101, which is used for mounting the power module and other devices, for example, the power module is connected to the heat sink through the lower copper surface 101, etc.

[0126] As an example, in the traditional shell sealing module, the size of the 34MM / P1 shell sealing module is 34mm wide x 94mm long x 30mm high, the size of the 62MM / P2 shell sealing module is 61.4mm wide x 106mm long x 30mm high, and the size of the Econodual3 / E3 shell sealing module is 62mm wide x 152mm long x 20mm high, while in the present application, the size of the power module is 22mm wide x 32mm long x 5mm high, the thickness is one fourth of the Econodual3 / E3 shell sealing module, and the volume is one twenty-seventh of the 34MM / P1 shell sealing module, and the size and power density are greatly improved.

[0127] As an example, in the present embodiment, the power module is packaged with four chips, and according to the power level requirement, it can be expanded to six chips, eight chips, etc., to be compatible with different devices such as IGBT devices (low frequency), SiC devices (high frequency), GaN devices (ultra-high frequency), etc.

[0128] As an example, the power module of the present embodiment can be loaded into the tape & reel tape and Tray disc commonly used in the industry, reducing the packaging cost during transfer.

[0129] As described above, in the manufacturing method of the power module packaging structure of the present embodiment, the thermistor is connected to the upper copper surface by pressureless silver sintering and electrical connection, the chip is connected to the upper copper surface by pressure silver sintering and electrical connection, the pressureless silver sintering of the thermistor and the pressure silver sintering of the chip are performed synchronously, which can reduce the process and reduce the cost; and the copper bridge is used to connect different regions and electrode leads, which can greatly reduce the size and volume of the power module, improve the power density, reduce the stray inductance, reduce the parasitic capacitance, and the power cycle reliability of the device is more than twice that of the traditional shell sealing module; in addition, a plurality of chips are connected in parallel on the third part of the upper copper surface, and a plurality of chips are connected in parallel on the fourth part of the upper copper surface, which can improve the overcurrent capacity, and the parallel chips share the gate line, which can make the switching speed of the parallel chips consistent, and the chip current sharing performance is good.

[0130] Thus, a power module packaging structure is prepared, which comprises a copper-clad ceramic substrate 1, a thermistor 3, a plurality of chips 4, a solder layer, a plurality of copper bridges and a packaging layer 6, the copper-clad ceramic substrate 1 comprises oppositely arranged upper and lower copper surfaces 100 and 101, the upper copper surface 100 comprises a first part of the upper copper surface 1001, a second part of the upper copper surface 1002, a third part of the upper copper surface 1003 and a fourth part of the upper copper surface 1004 arranged at intervals; one end of the thermistor 3 is electrically connected to the first part of the upper copper surface 1001 by pressureless silver sintering, and the other end of the thermistor 3 is electrically connected to the second part of the upper copper surface 1002 by pressureless silver sintering; the chip 4 comprises oppositely arranged first and second surfaces, the first surface of the chip 4 is provided with a drain electrode, and the second surface of the chip 4 is provided with a gate electrode and a source electrode, the first surfaces of at least two chips 4 are electrically connected to the third part of the upper copper surface 1003 by pressure silver sintering, and the first surfaces of at least two chips 4 are electrically connected to the fourth part of the upper copper surface 1004 by pressure silver sintering; the solder layer is located at the soldering positions of the first part of the upper copper surface 1001, the second part of the upper copper surface 1002, the third part of the upper copper surface 1003, the fourth part of the upper copper surface 1004 and the chip 4; a plurality of copper bridges are soldered through the solder layer and the corresponding soldering positions, wherein the chips 4 above the third part of the upper copper surface 1003 are connected in parallel, the chips 4 above the fourth part of the upper copper surface 1004 are connected in parallel, and the chips 4 above the third part of the upper copper surface 1003 and the chips 4 above the fourth part of the upper copper surface 1004 are connected in series; the upper surface of the packaging layer 6 exposes the upper surfaces of the copper bridges at the preset positions, and the lower surface of the packaging layer 6 exposes the lower copper surface 101.

[0131] As an example, the copper-clad ceramic substrate 1 adopts a double-sided copper-clad ceramic substrate, and the upper copper surface 100 and the lower copper surface 101 are separated by a ceramic layer 102.

[0132] As an example, the third part of the upper copper surface 1003 and the fourth part of the upper copper surface 1004 are spaced apart by a preset distance, and the first part of the upper copper surface 1001 and the second part of the upper copper surface 1002 are located at the gap between the third part of the upper copper surface 1003 and the fourth part of the upper copper surface 1004.

[0133] As an example, the thermistor 3 is used to monitor the internal temperature of the power module, and in this embodiment, the thermistor 3 adopts a glass-encapsulated thermistor; the glass-encapsulated thermistor has the advantages of high temperature resistance, good air tightness, good chemical inertness, good insulation and the like, and can provide accurate, stable and long-term temperature monitoring for the power module.

[0134] As an example, the number of chips 4 in the embodiment is four, the number of chips arranged on the third part copper surface 1003 is two, the drain (D) of the two chips on the third part copper surface 1003 is electrically connected through the third part copper surface 1003; the number of chips arranged on the fourth part copper surface 1004 is two, the drain (D) of the two chips on the fourth part copper surface 1004 is electrically connected through the fourth part copper surface 1004.

[0135] As an example, the solder layer includes tin paste and pre-solder sheet, wherein tin paste is used as the solder layer for the area with small soldering position, and pre-solder sheet is used as the solder layer for the area with large soldering position.

[0136] Specifically, tin paste is used as the solder layer on the first part copper surface 1001, tin paste is used as the solder layer on the second part copper surface 1002, pre-solder sheet is used as the solder layer on the third part copper surface 1003, and pre-solder sheet is used as the solder layer on the fourth part copper surface.

[0137] Specifically, in the embodiment, the second surface of the chip 4 is also provided with a Kelvin source (KS) to eliminate the interference of the source parasitic inductance / resistance in the chip on the gate drive signal and improve the switching performance. Tin paste is used as the solder layer on the gate (G) and the Kelvin source (KS) of the chip 4, and pre-solder sheet is used as the solder layer on the source (S) of the chip 4.

[0138] As an example, the copper bridge includes a first copper bridge 501 to a tenth copper bridge 510, wherein:

[0139] The first copper bridge 501 electrically connects the gate (G) of the chip 4 above the third part copper surface 1003;

[0140] The second copper bridge 502 electrically connects the source (S) of the chip 4 above the third part copper surface 1003;

[0141] The third copper bridge 503 electrically connects the gate (G) of the chip 4 above the fourth part copper surface 1004;

[0142] The fourth copper bridge 504 electrically connects the source (S) of the chip 4 above the fourth part copper surface 1004;

[0143] The fifth copper bridge 505 electrically connects the source (S) of the chip 4 above the third part copper surface 1003 and the fourth part copper surface 1004;

[0144] The bottom end of the sixth copper bridge 506 is soldered to the first part copper surface 1001;

[0145] the bottom end of the seventh copper bridge 507 is welded with the second part upper copper surface 1002;

[0146] the bottom end of the eighth copper bridge 508 is welded with the third part upper copper surface 1003;

[0147] the bottom end of the ninth copper bridge 509 is welded with the fourth part upper copper surface 1004;

[0148] the bottom end of the tenth copper bridge 510 is welded with the source (S) of the chip 4 above the fourth part upper copper surface 1004.

[0149] As an example, since the second surface of the chip 4 is also provided with a Kelvin source (KS), the copper bridge further comprises an eleventh copper bridge 511 and a twelfth copper bridge 512, wherein,

[0150] the eleventh copper bridge 511 electrically connects the Kelvin source (KS) of the chip 4 above the third part upper copper surface 1003;

[0151] the twelfth copper bridge 512 electrically connects the Kelvin source (KS) of the chip 4 above the fourth part upper copper surface 1004.

[0152] As an example, the chip 4 on the third part upper copper surface 1003 is recorded as a first group of parallel chips, the chip 4 on the fourth part upper copper surface 1004 is recorded as a second group of parallel chips, and the fifth copper bridge 505 electrically connects the source (D) of the chip 4 above the third part upper copper surface 1003 and the fourth part upper copper surface 1004, that is, the fifth copper bridge 505 electrically connects the source (S) of the first group of parallel chips and the drain (D) of the second group of parallel chips, so that the first group of parallel chips and the second group of parallel chips are connected in series.

[0153] As an example, the upper surface of the packaging layer 6 exposes the middle part of the first copper bridge 501, forming the gate terminal of the first group of parallel chips, marked as G1; the upper surface of the packaging layer 6 exposes the middle part of the second copper bridge 502, forming the source terminal of the first group of parallel chips, marked as S1; the upper surface of the packaging layer 6 exposes the middle part of the third copper bridge 503, forming the gate terminal of the second group of parallel chips, marked as G2; the upper surface of the packaging layer 6 exposes the middle part of the fourth copper bridge 504, forming the source terminal of the second group of parallel chips, marked as S2; the upper surface of the packaging layer 6 exposes the top end of the sixth copper bridge 506, and the upper surface of the packaging layer 6 exposes the top end of the seventh copper bridge 507, forming the lead-out terminals of the thermistor 3; the upper surface of the packaging layer 6 exposes the top end of the eighth copper bridge 508, forming the positive terminal of the DC bus of the power module, marked as P; the upper surface of the packaging layer 6 exposes the top end of the ninth copper bridge 509, forming the three-phase AC output terminal of the power module, marked as U / V / W; the upper surface of the packaging layer 6 exposes the top end of the tenth copper bridge 510, forming the negative terminal of the DC bus of the power module, marked as N; the upper surface of the packaging layer 6 exposes the middle part of the eleventh copper bridge 511, forming the Kelvin source terminal of the first group of parallel chips, marked as KS1; the upper surface of the packaging layer 6 exposes the middle part of the twelfth copper bridge 512, forming the Kelvin source terminal of the second group of parallel chips, marked as KS2.

[0154] As an example, the lower surface of the packaging layer 6 exposes the lower copper surface 101, which is used for mounting the power module and other devices, for example, the power module is connected to the heat sink through the lower copper surface 101, etc.

[0155] In summary, in the power module packaging structure and manufacturing method of the present application, the thermistor is connected to the upper copper surface by pressureless silver sintering, and the chip is connected to the upper copper surface by pressure silver sintering, the pressureless silver sintering of the thermistor and the pressure silver sintering of the chip are performed synchronously, which can reduce the process and reduce the cost; and the copper bridge is used to connect different regions and lead out the electrodes, which can greatly reduce the size and volume of the power module, improve the power density, reduce the stray inductance, reduce the parasitic capacitance, and the power cycle reliability of the device is more than twice that of the traditional shell sealing module; in addition, a plurality of chips are connected in parallel on the third part of the upper copper surface, and a plurality of chips are connected in parallel on the fourth part of the upper copper surface, which can improve the overcurrent capacity, and the parallel chips share the gate line, which can make the switching speed of the parallel chips consistent and the chip current sharing performance good. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0156] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method for manufacturing a power module packaging structure, characterized in that, Includes the following steps: A copper-clad ceramic substrate is provided, the copper-clad ceramic substrate includes an upper copper surface and a lower copper surface disposed opposite to each other, the upper copper surface includes a first part upper copper surface, a second part upper copper surface, a third part upper copper surface and a fourth part upper copper surface disposed at intervals; Silver paste is printed on the copper surfaces of the first part, the second part, the third part, and the fourth part. A thermistor and multiple chips are provided. One end of the thermistor is attached to the silver paste on the copper surface of the first part, and the other end of the thermistor is attached to the silver paste on the copper surface of the second part. Each chip has a first side and a second side arranged opposite to each other. The first side of the chip has a drain, and the second side of the chip has a gate and a source. At least two chips have their first sides attached to the silver paste on the copper surface of the third part, and at least two chips have their first sides attached to the silver paste on the copper surface of the fourth part. The structure with the thermistor and the chip attached is placed in a sintering furnace for sintering, wherein the chip is sintered with pressurized silver and the thermistor is sintered with non-pressurized silver. Solder layers are provided on the copper surfaces of the first portion, the second portion, the third portion, the fourth portion, and the soldering positions of the chip; Multiple copper bridges are provided, and all the copper bridges are placed in corresponding welding positions for welding. The chips above the copper surface of the third part are connected in parallel, the chips above the copper surface of the fourth part are connected in parallel, and the chips above the copper surface of the third part and the chips above the copper surface of the fourth part are connected in series. An encapsulation layer is formed, wherein the upper surface of the encapsulation layer exposes the upper surface of the copper bridge at a predetermined position, and the lower surface of the encapsulation layer exposes the lower copper surface.

2. The method for manufacturing the power module packaging structure according to claim 1, characterized in that: When the structure with the thermistor and the chip attached is placed in a sintering furnace for sintering, an upper mold is used to press against the second side of the chip, and the upper mold does not contact the thermistor.

3. The method for manufacturing the power module packaging structure according to claim 1, characterized in that, The bronze bridges include the first to the tenth bronze bridges, wherein: The first copper bridge electrically connects the gate of the chip above the copper surface of the third part, and the middle part of the first copper bridge is exposed on the upper surface of the package layer. The second copper bridge electrically connects the source of the chip above the copper surface of the third part, and the middle part of the second copper bridge is exposed on the upper surface of the package layer. The third copper bridge electrically connects the gate of the chip above the copper surface of the fourth part, and the middle part of the third copper bridge is exposed on the upper surface of the package layer. The fourth copper bridge electrically connects the source of the chip above the copper surface of the fourth part, and the middle part of the fourth copper bridge is exposed on the upper surface of the package layer. The fifth copper bridge electrically connects the source of the chip above the copper surface of the third part to the copper surface of the fourth part; The bottom end of the sixth copper bridge is welded to the upper copper surface of the first part, and the top end of the sixth copper bridge is exposed on the upper surface of the encapsulation layer; The bottom end of the seventh copper bridge is welded to the upper copper surface of the second part, and the top end of the seventh copper bridge is exposed on the upper surface of the encapsulation layer; The bottom end of the eighth copper bridge is welded to the copper surface of the third part, and the top end of the eighth copper bridge is exposed on the upper surface of the encapsulation layer; The bottom end of the ninth copper bridge is welded to the copper surface of the fourth part, and the top end of the ninth copper bridge is exposed on the upper surface of the encapsulation layer. The bottom end of the tenth copper bridge is soldered to the source electrode of the chip above the copper surface of the fourth part, the top end of the tenth copper bridge crosses the fifth copper bridge and approaches the eighth copper bridge, and the top end of the tenth copper bridge is exposed on the upper surface of the encapsulation layer.

4. The method for manufacturing the power module packaging structure according to claim 3, characterized in that, The second side of the chip is also provided with a Kelvin source electrode, and the copper bridge further includes an eleventh copper bridge and a twelfth copper bridge, wherein: The eleventh copper bridge electrically connects the Kelvin source electrode of the chip above the copper surface of the third part, and the middle part of the eleventh copper bridge is exposed on the upper surface of the package layer. The twelfth copper bridge electrically connects the Kelvin source electrode of the chip above the copper surface of the fourth part, and the middle part of the twelfth copper bridge is exposed on the upper surface of the package layer.

5. The method for manufacturing the power module packaging structure according to claim 1, characterized in that: Before forming the encapsulation layer, the process also includes a plasma surface treatment step on the structure with the copper bridge soldered on.

6. The method for manufacturing the power module packaging structure according to claim 1, characterized in that: The encapsulation layer is made of epoxy resin.

7. A power module packaging structure, characterized in that, include: A copper-clad ceramic substrate includes an upper copper surface and a lower copper surface disposed opposite to each other. The upper copper surface includes a first part upper copper surface, a second part upper copper surface, a third part upper copper surface and a fourth part upper copper surface disposed at intervals. A thermistor, one end of which is electrically connected to the copper surface of the first part through pressureless silver sintering, and the other end of which is electrically connected to the copper surface of the second part through pressureless silver sintering; Multiple chips, each chip having a first side and a second side disposed opposite to each other, the first side of the chip having a drain, the second side of the chip having a gate and a source, at least two of the first sides of the chips being electrically connected by a silver-bonded sintering and a copper surface on the third part, and at least two of the first sides of the chips being electrically connected by a silver-bonded sintering and a copper surface on the fourth part. The solder layer is located on the copper surface of the first part, the copper surface of the second part, the copper surface of the third part, the copper surface of the fourth part, and the soldering position of the chip; Multiple copper bridges are welded through the solder layer and corresponding welding positions, wherein the chips above the copper surface of the third part are connected in parallel, the chips above the copper surface of the fourth part are connected in parallel, and the chips above the copper surface of the third part and the chips above the copper surface of the fourth part are connected in series. The encapsulation layer has an upper surface that exposes the upper surface of the copper bridge at a predetermined position, and a lower surface that exposes the lower copper surface.

8. The power module packaging structure according to claim 7, characterized in that, The bronze bridges include the first to the tenth bronze bridges, wherein: The first copper bridge electrically connects the gate of the chip above the copper surface of the third part, and the middle part of the first copper bridge is exposed on the upper surface of the package layer. The second copper bridge electrically connects the source of the chip above the copper surface of the third part, and the middle part of the second copper bridge is exposed on the upper surface of the package layer. The third copper bridge electrically connects the gate of the chip above the copper surface of the fourth part, and the middle part of the third copper bridge is exposed on the upper surface of the package layer. The fourth copper bridge electrically connects the source of the chip above the copper surface of the fourth part, and the middle part of the fourth copper bridge is exposed on the upper surface of the package layer. The fifth copper bridge electrically connects the source of the chip above the copper surface of the third part to the copper surface of the fourth part; The bottom end of the sixth copper bridge is welded to the upper copper surface of the first part, and the top end of the sixth copper bridge is exposed on the upper surface of the encapsulation layer; The bottom end of the seventh copper bridge is welded to the upper copper surface of the second part, and the top end of the seventh copper bridge is exposed on the upper surface of the encapsulation layer; The bottom end of the eighth copper bridge is welded to the copper surface of the third part, and the top end of the eighth copper bridge is exposed on the upper surface of the encapsulation layer; The bottom end of the ninth copper bridge is welded to the copper surface of the fourth part, and the top end of the ninth copper bridge is exposed on the upper surface of the encapsulation layer. The bottom end of the tenth copper bridge is soldered to the source electrode of the chip above the copper surface of the fourth part, the top end of the tenth copper bridge crosses the fifth copper bridge and approaches the eighth copper bridge, and the top end of the tenth copper bridge is exposed on the upper surface of the encapsulation layer.

9. The power module packaging structure according to claim 8, characterized in that, The second side of the chip is also provided with a Kelvin source electrode, and the copper bridge further includes an eleventh copper bridge and a twelfth copper bridge, wherein: The eleventh copper bridge electrically connects the Kelvin source electrode of the chip above the copper surface of the third part, and the middle part of the eleventh copper bridge is exposed on the upper surface of the package layer. The twelfth copper bridge electrically connects the Kelvin source electrode of the chip above the copper surface of the fourth part, and the middle part of the twelfth copper bridge is exposed on the upper surface of the package layer.

10. The power module packaging structure according to claim 7, characterized in that: The encapsulation layer is made of epoxy resin.

Images