A fan-out wafer level chip packaging method

Abstract

The application relates to the field of design and manufacture of integrated circuit semiconductors, and particularly provides a fan-out wafer-level chip packaging method, which comprises the following process: wafer coating, ball planting, PI coating, wafer cutting, die mounting, primary plastic packaging, primary grinding, primary hole transferring, laser drilling, secondary RDL copper plating, secondary plastic packaging, carrier plate stripping, secondary hole transferring, secondary laser drilling, secondary RDL copper plating, pad copper plating, tertiary plastic packaging, secondary grinding, laser printing, pre-cutting, tinning, chip cutting, testing and banding, and packaging; the application adopts a Fanout process to replace a traditional ceramic packaging process, more I / O points can be arranged in limited space by "fan-out" of the I / O points to the outside of the chip boundary, the overall packaging size can be reduced due to the I / O points being rearranged on a larger carrier, and the design and layout of RDL can optimize signal transmission and improve electrical performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit semiconductor design and manufacturing, and specifically to a fan-out wafer-level chip packaging method. Background Technology

[0002] In the current semiconductor industry, electronic packaging has become a crucial aspect of industry development. The escalating global supply chain security issues are prompting countries to strengthen their domestic supply chains and reduce reliance on external sources. China also faces increasingly severe external sanctions and supply chain instability. Furthermore, China is the world's largest semiconductor market, with its market size continuously expanding. Especially driven by the application of cutting-edge technologies such as 5G communication, artificial intelligence, and the Internet of Things, the demand for high-performance, low-power, and highly integrated semiconductor products is growing rapidly, while the need for cost reduction and efficiency improvement is also urgent.

[0003] Due to its superior high-frequency performance, good insulation, and high thermal conductivity, ceramic packaging is commonly used in overseas markets for packaging electronic products. However, ceramic packaging manufacturing processes are complex, and the cost is higher than that of plastic encapsulation. Furthermore, ceramic materials are highly brittle and prone to breakage due to stress damage. Its automation and thinning capabilities are also inferior to plastic encapsulation, and the thermal expansion coefficient is not perfectly matched with the chip, potentially leading to solder joint fatigue. Currently, a new packaging type has been introduced to the domestic market to replace the high-cost ceramic packaging type from abroad: Fanout technology. Fanout technology has two main types: Fan-in and Fan-out. Traditional WLP packaging mostly uses the Fan-in type, suitable for ICs with low pin counts. However, as the number of IC signal output pins increases, the requirements for solder ball spacing become more stringent. Coupled with the PCB assembly requirements for adjusting the IC's post-packaging size and signal output pin positions, the Fan-out technology has emerged. The Fanout process deposits metal and dielectric layers on the chip surface to form a redistribution layer (RDL), connecting the chip's I / O points to the surface of the carrier, thereby achieving higher I / O density and better electrical performance.

[0004] A fan-out wafer-level packaging structure is disclosed in CN105390471B. The structure includes a carrier plate, a first opening in the carrier plate for loading a chip, a first redistribution layer formed on the carrier plate around the first opening, a conductive pillar formed on the first redistribution layer, a top surface of the conductive pillar being higher than a top surface of the chip, a first encapsulation layer formed on the carrier plate, the first encapsulation layer exposing the top surface of the conductive pillar and a connecting component of the chip, a second redistribution layer formed on the first encapsulation layer for connecting the conductive pillar and the chip, a second encapsulation layer formed on the second redistribution layer, the second encapsulation layer exposing a connecting area of the second redistribution layer, and a solder ball formed on the connecting area. The invention uses a fan-out process to form a fence-shaped pillar area to limit the expansion and contraction of the resin during the curing process and limit the offset of the chip. The first redistribution layer is arranged above the carrier plate and below the conductive pillar to increase the bonding force and improve the heat dissipation performance. However, the packaged chip product has the following disadvantages: 1) it needs to be molded based on the carrier plate, and the thickness is still large; 2) the molded product is a single-sided structure, and the design flexibility of the single-sided chip product is low.

[0005] CN114171507B discloses a wafer-level fan-out packaging method and structure. The method includes preparing a carrier plate with a recessed groove, forming a plastic encapsulation body directly on the carrier plate, removing the carrier plate to form a plastic encapsulation body with a recessed groove, using plastic encapsulation material to directly form the recessed groove, embedding a chip into the recessed groove, forming a passivation layer on the surface of the plastic encapsulation body to cover the recessed groove, and finally completing the wafer-level process of wiring layer and solder ball. The method takes advantage of the easy plasticity and low cost of plastic encapsulation material, uses mature plastic encapsulation molding process, and combines the recessed protrusion of the carrier plate to accurately mold the recessed groove and other structures with simple and low-technology difficulty. Furthermore, by embedding the chip into the recessed groove and re-wiring the front surface to fan out the signal contacts to the outside of the plastic encapsulation body, the reliability of the plastic encapsulation is improved. However, the invention forms the recessed groove first and then embeds the chip, which causes the chip and the recessed groove to not fit well. Specifically, when the size of the recessed groove is larger than that of the chip, the chip is easy to embed but prone to fall off after embedding; when the size of the recessed groove is smaller than that of the chip, the chip is not easy to embed and the edges of the chip are prone to damage if forced to embed; when the size of the recessed groove is equal to that of the chip, the processing precision of the recessed groove is extremely high and the molding difficulty is extremely great, which affects the packaging effect. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a fan-out wafer level chip packaging method, which can sequentially package RDL copper, pads and back pads based on the die chip by setting three plastic packaging steps, three copper plating steps, two grinding steps and two laser drilling steps, the plastic packaging and the particle chip are better matched, and the packaging effect is better; after packaging and forming, the carrier plate can be removed, so that the chip product presents a double-sided structure, the thickness of the finished product of the chip product is thinned on the basis of retaining or even enhancing the existing chip functions, meeting the market demand for high-density and small-size chip packaging; the problems of large chip thickness and single-sided structure of the product packaged by the fan-out process in the prior art can be solved, and the problem of insufficient matching between the chip and the recess formed by the chip loading method can be solved.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a fan-out wafer level chip packaging method, which comprises the following process steps:

[0008] Step one, wafer coating: a layer of high-thermal-conductivity silver glue is brushed on the back surface of the entire wafer sheet;

[0009] Step two, bumping: balls are planted in the pad area of each chip of the wafer sheet;

[0010] Step three, PI coating: a layer of PI insulating glue is brushed on the front surface of the wafer sheet to insulate the front surface of the chips on the entire wafer sheet;

[0011] Step four, wafer sawing: the entire wafer sheet is cut to form independent die chips;

[0012] Step five, die attaching: a carrier plate with a pre-applied adhesive film (DOF) is prepared, and the die chips are uniformly attached to the carrier plate one by one by the back surface;

[0013] Step six, first molding: a plastic packaging material is used to perform first molding on the carrier plate, so that the plastic packaging material completely wraps the die chips to form a first molding product;

[0014] Step seven, first grinding: the first molding product is ground to expose the upper end of the bump on the die chip;

[0015] Step eight, rotating hole: according to the RDL wiring diagram, a rotating hole is formed on the first molding product to generate the RDL wiring pattern; at the same time, positioning holes are formed at the four corners of the first molding product close to the edges;

[0016] Step nine, laser drilling: laser drilling technology is used to drill holes on the first molding product to make the upper and lower circuit conductive;

[0017] Step ten, first RDL copper plating (1ST RDL Cu Plating): copper is plated on the trace pattern of the RDL that has been processed, completing the RDL copper plating process, and copper is plated on the upper end of the ball to form a pad;

[0018] Step eleven, second molding (DOF Molding2): using molding material to perform secondary molding on the front of the first molding product, so that the molding material completely covers the part of the ball that leaks out together with the RDL copper plating area, forming a second molding product;

[0019] Step twelve, panel stripping: the carrier plate of the second molding product is stripped and removed;

[0020] Step thirteen, second rotating hole (Rotating hole 2): rotating holes are made on the four corners of the second molding product near the edge to make the positioning holes connected to the front of the second molding product;

[0021] Step fourteen, second laser drilling (Laser Drilling 2): laser drilling technology is used to drill holes on the second molding product to make the trace pattern of the RDL generated by the first rotating hole connected to the back of the second molding product;

[0022] Step fifteen, second RDL copper plating (2ND RDL Cu Plating): RDL is made on the back of the second molding product corresponding to the pad and RDL copper plating area to manufacture the pad area on the back of the second molding product;

[0023] Step sixteen, lead copper plating (Lead Cu Plating): copper is plated on the pad area on the back of the second molding product to manufacture the outer lead area with serrated edges;

[0024] Step seventeen, third molding (DOF Molding3): using molding material to perform third molding on the back of the second molding product, the molding material completely covers the pad area and outer lead area, forming a third molding product;

[0025] Step eighteen, second panel grinding (Panel Grinding2): grinding the back of the third molding product to expose the outer lead area;

[0026] Step 19, Laser Marking: Laser marking on the front side of the third plastic package product;

[0027] Step 20, Pre-cut: Pre-cutting on the back side of the third plastic package product, i.e. cutting a part on the back side of the third plastic package product, reserving a step and leaking the side metal of the pad area and outer lead area;

[0028] Step 21, Tin Plating: Tin plating on the back side and the side leakage part of the pad area and outer lead area;

[0029] Step 22, Package Saw: Cutting the third plastic package product along the pre-cutting contour to form a single independent chip product, and a step is formed on the side of the product;

[0030] Step 23, Test and Tape: Testing and taping the chip product;

[0031] Step 24, Packing: Packing the chip product.

[0032] In an embodiment of the present application, in step 2, the number of balls on a single chip is four, and the diameter of a single ball is ≥ 60 um.

[0033] In an embodiment of the present application, in step 15, the thickness of the pad area is ≥ 30 um.

[0034] In an embodiment of the present application, in step 16, the thickness of the outer lead area is ≥ 75 um.

[0035] In an embodiment of the present application, in step 20, the depth of the pre-cutting is not greater than one-half of the width of the third plastic package product.

[0036] In an embodiment of the present application, in step 21, the thickness of the tin layer of the tin plating is 0.8-1.5 um.

[0037] In an embodiment of the present application, the plastic packaging material used in steps 6, 11 and 17 is an EMC material, which is a powdery molding compound prepared by mixing epoxy resin as a base resin, high-performance phenolic resin as a curing agent, silicon powder as a filler, and various additives.

[0038] In an embodiment of the present application, in step twenty-three, the test ribbon includes an open / short test, a DC test, an Eflash test, a function test, an AC test, and an RF test.

[0039] As described above, the fan-out wafer level chip packaging method of the present application has the following beneficial effects:

[0040] 1. The process can package RDL copper, pads and back pads in sequence based on the die chip by setting three plastic packaging steps, three copper plating steps, two grinding steps and two laser drilling steps, the plastic packaging and the particle chip are better adhered, and the packaging effect is better; after packaging and forming, the carrier plate can be removed, so that the chip product presents a double-sided structure, the chip product with a double-sided structure has higher design flexibility, the present application thins the finished product thickness of the chip product on the basis of retaining or even enhancing the existing chip functions, and meets the market demand for high-density and small-size chip packaging.

[0041] 2. By setting two hole turning steps, the first hole turning can not only generate the wiring pattern of the RDL, but also turn positioning holes at the four corners of the chip product close to the edge, and the second hole turning can connect the positioning holes to the back of the chip product, improve the positioning effect of the chip product, and further improve the processing effect of the chip product.

[0042] 3. By setting a pre-cutting step, pre-cutting can disperse the stress during cutting, reduce the stress concentration at the edge of the chip product, and reduce cracks and damage; pre-cutting also helps to more accurately control the cutting path, make the cutting line clearer, improve the cutting precision of the chip product and simplify the subsequent cutting step.

[0043] 4. By setting a tin plating step, the tin plating step can tin the back and side leakage parts of the pad area and the outer lead area, the tin layer can be melted at a lower temperature to form a good alloy layer with solder, thereby improving the quality and efficiency of welding; the tin layer as a protective film is not only smooth, flat and dense, but also can effectively isolate the copper layer from contact with oxygen and moisture in the air to prevent oxidation reaction; and tin as a resistivity metal, after being uniformly attached to the surface of the copper layer by electroplating technology, can effectively reduce the contact resistance, thereby enhancing the current conduction capacity.

[0044] 5、The application adopts Fanout process to replace traditional ceramic packaging process, more I / O points can be arranged in limited space by "fanout" I / O points to the outside of chip boundary, and the overall packaging size can be reduced due to the I / O points being rearranged to a larger carrier; the design and layout of RDL can optimize signal transmission and improve electrical performance; the application is based on die chip for packaging, compared with the prior art which adopts the mode of forming a recess for chip first and then loading the chip, the application is based on die chip for packaging, and the plastic sealing and particle chip are better, and the packaging effect is better; compared with the prior art which relies on the mode of forming a bearing plate, the application only uses a carrier plate as a carrier, and the carrier plate is removed after packaging and forming, so that the chip product presents a double-sided structure, the finished product thickness of the chip product is thinned on the basis of retaining or even enhancing the existing chip function, and the packaging demand of high density and small size chip in the market is met. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A process flow chart of the product of the application is shown.

[0046] Figure 2 A process schematic diagram of step one in example 1 is shown.

[0047] Figure 3 A process schematic diagram of step two in example 1 is shown.

[0048] Figure 4 A process schematic diagram of step four in example 1 is shown.

[0049] Figure 5 A process schematic diagram of step five in example 1 is shown.

[0050] Figure 6 A process schematic diagram of step six in example 1 is shown.

[0051] Figure 7 A process schematic diagram of step seven in example 1 is shown.

[0052] Figure 8 A process schematic diagram of step eight in example 1 is shown.

[0053] Figure 9 A process schematic diagram of step nine in example 1 is shown.

[0054] Figure 10 A process schematic diagram of step ten in example 1 is shown.

[0055] Figure 11 A process schematic diagram of step eleven in example 1 is shown.

[0056] Figure 12The diagram shows a process diagram of step 12 in Example 1.

[0057] Figure 13 The diagram shows a process diagram of step thirteen in Example 1.

[0058] Figure 14 The diagram shows a process diagram of step fourteen in Example 1.

[0059] Figure 15 The diagram shows a process diagram of step fifteen in Example 1.

[0060] Figure 16 The diagram shows a process diagram of step sixteen in Example 1.

[0061] Figure 17 Displayed as Figure 16 A magnified view of the local structure.

[0062] Figure 18 The diagram shows a process diagram of step seventeen in Example 1.

[0063] Figure 19 The diagram shows a process diagram of step eighteen in Example 1.

[0064] Figure 20 The diagram shows a process diagram of step nineteen in Example 1.

[0065] Figure 21 The diagram shows a process diagram of step 20 in Example 1.

[0066] Figure 22 The diagram shows a process diagram of step twenty-one in Example 1.

[0067] Figure 23 The diagram shows a process diagram of step twenty-two in Example 1.

[0068] Figure 24 The diagram shows a process diagram of step twenty-three in Example 1.

[0069] Figure 25 This invention is shown as Figure 23 A cross-sectional view of a single chip.

[0070] Figure 26 The image shown is a top-view perspective view of the chip product packaged according to the present invention.

[0071] Component designation explanation

[0072] 1. Wafer; 2. Chip; 3. Ball bearing; 4. Carrier board; 5. Molding material; 6. Positioning hole; 7. Pad; 8. Outer lead; 9. Tin layer; 10. Silver paste; 11. Solder pad. DETAILED DESCRIPTION

[0073] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is to be understood that variations and modifications of the application can be made while still falling within the scope of the application.

[0074] Reference will now be made to the drawings, in which Figures 1-26 It is to be understood that the structure, proportions, elements, materials and dimensions provided herein are by way of example only and that the scope of the application is not to be limited thereby. Any structure, proportion, element, material or dimension that can suggest themselves to one of ordinary skill in the art based on the teachings herein are intended to fall within the scope of the application.

[0075] Reference will now be made to the drawings, in which Figures 1-26 The present embodiment provides a fan-out wafer level chip scale packaging method, the method comprising the following processes:

[0076] Step one, wafer coating: a layer of high thermal conductivity silver glue 10 is brushed on the back of the entire wafer 1; this step can solve the problem of chip 2 breakage caused by stress and tension of the chip 2.

[0077] Step two, bumping: balls 3 are planted in the pad 11 area of each chip 2 on the wafer 1, the number of balls 3 on a single die chip 2 is four, and the diameter of a single ball 3 is ≥60um.

[0078] Step three, PI coating: a layer of PI insulating glue is brushed on the front of the wafer 1 to insulate the front of the chip 2 on the entire wafer 1; this step can protect the completed bumping and prevent subsequent electroplating / flash etching from being affected by the chemical solution.

[0079] Step four, wafer sawing: the entire wafer 1 is cut to form independent die chips 2.

[0080] Step five, die attaching: a carrier plate 4 with a pre-applied adhesive film (DOF) is prepared, and the die chips 2 are attached to the carrier plate 4 one by one in a back-to-back manner.

[0081] Step six, one-time molding: a molding material 5 is used to perform one-time molding on the carrier plate 4, so that the molding material 5 completely wraps the die chips 2 to form a one-time molding product.

[0082] Step seven, Panel Grinding: grinding the primary plastic sealing product to make the upper end of the soldering ball 3 on the die chip 2 leak out; in this step, the diameter of the upper end of each leaked soldering ball 3 is controlled to be greater than or equal to 30 um, and the overall thickness of the product after grinding is controlled to be in the range of 439 um to 459 um.

[0083] Step eight, Rotating hole: rotating holes on the primary plastic sealing product according to the wiring diagram of the RDL to generate the wiring pattern of the RDL, in order to prepare for the subsequent RDL process exposure and development; at the same time, positioning holes 6 are rotated out at the four corners of the primary plastic sealing product close to the edges, which are used for positioning.

[0084] Step nine, Laser Drilling: the product is a double-sided structure, laser drilling technology is used to drill holes on the primary plastic sealing product, which can make the upper and lower circuits conductive; in this step, the shape of the drilled hole is a trapezoid with a wide upper end and a narrow lower end, and the trapezoidal drilled hole includes a hole mouth and a hole bottom, wherein the outer diameter of the hole mouth is controlled in the range of 1000 um to 1040 um, and the minimum inner diameter of the hole mouth is controlled to be 970 um; the outer diameter of the hole bottom is controlled in the range of 200 um to 240 um, and the minimum inner diameter of the hole bottom is controlled to be 170 um.

[0085] Step ten, 1ST RDL Cu Plating: copper plating is performed on the wiring pattern of the RDL that has been processed, completing the RDL copper plating operation, and forming a solder pad 11 on the upper end of the soldering ball 3; the RDL width is controlled to be in the range of 512 um to 768 um, and the RDL pitch is controlled to be in the range of 1430 um to 1470 um.

[0086] Step eleven, DOF Molding2: using plastic sealing material 5 to perform secondary plastic sealing on the front surface of the primary plastic sealing product, so that the plastic sealing material 5 completely wraps the part of the soldering ball 3 that leaks out of the upper end together with the RDL copper plating area, forming a secondary plastic sealing product; the thickness of the secondary plastic sealing product is controlled to be in the range of 639 um to 679 um.

[0087] Step twelve, Panel stripping: stripping and removing the carrier plate 4 of the secondary plastic sealing product, the present application only uses the carrier plate 4 as a carrier, and after packaging and molding, the carrier plate 4 is removed, so that the chip 2 product presents a double-sided structure, which reduces the thickness of the finished product of the chip 2 product on the basis of retaining or even enhancing the existing functions of the chip 2, and meets the market demand for high-density and small-size chip 2 packaging.

[0088] Step 13, second rotating hole (Rotating hole 2): rotating holes are made at the four corners near the edge of the second plastic package to connect the positioning hole 6 to the front of the second plastic package, which can improve the positioning effect of the chip 2 product and further improve the processing effect of the chip 2 product.

[0089] Step 14, second laser drilling (Laser Drilling 2): laser drilling technology is used to drill holes on the second plastic package to connect the trace pattern of the RDL generated by the first rotating hole to the back of the second plastic package; the shape of the hole in this step is also a trapezoidal shape with a large upper and a small lower, including a hole mouth and a hole bottom, the outer diameter of the hole mouth is controlled in the range of 200um~240um, and the inner diameter of the hole mouth is controlled to be at least 170um; the outer diameter of the hole bottom is controlled in the range of 140um~180um, and the inner diameter of the hole bottom is controlled to be at least 110um.

[0090] Step 15, second RDL copper plating (2ND RDL Cu Plating): RDL is made on the area corresponding to the pad 11 and RDL copper plating on the back of the second plastic package to manufacture the pad 7 area on the back of the second plastic package, the RDL width is controlled in the range of 216um~324um, the RDL spacing is controlled in the range of 480um~720um, and the thickness of the pad 7 area is ≥30um.

[0091] Step 16, lead copper plating (Lead Cu Plating): copper plating is made on the pad 7 area on the back of the second plastic package to manufacture the outer lead 8 area with serrated edges, the thickness of the outer lead 8 area is ≥75um, the outer lead 8 width is controlled in the range of 200um~300um, and the outer lead 8 spacing is controlled in the range of 750um~850um.

[0092] In this step, the serrated edge design of the outer lead 8 area has the following advantages: 1) The contact perimeter of the pad and the solder is increased, and the actual pad contact area can be increased by 20% to 40% compared to a smooth pad; the serrated structure can form a "mechanical lock", and the solder fills the gap between the teeth and solidifies, preventing lateral displacement of the solder joint, effectively enhancing the product soldering strength and mechanical reliability; 2) The gap between the teeth blocks the excessive flow of molten solder, preventing short circuits between adjacent pads; the serrated edge can break the continuous tension of the solder paste, promote uniform separation of the solder paste after printing, and effectively improve the soldering process; 3) By increasing the current path to disperse impedance and reduce the skin effect at high frequencies; at the same time, the larger contact area and metallurgical bonding interface reduce current crowding and effectively improve the electrical performance of the product; 4) Increase the thermal conduction path of the pad and the PCB copper layer to improve the heat dissipation efficiency; and disperse the stress caused by CTE (thermal expansion coefficient) mismatch through the serrated edge to delay the propagation of thermal fatigue cracks.

[0093] Step seventeen, three times of molding (DOF Molding 3): three times of molding is performed on the back of the twice-molded product using molding material 5, and the molding material 5 completely wraps the pad 7 area and the outer lead 8 area, forming a three times-molded product, and the thickness of the three times-molded product is controlled to be 872 um to 912 um.

[0094] Step eighteen, second grinding (Panel Grinding 2): the back of the three times-molded product is ground to expose the outer lead 8 area, and the thickness of the product after grinding is controlled to be 540 um to 560 um.

[0095] The process can encapsulate the RDL copper, the pad 11 and the back pad 7 in sequence based on the die chip 2 by setting the three times of molding step, the three times of copper plating step, the two times of grinding step and the two times of laser drilling step, the encapsulation effect is better, and the encapsulation effect is better; after encapsulation, the carrier board 4 can be removed, so that the chip 2 product presents a double-sided structure, the chip 2 product with a double-sided structure has higher design flexibility, the present application thins the finished product thickness of the chip 2 product on the basis of retaining or even enhancing the functions of the existing chip 2, and meets the market demand for high-density and small-size chip 2 encapsulation.

[0096] Step nineteen, laser printing (Laser Marking): laser marking is performed on the front of the three times-molded product, and the laser marking depth is controlled to be 10 um to 20 um.

[0097] Step twenty, pre-cut: using a 0.2mm wide blade to pre-cut the three times plastic package product, that is, cutting a part on the back of the three times plastic package product, the cutting depth is 0.165mm, leaving a step and leaking the side metal of pad 7 area and outer lead 8 area, facilitating the subsequent soldering tin climbing and product formal cutting; the depth of the pre-cut is not more than half of the width of the three times plastic package product, and reasonable control of the pre-cut depth has multiple advantages in the chip 2 packaging process, including preventing the plastic package layer from cracking, protecting the chip 2 and internal structure, improving yield, optimizing cutting efficiency, reducing stress concentration, adapting to subsequent processes and reducing cost, which together ensure the reliability and efficiency of the packaging process, and improve the quality of the final product.

[0098] This step can disperse the stress during cutting by pre-forming the cutting line on the wafer, reduce the stress concentration of the edge of the chip 2 product, and reduce cracks and damage; pre-cutting also helps to more accurately control the cutting path, make the cutting line clearer, improve the cutting precision of the chip 2 product and simplify the subsequent cutting step.

[0099] Step twenty-one, tin plating: tin plating is performed on the back and side leakage parts of the pad 7 area and the outer lead 8 area, and the thickness of the tin layer 9 is 0.8-1.5μm; the main effects of tin plating in the pad 7 area and the outer lead 8 area include improving the soldering performance, enhancing the corrosion resistance, improving the electrical conductivity and protecting the copper layer. Specifically, 1) the tin layer 9 can melt at a lower temperature and form a good alloy layer with the solder, thereby improving the quality and efficiency of soldering. This is particularly important for the pin and wire connection of electronic components; 2) the tin layer 9 as a protective film can effectively isolate the copper layer from contact with oxygen and moisture in the air, preventing oxidation reaction. Especially in harsh environments such as humidity and salt spray, the tin plated copper layer exhibits superior corrosion resistance, prolonging the service life of the circuit board; 3) tin as a low resistivity metal, after being uniformly attached to the surface of the copper layer by electroplating technology, can effectively reduce the contact resistance, thereby enhancing the current conduction capacity. This is particularly important for circuit boards that need to efficiently transmit power or electrical signals; 4) the tin plating layer 9 is not only smooth, flat and dense, but also difficult to form copper-tin intermetallic compounds, which can effectively prevent the oxidation and corrosion of the copper layer, protecting the copper layer from the influence of the external environment. In addition, the thickness of the tin layer 9 formed by the tin plating process is 0.8-1.5μm, and the tin layer 9 with this thickness can withstand multiple lead-free soldering impacts, helping to maintain the electrical performance of the circuit board, especially in high frequency and high speed signal transmission applications, which can reduce signal loss and interference.

[0100] Step 22, Package Saw: Using a 0.1mm wide blade, the triple-encapsulated product is cut along the pre-cut contour to form a single, independent chip 2 product, creating a step on the side of the product.

[0101] In this step, the design of the chip 2 product with a stepped edge on the product pad has the following advantages: 1) Enhanced mechanical strength and impact resistance: (1) Dispersed stress concentration, the stepped structure disperses external stress (such as drop, vibration) through multi-level transition, avoids stress concentration on a single plane, and reduces the risk of cracking; (2) Improved anti-delamination ability: The steps increase the contact area between the molding compound and the substrate (such as PCB, lead frame), and combined with the interface locking effect, suppress delamination; 2. Optimized sealing and moisture-proof performance: (1) Extended moisture penetration path, the tortuous path formed by the steps delays moisture intrusion, reduces the moisture absorption rate, and improves the moisture sensitivity level; (2) Enhanced interface sealing, the stepped structure and the sealant (such as epoxy resin) form a multi-level interlock, reducing capillary action. 3. Improve assembly accuracy and compatibility: (1) Positioning and guiding role: the step serves as a mechanical positioning reference, simplifying the alignment process of PCB mounting or shell assembly; (2) Compatibility with heterogeneous materials: the step transition alleviates the CTE (coefficient of thermal expansion) mismatch of different materials (such as epoxy resin and metal frame); 4. Thermal management optimization: (1) Increase heat dissipation surface area: the step structure enhances convection heat dissipation through multi-level exposure, especially suitable for compact designs without heat sinks; (2) Heat dissipation effect: the step disperses the heat flow path, avoids local overheating, and improves high-temperature reliability; 5. Enhanced electromagnetic shielding (EMI): (1) Shielding continuity: the edge of the step can form a stepped overlap with the metal shell or shielding layer, reducing electromagnetic leakage gaps.

[0102] Step 23, Test and Tape: Test and tape the chip 2 product. The test and tape items include Open / short test (checking for open or short circuits), DC test (DC parameter test), Eflash test (embedded flash function and performance test), Function test (logic function test), AC test (AC specification test), RF test (RF module function test), etc. Required test equipment: The hardware equipment required for FT testing includes test boards, test sockets, ATE (Automation Test Equipment) test benches, Handlers (automated sorting machines), etc.

[0103] Step 24, Packing: Packaging of Chip 2 product.

[0104] In this embodiment, the plastic sealing material 5 used in steps six, eleven and seventeen is EMC material. The EMC material is a powder molding compound made from epoxy resin as the base resin, high-performance phenolic resin as the curing agent, silicon powder as the filler, and various additives. The use of EMC material as the plastic sealing material 5 has the following advantages: 1) EMC material has high mechanical strength, which can provide good physical protection for the chip 2, preventing damage to the chip 2 due to mechanical stress or impact during packaging, transportation and use; 2) EMC material has a low coefficient of thermal expansion (CTE), which can match the chip 2 and the substrate material, reducing thermal stress and reducing the risk of package cracking or delamination due to thermal expansion mismatch; 3) EMC material is an excellent insulator, which can effectively isolate the electrical connections inside the chip 2, preventing short circuits and electrical interference, and ensuring reliable operation of the chip 2; 4) EMC material has high resistance to most chemicals and can maintain stable performance in harsh environments such as high temperature, high humidity and corrosive gas, extending the life of the chip 2; 5) EMC material has relatively low cost, suitable for mass production, reducing the overall cost of packaging and improving economic efficiency; 6) EMC material has good flowability, which can fill complex mold structures and chip 2 gaps, ensuring that there are no cavities or defects inside the package, improving packaging reliability; 7) EMC material has good moisture resistance after optimization, preventing moisture from entering the chip 2, avoiding corrosion or delamination caused by moisture; 8) The formula of EMC material can be adjusted according to specific requirements, such as adjusting thermal conductivity, flame retardancy, CTE, etc. to meet the performance requirements of different application scenarios.

[0105] In summary, the present application uses Fanout technology to replace traditional ceramic packaging technology. By "fanout" the I / O points to the outside of the chip 2 boundary, more I / O points can be arranged in a limited space. The overall package size can be reduced because the I / O points are relocated to a larger carrier. The design and layout of RDL can optimize signal transmission and improve electrical performance. The present application uses die chips 2 as the basis for packaging. Compared with the prior art method of forming a recess first and then loading the chip 2, the die chip 2 in the present application is more closely matched with the plastic sealing, resulting in better molding effect. Compared with the prior art method of relying on the carrier board 4 for molding, the present application only uses the carrier board 4 as a carrier, and the carrier board 4 is removed after packaging and molding, resulting in a double-sided structure of the chip 2 product. The finished thickness of the chip 2 product is reduced based on retaining or even enhancing the existing chip 2 functions, meeting the market demand for high-density and small-size chip 2 packaging. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0106] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A fan-out wafer level packaging method, characterized by: The method comprises the following processes: Step one, wafer coating: a layer of high-thermal-conductivity silver glue is brushed on the back of the wafer; Step two, bumping: balls are planted on the pad area of each chip of the wafer; Step three, PI coating: a layer of PI insulating glue is brushed on the front of the wafer to insulate the front of the chips on the wafer; Step four, wafer sawing: the wafer is sawed to form independent die chips; Step five, die attaching: a carrier plate with a pre-pasted adhesive film (DOF) is prepared, and the die chips are attached to the carrier plate one by one in a back-attached manner; Step six, first molding: a plastic sealing material is used to mold the carrier plate to completely wrap the die chips to form a first molded product; Step seven, panel grinding: the first molded product is ground to expose the upper ends of the planted balls on the die chips; Step eight, rotating hole: according to the RDL wiring diagram, holes are rotated on the first molded product to form the RDL wiring pattern; meanwhile, positioning holes are rotated on the four corners of the first molded product close to the edges; Step nine, laser drilling: laser drilling technology is used to drill holes on the first molded product to make the upper and lower circuits conductive; Step ten, first RDL copper plating: copper is plated on the RDL wiring pattern that has been processed to complete the RDL copper plating and form pads on the upper ends of the planted balls; Step eleven, second molding: a plastic sealing material is used to mold the front of the first molded product to completely wrap the exposed parts of the upper ends of the planted balls together with the RDL copper plating area to form a second molded product; Step twelve, panel stripping: the carrier plate of the second molded product is stripped and removed; Step thirteen, second rotating hole: holes are rotated on the four corners of the second molded product close to the edges to make the positioning holes communicate with the front of the second molded product; Step fourteen, second laser drilling: laser drilling technology is used to drill holes on the second molded product to make the RDL wiring pattern generated by the first rotating hole communicate with the back of the second molded product; Step fifteen, second RDL copper plating: RDL is made on the back of the second molded product corresponding to the pad and RDL copper plating area to manufacture the pad area on the back of the second molded product; Step sixteen, lead copper plating: copper is plated on the pad area on the back of the second molded product to manufacture an outer lead area with serrated edges; Step seventeen, three times plastic packaging (DOF Molding 3): using plastic packaging material to make three times plastic packaging on the back of the second plastic packaging product, the plastic packaging material completely wraps the pad area and the outer lead area, forming a three times plastic packaging product; Step eighteen, second grinding (Panel Grinding 2): grinding the back of the three times plastic packaging product to expose the outer lead area; Step nineteen, laser printing (Laser Marking): laser marking on the front of the three times plastic packaging product; Step twenty, pre-cutting (Pre-cut): pre-cutting the three times plastic packaging product, that is, cutting a part on the back of the three times plastic packaging product, reserving a step and leaking the side metal of the pad area and the outer lead area; Step twenty-one, tin plating (Less Sn): tin plating on the back and side leakage part of the pad area and the outer lead area; Step twenty-two, chip cutting (Package Saw): cutting the three times plastic packaging product along the pre-cutting contour to form a single independent chip product, and a step is formed on the side of the product; Step twenty-three, test and tape (Test and Tape): testing and taping the chip product; Step twenty-four, packing (Packing): packing the chip product.

2. The fan-out wafer level packaging method of claim 1, wherein: In step two, the number of balls on a single chip is four, and the diameter of a single ball is ≥60um.

3. The fan-out wafer level packaging method of claim 1, wherein: In step fifteen, the thickness of the pad area is ≥30um.

4. The fan-out wafer level packaging method of claim 3, wherein: In step sixteen, the thickness of the outer lead area is ≥75um.

5. The fan-out wafer level packaging method of claim 1, wherein: In step twenty, the depth of the pre-cutting is not greater than one-half of the width of the three times plastic packaging product.

6. The fan-out wafer level packaging method of claim 1, wherein: In step twenty-one, the thickness of the tin layer of the tin plating is 0.8-1.5um.

7. The fan-out wafer level packaging method of claim 1, wherein: In steps six, eleven, and seventeen, the plastic packaging material used is an EMC material, which is a powder molding compound mixed with epoxy resin as the base resin, high-performance phenolic resin as the curing agent, silicon powder as the filler, and various additives.

8. The fan-out wafer level packaging method of claim 1, wherein: In step twenty-three, the test and tape includes open / short test, DC test, Eflash test, function test, AC test, and RF test.

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