Fan-out package detection method and system based on photoetching positive resist

Abstract

The present application relates to the technical field of package detection, and particularly relates to a fan-out package detection method and system based on photoetching positive glue, which comprises the following steps: dividing a photoetching positive glue developing area into units to obtain a plurality of developing units; performing three-dimensional profile scanning on a copper pillar array after etching of each developing unit to obtain size characteristic parameters of the copper pillar array; collecting a circuit plating image of each developing unit and performing microscopic feature identification thereon to obtain microscopic characteristic parameters; comparing and analyzing the size characteristic parameters and the microscopic characteristic parameters with corresponding preset quality standards respectively for each developing unit, and generating an out-of-standard feature set when any one of the size characteristic parameters and the microscopic characteristic parameters exceeds the preset quality standards; performing quality evaluation on the out-of-standard feature set to obtain a quality score corresponding to each developing unit; and realizing accurate positioning of local defects of the developing area to avoid misjudgment or missed detection.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging detection, and in particular to a fan-out packaging detection method and system based on positive photoresist. Background Art

[0002] As an advanced semiconductor packaging technology, fan-out packaging has seen a surge in demand in fields such as 5G communications and artificial intelligence due to its high I / O density, three-dimensional integration capabilities and miniaturization advantages. Its core process, the redistribution layer (RDL) lithography process, achieves electrical connection between the chip and the outside world through a copper pillar array. As the core material in the redistribution layer lithography process, the patterning quality of positive photoresist has a decisive influence on subsequent process steps such as electroplating and etching.

[0003] Existing inspection methods often adopt a unified inspection method for the entire wafer, lacking a refined unit division of the development area; when local process fluctuations occur, global inspection can easily mask local defects, such as differences in film thickness caused by uneven spin coating. Edge and masking ability inspection requires targeted evaluation, but traditional methods are difficult to achieve regional precise positioning; moreover, existing inspection methods usually only independently evaluate a single indicator, such as the CD size after etching and the number of AOI defects. The three-dimensional dimensional characteristics of the copper pillar array are not combined with the microscopic characteristics of the circuit electroplating for analysis, and the correlation between dimensional deviations and microscopic defects cannot be revealed, which can easily lead to misjudgment or missed detection. Summary of the Invention

[0004] The present invention provides a fan-out packaging inspection method and system based on positive photoresist, which can achieve accurate positioning of local defects in the development area and avoid misjudgment or missed detection, and can effectively solve the problems in the background technology.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a fan-out packaging inspection method based on positive photoresist, comprising:

[0006] Dividing the photoresist positive resist developing area into units to obtain a plurality of developing units;

[0007] Performing a three-dimensional profile scan on the copper pillar array etched by each developing unit to obtain dimensional characteristic parameters of the copper pillar array;

[0008] Collecting the circuit electroplating image of each developing unit, and performing microscopic feature recognition on the image to obtain microscopic feature parameters;

[0009] For each of the developing units, the size characteristic parameter and the microscopic characteristic parameter are respectively compared and analyzed with corresponding preset quality standards, and when any one of the size characteristic parameter and the microscopic characteristic parameter exceeds the preset quality standard, an exceeding standard feature set is generated;

[0010] Performing a quality assessment on the exceeding-standard feature set to obtain a quality score corresponding to each developing unit;

[0011] Assigning a quality score corresponding to each of the developing units according to their actual spatial position to obtain a wafer packaging quality distribution map;

[0012] The wafer packaging quality distribution map is identified using a predetermined wafer packaging quality identification model to obtain a wafer packaging quality detection result.

[0013] In combination with the first aspect, in a possible design, the dimension characteristic parameters include the copper pillar height, the copper pillar diameter, and the verticality of the copper pillar sidewall.

[0014] In combination with the first aspect, in a possible design, the microscopic characteristic parameters include at least line defect characteristics, line edge roughness characteristics, and plating uniformity characteristics.

[0015] In combination with the first aspect, in a possible design, the exceeding-standard feature set includes the types and exceeding-standard amplitudes of all exceeding-standard feature parameters in the developing unit.

[0016] In conjunction with the first aspect, in a possible design, a dynamic partitioning strategy is adopted for cell partitioning of the positive resist development area of ​​the photoresist, including:

[0017] Classify functional areas into different levels;

[0018] The graphic density of each area is calculated through image recognition. The area with a density above the preset threshold is reduced in size according to the set ratio, and the area with a density below the preset threshold is merged with adjacent units.

[0019] In combination with the first aspect, in one possible design, the line defect characteristic calculation formula is:

[0020] ;

[0021] Among them, D f represents the line defect density; N represents the number of defects detected; L i represents the length of the i-th defect; W i represents the width of the i-th defect; L total Indicates the total line length of the detection area.

[0022] In combination with the first aspect, in a possible design, the edge roughness characteristic calculation formula is:

[0023] ;

[0024] Among them, R q represents the root mean square roughness; M represents the total number of edge sampling points; h jIndicates the vertical height deviation of the jth sampling point relative to the ideal edge reference line; It represents the average value of the height deviation of all sampling points.

[0025] In combination with the first aspect, in one possible design, the coating uniformity characteristic is calculated as:

[0026] ;

[0027] Among them, U c Indicates the coating uniformity coefficient; σ t Indicates the standard deviation of coating thickness; t avg Indicates the average thickness of the coating.

[0028] In combination with the first aspect, in one possible design, the calculation formula for the developing unit quality score is:

[0029] ;

[0030] Among them, Q s represents the quality score of the developing unit; n represents the total number of types of characteristic parameters that exceed the standard; w k represents the weight coefficient of the kth category of exceeding standard characteristic parameters; x k Indicates the actual exceeding range of the kth category exceeding standard characteristic parameter; T k Indicates the preset standard threshold value of the kth category of excessive characteristic parameters.

[0031] In a second aspect, the present invention further provides a fan-out packaging inspection system based on positive photoresist, comprising:

[0032] A developing area division module is used to divide the photoresist positive resist developing area into units to obtain multiple developing units;

[0033] A three-dimensional profile scanning module is used to perform three-dimensional profile scanning on the copper pillar array after etching by each developing unit to obtain the dimensional characteristic parameters of the copper pillar array;

[0034] A microscopic feature recognition module is used to collect the circuit electroplating image of each developing unit, perform microscopic feature recognition on it, and obtain microscopic feature parameters;

[0035] a comparison and analysis module, configured to compare and analyze the dimensional characteristic parameter and the microscopic characteristic parameter with corresponding preset quality standards for each developing unit, and generate an exceeding-standard feature set when any one of the dimensional characteristic parameter and the microscopic characteristic parameter exceeds the preset quality standard;

[0036] A quality assessment module, configured to perform quality assessment on the exceeding-standard feature set to obtain a quality score corresponding to each developing unit;

[0037] The spatial position assignment module is used to assign the quality score corresponding to each developing unit according to its actual spatial position to obtain a wafer packaging quality distribution map;

[0038] The quality recognition model module is used to use a predetermined wafer packaging quality recognition model to identify the wafer packaging quality distribution map and obtain a wafer packaging quality detection result.

[0039] Through the technical solution of the present invention, the following technical effects can be achieved: the present invention realizes precise positioning of local defects in the developing area through refined unit division, effectively solving the problem of local process fluctuations being masked by global detection in traditional methods; the three-dimensional size characteristics of the copper pillar array are combined with the microscopic characteristics of the circuit electroplating for analysis, so as to realize the correlation between size deviation and microscopic defects and avoid misjudgment or missed detection; the present invention combines multiple detection steps, and through steps such as unit division, feature parameter acquisition, comparative analysis, quality assessment and spatial position assignment, it can comprehensively assess the quality status of each developing unit and generate a wafer packaging quality distribution map; finally, the quality distribution map is identified using a wafer packaging quality recognition model, thereby improving the detection accuracy of the wafer packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a logic flow chart of the fan-out packaging detection method based on positive photoresist in the present invention;

[0041] Figure 2 This is a structural block diagram of the fan-out packaging detection system based on positive photoresist in the present invention. DETAILED DESCRIPTION

[0042] The present application is described below in conjunction with the accompanying drawings in the present application;

[0043] like Figure 1 As shown, the fan-out packaging detection method based on positive photoresist of the present invention specifically includes the following steps:

[0044] Step S100, dividing the photoresist positive resist developing area into units to obtain a plurality of developing units;

[0045] Step S200, performing a three-dimensional profile scan on the copper pillar array etched by each developing unit to obtain dimensional characteristic parameters of the copper pillar array;

[0046] Step S300: collecting the circuit electroplating image of each of the developing units, and performing microscopic feature recognition on the image to obtain microscopic feature parameters; the microscopic feature parameters at least include circuit defect features, circuit edge roughness features, and plating uniformity features;

[0047] Step S400: For each developing unit, the dimensional characteristic parameter and the microscopic characteristic parameter are compared and analyzed with corresponding preset quality standards. When any one of the dimensional characteristic parameter and the microscopic characteristic parameter exceeds the preset quality standard, an exceeding standard characteristic set is generated; the exceeding standard characteristic set includes the type and exceeding range of all exceeding standard characteristic parameters in the developing unit;

[0048] Step S500: performing a quality assessment on the exceeding-standard feature set to obtain a quality score corresponding to each developing unit;

[0049] Step S600: Assigning a quality score corresponding to each of the developing units according to their actual spatial locations to obtain a wafer packaging quality distribution map;

[0050] Step S700: using a predetermined wafer packaging quality recognition model to identify the wafer packaging quality distribution map to obtain a wafer packaging quality detection result.

[0051] In this embodiment, the wafer surface is deconstructed into quantifiable, independent detection units by dividing the developed area into units. When the spin coating process causes regional differences in film thickness, the units with out-of-tolerance film thickness in the edge area can be accurately located, avoiding local anomalies being masked by the average thickness of the entire wafer meeting the standard.

[0052] By performing cross-dimensional correlation analysis between copper pillar dimensional features acquired through 3D profile scanning and circuit electroplating microfeatures, the correlation between dimensional deviations and micro defects is established. For example, when the diameter of a copper pillar unit is within the standard range but the edge roughness exceeds the standard, traditional methods may determine that it is qualified. However, this solution can identify potential resistance anomaly risks even though the size meets the standard through feature coupling. This collaborative evaluation mechanism of multi-dimensional features effectively uncovers quality risks hidden under the appearance of a single qualified indicator, achieving a leap from indicator compliance testing to risk predictive testing.

[0053] By mapping the quality scores of each developing unit into a quality distribution map based on actual coordinates, an intuitive thermal distribution of wafer surface quality is generated. This not only reveals the spatial location of local defects but also reveals spatial offsets of process parameters through regional quality fluctuations. Compared to traditional methods that only output overall yield, the quality distribution map can quickly locate the source of systematic defects, improving process improvement efficiency.

[0054] This method constructs a complete quality assessment logic from micro to macro level through a multi-level processing flow from unit-level feature extraction to full-wafer quality determination. The comparative analysis of dimensional features and micro features generates a set of out-of-standard features. The quality score quantifies multi-dimensional risks into a unified standard. The quality distribution map realizes the visualization of spatial dimensions. Finally, the recognition model outputs comprehensive test results, avoiding the impact of misjudgment in a single link on the overall result, and improving the quality control level of fan-out packaging.

[0055] In some embodiments of the present invention, the dynamic partitioning strategy for the developing unit in step S100 is as follows: setting inspection priorities according to the importance of functional areas, adaptively adjusting unit sizes based on pattern density, and optimizing edge partitioning rules in combination with wafer diameter to achieve precise matching of inspection resources and process risks. The dynamic partitioning strategy is specifically implemented as follows:

[0056] Step S101: hierarchically divide the functional areas. The core functional area includes key pads and interconnect channels and adopts a honeycomb high-density division. The unit size is dynamically adjusted with the pattern line width to ensure that each unit accommodates the complete pattern structure and avoid feature fragmentation. The edge functional area includes the WEE and WEP areas and adopts a circular gradient division. Different density detection bands are set starting from the wafer edge. The closer to the edge, the finer the unit division, focusing on monitoring the edge effect of uneven spin coating. The non-critical functional area includes areas such as chip gaps and adopts a sparse grid division to ensure detection coverage while improving overall efficiency.

[0057] Step S102: Calculate the graphic density of each area through image recognition. Automatically reduce the cell size in high-density areas to ensure the integrity of the graphics within a single cell. Merge adjacent cells in low-density areas to reduce the amount of data and avoid feature confusion in high-density areas and redundant detection in low-density areas. For example, set a high-density area (>20 pieces / 100μm²), a medium-density area (5-20 pieces / 100μm²), and a low-density area (<5 pieces / 100μm²). The cell size in the high-density area is automatically reduced to 50μm×50μm to avoid feature confusion caused by a single cell spanning multiple graphics. The default cell size of 75μm×75μm is used for the medium-density area. The cell size in the low-density area is enlarged to 150μm×150μm. Furthermore, a dynamic merging mechanism can be set to automatically merge 3×3 consecutive low-density cells into a large cell (300μm×300μm), reducing the data volume while ensuring detection coverage.

[0058] Step S103: Establish a mapping relationship between unit size and wafer diameter. In view of the greater edge curvature of 12-inch wafers, polar coordinate division is introduced in the edge gradient zone. The center of the wafer is used as the pole, and the fan-shaped units are divided according to the angle θ and the radius r to ensure the consistency of the unit area in the edge area and avoid the deformation of the traditional Cartesian coordinate division at the edge of the large wafer.

[0059] In the embodiment, the detection resource is accurately allocated by hierarchical division of functional areas, the core functional area is divided in a honeycomb shape to ensure the integrity of the pattern, the edge functional area is divided in a ring shape to strengthen the edge effect monitoring, and the non-critical area is divided in a sparse grid to improve the efficiency; the pattern density is adaptively adjusted by dynamic optimization of the size of three levels of units, i.e., high, medium and low density, to avoid feature confusion and detection redundancy, and a dynamic merging strategy is innovatively introduced to further reduce the data volume; the wafer diameter adaptive design adopts polar coordinate division to solve the edge deformation problem of large-size wafers, ensure the uniformity of the area of the edge unit, and achieve a balance between detection accuracy, efficiency and process risk control, thereby providing a dynamic division scheme with strong adaptability for high-density fan-out packaging.

[0060] As a preferred embodiment of the application, in the photoetching process of the redistribution layer of the fan-out package, the copper pillar array is the main structure for electrical interconnection between the chip and the external circuit, and the positive resist development characteristics are prone to cause fluctuations in the verticality of the pattern sidewall. The three-dimensional scanning can quantitatively measure the transmission error between development and etching, thereby avoiding the hidden failure in the application of the positive resist. The two-dimensional detection method can only measure the critical dimension of the pattern, and cannot capture three-dimensional defects such as the verticality of the sidewall. For example, if the sidewall inclination is less than 85 degrees, the seed layer will not be evenly covered, which is prone to cause sputtering process risks. The specific implementation is as follows:

[0061] In step S210, the white light interferometer is used for three-dimensional profile scanning, and the vertical resolution needs to reach the level of 0.1 μm, and the lateral resolution is not more than 0.5 μm, so as to meet the tolerance requirement of the critical dimension of 17 to 23 μm after etching. The device calibration takes the sputtering seed layer plane as the reference surface, and ensures the traceability of the value through the NIST certified standard block. The scanning path is executed according to the development unit coordinates divided in step S100, and the point cloud scanning collection is performed unit by unit according to the stepping path of the photoetching machine.

[0062] In step S220, after the point cloud scanning collection, the original point cloud is subjected to outlier filtering processing, a radius of 3 μm filtering algorithm is used to remove the noise points deviating from the neighborhood point group by more than 0.2 μm. The base plane is fitted by the RANSAC algorithm to generate a height calculation reference. The copper pillar point cloud is segmented based on the Euclidean clustering algorithm, and the minimum distance is 5 μm to separate adjacent copper pillars. The extraction and calculation of the specific size feature parameters are as follows:

[0063] Copper pillar height: the Z-axis coordinate of the highest point of the copper pillar is extracted, and the vertical distance from the base plane is calculated.

[0064] Copper pillar diameter: the cross-sectional point cloud is intercepted at 1 μm above the base plane, and the least square method is used to fit the circle diameter.

[0065] Copper pillar sidewall verticality: the sidewall point cloud in the height interval of 1 to 20 μm is extracted, a conical surface is fitted, and the included angle between the generatrix and the Z-axis is calculated.

[0066] In this embodiment, submicron three-dimensional scanning is achieved through a white light interferometer, and the sputtering seed layer is used as the reference plane to ensure the traceability of the measurement value. Combined with the coordinate scanning of the developing unit, the technical problem that two-dimensional detection in the existing technology cannot capture the side wall verticality defects is solved; outlier radius filtering and RANSAC base plane fitting eliminate noise interference; not only can the key dimensions such as the height and diameter of the copper column be accurately measured, but also three-dimensional defects such as the side wall verticality can be quantified, making up for the shortcomings of the two-dimensional detection method.

[0067] As a preference of the above embodiment, during the point cloud scanning and acquisition process of step S210, the point cloud density control strategy collects the top area of ​​the copper pillar at a point pitch of less than 1 μm to capture micron-level protrusions or depressions; collects the sidewall area at a point pitch of no more than 2 μm to restore the inclination angle change; relaxes the point pitch to 5 μm for the base area to reduce background noise interference; and enables multi-band polarization filtering to suppress reflection interference on the highly reflective surface of the copper pillar.

[0068] In this embodiment, through differentiated point cloud density control strategies, the key features of the copper pillar array can be captured more accurately while reducing data redundancy and background noise interference; different acquisition strategies for the top, sidewall and base areas of the copper pillars ensure accurate detection of key features and improve the quality and reliability of the scanning data; multi-band polarization filtering technology can solve the problem of reflection interference on highly reflective surfaces and further improve the accuracy of the scanning data; the above settings help to more accurately evaluate the three-dimensional dimensional characteristics of the copper pillar array.

[0069] In some embodiments of the present invention, the circuit plating image of each developing unit is collected, and then the microscopic features of the copper pillar array and circuit plating, such as circuit defects, edge roughness and plating uniformity, are extracted. Traditional detection methods usually only focus on dimensional features, such as the CD size after etching, but it is difficult to reveal the correlation between dimensional deviations and microscopic defects, which can easily lead to misjudgment or missed detection; through microscopic feature recognition, the application effect of photoresist positive resin in the redistribution layer lithography process can be more comprehensively evaluated, thereby improving the accuracy and reliability of detection.

[0070] Specifically, a multispectral automated optical inspection system covering ultraviolet, visible, and infrared wavelengths is employed. The optimal detection wavelengths are selected for different defect types. Ultraviolet light is used to identify nanoscale residues on circuit edges; visible light is used to detect macroscopic defects such as circuit breaks and bridges; and infrared light penetrates the coating surface to identify internal voids or cold solder joints. The development units, divided according to step S100, capture images unit by unit at a set resolution, ensuring that each circuit feature contains at least 10 pixels to avoid missing features. Subsequently, a convolutional neural network is used to identify defects such as circuit breaks, bridges, and voids, and defect outlines are extracted using threshold segmentation and morphological operations. The undulation of the circuit edges is analyzed based on grayscale gradients to calculate roughness parameters. Finally, grayscale statistical methods are used to assess coating thickness consistency.

[0071] More specifically, the line defect characteristic calculation formula is:

[0072] ;

[0073] Among them, D f represents the line defect density; N represents the number of defects detected; L i represents the length of the i-th defect; W i represents the width of the i-th defect; L total Indicates the total line length in the inspection area; reflects the severity of defects per unit length by calculating the ratio of the total area of ​​all defects to the total line length.

[0074] The edge roughness characteristic calculation formula is:

[0075] ;

[0076] Among them, R q represents the root mean square roughness; M represents the total number of edge sampling points; h j Indicates the vertical height deviation of the jth sampling point relative to the ideal edge reference line; Represents the average value of the height deviation of all sampling points; the edge roughness feature calculation formula is based on the profile height data of the line edge, and calculates the root mean square value of the height deviation to characterize the micro-roughness of the edge.

[0077] The coating uniformity characteristic is calculated as:

[0078] ;

[0079] Among them, U c Indicates the coating uniformity coefficient; σ t Indicates the standard deviation of coating thickness; t avg Indicates the average thickness of the coating; the ratio of the standard deviation of the coating thickness to the average value reflects the consistency of the coating thickness. The closer the coating uniformity coefficient is to 0, the better the uniformity.

[0080] In this embodiment, a multi-spectral automatic optical inspection system covering ultraviolet, visible light, and infrared bands is used to select the best detection band for different defect types. Ultraviolet light is used to identify circuits, visible light is used to detect macro defects, and infrared light is used to detect internal voids, thereby improving the comprehensiveness and accuracy of defect detection. The collected images are divided according to the developing unit and the circuit feature pixels are ensured. The convolutional neural network is combined to identify defects such as circuit breaks, bridges, and voids. The defect contours are extracted using threshold segmentation and morphological operations to achieve accurate identification of micro defects. The circuit edge roughness parameters are calculated based on the grayscale gradient, and the grayscale statistical method is used to evaluate the consistency of the coating thickness. The micro features are quantified through the circuit defect density formula, the edge root mean square roughness formula, and the coating uniformity coefficient formula, so that circuit board defects can be accurately detected.

[0081] In some embodiments of the present invention, the preset quality standards include a standard range of dimensional characteristic parameters and a standard range of microscopic characteristic parameters; wherein the standard range of dimensional characteristic parameters specifically includes:

[0082] The standard range for copper pillar height is set within ±10% of the design target value. For example, if the design target height is 20μm, the standard range can be set to 18-22μm. The standard range for copper pillar height is determined based on the accuracy of the chip manufacturing process and the requirements for electrical performance after packaging. If the copper pillar height is too low, it may cause poor electrical connection between the chip and the external circuit; if it is too high, it may affect the flatness and mechanical stability of the package.

[0083] The standard range for copper pillar diameter is set at ±5%-±8% of the design size. Assuming a design diameter of 15μm, the standard range could be 14.2-15.7μm or 13.8-16.2μm. The standard range for copper pillar diameter takes into account the precision of the photolithography and etching processes, as well as the impact of the subsequent electroplating process on the lateral growth of the copper pillar. Exceeding the diameter tolerance may affect the current carrying capacity of the copper pillar and the spacing with adjacent circuits, thereby affecting chip performance and reliability.

[0084] The standard range for the verticality of the copper pillar sidewall is set at 85°-95°. During the chip manufacturing process, if the sidewall inclination is too large, it will lead to uneven coverage of the seed layer, which will in turn cause risks in the sputtering process, affecting the electroplating quality of the copper pillar and the bonding strength with the substrate. Excessive verticality may increase the process difficulty and cost.

[0085] The standard range of microscopic characteristic parameters specifically includes:

[0086] The standard range for circuit defect characteristics is set at less than 0.05μm² / μm; this is determined based on the chip's reliability and performance requirements. A small number of defects may have little impact on the overall performance of the chip, but when the defect ratio is too high, it may cause problems such as reduced circuit conductivity and signal transmission delays.

[0087] The standard range of edge roughness is set at 0.5-1.2μm, determined based on the precision of the chip manufacturing process and the performance requirements of the chip after packaging. Excessive edge roughness may affect the electrical performance of the circuit, leading to problems such as signal interference. It may also affect subsequent packaging processes, such as filling and adhesion of packaging materials.

[0088] The standard range of the coating uniformity characteristic is set at 0.85-1.15; that is, the ratio of the standard deviation of the coating thickness to the average value does not exceed 15%; it is determined based on the stability of the electroplating process and the reliability requirements of the chip; if the coating uniformity coefficient is too low, it means that the coating thickness is too uniform, and there may be a problem of excessive process control; if it is too high, it may indicate that the coating thickness is uneven, resulting in unstable electroplating quality on the chip surface, affecting the electrical performance and corrosion resistance of the chip.

[0089] Furthermore, in step S500, the calculation formula for the developing unit quality score is:

[0090] ;

[0091] Among them, Q s Indicates the quality score of the developing unit in percentage, ranging from 0 to 100%; n indicates the total number of types of characteristic parameters that exceed the standard, such as dimensional tolerance, line defects, roughness exceeding the standard, etc.; w k represents the weight coefficient of the kth category of exceeding standard characteristic parameters; x k Indicates the actual exceeding range of the kth category of exceeding standard characteristic parameters, such as the size exceeding tolerance value, defect density exceeding value, etc.; T k Indicates the preset standard threshold value of the kth category of excessive characteristic parameters, such as the upper limit of the allowable defect density.

[0092] In the calculation formula of the above developing unit quality score, Normalize the actual value of each type of exceeding standard characteristic parameter into relative proportion to eliminate the influence of different parameter dimensions; The influence of different parameters on quality is reflected through weight coefficients. For example, the weight of line defects is higher than that of edge roughness. The weight coefficient can be dynamically adjusted for different products or process stages. For example, the weight of edge roughness is higher in the electroplating process. The square operation is used to amplify the impact of the deviation from the standard. The penalty points for minor deviations are less, while the penalty points for serious deviations are significantly increased. The cumulative impact of exceeding the standard is mapped into a quality score through an exponential function to ensure that the score decreases monotonically with the degree of exceeding the standard and the decrease is controllable, so as to avoid a single item exceeding the standard directly leading to zero score.

[0093] As a preferred embodiment of the above embodiment, after obtaining the quality score of each developing unit, the discrete score data is difficult to intuitively reflect the overall quality condition of the wafer; in the production process, it is necessary to quickly locate the high-risk area on the wafer, judge whether the defect distribution has systematicity, and trace the correlation between process parameters and quality fluctuation; if there is no visual quality distribution map, only relying on a single unit score cannot efficiently identify the spatial law of quality abnormality, and it is also difficult to support process improvement decision; therefore, converting the score into a quality distribution map can convert abstract data into intuitive information and improve the quality analysis efficiency.

[0094] Specifically, the division result of step S100 is used, and each developing unit corresponds to a unique coordinate (X, Y) or polar coordinate (r, θ) in the wafer global coordinate system. For example, the edge region of a 12-inch wafer is divided by polar coordinates, taking the center of the wafer as the pole point, defining the position of the fan-shaped unit by radius r (0-150 mm) and angle θ (0-360°) to avoid the distortion problem of Cartesian coordinates at the edge of a large wafer. A database corresponding to the unit number, coordinate and quality score is established, such as the edge unit with the number EDGE-01-01, the coordinate (r=145 mm, θ=45°) and the quality score of 65 points.

[0095] The quality score of each developing unit is mapped to the wafer plane according to its spatial coordinate by using professional graphics processing software or self-defined script. Color coding or gray scale is used to distinguish the score, for example, high-score areas are marked in green, indicating good quality; low-score areas are marked in red, indicating significant quality risk; intermediate-score areas are marked in yellow or orange, which intuitively shows the quality gradient change.

[0096] In this embodiment, the wafer packaging quality distribution map can intuitively show the quality conditions of different regions on the entire wafer, so that the wafer packaging quality identification model can quickly identify the regions with higher quality risk; through spatial coordinate mapping and data visualization, the discrete quality score is converted into defect distribution information with physical meaning, and the quality data is given spatial dimension, so that the detection result is upgraded from simple pass or fail judgment to deep problem tracing of where and why it fails, providing an indispensable spatial quality control tool for high-precision manufacturing of fan-out packaging.

[0097] As a preferred embodiment of the above embodiment, the wafer edge, chip layout area, high-risk process area and other key positions are marked in the wafer packaging quality distribution map to assist in quickly correlating the relationship between quality abnormalities and physical positions; through the above setting, it can quickly focus on the main area of the chip and identify whether there is a quality problem in these areas, so as to quickly respond and reduce the production delay and cost increase caused by quality problems.

[0098] Further, the DBSCAN algorithm is used to identify a defect hotspot formed by a plurality of low-score units in succession, for example, if the scores of three adjacent units are all less than 70%, the three adjacent units are marked as a systematic defect area, which is helpful to mine a defect mode with statistical significance from a large amount of data, and not only a single defect can be identified, but also a systematic defect area can be found, which represents some common problems in a process, such as improper equipment calibration or material batch problems.

[0099] In some embodiments of the present application, the wafer packaging quality recognition model is used to recognize the quality distribution map generated in step S600, so as to realize automatic classification of defects, yield prediction and process abnormality tracing.

[0100] Specifically, the input layer of the wafer packaging quality recognition model receives the quality distribution map, extracts defect spatial features such as edge ring and center spot distribution through multi-layer convolution and pooling operations of the convolutional neural network, and finally outputs results including defect types, yield grades and process abnormality traces by the full connection layer combined with the Softmax classifier; wherein the defect types include edge development residue and uneven exposure energy, and the process abnormality traces include edge spray pressure deficiency in the development process.

[0101] The construction of the wafer packaging quality recognition model is based on a large number of training sets of images constructed from historical batch quality distribution maps and artificially labeled defect types and process abnormality sources, the generalization ability is improved through data enhancement such as rotation and scaling, the classification accuracy is optimized by using the cross-entropy loss function, and the quality feature changes of new materials or new processes are adapted by using real-time production data for online iteration.

[0102] All unit determination results are summarized to generate a wafer-level quality report, which includes the proportion of qualified units, high-risk area distribution map and main defect type statistics; the report also outputs process parameter correlation analysis results, for example, the correlation analysis of electroplating current density and high-risk units.

[0103] In the present embodiment, the convolutional neural network structure of the wafer packaging quality recognition model automatically extracts spatial feature patterns such as edge ring and center spot in the quality distribution map, realizes intelligent classification of defect types and accurate tracing of process abnormalities, and based on the historical data training and real-time online iteration mechanism, the model dynamically adapts to the characteristics of new materials and processes, effectively predicts the overall yield trend, and finally generates a wafer-level quality report integrating qualified unit distribution, defect statistics and process parameter correlation analysis, which provides decision support from defect positioning, root cause tracing to production line optimization.

[0104] As shown in Figure 2 The present application also provides a fan-out packaging detection system based on a photoetching positive resist, which specifically includes the following modules.

[0105] A developing area division module is used to divide the photoresist positive resist developing area into units to obtain multiple developing units;

[0106] A three-dimensional profile scanning module is used to perform three-dimensional profile scanning on the copper pillar array after etching by each developing unit to obtain the dimensional characteristic parameters of the copper pillar array;

[0107] A microscopic feature recognition module is used to collect the circuit electroplating image of each developing unit, perform microscopic feature recognition on it, and obtain microscopic feature parameters;

[0108] a comparison and analysis module, configured to compare and analyze the dimensional characteristic parameter and the microscopic characteristic parameter with corresponding preset quality standards for each developing unit, and generate an exceeding-standard feature set when any one of the dimensional characteristic parameter and the microscopic characteristic parameter exceeds the preset quality standard;

[0109] A quality assessment module, configured to perform quality assessment on the exceeding-standard feature set to obtain a quality score corresponding to each developing unit;

[0110] The spatial position assignment module is used to assign the quality score corresponding to each developing unit according to its actual spatial position to obtain a wafer packaging quality distribution map;

[0111] The quality recognition model module is used to use a predetermined wafer packaging quality recognition model to identify the wafer packaging quality distribution map and obtain a wafer packaging quality detection result.

[0112] In this embodiment, the developing area division module divides the developing area into multiple units in a refined manner, which can accurately locate local process fluctuations, solve the problem of global detection masking local defects, and realize targeted evaluation of special areas such as edges and shielding; the three-dimensional contour scanning is combined with the micro-feature recognition module to obtain the three-dimensional size characteristics of the copper pillar array and the micro-features of the circuit electroplating, changing the mode of independent evaluation of a single indicator, and can characterize the correlation between dimensional deviations and micro-defects, avoiding misjudgment or missed detection; the comparative analysis and quality assessment module generates a developing unit quality score, and the spatial position assignment module forms a quality distribution map, giving the quality data a spatial dimension, which is convenient for intuitively identifying the defect distribution law; the quality recognition model module uses an intelligent model to automatically process the distribution map, realize defect classification, yield prediction and process anomaly tracing, and improve detection efficiency.

[0113] The above shows and describes the basic principles, main features and advantages of the present invention; those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for illustrating the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements fall within the scope of the present invention to be protected; the scope of protection claimed in the present invention is defined by the attached claims and their equivalents.

Claims

1. A fan-out packaging detection method based on positive photoresist, characterized in that: include: Dividing the photoresist positive resist developing area into units to obtain a plurality of developing units; Performing a three-dimensional profile scan on the copper pillar array etched by each developing unit to obtain dimensional characteristic parameters of the copper pillar array; Collecting the circuit electroplating image of each developing unit, and performing microscopic feature recognition on the image to obtain microscopic feature parameters; For each of the developing units, the size characteristic parameter and the microscopic characteristic parameter are respectively compared and analyzed with corresponding preset quality standards, and when any one of the size characteristic parameter and the microscopic characteristic parameter exceeds the preset quality standard, an exceeding standard feature set is generated; Performing a quality assessment on the exceeding-standard feature set to obtain a quality score corresponding to each developing unit; Assigning a quality score corresponding to each of the developing units according to their actual spatial position to obtain a wafer packaging quality distribution map; The wafer packaging quality distribution map is identified using a predetermined wafer packaging quality identification model to obtain a wafer packaging quality detection result.

2. The fan-out packaging detection method based on positive photoresist according to claim 1, characterized in that: The dimension characteristic parameters include the copper pillar height, the copper pillar diameter and the verticality of the copper pillar sidewall.

3. The fan-out packaging detection method based on positive photoresist according to claim 2, characterized in that: The microscopic characteristic parameters include at least line defect characteristics, line edge roughness characteristics and coating uniformity characteristics.

4. The fan-out packaging detection method based on positive photoresist according to claim 3, characterized in that: The exceeding-standard feature set includes the types and exceeding-standard amplitudes of all exceeding-standard feature parameters in the developing unit.

5. The fan-out packaging detection method based on positive photoresist according to claim 4, characterized in that: The dynamic division strategy is used to divide the photoresist positive film development area into units, including: Classify functional areas into different levels; The graphic density of each area is calculated through image recognition. The area with a density above the preset threshold is reduced in size according to the set ratio, and the area with a density below the preset threshold is merged with adjacent units.

6. The fan-out packaging detection method based on positive photoresist according to claim 5, characterized in that: The line defect characteristic calculation formula is: ； Among them, D f represents the line defect density; N represents the number of defects detected; L i represents the length of the i-th defect; W i represents the width of the i-th defect; L total Indicates the total line length of the detection area.

7. The fan-out packaging detection method based on positive photoresist according to claim 6, characterized in that: The edge roughness characteristic calculation formula is: ； Among them, R q represents the root mean square roughness; M represents the total number of edge sampling points; h j Indicates the vertical height deviation of the jth sampling point relative to the ideal edge reference line; It represents the average value of the height deviation of all sampling points.

8. The fan-out packaging detection method based on positive photoresist according to claim 7, characterized in that: The coating uniformity characteristic is calculated as: ； Among them, U c Indicates the coating uniformity coefficient; σ t Indicates the standard deviation of coating thickness; t avg Indicates the average thickness of the coating.

9. The fan-out packaging detection method based on positive photoresist according to claim 8, characterized in that: The calculation formula of the developing unit quality score is: ； Among them, Q s represents the quality score of the developing unit; n represents the total number of types of characteristic parameters that exceed the standard; w k represents the weight coefficient of the kth category of exceeding standard characteristic parameters; x k Indicates the actual exceeding range of the kth category exceeding standard characteristic parameter; T k Indicates the preset standard threshold value of the kth category of excessive characteristic parameters.

10. A fan-out packaging inspection system based on positive photoresist, characterized in that: include, A developing area division module is used to divide the photoresist positive resist developing area into units to obtain multiple developing units; A three-dimensional profile scanning module is used to perform three-dimensional profile scanning on the copper pillar array after etching by each developing unit to obtain the dimensional characteristic parameters of the copper pillar array; A microscopic feature recognition module is used to collect the circuit electroplating image of each developing unit, perform microscopic feature recognition on it, and obtain microscopic feature parameters; a comparison and analysis module, configured to compare and analyze the dimensional characteristic parameter and the microscopic characteristic parameter with corresponding preset quality standards for each developing unit, and generate an exceeding-standard feature set when any one of the dimensional characteristic parameter and the microscopic characteristic parameter exceeds the preset quality standard; A quality assessment module, configured to perform quality assessment on the exceeding-standard feature set and obtain a quality score corresponding to each developing unit; The spatial position assignment module is used to assign the quality score corresponding to each developing unit according to its actual spatial position to obtain a wafer packaging quality distribution map; The quality recognition model module is used to use a predetermined wafer packaging quality recognition model to identify the wafer packaging quality distribution map and obtain a wafer packaging quality detection result.

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