Semiconductor package and assembling method thereof

Abstract

The invention relates to a semiconductor package and a method of assembling the same. The semiconductor package includes an interposer having opposite first and second major surfaces. The semiconductor die is on the first major surface and electrically connected to the second major surface via a plurality of electrical vias through the interposer. The heat dissipation cover is located on the semiconductor die. The heat conduction material is located between the semiconductor crystal grain and the heat dissipation cover. The thermally conductive material is thermally coupled to the semiconductor die and the heat dissipation cover. The heat dissipation cover may be a thermoelectric cooler. The heat conduction material can be a mixture of colloid and liquid metal.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor packaging. Background Art

[0002] The following relates to semiconductor packages, semiconductor packages with integrated heat sinking and / or cooling, and the like. Summary of the Invention

[0003] In a non-limiting exemplary embodiment, a semiconductor package includes: an interposer having a first major surface and a second major surface, the first major surface opposing the second major surface; one or more semiconductor dies disposed on the first major surface of the interposer and electrically connected to the second major surface of the interposer via a plurality of electrical vias extending through the interposer; a heat sink disposed on the semiconductor dies; and a thermally conductive material disposed between the semiconductor dies and the heat sink, thermally coupling the semiconductor dies to the heat sink. The heat sink may include a thermoelectric cooler, a metal, single crystal diamond, or a combination thereof.

[0004] In a non-limiting exemplary embodiment, a method for assembling a semiconductor package includes embedding one or more semiconductor dies on a first major surface of an interposer, the semiconductor dies being electrically connected to a second major surface of the interposer via a plurality of electrical vias passing through the interposer, with the first major surface and the second major surface being opposite to each other; placing a support ring on the first major surface of the interposer, the support ring surrounding the semiconductor dies; molding a molding material around the support ring and the semiconductor dies; placing a thermally conductive material on the semiconductor dies; and placing a heat dissipation cover on the thermally conductive material.

[0005] In a non-limiting exemplary embodiment, a semiconductor package includes: an interposer having a first major surface and a second major surface, the first major surface opposing the second major surface; one or more semiconductor dies disposed on the first major surface of the interposer and electrically connected to the second major surface of the interposer via a plurality of electrical vias extending through the interposer; a support ring disposed on the first major surface of the interposer and surrounding the semiconductor dies; a molding material molded around the support ring and the semiconductor dies; a thermally conductive material disposed on the semiconductor dies; and a heat dissipation cover disposed on the thermally conductive material. The heat dissipation cover includes a thermoelectric cooler and / or the thermally conductive material includes a mixture of a colloid and a liquid metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An exploded cross-sectional view of a semiconductor package containing a thermoelectric cooler thermally coupled to the semiconductor die via a thermal interface material.

[0007] Figure 2 yes Figure 1 A cross-sectional view of a semiconductor package.

[0008] Figure 3 yes Figure 1 and Figure 2 Bottom view of a thermoelectric cooler for a semiconductor package.

[0009] Figure 4 An exploded cross-sectional view of a semiconductor package containing a thermoelectric cooler thermally coupled to the semiconductor die via liquid metal.

[0010] Figure 5 An exploded cross-sectional view of a semiconductor package, which includes a highly thermally conductive lid thermally coupled to the semiconductor die via liquid metal.

[0011] Figure 6 is a flow chart of a method of assembling a semiconductor package.

[0012] The description of the accompanying drawings is as follows:

[0013] A: Partial

[0014] B,C,D,E: Illustration

[0015] 10,100,200: Semiconductor packaging

[0016] 11, 12, 13: semiconductor grains

[0017] 14: Intermediary layer

[0018] 16: First major surface

[0019] 18: Second major surface

[0020] 20: Electrical through-hole

[0021] 22,24: Engagement bumps

[0022] 26: Bottom filling material

[0023] 30: Thermoelectric Cooler

[0024] 32: First heat conduction plate

[0025] 34: Second heat conduction plate

[0026] 35: Back side metal coating

[0027] 36: First electrical connection

[0028] 38: Second electrical connection

[0029] 40: n-type region

[0030] 42: p-type region

[0031] 44: Thermoelectric Cooler Power Supply

[0032] 45: Line

[0033] 46: Cold plate or radiator

[0034] 48: Heat sink fins

[0035] 49,50: Thermal interface materials

[0036] 54: Support ring

[0037] 56: Molding material

[0038] 58: Base or foot

[0039] 60,260: Grooves

[0040] 80: Area

[0041] 82: Grain projection area

[0042] 150: Mixture

[0043] 152: Adhesive layer

[0044] 230: Heat dissipation cover

[0045] 270: First floor

[0046] 272: Second Floor

[0047] 300,302,304,306,308,310,312: Steps DETAILED DESCRIPTION

[0048] The following detailed description is accompanied by accompanying drawings to facilitate an understanding of various aspects of the present invention. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is common practice in the industry. In practice, the dimensions of the various structures may be arbitrarily increased or decreased for clarity.

[0049] The following provides different embodiments or examples for implementing different structures of the embodiments of the present invention. The specific components and arrangements are provided to simplify the present disclosure and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by additional components rather than in direct contact. The same reference numerals may be repeatedly used in various embodiments of the present invention for simplicity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0050] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or similar terms are used to describe the relationship of one element or structure to another element or structure in the drawings. These spatially relative terms encompass various orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative adjectives used will be interpreted based on that orientation.

[0051] A semiconductor assembly or package includes one or more semiconductor dies, such as integrated circuit chips, fabricated on or in silicon, which are embedded on a first major surface (e.g., an upper surface) of an interposer, which is in turn disposed on a substrate, such as a printed circuit board. For example, the interposer may include a silicon wafer having through-holes to provide electrical communication from the first major surface on which the one or more semiconductor dies are embedded to an opposing second major surface (e.g., a lower surface) in contact with the substrate. The interposer may optionally include a redistribution layer to provide complex electrical routing of electrical signals and / or power between the first and second major sides of the interposer. The combination of one or more semiconductor dies embedded in the interposer may be embedded on a substrate. Although the foregoing is cited herein as an illustrative example, the thermal management methods disclosed herein are also applicable to other types of semiconductor packages referred to by different nomenclatures, such as three-dimensional integrated circuit packages.

[0052] Thermal management in semiconductor packaging is challenging. Some package designs aim to closely place multiple semiconductor dies (some or all of which may be high-power integrated circuit chips) on an interposer to reduce package footprint, thereby creating a concentrated high-power heat source. The underlying substrate can be cooled through the interposer, but this heat dissipation path is limited by the thermal conductivity of the ball grid array and underfill material (which form the interface between the semiconductor dies and the interposer, and between the interposer and the substrate), as well as the thermal resistance of the interposer itself. For further cooling, a cold plate or heat sink can be placed on top of one or more semiconductor dies. However, with advances in semiconductor die and package design (such as the packaging of advanced CPUs and GPUs used in high-performance computing and artificial intelligence applications), overall energy consumption and power density continue to increase. In some non-limiting illustrative examples, the maximum power density of a hot spot in a commercial CPU or GPU package is approximately 4 W / mm 2 , and total chip power is about 400 watts to 600 watts or more.

[0053] The semiconductor chip package and corresponding method for assembling the semiconductor package described herein can improve thermal management. In some exemplary embodiments, the semiconductor package includes one or more semiconductor dies located on a first major surface of an interposer and electrically connected to an opposing second major surface of the interposer via electrical vias extending through the interposer. A heat sink is located on the one or more semiconductor dies. A thermally conductive material is located between the one or more semiconductor dies and the heat sink, thermally coupling the one or more semiconductor dies to the heat sink. A cold plate or heat sink is located on the heat sink. In some embodiments, the heat sink includes a thermoelectric cooler, while in other embodiments, the heat sink includes a metal, single crystal diamond, or a combination thereof (e.g., a high thermal conductivity single crystal diamond layer adjacent to the one or more semiconductor dies and a low thermal conductivity metal layer distal to the one or more semiconductor dies). The thermally conductive material can include a thermally conductive metal or metal alloy, such as indium, silver, copper, an indium alloy, a silver alloy, a copper alloy, or a solder material. In other embodiments, the thermally conductive material may include a mixture of a colloid and a liquid metal, such as a mixture of a polymer colloid and a liquid metal with a sufficiently low melting point, such as gallium, such that the liquid metal is liquid at the operating temperature of the semiconductor package design. The semiconductor package may also include a support ring positioned on the first major surface of the interposer and surrounding one or more semiconductor dies, and a molding material molded around the support ring and the one or more semiconductor dies. In embodiments where the thermally conductive material includes a colloid and a liquid metal, an adhesive layer may be positioned around the heat sink. The adhesive layer contains a mixture of the colloid and the liquid metal when the metal liquefies at the operating temperature of the package. The adhesive layer may also bond a thermoelectric cooler to the molding material.

[0054] Figure 1 and Figure 2 1 is a non-limiting exemplary embodiment of a semiconductor package 10 . Figure 1 is an exploded sectional view of the semiconductor package 10, and Figure 2 1 is a cross-sectional view of a semiconductor package 10. The semiconductor package 10 includes one or more (three as shown) semiconductor dies 11, 12, and 13 located on an interposer 14. Specifically, the one or more semiconductor dies 11, 12, and 13 are located on a first major surface 16 (e.g., an upper side surface or an upper surface) of the interposer 14. An opposite second major surface 18 (e.g., a lower side surface or an underside surface) of the interposer 14 is opposite to the first major surface 16. The one or more semiconductor dies 11, 12, and 13 located on the first major surface 16 of the interposer 14 are electrically connected to the second major surface 18 of the interposer 14 via an electrical via 20 passing through the interposer 14. Specifically, Figure 1 and Figure 2In the exemplary embodiment, a first set of bonding bumps 22 are located on first major surface 16 of interposer 14 and provide electrical connections between contact pads (not shown) of one or more semiconductor dies 11, 12, and 13 and the ends of electrical vias 20 on first major surface 16. A second set of bonding bumps 24 are located on second major surface 18 of interposer 14 and electrically connect to the ends of electrical vias 20 on second major surface 18. First set of bonding bumps 22 may be microspheres and may be formed into a ball grid array aligned with the contact pads of one or more semiconductor dies 11, 12, and 13. First set of bonding bumps 22 generally provide or facilitate mechanical attachment of one or more semiconductor dies 11, 12, and 13 to first major surface 16 of interposer 14. In some embodiments, underfill material 26 fills the spaces between bonding bumps 22, first major surface 16 of interposer 14, and adjacent surfaces of one or more semiconductor dies 11, 12, and 13. For example, the second set of bonding bumps 24 may form a ball grid array for bonding the semiconductor package 10 to alignment pads of a printed circuit board or other substrate (not shown). The bonding bumps 22 and 24 may include solder bumps, solder-coated copper balls, or other suitable conductive bumps.

[0055] The one or more semiconductor dies 11, 12, and 13 may generally comprise any type of semiconductor die or a combination of multiple semiconductor dies. By way of non-limiting example, the one or more semiconductor dies 11, 12, and 13 may comprise an integrated circuit die such as a microprocessor, a microcontroller, a central processing unit die, a graphics processing unit die, a solid-state memory die, a special-purpose integrated circuit, a field-programmable gate array, an optical die (e.g., a semiconductor light-emitting diode, a laser, a photodetector, and / or the like), combinations thereof, and / or the like. These are merely non-limiting examples. The one or more semiconductor dies 11, 12, and 13 may be silicon dies or silicon-based dies, or Group III-V semiconductor dies, silicon germanium and / or silicon carbide dies, combinations thereof, and the like. Although the semiconductor dies 11, 12, and 13 are each depicted as a single die in the figures, a given semiconductor die (e.g., semiconductor die 12) may also be implemented as a stack of two (or more) semiconductor dies.

[0056] Interposer 14 is typically a silicon interposer, but may also be a sapphire interposer, a silicon carbide interposer, or an interposer made of other materials. For example, electrical vias 20 extending through interposer 14 may include through-silicon vias (TSVs) extending through interposer 14 (in this case, a silicon interposer), and / or electrical vias 20 may include a redistribution layer (not shown) formed on one or both of first major surface 16 and second major surface 18 of interposer 14. The inclusion of a redistribution layer may provide an electrical path for redistributing electrical signals and / or power between one or more semiconductor dies 11, 12, and 13 and the second set of bonding bumps 24.

[0057] In order to provide thermal management such as cooling required for one or more semiconductor dies 11, 12, and 13, a heat dissipation cover in the form of a thermoelectric cooler 30 may be placed on one or more semiconductor dies 11, 12, and 13. Figure 1 As shown in part A of the , the thermoelectric cooler 30 can be constructed as a Peltier cooling device, which includes a first thermally conductive plate 32, a second thermally conductive plate 34 (optionally having a backside metal coating 35), a first electrical connection 36 located on the first thermally conductive plate 32, a second electrical connection 38 located on the second thermally conductive plate 34, and an n-type region 40 and a p-type region 42 located between the first thermally conductive plate 32 and the second thermally conductive plate 34 and electrically connected to the first electrical connection 36 and the second electrical connection 38. The first thermally conductive plate 32 and the second thermally conductive plate 34 can be thermally conductive but electrically insulating, and can include ceramic plates such as ceramic barium oxide plates. Therefore, the n-type region 40 and the p-type region 42 are thermally connected in parallel between the first thermally conductive plate 32 and the second thermally conductive plate 34. On the other hand, as shown in part A, the n-type region 40 and the p-type region 42 are electrically connected in series via the first electrical connection 36 and the second electrical connection 38 to form a series junction of ...n / p / n / p / ... In response to current flowing through the series-connected n-type region 40 and the p-type region 42 (e.g., current driven by a thermoelectric cooler power supply 44 connected to the thermoelectric cooler 30 via line 45), heat can be transferred from the hot side corresponding to the second thermally conductive plate 34 that is in thermal contact with one or more semiconductor dies 11, 12, and 13 to the cold side corresponding to the first thermally conductive plate 32 that is in thermal contact with a cold plate or heat sink 46 located on the thermoelectric cooler 30 for dissipating heat (see FIG. Figure 1 Main picture, note Figure 2 The Peltier effect operates as a heat transfer mechanism, actively transferring heat from one or more semiconductor dies 11, 12, and 13 to a cold plate or heat sink 46. Thermoelectric cooler 30 can have various thicknesses. In some non-limiting examples, the thickness of thermoelectric cooler 30 is greater than or equal to approximately 1 micron to 5 microns.

[0058] exist Figure 1 In the illustrated exemplary embodiment, an exemplary thermoelectric cooling power supply 44 provides operating power for the thermoelectric cooler 30. However, in various embodiments (not shown), the thermoelectric cooler power supply may be integrated into one or more semiconductor dies 11, 12, and 13, such as being implemented as a DC power supply circuit implemented as an integrated circuit of one or more semiconductor dies 11, 12, and 13. In these embodiments, the traces 45 may be suitably implemented as isolated electrical feedthroughs (not shown) that connect to the thermoelectric cooler 30.

[0059] The cold plate or heat sink 46 can be constructed in a variety of ways. In some embodiments, the cold plate or heat sink 46 can be a passive cooling component such as a metal plate or flat plate, which has a suitably large heat capacity to absorb and dissipate the heat generated by one or more semiconductor dies 11, 12, and 13, and transfer the heat to the cold plate or heat sink 46 via the action of the thermoelectric cooler 30. In other embodiments, the cold plate or heat sink 46 can be actively cooled, such as a conduit containing a cooling fan or a fluid such as gas or water (which can optionally have a positive fluid flow supplied by a pipe or tubing and driven by a cooling pump, and the components used are not shown). The exemplary cold plate or heat sink 46 optionally includes heat dissipation fins 48, which can increase the surface area to facilitate heat transfer to the environment (such as the atmosphere). In addition, as Figure 1 As shown, thermal interface material 49 is applied to the opposing surface of cold plate or heat sink 46 contacting thermoelectric cooler 30 to improve heat transfer from thermoelectric cooler 30 to cold plate or heat sink 46. In some non-limiting examples, thermal interface material 49 may include indium, silver, copper, an indium alloy, a silver alloy, a copper alloy, or a solder material. In some non-limiting exemplary embodiments, thermal interface material 49 has a thickness of less than or equal to 200 microns. In some embodiments, thermal interface material 49 has a thickness of 50 to 100 microns.

[0060] To provide a conductive thermal coupling between the thermoelectric cooler 30 and the one or more semiconductor dies 11, 12, and 13, the second thermally conductive plate 34 (see Section A) of the thermoelectric cooler 30 proximate to the one or more semiconductor dies 11, 12, and 13 may optionally include a backside metal coating 35. In a non-limiting example, the backside metal coating 35 may be a stack of titanium / copper / nickel vanadium / gold (wherein nickel vanadium is a nickel vanadium alloy), with the titanium closest to the one or more semiconductor dies 11, 12, and 13 and the gold contacting the second thermally conductive plate 34. In a non-limiting example, the thickness of the nickel vanadium may be about 1000 Å. The thickness of gold can be about A thermally conductive material may additionally or alternatively be located between the one or more semiconductor dies and the thermoelectric cooler 30 to thermally couple the one or more semiconductor dies 11, 12, and 13 to the thermoelectric cooler 30. Figure 1 and Figure 2 In the semiconductor package 10, the thermal conductive material is a thermal interface material 50 located between one or more semiconductor dies 11, 12, and 13 and the thermoelectric cooler 30, which can form Figure 1 and Figure 2The thermal interface material 50 is a heat dissipation cover for the semiconductor package 10. The thermal interface material 50 is a thermally conductive material and has a sufficient degree of mechanical deformation under pressure to deform and shape to conform to the surface of the thermoelectric cooler 30 facing one or more semiconductor dies 11, 12, and 13, thereby increasing the contact area for heat transfer. In some non-limiting examples, the thermal interface material 50 may include indium, silver, copper, an indium alloy, a silver alloy, a copper alloy, or a solder material. The thickness of the thermal interface material 50 may vary depending on parameters such as the type of material, the geometry of the semiconductor dies 11, 12, and 13, the surface of the thermoelectric cooler 30 facing the thermal interface material 50, and similar parameters. In some non-limiting exemplary embodiments, the thickness of the thermal interface material 50 is less than or equal to 200 microns. In some embodiments, the thickness of the thermal interface material 50 is 50 microns to 100 microns.

[0061] In order to improve the structural stability of the semiconductor package 10, a support ring 54 may be placed on the first major surface 16 of the interposer 14. The support ring 54 surrounds the one or more semiconductor dies 11, 12, and 13. A molding material 56 is molded around the support ring 54 and the one or more semiconductor dies 11, 12, and 13. The support ring 54 is as shown in FIG. Figure 1 The main picture and Figure 2 Illustration B is a perspective view of the support ring 54, also included in Figure 1 Inset B shows that the support ring 54 is rectangular and optionally includes a base or feet 58 on which the support ring 54 is supported on the first major surface 16 of the interposer 14 . Figure 1 In illustration B of FIG, optionally formed pedestals or pins 58 are located on two opposing sides of the exemplary support ring 54. However, in other embodiments, pedestals or pins may be included on all four sides of the support ring. Providing pedestals or pins 58 facilitates the flow of molding material 56 beneath the support ring 54 to seal the support ring 54. The support ring 54 may be composed of a suitable support material to provide the required support for the entire semiconductor package 10. In some non-limiting examples, the coefficient of thermal expansion of the support ring 54 is 3 ppm / °C to 10 ppm / °C, although values ​​outside this range may also be implemented. In some embodiments, the elastic modulus of the support ring 54 is 60 GPa to 380 GPa, although values ​​outside this range may also be implemented. In some non-limiting examples, the support ring 54 may include copper, a nickel-iron alloy such as Alloy 42, stainless steel such as SUS420, nickel, tungsten, copper-tungsten, copper-molybdenum, a nickel-iron alloy, or the like.

[0062] like Figure 1 and Figure 2 As shown, the upper surface of the molding material 56 (ie, the surface away from the interposer 14 ) is approximately coplanar with the upper surface of the one or more semiconductor dies 11 , 12 , and 13 (ie, the surface away from the interposer 14 ).

[0063] In some embodiments, the thermoelectric cooler 30 has a groove 60 formed on the surface of the thermoelectric cooler 30 facing the one or more semiconductor dies 11, 12, and 13 and the support ring 54. The thermal interface material 50 is filled into the groove 60 of the thermoelectric cooler 30. The groove 60 formed as appropriate can provide an exhaust path when the thermoelectric cooler 30 is compressed and placed on the thermal interface material 50. Filling the thermal interface material 50 into the groove 60 can also improve the effect of heat conduction from the one or more semiconductor dies 11, 12, and 13 to the thermoelectric cooler 30 through the thermal interface material 50. The groove 60 can have various geometric shapes, such as Figure 1 Figure C is included. Figure C shows a bottom view of the thermoelectric cooler 30 with three different embodiments of grooves 60. These patterns are provided as non-limiting examples. In some embodiments, the grooves 60 have a depth of 0.1 mm to 0.5 mm and a width of 0.5 mm to 2 mm, although values ​​outside these ranges may also be implemented.

[0064] like Figure 3 The projection diagram of specific structures of the semiconductor package 10 is shown to illustrate the relative positions of the layout of the specific structures. Figure 3 The specific structure shown includes a non-limiting exemplary layout of a region 80 of the interposer 14, a die projection area 82 (indicated by dashed lines) of one or more semiconductor dies 11, 12, and 13, and a recess 60 of the thermoelectric cooler 30. It should be understood that Figure 3 This is a non-limiting exemplary layout of the semiconductor package 10 , and the die projection area and the cavity may each implement other layouts.

[0065] As mentioned above, Figure 1 and Figure 2 In the embodiment of the present invention, one or more semiconductor chips 11, 12, and 13 are located between the heat dissipation cover (such as Figure 1 and Figure 2 The thermally conductive material between the thermoelectric cooler 30 implemented in the embodiment is a thermal interface material 50. In non-limiting illustrative examples, the thermal interface material 50 can be indium, silver, copper, indium alloy, silver alloy, copper alloy, or solder material.

[0066] Figure 4 In another embodiment, the semiconductor package 100 is an exploded cross-sectional view, which again uses the thermoelectric cooler 30 with the groove 60 as the heat dissipation cover (for example, with Figure 1 The semiconductor package 100 also includes many other components that can be used in conjunction with Figure 1 and Figure 2The semiconductor package 10 described above uses the same components, including one or more semiconductor dies 11, 12, and 13; an interposer 14 having a first major surface 16 and a second major surface 18 and electrical vias 20 therethrough; a plurality of bonding bumps 22 and 24 and an underfill material 26 filling the spaces between the bonding bumps 22; a thermoelectric cooler power supply 44 and connecting lines 45 (or if the power supply used in the power cooler 30 is integrated with one or more semiconductor dies 11, 12, or 13 as described above, the connecting lines 45 can be replaced by suitable insulated electrical feedthroughs to connect the one or more semiconductor dies 11, 12, or 13 to the thermoelectric cooler 30); a cold plate or heat sink 46 optionally having heat dissipation fins 48 and a thermal interface material 49 coated on its surface contacting the thermoelectric cooler 30; and a support ring 54 optionally having a base or pins 58 surrounding the molding material 56.

[0067] However Figure 4 The semiconductor package 100 is different from Figure 1 and Figure 2 The difference between the semiconductor package 10 and Figure 4 The semiconductor package 100 has different types of thermally conductive materials between one or more semiconductor dies 11, 12, and 13 and a thermoelectric cooler 30 serving as a heat dissipation cover. Figure 4 In the semiconductor package 100, the thermally conductive material between one or more semiconductor dies 11, 12, and 13 and the thermoelectric cooler 30 is a mixture 150 of colloid and liquid metal. In some non-limiting exemplary embodiments, the liquid metal comprises gallium, which has a melting point of approximately 30°C, and the colloid comprises a polymer. Because the melting point of gallium is slightly above room temperature (typically approximately 20°C to 24°C) and below the designed operating temperature of the semiconductor package 100, the gallium is liquid at the operating temperature of the semiconductor package 100. This liquefaction facilitates close thermal contact between the liquid gallium and the one or more semiconductor dies 11, 12, and 13 and the thermoelectric cooler 30, effectively transferring heat from the one or more semiconductor dies 11, 12, and 13 to the thermoelectric cooler 30. While gallium is suitable for the liquid metal in the mixture 150 of colloid and liquid metal, other suitable metals that are liquid at the operating temperature of the semiconductor package 100 may also be implemented as the liquid metal in the mixture 150. In a non-limiting example, the thickness of the colloid and liquid metal mixture 150 may be less than or equal to about 100 microns. In some embodiments, the thickness of the colloid and liquid metal mixture 150 may be inconsistent, such as having a thickness of less than or equal to about 30 microns in the center and a thickness of greater than or equal to about 100 microns in the peripheral portion. These are merely non-limiting examples.

[0068] exist Figure 1 In the semiconductor package 10, the thermal interface material 50 is generally solid at the operating temperature of the semiconductor package 10, so Figure 1and Figure 2 The thermal interface material 50 shown may be appropriately extended onto the support ring 54 (or more specifically, onto the molding material 56 coating the support ring 54). In contrast, the semiconductor package 100 uses a mixture of colloid and liquid metal 150 as a thermally conductive material, which is located between one or more semiconductor dies 11, 12, and 13 and the heat dissipation cover. Since metals such as gallium are liquid at the operating temperature of the semiconductor package 100, Figure 4 The semiconductor package 100 includes an adhesive layer 152 located around the periphery of the thermoelectric cooler 30, such as on the molding material 56 surrounding the support ring 54. The adhesive layer 152 may surround and contain the colloid and liquid metal mixture 150 to prevent the liquefied metal (e.g., liquid gallium) at operating temperatures from flowing out of the semiconductor package 100. The adhesive layer 152 may include an elastomeric adhesive layer, a sealing adhesive layer, a thermal paste, or the like.

[0069] like Figure 4 As shown, the adhesive layer 152 also fills the grooves 60 around the surface of the thermoelectric cooler 30, thereby further facilitating the accommodation of the colloid and liquid metal mixture 150. In some non-limiting embodiments, the adhesive layer 152 may be initially applied in a liquid state to fill the grooves 60, but may be converted to a solid state after the curing and / or packaging operation. Meanwhile, the colloid and liquid metal mixture 150 remains in a liquid state during the packaging operation. The adhesive layer 152 may also be used to bond the thermoelectric cooler 30 to the molding material 56, as appropriate. The colloid and liquid metal mixture 150 may also be filled into the internal grooves 60 on one or more semiconductor dies 11, 12, and 13 to increase the thermal contact area.

[0070] Figure 4 Also included is Illustration D, which is Figure 1 Inset C is the same as inset C. Inset D shows a bottom view of thermoelectric cooler 30 with three different patterns of embodiments for grooves 60. These patterns are provided for non-limiting illustration only.

[0071] Figure 1 and Figure 2 The semiconductor package 10 and Figure 4 Each of the semiconductor packages 100 includes a thermoelectric cooler 30 such as a heat dissipation cap located on one or more semiconductor dies 11 , 12 , and 13 .

[0072] Figure 5 is an exploded cross-sectional view of a semiconductor package 200 according to another embodiment. Figure 4 The difference of the semiconductor package 100 is that Figure 4 The thermoelectric cooler 30 of the semiconductor package 100 is replaced with a heat dissipation cover 230 comprising metal, single crystal diamond, or a combination thereof. Figure 5 The semiconductor package 200 and Figure 4The semiconductor package 100 is similar to the semiconductor package 100 and includes many components and matching Figure 4 Many components of the semiconductor package 100 described above are the same, such as one or more semiconductor dies 11, 12, and 13; an interposer 14 having a first major surface 16 and a second major surface 18, with electrical vias 20 extending through the interposer 14; a plurality of bonding bumps 22 and 24 and an underfill material 26 filling spaces between the bonding bumps 22; a cold plate or heat sink 46 optionally having heat dissipation fins 48; and a support ring 54 optionally having a base or pins 58 and surrounding a molding material 56.

[0073] Figure 5 The exemplary semiconductor package 200 and Figure 4 Similar to the exemplary semiconductor package 100, the thermal conductive material is located between one or more semiconductor dies 11, 12, and 13 and the heat dissipation cover 230 containing metal, single crystal diamond, or a combination thereof, and the thermal conductive material can be similar to the combination of Figure 4 A mixture 150 of the colloid described and a liquid metal (such as gallium having a melting point of about 30°C) is prepared. Figure 4 Similar to the exemplary semiconductor package 100, Figure 5 The exemplary semiconductor package 200 includes an adhesive layer 152 disposed around the periphery of a heat spreader lid 230 comprising metal, single crystal diamond, or a combination thereof, such as on the molding material 56 surrounding the support ring 54. The adhesive layer 152 surrounds and contains the colloid and liquid metal mixture 150, preventing the liquefied metal (e.g., liquid gallium) at operating temperatures from flowing out of the semiconductor package 200. A thermal interface material 49, optionally formed, is also coated on the opposite surface of the cold plate or heat sink 46 contacting the heat spreader lid 230 to improve heat transfer from the heat spreader lid 230 to the cold plate or heat sink 46.

[0074] The heat dissipation cover 230 comprising metal, single crystal diamond, or a combination thereof may optionally include a groove 260 formed in the surface of the heat dissipation cover 230 facing the one or more semiconductor dies 11, 12, and 13 and the support ring 54. The mixture of colloid and liquid metal 150 and the adhesive layer 152 may be filled into the groove 260 of the heat dissipation cover 230. The groove 260 may have various geometric shapes, such as Figure 5 2. As shown in the included illustration E, the illustration E is a bottom view of the heat dissipation cover 230, which has three different patterns of embodiments for the grooves 260. These patterns are only non-limiting examples.

[0075] As mentioned above, Figure 5 The semiconductor package 200 shown includes a mixture of colloid and liquid metal 150, which can be used as a thermally conductive material between one or more semiconductor dies 11, 12, and 13 and a heat dissipation cover 230. In various embodiments (not shown), Figure 5The heat dissipation cover 230 of the semiconductor package 200 includes metal, single crystal diamond, or a combination thereof, and may alternatively have a thermally conductive material such as a thermal interface material 50 (which may be indium, silver, copper, indium alloy, silver alloy, copper alloy, or solder material in a non-limiting example) between the one or more semiconductor dies 11, 12, and 13 and the heat dissipation cover 230, such as with Figure 1 and Figure 2 Explain the above content.

[0076] Figure 1 、 Figure 2 ,and Figure 4 The thermoelectric coolers 30 of the semiconductor packages 10 and 100 provide active cooling effects through the Peltier effect implemented by the thermoelectric coolers 30. Figure 1 and Figure 4 Thermoelectric cooler power supply 44 and connection line 45 (or other power supply connection if the power supply is integrated into one or more semiconductor dies 11, 12, and 13) are shown to supply power to thermoelectric cooler 30. Figure 5 The heat dissipation cover 230 in the embodiment includes metal, single crystal diamond, or a combination thereof to provide passive heat transfer from one or more semiconductor dies 11, 12, and 13 to the cold plate or heat sink 46. Figure 5 The heat dissipation cover 230 of the semiconductor package 200 is not connected to a power source. Instead, the heat dissipation cover 230 has a sufficiently high thermal conductivity to provide passive heat transfer from the one or more semiconductor dies 11, 12, and 13 to the cold plate or heat sink 46. In some non-limiting examples, the thickness of the heat dissipation cover 230 may be from about 0.5 mm to about 3.0 mm, although thicknesses outside this range may also be implemented.

[0077] In some embodiments, Figure 5 The heat dissipation cover 230 of the semiconductor package 200 includes a first layer 270 of a first material located proximate to one or more semiconductor dies 11, 12, and 13, and a second layer 272 of a second material located distal to the one or more semiconductor dies 11, 12, and 13 and in contact with a cold plate or heat sink 46 (or in contact with a thermal interface material 49 coating the cold plate or heat sink 46). The first material of the first layer 270 and the second material of the second layer 272 are different materials, and the thermal conductivity of the first material is higher than that of the second material. In summary, the thermal conductivity of the first layer 270 is greater than that of the second layer 272, at least when the thicknesses of the first and second layers are the same. In some non-limiting exemplary embodiments, the first layer 270 is a single crystal diamond layer located proximate to the one or more semiconductor dies 11, 12, and 13, while the second layer 272 is a metal layer located distal to the one or more semiconductor layers 11, 12, and 13.

[0078] Matching Figures 1 to 5The various exemplary embodiments described above include a semiconductor package 10, 100, or 200 including an interposer 14 having a first major surface 16 and a second major surface 18, with the first major surface 16 opposing the second major surface 18; one or more semiconductor dies 11, 12, and 13 disposed on the first major surface 16 of the interposer 14 and electrically connected to the second major surface 18 of the interposer 14 via electrical vias 20 extending through the interposer 14; a heat spreader, such as a thermoelectric cooler 30 or a heat spreader 230, disposed on the one or more semiconductor dies 11, 12, and 13; and a thermally conductive material, such as a thermal interface material 50 or a mixture 150, disposed between the one or more semiconductor dies 11, 12, and 13 and the heat spreader, such as the thermoelectric cooler 30 or the heat spreader 230. The thermally conductive material, such as the thermal interface material 50 or the mixture 150, thermally couples the one or more semiconductor dies 11, 12, and 13 to the heat spreader, such as the thermoelectric cooler 30 or the heat spreader 230.

[0079] Figure 6 A method of assembling semiconductor package 10, 100, or 200 is shown. In step 300, one or more semiconductor dies 11, 12, and 13 are embedded on first major surface 16 of interposer 14. By way of non-limiting example, this can be accomplished by placing bonding bumps 22 on one or more semiconductor dies 11, 12, and 13 or on first major surface 16 of interposer 14, and bonding one or more semiconductor dies 11, 12, and 13 to first major surface 16 of interposer 14 via bonding bumps 22, such as by applying heat to partially melt bonding bumps 22 (or solder coating on bonding bumps 22). An underfill material 26 can then be applied by capillary force or similar means to fill the spaces between bonding bumps 22. A curing step can optionally be performed at one or more stages of step 300. In step 302, a support ring 54 is positioned on first major surface 16 of interposer 14 to surround one or more semiconductor dies 11, 12, and 13. In step 304, a molding material 56 is molded around the support ring 54 and the one or more semiconductor dies 11, 12, and 13. It should be noted that steps 300, 302, and 304 may generally be performed in various orders.

[0080] Step 306 is to place a thermally conductive material such as thermal interface material 50 or mixture 150 on one or more semiconductor dies 11, 12, and 13. Figure 4 and Figure 5In the case of semiconductor packages 100 and 200, the thermally conductive material is a mixture 150 of colloid and liquid metal, and step 306 may also appropriately place an adhesive layer 152 near the area of ​​the mixture 150. It is noteworthy that assembly is typically performed at room temperature, and the liquid metal during assembly may be solid (for example, the melting point of gallium is approximately 30°C, which is higher than room temperature). Therefore, the adhesive layer 152 may be placed before or after the placement of the mixture 150 of colloid and liquid metal. In step 308, a heat dissipation cover, such as a thermoelectric cooler 30 or a heat dissipation cover 230, is placed on the thermally conductive material, such as the thermal interface material 50 or the mixture 150. In other embodiments, step 308 may be performed before step 306, which involves injecting a thermally conductive material into the gap between one or more semiconductor dies 11, 12, and 13 and the heat dissipation cover, such as the thermoelectric cooler 30 or the heat dissipation cover 230. In step 310, a cold plate or heat sink 46 is placed on the heat dissipation cover, such as the thermoelectric cooler 30 or the heat dissipation cover 230. Thermal interface material 49 may bond the cold plate or heat sink 46 to a heat dissipation cover such as thermoelectric cooler 30 or heat dissipation cover 230 sufficient to maintain the former on the latter.

[0081] In some workflows, step 310 may be considered the completion of fabricating semiconductor package 10, 100, or 200. To configure semiconductor package 10, 100, or 200 in an electronic device or system, step 312 involves mounting semiconductor package 10, 100, or 200 on a printed circuit board or other substrate (not shown). This may require placing bonding bumps 24 on second major surface 18 of interposer 14 (or alternatively, placing bonding bumps 24 on second major surface 18 of interposer 14 at an earlier stage of semiconductor package assembly) to bond semiconductor package 10, 100, or 200 to the printed circuit board or other substrate. This also allows for electrical connection of one or more semiconductor dies 11, 12, and 13 to circuitry on the printed circuit board or other substrate via the electrical connections provided by interposer 14 and bonding bumps 22 and 24.

[0082] Step 312 may optionally employ an external retaining mechanism (not shown), such as a clamping mechanism, to further secure the semiconductor package 10, 100, or 200 to the printed circuit board or other substrate. For example, the clamping mechanism may clamp down onto the cold plate or heat sink 46 to press the semiconductor package 10, 100, or 200 down onto the printed circuit board or other substrate. In some other embodiments, it is contemplated that the cold plate or heat sink 46 is a component of the clamping mechanism, and thus the clamping mechanism includes the cold plate or heat sink 46, and the clamping mechanism presses the cold plate or heat sink 46 against a heat dissipation cover, such as the thermoelectric cooler 30 or heat dissipation cover 230, of the semiconductor package 10, 100, or 200 via the cold plate or heat sink 46.

[0083] Should understand the collocation Figure 6The semiconductor package assembly described herein is intended to be a non-limiting example, and the semiconductor package 10 , 100 , or 200 may be assembled in other ways and / or using assembly steps in a different order.

[0084] The following describes some other embodiments.

[0085] In a non-limiting exemplary embodiment, a semiconductor package includes: an interposer having a first major surface and a second major surface, the first major surface opposing the second major surface; one or more semiconductor dies disposed on the first major surface of the interposer and electrically connected to the second major surface of the interposer via a plurality of electrical vias extending through the interposer; a heat sink disposed on the semiconductor dies; and a thermally conductive material disposed between the semiconductor dies and the heat sink, thermally coupling the semiconductor dies to the heat sink. The heat sink may include a thermoelectric cooler, a metal, single crystal diamond, or a combination thereof.

[0086] In some embodiments, the heat dissipating cover includes a thermoelectric cooler.

[0087] In some embodiments, the thermally conductive material includes indium, silver, copper, an indium alloy, a silver alloy, a copper alloy, or a solder material.

[0088] In some embodiments, the semiconductor package further includes a metal coating on a surface of the thermoelectric cooler that contacts the thermally conductive material.

[0089] In some embodiments, the semiconductor package further includes a support ring located on the first major surface of the interposer and surrounding the semiconductor die; and a molding material molded around the support ring and the semiconductor die. The thermoelectric cooler has a plurality of grooves formed in its surface, and the thermally conductive material is filled in the grooves of the thermoelectric cooler.

[0090] In some embodiments, the thermally conductive material includes a mixture of colloid and liquid metal.

[0091] In some embodiments, the liquid metal comprises gallium and the colloid comprises a polymer.

[0092] In some embodiments, the semiconductor package further includes a support ring located on the first major surface of the interposer and surrounding the semiconductor die; a molding material molded around the support ring and the semiconductor die; and an adhesive layer located around the periphery of the thermoelectric cooler and comprising a mixture of colloid and liquid metal, the adhesive layer bonding the thermoelectric cooler to the molding material. The surface of the thermoelectric cooler has a plurality of grooves, and the adhesive layer fills the grooves.

[0093] In some embodiments, the heat dissipation cover comprises metal, single crystal diamond, or a combination thereof.

[0094] In some embodiments, the heat dissipation cap includes a single crystal diamond layer adjacent to the semiconductor die and a metal layer distal to the semiconductor die.

[0095] In some embodiments, the heat dissipation cover includes a first layer of a first material close to the semiconductor die and a second layer of a second material away from the semiconductor die, wherein the first material is different from the second material and has a higher thermal conductivity than the second material.

[0096] In some embodiments, the thermally conductive material includes a mixture of colloid and liquid metal.

[0097] In some embodiments, the semiconductor package further includes a support ring located on the first major surface of the interposer and surrounding the semiconductor die; a molding material molded around the support ring and the semiconductor die; and an adhesive layer located on a periphery of the thermoelectric cooler and containing a mixture of colloid and liquid metal, wherein the adhesive layer bonds the thermoelectric cooler to the molding material.

[0098] In a non-limiting exemplary embodiment, a method for assembling a semiconductor package includes embedding one or more semiconductor dies on a first major surface of an interposer, the semiconductor dies being electrically connected to a second major surface of the interposer via a plurality of electrical vias passing through the interposer, with the first major surface and the second major surface being opposite to each other; placing a support ring on the first major surface of the interposer, the support ring surrounding the semiconductor dies; molding a molding material around the support ring and the semiconductor dies; placing a thermally conductive material on the semiconductor dies; and placing a heat dissipation cover on the thermally conductive material.

[0099] In some embodiments, the heat dissipation cover includes a thermoelectric cooler having a plurality of grooves on a surface thereof, and the grooves are filled with a thermal conductive material.

[0100] In some embodiments, the thermally conductive material comprises a mixture of colloid and liquid metal, and the method further comprises: placing an adhesive layer around the mixture of colloid and liquid metal, and the adhesive layer filling a groove on a surface of the thermoelectric cooler contacting the adhesive layer and the mixture of colloid and liquid metal.

[0101] In some embodiments, the heat dissipation cover includes a single crystal diamond layer close to the semiconductor grains and a metal layer away from the semiconductor grains, and the thermal conductive material includes a mixture of colloid and liquid metal.

[0102] In a non-limiting exemplary embodiment, a semiconductor package includes: an interposer having a first major surface and a second major surface, the first major surface opposing the second major surface; one or more semiconductor dies disposed on the first major surface of the interposer and electrically connected to the second major surface of the interposer via a plurality of electrical vias extending through the interposer; a support ring disposed on the first major surface of the interposer and surrounding the semiconductor dies; a molding material molded around the support ring and the semiconductor dies; a thermally conductive material disposed on the semiconductor dies; and a heat dissipation cover disposed on the thermally conductive material. The heat dissipation cover includes a thermoelectric cooler and / or the thermally conductive material includes a mixture of a colloid and a liquid metal.

[0103] In some embodiments, the heat dissipating cover includes a thermoelectric cooler.

[0104] In some embodiments, the thermally conductive material includes a mixture of colloid and liquid metal, and the semiconductor package further includes an adhesive layer surrounding the mixture of colloid and liquid metal and sealing the mixture of colloid and liquid metal in a sealed space.

[0105] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, comprising: an interposer having a first major surface and a second major surface, wherein the first major surface is opposite to the second major surface; One or more semiconductor dies located on the first major surface of the interposer and electrically connected to the second major surface of the interposer via a plurality of electrical vias passing through the interposer; a heat dissipation cover, located on the semiconductor die; as well as a heat conductive material located between the semiconductor die and the heat dissipation cover, and the heat conductive material thermally couples the semiconductor die and the heat dissipation cover; The heat dissipation cover includes a thermoelectric cooler, a metal, a single crystal diamond, or a combination thereof. 2 . The semiconductor package of claim 1 , wherein the heat dissipation cover comprises the thermoelectric cooler. 3 . The semiconductor package as claimed in claim 2 , wherein the thermally conductive material comprises indium, silver, copper, an indium alloy, a silver alloy, a copper alloy, or a solder material.

4. The semiconductor package according to claim 3, further comprising: A metal coating is located on the surface of the thermoelectric cooler contacting the heat conductive material.

5. A method for assembling a semiconductor package, comprising: Embedding one or more semiconductor dies on a first major surface of an interposer, wherein the semiconductor dies are electrically connected to a second major surface of the interposer via a plurality of electrical vias passing through the interposer, and the first major surface is opposite to the second major surface; placing a support ring on the first major surface of the interposer, with the support ring surrounding the semiconductor die; forming a molding material around the support ring and the semiconductor die; placing a thermally conductive material on the semiconductor die; and A heat dissipation cover is placed on the thermally conductive material. 6 . The method for assembling a semiconductor package as claimed in claim 5 , wherein the heat dissipation cover comprises a thermoelectric cooler having a plurality of grooves on a surface thereof, and the thermal conductive material is filled into the plurality of grooves.

7. The method for assembling a semiconductor package as claimed in claim 6 , wherein the thermally conductive material comprises a mixture of a colloid and a liquid metal, and the method further comprises: placing an adhesive layer to surround the mixture of the colloid and the liquid metal; The adhesive layer fills the plurality of grooves on the surface of the thermoelectric cooler contacting the adhesive layer and the mixture of the colloid and the liquid metal.

8. A semiconductor package comprising: an interposer having a first major surface and a second major surface, wherein the first major surface is opposite to the second major surface; One or more semiconductor dies are located on the first major surface of the interposer and are electrically connected to the second major surface of the interposer via a plurality of electrical vias passing through the interposer; a support ring located on the first major surface of the interposer and surrounding the semiconductor die; a molding material formed around the support ring and the semiconductor die; a thermally conductive material located on the semiconductor die; and a heat dissipation cover, located on the thermally conductive material, The heat dissipation cover includes a thermoelectric cooler, and / or the heat conductive material includes a mixture of a colloid and a liquid metal. 9 . The semiconductor package of claim 8 , wherein the heat dissipation cover comprises the thermoelectric cooler.

10. The semiconductor package as claimed in claim 8, wherein the thermally conductive material comprises the mixture of the colloid and the liquid metal, and the semiconductor package further comprises: An adhesive layer surrounds the mixture of the colloid and the liquid metal and seals the mixture of the colloid and the liquid metal in a sealed space.

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