Timing type valley current protection circuit
Through the design of a timing-type valley current protection circuit and the combination of a storage circuit and a comparison circuit, the offset voltage of the comparator is eliminated, the accuracy of the valley current limiting is improved, the cost and power consumption of the chip are reduced, and the problems of low accuracy and high power consumption in the existing technology are solved.
Patent Information
- Application Number
- CN202510943258.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-09
- Publication Date
- 2025-09-12
AI Technical Summary
The existing valley current protection circuit is triggered only after the overcurrent protection function is triggered, resulting in low accuracy and requiring a large area and current, which increases the cost and power consumption of the chip.
A timing-type valley current protection circuit is used to charge and discharge the energy storage unit through the energy storage circuit. The comparison circuit outputs a comparison signal based on the charge and discharge voltage and threshold voltage of the energy storage unit. The logic circuit outputs a valley current limiting signal based on the overcurrent trigger signal and the comparison signal, eliminating the offset voltage of the comparator, improving accuracy and reducing chip cost and power consumption.
This improves the accuracy of the valley current limit, reduces chip cost and power consumption, and avoids the need for a three-stage comparator.
Smart Images
Figure CN120638265A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a timing type valley current protection circuit. Background Art
[0002] With the continuous development of the integrated circuit industry, chips are required to work safely under various extreme working conditions. Therefore, internal protection circuits of the chip are indispensable, such as undervoltage protection, overvoltage protection, overcurrent protection, valley current protection and other protection circuits.
[0003] Currently, valley current protection is typically triggered only after overcurrent protection. The valley current protection circuit samples the voltage at the SW point. When the sampled voltage is less than the reference voltage, indicating that the valley current is less than the target current, the upper power tube is turned on and the lower power tube is turned off. Typically, to obtain a more accurate valley current point, valley current protection circuits use a three-stage comparator structure to reduce comparator delay and comparator offset voltage. However, this structure requires a larger area and current, increasing chip cost and power consumption. Summary of the Invention
[0004] The present invention provides a timing type valley current protection circuit, which can improve the accuracy of valley current points and reduce chip cost and power consumption.
[0005] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a timing-type valley current protection circuit, comprising: An energy storage circuit, comprising an energy storage unit, the energy storage circuit being connected to a first voltage, a second voltage, and a control signal, and being configured to charge and discharge the energy storage unit according to the control signal; A comparison circuit is connected to the energy storage circuit and is used to output a comparison signal according to the charge and discharge voltage of the energy storage unit and the threshold voltage; The logic circuit is connected to the comparison circuit and receives the overcurrent trigger signal. It is used to output a valley current limiting signal according to the overcurrent trigger signal and the comparison signal, and determine whether to trigger the valley current limiting function according to the overcurrent trigger signal and the valley current limiting signal. The overcurrent trigger signal is used to indicate whether the overcurrent protection function is triggered.
[0006] In a possible implementation, the energy storage circuit further includes a first switching circuit and a second switching circuit; Wherein, the first switch circuit is connected to the control signal, the first end is connected to the first voltage, the second end is connected to one end of the energy storage unit, and the third end and the fourth end are respectively connected to the comparison circuit; a second switch circuit, connected to the control signal, with a first end grounded, a second end connected to the second voltage, and a third end connected to the other end of the energy storage unit; The energy storage circuit is specifically used to control the on and off of the first switch circuit and the second switch circuit according to the control signal to charge and discharge the energy storage unit.
[0007] In one possible implementation, the control signal includes a first signal, a second signal, and a third signal, wherein the first signal and the second signal are opposite signals, and the third signal is obtained according to the second signal and the overcurrent trigger signal; The first switch circuit includes: a first switch and a second switch, and the second switch circuit includes a third switch, a fourth switch and a first resistor; The control end of the first switch is connected to the third signal, the first end is connected to the first voltage, the second end is connected to the second signal, and the third end is connected to one end of the energy storage unit; The control end of the second switch is connected to the second signal, the first end is connected to one end of the energy storage unit and the first end of the comparison circuit, the second end is connected to the first signal, and the third end is connected to the second end of the comparison circuit; The control end of the third switch is connected to the first signal, the first end is connected to one end of the first resistor, the second end is connected to the second signal, and the third end is connected to the other end of the energy storage unit; The control end of the fourth switch is connected to the second signal, the first end is grounded, the second end is connected to the first signal, and the third end is connected to the other end of the energy storage unit; The other end of the first resistor is connected to the second voltage.
[0008] In one possible implementation, the energy storage unit includes a capacitor and an energy storage circuit, specifically configured to: When the first signal is at a high level and the overcurrent trigger signal is at a low level, the first switch and the third switch are controlled to be turned off, and the second switch and the fourth switch are controlled to be turned on, so as to charge the capacitor. The charging voltage is the threshold voltage, and the overcurrent trigger signal is at a low level, indicating that the overcurrent protection function is not triggered; When the first signal changes from a high level to a low level and the overcurrent trigger signal is a low level, the third switch is controlled to be turned on, and the first switch, the second switch and the fourth switch are controlled to be turned off, and the voltage on the upper plate of the capacitor is the sum of the threshold voltage and the second voltage; When the first signal is at a low level and the overcurrent trigger signal changes from a low level to a high level, the first switch and the third switch are controlled to be turned on, and the second switch and the fourth switch are controlled to be turned off to discharge the capacitor. The overcurrent trigger signal is at a high level, indicating that the overcurrent protection function is triggered.
[0009] In one possible implementation, the comparison circuit includes a first current source, a second current source, a first NMOS, and a second NMOS; The first end of the first current source is connected to the power supply voltage, and the second end is connected to the drain of the first NMOS, the energy storage circuit, and the gate of the second NMOS; The gate of the first NMOS is connected to the energy storage circuit, and the source is grounded; A first end of the second current source is connected to the power supply voltage, and a second end is connected to the drain of the second NMOS and the logic circuit; The source of the second NMOS is grounded; Comparison circuit, specifically used for: When the voltage of the upper plate of the capacitor is greater than the threshold voltage, the output comparison signal is high level; When the capacitor upper plate voltage is less than the threshold voltage, the output comparison signal is low level.
[0010] In one possible implementation, the logic circuit includes: a NAND gate, a first inverter, and a second inverter; The first input terminal of the NAND gate is connected to the comparison signal, the second input terminal is connected to the overcurrent trigger signal, and the output terminal is connected to one end of the first inverter; The other end of the first inverter is connected to one end of the second inverter; The other end of the second inverter is used to output a valley current limiting signal.
[0011] In one possible implementation, the logic circuit is specifically configured to: When the overcurrent trigger signal is low, it indicates that the overcurrent protection function is not triggered. When the comparison signal is low or high, the output valley current limit signal is high, controlling the normal operation of the upper and lower tubes. When the overcurrent trigger signal is high, it indicates that the overcurrent protection function is triggered. When the comparison signal is high, the output valley current limit signal is low, and the valley current protection circuit starts to work, continuing to keep the upper tube off and the lower tube on. When the overcurrent trigger signal is high, it indicates that the overcurrent protection function is triggered. When the comparison signal is low, the output valley current limiting signal is high, triggering the valley current limiting function, controlling the upper tube to turn on and the lower tube to turn off.
[0012] In one possible implementation, the control signal includes a first signal, a second signal, and a third signal, wherein the first signal and the second signal are opposite signals, and the third signal is obtained according to the first signal and the overcurrent trigger signal; The first switch circuit includes: a first switch and a second switch, and the second switch circuit includes a third switch, a fourth switch and a first resistor; The control end of the first switch is connected to the third signal, the first end is connected to the first voltage, the second end is connected to the second signal, and the third end is connected to one end of the energy storage unit; The control end of the second switch receives the first signal, the first end is connected to one end of the energy storage unit and the first end of the comparison circuit, the second end receives the second signal, and the third end is connected to the second end of the comparison circuit; The control end of the third switch is connected to the first signal, the first end is connected to one end of the first resistor, the second end is connected to the second signal, and the third end is connected to the other end of the energy storage unit; The control end of the fourth switch is connected to the second signal, the first end is grounded, the second end is connected to the first signal, and the third end is connected to the other end of the energy storage unit; The other end of the first resistor is connected to the second voltage.
[0013] In one possible implementation, the energy storage circuit is specifically configured to: When the first signal is at a low level and the overcurrent trigger signal is at a low level, the first switch and the fourth switch are controlled to be turned off, and the second switch and the third switch are controlled to be turned on, so as to charge the capacitor, and the upper plate voltage of the capacitor is the threshold voltage; When the first signal changes from a low level to a high level and the overcurrent trigger signal is at a low level, the first switch, the second switch, and the third switch are controlled to be turned off, and the fourth switch is controlled to be turned on, and the voltage on the upper plate of the capacitor is the difference between the threshold voltage and the second voltage; When the first signal is at a high level and the overcurrent trigger signal changes from a low level to a high level, the second switch and the third switch are controlled to be turned off, and the first switch and the fourth switch are controlled to be turned on, so as to charge the capacitor.
[0014] In a possible implementation, the comparison circuit includes: a first current source, a second current source, a first NMOS, a second NMOS, and a third inverter; The first end of the first current source is connected to the power supply voltage, and the second end is connected to the drain of the first NMOS, the energy storage circuit, and the gate of the second NMOS; The gate of the first NMOS is connected to the energy storage circuit, and the source is grounded; A first end of the second current source is connected to the power supply voltage, and a second end is connected to the drain of the second NMOS and one end of the third inverter; The source of the second NMOS is grounded; The other end of the third inverter is connected to the logic circuit; Comparison circuit, specifically used for: When the voltage of the upper plate of the capacitor is greater than the threshold voltage, the output comparison signal is low level; When the capacitor upper plate voltage is less than the threshold voltage, the output comparison signal is high level.
[0015] In a second aspect, the present invention provides a chip, which may include the timing-type valley current protection circuit of the first aspect and any possible implementation thereof.
[0016] The present invention provides a timing-type valley current protection circuit. The energy storage circuit charges and discharges the energy storage unit according to a control signal. The comparison circuit outputs a comparison signal based on the charge and discharge voltages and threshold voltage of the energy storage unit. The logic circuit outputs a valley current limiting signal based on the overcurrent trigger signal and the comparison signal. The logic circuit then determines whether to trigger the valley current limiting function based on the overcurrent trigger signal and the valley current limiting signal. Thus, by comparing the charge and discharge voltages and threshold voltages of the energy storage unit and outputting a valley current limiting signal based on the comparison signal and the overcurrent trigger signal, the triggering of valley current limiting is determined. Compared to prior art solutions that determine whether to trigger valley current limiting based on the SW point sampling voltage and the reference voltage, the present invention stores the offset voltage of the comparator in the energy storage unit, eliminating the offset voltage of the comparator and thereby improving the accuracy of the valley current limiting function, i.e., improving the accuracy of the valley current limiting point. Furthermore, by improving accuracy by storing the offset voltage in the energy storage unit, the present invention eliminates the need for a three-stage comparator to improve accuracy. Instead, a one-stage or two-stage comparator with a smaller area can be selected, reducing chip cost and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A circuit principle block diagram of a timing-type valley current protection circuit provided by an embodiment of the present invention; Figure 2 A circuit principle block diagram of another timing-type valley current protection circuit provided by an embodiment of the present invention; Figure 3 A schematic diagram of the relationship between control signals provided by an embodiment of the present invention; Figure 4 A circuit schematic diagram of a timing-type valley current protection circuit provided by an embodiment of the present invention; Figure 5 A circuit schematic diagram of a capacitor discharge circuit provided by an embodiment of the present invention; Figure 6 A circuit timing diagram of a timing-type valley current protection circuit provided by an embodiment of the present invention; Figure 7 A schematic diagram of another control signal relationship provided by an embodiment of the present invention; Figure 8 A circuit schematic diagram of another timing-type valley current protection circuit provided by an embodiment of the present invention; Figure 9 A circuit schematic diagram of a capacitor charging circuit provided by an embodiment of the present invention; Figure 10 This is a circuit timing diagram of another timing-type valley current protection circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0019] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values may be based on additional conditions or values beyond the stated in practice.
[0020] Figure 1 This is a circuit principle block diagram of a timing type valley current protection circuit provided by an embodiment of the present invention. Figure 1 As shown, the timing type valley current protection circuit may include: an energy storage circuit 11 , a comparison circuit 12 and a logic circuit 13 .
[0021] The energy storage circuit 11 includes an energy storage unit 111 . The energy storage circuit 11 is connected to a first voltage VD, a second voltage VR, and a control signal, and is used to charge and discharge the energy storage unit 111 according to the control signal.
[0022] The comparison circuit 12 is connected to the energy storage circuit 11 and is used to output a comparison signal according to the charge and discharge voltage of the energy storage unit 111 and the threshold voltage.
[0023] Logic circuit 13 is connected to comparison circuit 12 and receives an overcurrent trigger signal. It is configured to output a valley current limiting signal based on the overcurrent trigger signal and the comparison signal. Furthermore, based on the overcurrent trigger signal and the valley current limiting signal, it determines whether the valley current limiting function has been triggered. The overcurrent trigger signal indicates whether the overcurrent protection function has been triggered. Once logic circuit 13 determines that the valley current limiting function has been triggered, it can control the upper transistor to turn on and the lower transistor to turn off, indicating that the valley current protection circuit has terminated protection and that subsequent circuits can operate normally.
[0024] In a timing-based valley current protection circuit provided by an embodiment of the present invention, an energy storage circuit charges and discharges an energy storage unit according to a control signal, a comparison circuit outputs a comparison signal based on the charge and discharge voltages and threshold voltage of the energy storage unit, and a logic circuit outputs a valley current limit signal based on an overcurrent trigger signal and the comparison signal. The logic circuit then determines whether to trigger the valley current limit function based on the overcurrent trigger signal and the valley current limit signal. Thus, by comparing the charge and discharge voltages and threshold voltage of the energy storage unit and outputting a valley current limit signal based on the comparison signal and the overcurrent trigger signal, the triggering of valley current limit is determined. Compared to prior art solutions that determine whether to trigger valley current limit based on a sampled voltage at the SW point and a reference voltage, the embodiment of the present invention stores the offset voltage of the comparator in the energy storage unit, eliminating the offset voltage of the comparator and thereby improving the accuracy of the valley current limit function, i.e., improving the accuracy of the valley current limit point. Furthermore, by improving accuracy by storing the offset voltage in the energy storage unit, the embodiment of the present invention eliminates the need for a three-stage comparator to improve accuracy. Instead, a one-stage or two-stage comparator with a smaller area can be selected, reducing chip cost and power consumption.
[0025] Optional, reference Figure 1 , Figure 2 FIG1 is a circuit principle block diagram of another valley current protection circuit provided by an embodiment of the present invention. Figure 2 As shown, the energy storage module 11 may further include: a first switch circuit 112 and a second switch circuit 113 .
[0026] The first switch circuit 112 receives the control signal, has a first terminal connected to the first voltage VD, a second terminal connected to one terminal of the energy storage unit 111 , and a third terminal and a fourth terminal connected to the comparison circuit 12 respectively.
[0027] The second switch circuit 113 receives the control signal, has a first terminal connected to the ground, a second terminal connected to the second voltage VR, and a third terminal connected to the other terminal of the energy storage unit 111 .
[0028] The energy storage circuit 11 is specifically configured to control the on / off of the first switch circuit 112 and the second switch circuit 113 according to a control signal, so as to charge and discharge the energy storage unit 111 .
[0029] Optionally, the energy storage unit 111 may include a capacitor C.
[0030] It can be understood that the first switch circuit 112 mainly determines the voltage of the upper plate of the capacitor C, and the second switch circuit 113 mainly determines the voltage of the lower plate of the capacitor C.
[0031] In one possible implementation, the control signal may include a first signal SEL, a second signal SELB, and a third signal SEL1, wherein the first signal SEL and the second signal SELB are opposite signals, and the third signal SEL1 is obtained according to the second signal SELB and the overcurrent trigger signal OCP-s.
[0032] For example, the relationship between the second signal SELB, the overcurrent trigger signal OCP-s and the third signal SEL1 can be represented by Figure 3 The circuit diagram shown is shown. Figure 3 As shown, the first input terminal of the second NAND gate NAND2 inputs the second signal SELB, the second input terminal inputs the overcurrent trigger signal OCP-s, and the output terminal outputs the third signal SEL1.
[0033] Optional, Figure 4 The circuit principle diagram of a timing type valley current protection circuit provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the first switch circuit 112 may include a first switch TG1 and a second switch TG2 , and the second switch circuit 113 may include a third switch TG3 , a fourth switch TG4 and a first resistor R1 .
[0034] The control end of the first switch TG1 is connected to the third signal SEL1 , the first end is connected to the first voltage VD, the second end is connected to the second signal SELB, and the third end is connected to one end of the energy storage unit 111 .
[0035] The control end of the second switch TG2 receives the second signal SELB, the first end is connected to one end of the energy storage unit 111 and the first end of the comparison circuit 12 , the second end receives the first signal SEL, and the third end is connected to the second end of the comparison circuit 12 .
[0036] The control end of the third switch TG3 receives the first signal SEL, the first end is connected to one end of the first resistor R1 , the second end is connected to the second signal SELB, and the third end is connected to the other end of the energy storage unit 111 .
[0037] The control end of the fourth switch TG4 is connected to the second signal SELB, the first end is grounded, the second end is connected to the first signal SEL, and the third end is connected to the other end of the energy storage unit 111 .
[0038] The other end of the first resistor R1 is connected to the second voltage VR.
[0039] In one possible implementation, the first switch TG1, the second switch TG2, the third switch TG3, and the fourth switch TG4 can be a combination of an NMOS and a PMOS switch, with the on / off state of each switch determined by a signal at a control terminal. The voltage drop across these switches is minimal, reducing the circuit's power supply voltage requirements and minimizing power consumption. Of course, these four switches can also be implemented in other ways, which are not limited here.
[0040] In a specific implementation, the overcurrent trigger signal can be a high level or a low level, respectively used to indicate whether to trigger the overcurrent protection function.
[0041] For example, assuming that the overcurrent trigger signal is at a low level, indicating that the overcurrent protection function is not triggered, and the overcurrent trigger signal is at a high level, indicating that the overcurrent protection function is triggered, that is, the upper tube is controlled to be turned off and the lower tube is controlled to be turned on, then according to the specific structure of the first switching circuit 112 and the second switching circuit 113, the energy storage circuit 11 can be specifically used for: When the first signal SEL is at a high level and the overcurrent trigger signal OCP-s is at a low level, the second signal SELB is at a low level and the third signal SEL1 is at a high level, the first switch TG1 and the third switch TG3 are controlled to be turned off, and the second switch TG2 and the fourth switch TG4 are controlled to be turned on to charge the capacitor C. The upper plate voltage of the capacitor C is the threshold voltage and the lower plate voltage is zero, that is, the charging voltage is the threshold voltage.
[0042] When the first signal SEL changes from a high level to a low level and the overcurrent trigger signal OCP-s is a low level, the second signal SELB is a high level, the third signal SEL1 is a high level, the third switch TG3 is controlled to be turned on, and the first switch TG1, the second switch TG2 and the fourth switch TG4 are controlled to be turned off. At this time, the lower plate voltage of the capacitor C is the second voltage VR. Since the capacitor voltage cannot change suddenly, the upper plate voltage of the capacitor C is the sum of the threshold voltage and the second voltage VR.
[0043] When the first signal SEL is at a low level and the overcurrent trigger signal OCP-s changes from a low level to a high level, the second signal SELB is at a high level and the third signal SEL1 is at a low level, the first switch TG1 and the third switch TG3 are controlled to be turned on, and the second switch TG2 and the fourth switch TG4 are controlled to be turned off, so as to discharge the capacitor C.
[0044] In one possible implementation, Figure 5 The circuit principle diagram of a capacitor discharge circuit provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the capacitor discharge circuit may include: a first PMOS transistor PM1, a second resistor R2, a third current source and a fourth current source.
[0045] The source of the first PMOS transistor PM1 is connected to the power supply voltage Vin, the gate is connected to the overcurrent trigger signal OCP-s, and the drain is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of a third current source and one end of a fourth current source, respectively. The other ends of the third current source and the fourth current source are grounded. Furthermore, the current of the third current source is VOUT / R3, where VOUT is the output voltage and R3 is the third resistor. The current of the fourth current source is Ibias.
[0046] It is understood that when the overcurrent trigger signal OCP-s is at a low level, the overcurrent protection function is not triggered and the first PMOS transistor is turned on. When the first signal SEL is at a low level and the overcurrent trigger signal OCP-s is at a high level, the overcurrent protection function is triggered, the first PMOS transistor is turned off, and the capacitor C can be discharged through the third current source and the fourth current source.
[0047] like Figure 5 As shown, the current ID at point D can be expressed by the following formula (1), and the first voltage VD at point D can be expressed by the following formula (2).
[0048] (1) (2) As can be seen above, ID has a minimum discharge current, Ibias. Even when VOUT is zero, the discharge voltage of capacitor C gradually decreases to the threshold voltage, resulting in the valley current limit. Furthermore, since the valley current is equal to the product of the inductor current's falling slope and the capacitor discharge time, and the inductor current's falling slope is proportional to VOUT while the capacitor discharge time is inversely proportional to VOUT, the two offset each other, resulting in a relatively constant valley current.
[0049] Optionally, in an embodiment of the present invention, if Figure 4 As shown, the comparison circuit 12 may include: a first current source I1 , a second current source I2 , a first NMOS NM1 , and a second NMOS NM2 .
[0050] The first end of the first current source I1 is connected to the power supply voltage, and the second end is connected to the drain of the first NMOS NM1 , the energy storage circuit 11 , and the gate of the second NMOS NM2 .
[0051] The gate of the first NMOS NM1 is connected to the energy storage circuit 11 , and the source is grounded.
[0052] A first end of the second current source I2 is connected to the power supply voltage, and a second end thereof is connected to the drain of the second NMOS NM2 and the logic circuit 13 .
[0053] A source of the second NMOS NM2 is grounded.
[0054] It can be understood that, in the embodiment of the present invention, the threshold voltage may be the turn-on voltage of NM1 or NM2.
[0055] In a specific implementation, the comparison circuit 12 can be specifically used to: when the upper plate voltage of the capacitor C is greater than the threshold voltage, the output comparison signal is a high level; when the upper plate voltage of the capacitor C is less than the threshold voltage, the output comparison signal is a low level.
[0056] As can be seen from the above, the comparison circuit in the embodiment of the present invention adopts a one-level comparison structure, which reduces the cost and power consumption of the chip.
[0057] Optionally, in an embodiment of the present invention, if Figure 4 As shown, the logic circuit 13 may include: a NAND gate NAND1 , a first inverter INV1 , and a second inverter INV2 .
[0058] The first input terminal of the NAND gate NAND1 is connected to the comparison signal, the second input terminal is connected to the overcurrent trigger signal OCP-s, and the output terminal is connected to one terminal of the first inverter INV1.
[0059] The other end of the first inverter INV1 is connected to one end of the second inverter INV2.
[0060] The other end of the second inverter INV2 is used to output a valley current limiting signal VALLY.
[0061] In a specific implementation, the valley current protection function is triggered only after the overcurrent protection function is triggered. The logic circuit 13 can be specifically used to: When the overcurrent trigger signal OCP-s is low, indicating that the overcurrent protection function is not triggered, and the comparison signal is low or high, the output valley current limiting signal is high, indicating that the overcurrent protection function is not triggered and the valley current protection function is not triggered, and the upper and lower tubes can be controlled to work normally.
[0062] When the overcurrent trigger signal OCP-s is high, it indicates that the overcurrent protection function is triggered, controlling the upper tube to shut down and the lower tube to conduct. When the comparison signal is high, the output valley current limit signal is low, and the valley current protection circuit starts to operate, requiring the upper tube to continue to be shut down and the lower tube to be conducted.
[0063] When the overcurrent trigger signal OCP-s is high, it indicates that the overcurrent protection function is triggered, controlling the upper tube to shut down and the lower tube to conduct. When the comparison signal is low, the output valley current limit signal is high, triggering the valley current limit function. After that, the upper tube can be turned on and the lower tube can be turned off.
[0064] Optionally, in an embodiment of the present invention, two delay units are further provided at the second input end of the NAND gate NAND1. After the overcurrent trigger signal passes through the delay unit, the overcurrent trigger delay signal OCP-s-delay is input to the NAND gate NAND1.
[0065] By setting a delay unit, false triggering of valley current protection can be avoided.
[0066] It is worth noting that in the embodiment of the present invention, in the overcurrent protection circuit, when the current reaches the upper threshold, an overcurrent signal OCP pulse signal can be output. The overcurrent signal OCP passes through the RS trigger and outputs the overcurrent trigger signal OCP-s.
[0067] Figure 6 A timing diagram of a timing type valley current protection circuit provided by an embodiment of the present invention, combined with Figure 4 and Figure 5 ,like Figure 6 As shown in FIG, the circuit principle of the timing type valley current protection circuit is: When SEL = 1 and OCP-s = 0, the overcurrent protection function is not triggered. SELB = 0, SEL1 = 1, TG1 and TG3 are off, and TG2 and TG4 are on, charging capacitor C. The charging voltage of capacitor C is the threshold voltage VTH. The comparison signal output by the comparator circuit is low level 0, OCP-s-delay is 0, and the valley current limit signal VALLY = 1 output by the logic circuit. OCP-s-delay = 0, VALLY = 1 indicates that the overcurrent protection function and the valley current protection function are not triggered, and the high-side and low-side transistors can operate normally.
[0068] When SEL = 0 and OCP-s = 0, the overcurrent protection function is not triggered. SELB = 1, SEL1 = 1, TG3 is on, TG1, TG2, and TG4 are off, and the voltage on the lower plate of capacitor C is the second voltage VR. The voltage on the upper plate of capacitor C = VTH + VR. The upper plate voltage is greater than the threshold voltage VTH, and the output comparison signal is a high level 1. OCP-s-delay is 0, and the logic circuit outputs the valley current limit signal VALLY = 1. OCP-s-delay = 0, VALLY = 1, indicating that the overcurrent protection function and the valley current protection function are not triggered, and the upper and lower tubes can be controlled to operate normally.
[0069] When SEL = 0 and OCP-s = 1, the overcurrent protection function is triggered, shutting down the upper transistor and turning on the lower transistor. When SELB = 1 and SEL1 = 0, TG1 and TG3 are turned on, while TG2 and TG4 are turned off, to discharge capacitor C. When the voltage on the upper side of capacitor C exceeds the threshold voltage VTH, the output comparison signal is high. When OCP-s-delay is 1, the logic circuit outputs the valley current limit signal VALLY = 0. When OCP-s-delay = 1 and VALLY = 0, the valley current protection circuit activates, requiring the upper transistor to remain off and the lower transistor on. When the voltage on the upper side of capacitor C discharges to VTH, the output comparison signal is low. When OCP-s-delay is 1, the logic circuit outputs the valley current limit signal VALLY = 1. When OCP-s-delay = 1 and VALLY = 1, the valley current limit function is triggered. After this, the upper transistor can be turned on and the lower transistor can be turned off.
[0070] In another possible implementation, the control signal may include a first signal SEL, a second signal SELB, and a third signal SEL1, wherein the first signal SEL and the second signal SELB are opposite signals, and the third signal SEL1 is obtained according to the first signal SEL and the overcurrent trigger signal OCP-s.
[0071] For example, the relationship between the first signal SEL, the overcurrent trigger signal OCP-s and the third signal SEL1 can be represented by Figure 7 The circuit diagram shown is shown. Figure 7 As shown, the first input terminal of the third NAND gate NAND3 inputs the first signal SEL, the second input terminal inputs the overcurrent trigger signal OCP-s, and the output terminal outputs the third signal SEL1.
[0072] Optional, Figure 8 This is a circuit diagram of another timing type valley current protection circuit provided by an embodiment of the present invention. Figure 8 As shown, the first switch circuit 112 may include a first switch TG1 and a second switch TG2 , and the second switch circuit 113 may include a third switch TG3 , a fourth switch TG4 and a first resistor R1 .
[0073] The control end of the first switch TG1 is connected to the third signal SEL1 , the first end is connected to the first voltage VD, the second end is connected to the second signal SELB, and the third end is connected to one end of the energy storage unit 111 .
[0074] The control end of the second switch TG2 receives the first signal SEL, the first end is connected to one end of the energy storage unit 111 and the first end of the comparison circuit 12 , the second end receives the second signal SELB, and the third end is connected to the second end of the comparison circuit 12 .
[0075] The control end of the third switch TG3 receives the first signal SEL, the first end is connected to one end of the first resistor R1 , the second end is connected to the second signal SELB, and the third end is connected to the other end of the energy storage unit 111 .
[0076] The control end of the fourth switch TG4 is connected to the second signal SELB, the first end is grounded, the second end is connected to the first signal SEL, and the third end is connected to the other end of the energy storage unit 111 .
[0077] The other end of the first resistor R1 is connected to the second voltage VR.
[0078] In a specific implementation, assuming that the overcurrent trigger signal is at a low level, indicating that the overcurrent protection function is not triggered, and the overcurrent trigger signal is at a high level, indicating that the overcurrent protection function is triggered, the energy storage circuit 11 can be specifically used to: When the first signal SEL is at a low level and the overcurrent trigger signal OCP-s is at a low level, the second signal SELB is at a high level, and the third signal SEL1 is at a high level, the first switch TG1 and the fourth switch TG4 are controlled to be turned off, and the second switch TG2 and the third switch TG3 are controlled to be turned on, so as to charge the capacitor C. The upper plate voltage of the capacitor C is the threshold voltage, and the lower plate voltage is the second voltage VR.
[0079] When the first signal SEL changes from a low level to a high level and the overcurrent trigger signal OCP-s is a low level, the second signal SELB is a low level and the third signal SEL1 is a high level, the first switch TG1, the second switch TG2 and the third switch TG3 are controlled to be turned off and the fourth switch TG4 is controlled to be turned on. At this time, the lower plate of the capacitor C is grounded. Since the capacitor voltage cannot change suddenly, the upper plate voltage of the capacitor C is the difference between the threshold voltage and the second voltage VR.
[0080] When the first signal SEL is at a high level and the overcurrent trigger signal OCP-s changes from a low level to a high level, the second signal SELB is at a low level and the third signal SEL1 is at a low level, the second switch TG2 and the third switch TG3 are controlled to be turned off, and the first switch TG1 and the fourth switch TG4 are controlled to be turned on, so as to charge the capacitor C.
[0081] In one possible implementation, Figure 9 The circuit principle diagram of a capacitor charging circuit provided by an embodiment of the present invention is shown in FIG. Figure 9 As shown, the capacitor charging circuit may include: a third NMOS transistor NM3, a second resistor R2, a third current source and a fourth current source.
[0082] One end of the third current source and one end of the fourth current source are respectively connected to the power supply voltage Vin. The other ends of the third current source and the other ends of the fourth current source are connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the drain of the third NMOS transistor NM3. The gate of the third NMOS transistor NM3 is connected to the overcurrent trigger inverted signal OCP_B-s, and the source is grounded. The overcurrent trigger inverted signal OCP_B-s is the opposite of the overcurrent trigger signal OCP-s. The current of the third current source is VOUT / R3, where VOUT is the output voltage and R3 is the third resistor. The current of the fourth current source is Ibias.
[0083] It can be understood that when the overcurrent trigger signal OCP-s is low, the overcurrent protection function is not triggered, the overcurrent trigger inverting signal OCP_B-s is high, and the third NMOS transistor is turned on. When the first signal SEL is high and the overcurrent trigger signal OCP-s is high, the overcurrent protection function is triggered, the overcurrent trigger inverting signal OCP_B-s is low, the third NMOS transistor is turned off, and the power supply voltage Vin charges the capacitor C through the third current source and the fourth current source.
[0084] Optionally, in an embodiment of the present invention, if Figure 8 As shown, the comparison circuit 12 may include: a first current source I1 , a second current source I2 , a first NMOS NM1 , a second NMOS NM2 , and a third inverter INV3 .
[0085] The first end of the first current source I1 is connected to the power supply voltage, and the second end is connected to the drain of the first NMOS NM1 , the energy storage circuit 11 , and the gate of the second NMOS NM2 .
[0086] The gate of the first NMOS NM1 is connected to the energy storage circuit 11 , and the source is grounded.
[0087] A first end of the second current source I2 is connected to the power supply voltage, and a second end thereof is connected to the drain of the second NMOS NM2 and one end of the third inverter INV3 .
[0088] The source of the second NMOS NM2 is connected to .
[0089] The other end of the third inverter INV3 is connected to the logic circuit 13 .
[0090] In a specific implementation, the comparison circuit 12 can be specifically used to: when the upper plate voltage of the capacitor C is greater than the threshold voltage, the output comparison signal is a low level; when the upper plate voltage of the capacitor C is less than the threshold voltage, the output comparison signal is a high level.
[0091] Optional, such as Figure 8 As shown, the structure of the logic circuit 13 is the same as Figure 4The structure of the logic circuit is the same, and detailed description can refer to the above embodiment, which will not be repeated here.
[0092] Figure 10 A circuit timing diagram of another timing type valley current protection circuit provided by an embodiment of the present invention, combined with Figure 8 and Figure 9 ,like Figure 10 As shown in FIG, the circuit principle of the timing type valley current protection circuit is: When SEL = 0 and OCP-s = 0, the overcurrent protection function is not triggered. SELB = 1, SEL1 = 1, TG1 and TG4 are off, and TG2 and TG3 are on, charging capacitor C. The upper plate voltage of capacitor C is the threshold voltage, and the lower plate voltage is the second voltage VR. The comparison signal output by the comparator circuit is high, OCP-s-delay is 0, and the valley current limit signal VALLY = 1 output by the logic circuit. OCP-s-delay = 0, VALLY = 1 indicates that the overcurrent protection function and the valley current protection function are not triggered, and the upper and lower tubes can be controlled to operate normally.
[0093] When SEL = 1 and OCP-s = 0, the overcurrent protection function is not triggered. SELB = 0, SEL1 = 1, TG4 is on, TG1, TG2, and TG3 are off, the lower plate of capacitor C is grounded, and the upper plate voltage of capacitor C = VTH - VR. The upper plate voltage is less than the threshold voltage VTH, and the output comparison signal is high. OCP-s-delay is 0, and the logic circuit outputs the valley current limit signal VALLY = 1. OCP-s-delay = 0, VALLY = 1, indicating that the overcurrent protection function and the valley current protection function are not triggered, and the upper and lower tubes can operate normally.
[0094] When SEL = 1 and OCP-s = 1, the overcurrent protection function is triggered, shutting down the upper transistor and turning on the lower transistor. SELB = 0, SEL1 = 0, TG1 and TG4 are turned on, and TG2 and TG3 are turned off to charge capacitor C. When the voltage on the upper side of capacitor C is less than the threshold voltage VTH, the output comparison signal is high. When OCP-s-delay is 1, the logic circuit outputs the valley current limit signal VALLY = 0. When OCP-s-delay = 1 and VALLY = 0, the valley current protection circuit activates, requiring the upper transistor to remain off and the lower transistor to remain on. When the voltage on the upper side of capacitor C reaches VTH, the output comparison signal is low. When OCP-s-delay is 1, the logic circuit outputs the valley current limit signal VALLY = 1. OCP-s-delay = 1 and VALLY = 1 indicates that the valley current limit function has been triggered. After this, the upper transistor can be turned on and the lower transistor can be turned off.
[0095] The embodiment of the present invention further provides a chip, which may include: Figures 1-10 Any timing type valley current protection circuit in.
[0096] In a possible implementation, the chip may be a power management chip. Of course, it may also be other chips including protection circuits such as an overcurrent protection circuit and a valley current protection circuit, which is not specifically limited here.
[0097] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention shall be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.
Claims
1. A timing type valley current protection circuit, characterized in that: include: An energy storage circuit, comprising an energy storage unit, the energy storage circuit being connected to a first voltage, a second voltage, and a control signal, and being configured to charge and discharge the energy storage unit according to the control signal; a comparison circuit connected to the energy storage circuit, and configured to output a comparison signal according to the charge and discharge voltage and the threshold voltage of the energy storage unit; A logic circuit is connected to the comparison circuit and receives an overcurrent trigger signal, and is used to output a valley current limiting signal according to the overcurrent trigger signal and the comparison signal, and determine whether to trigger the valley current limiting function according to the overcurrent trigger signal and the valley current limiting signal, wherein the overcurrent trigger signal is used to indicate whether the overcurrent protection function is triggered.
2. The timing type valley current protection circuit according to claim 1, characterized in that: The energy storage circuit further includes a first switch circuit and a second switch circuit; Wherein, the first switch circuit is connected to the control signal, the first end is connected to the first voltage, the second end is connected to one end of the energy storage unit, and the third end and the fourth end are respectively connected to the comparison circuit; The second switch circuit is connected to the control signal, the first end is grounded, the second end is connected to the second voltage, and the third end is connected to the other end of the energy storage unit; The energy storage circuit is specifically used to control the on and off of the first switch circuit and the second switch circuit according to the control signal, so as to charge and discharge the energy storage unit.
3. The timing type valley current protection circuit according to claim 2, characterized in that: The control signal includes a first signal, a second signal and a third signal, wherein the first signal and the second signal are opposite signals, and the third signal is obtained according to the second signal and the overcurrent trigger signal; The first switch circuit includes: a first switch and a second switch, and the second switch circuit includes a third switch, a fourth switch and a first resistor; The control end of the first switch is connected to the third signal, the first end is connected to the first voltage, the second end is connected to the second signal, and the third end is connected to one end of the energy storage unit; The control end of the second switch is connected to the second signal, the first end is connected to one end of the energy storage unit and the first end of the comparison circuit, the second end is connected to the first signal, and the third end is connected to the second end of the comparison circuit; The control end of the third switch is connected to the first signal, the first end is connected to one end of the first resistor, the second end is connected to the second signal, and the third end is connected to the other end of the energy storage unit; The control end of the fourth switch is connected to the second signal, the first end is grounded, the second end is connected to the first signal, and the third end is connected to the other end of the energy storage unit; The other end of the first resistor is connected to the second voltage.
4. The timing type valley current protection circuit according to claim 3, characterized in that: The energy storage unit includes a capacitor, and the energy storage circuit is specifically used for: When the first signal is at a high level and the overcurrent trigger signal is at a low level, the first switch and the third switch are controlled to be turned off, and the second switch and the fourth switch are controlled to be turned on, so as to charge the capacitor, the charging voltage being the threshold voltage, and the overcurrent trigger signal being at a low level, indicating that the overcurrent protection function is not triggered; When the first signal changes from a high level to a low level and the overcurrent trigger signal is at a low level, the third switch is controlled to be turned on, and the first switch, the second switch and the fourth switch are controlled to be turned off, and the upper plate voltage of the capacitor is the sum of the threshold voltage and the second voltage; When the first signal is at a low level and the overcurrent trigger signal changes from a low level to a high level, the first switch and the third switch are controlled to be turned on, and the second switch and the fourth switch are controlled to be turned off to discharge the capacitor. The overcurrent trigger signal is at a high level, indicating that the overcurrent protection function is triggered.
5. The timing type valley current protection circuit according to any one of claims 1 to 4, characterized in that: The comparison circuit includes a first current source, a second current source, a first NMOS and a second NMOS; A first end of the first current source is connected to a power supply voltage, and a second end is connected to the drain of the first NMOS, the energy storage circuit, and the gate of the second NMOS; The gate of the first NMOS is connected to the energy storage circuit, and the source is grounded; A first end of the second current source is connected to a power supply voltage, and a second end is connected to a drain of the second NMOS and the logic circuit; The source of the second NMOS is grounded; The comparison circuit is specifically used for: When the voltage of the upper plate of the capacitor is greater than the threshold voltage, the output comparison signal is a high level; When the capacitor upper plate voltage is less than the threshold voltage, the output comparison signal is a low level.
6. The timing type valley current protection circuit according to any one of claims 1 to 4, characterized in that: The logic circuit includes: a NAND gate, a first inverter and a second inverter; The first input terminal of the NAND gate is connected to the comparison signal, the second input terminal is connected to the overcurrent trigger signal, and the output terminal is connected to one end of the first inverter; The other end of the first inverter is connected to one end of the second inverter; The other end of the second inverter is used to output the valley current limiting signal.
7. The timing type valley current protection circuit according to claim 6, characterized in that: The logic circuit is specifically used for: When the overcurrent trigger signal is at a low level, indicating that the overcurrent protection function is not triggered, and the comparison signal is at a low level or a high level, the output valley current limiting signal is at a high level, controlling the upper tube and the lower tube to work normally; When the overcurrent trigger signal is at a high level, indicating that the overcurrent protection function is triggered, and the comparison signal is at a high level, the output valley current limiting signal is at a low level, and the valley current protection circuit starts to work, continuing to keep the upper tube off and the lower tube on; When the overcurrent trigger signal is high, indicating that the overcurrent protection function is triggered, and the comparison signal is low, the output valley current limiting signal is high, triggering the valley current limiting function, controlling the upper tube to turn on and the lower tube to turn off.
8. The timing type valley current protection circuit according to claim 2, wherein: The control signal includes a first signal, a second signal and a third signal, wherein the first signal and the second signal are opposite signals, and the third signal is obtained according to the first signal and the overcurrent trigger signal; The first switch circuit includes: a first switch and a second switch, and the second switch circuit includes a third switch, a fourth switch and a first resistor; The control end of the first switch is connected to the third signal, the first end is connected to the first voltage, the second end is connected to the second signal, and the third end is connected to one end of the energy storage unit; The control end of the second switch is connected to the first signal, the first end is connected to one end of the energy storage unit and the first end of the comparison circuit, the second end is connected to the second signal, and the third end is connected to the second end of the comparison circuit; The control end of the third switch is connected to the first signal, the first end is connected to one end of the first resistor, the second end is connected to the second signal, and the third end is connected to the other end of the energy storage unit; The control end of the fourth switch is connected to the second signal, the first end is grounded, the second end is connected to the first signal, and the third end is connected to the other end of the energy storage unit; The other end of the first resistor is connected to the second voltage.
9. The timing type valley current protection circuit according to claim 8, characterized in that: The energy storage circuit is specifically used for: When the first signal is at a low level and the overcurrent trigger signal is at a low level, the first switch and the fourth switch are controlled to be turned off, and the second switch and the third switch are controlled to be turned on, so as to charge the capacitor, and the upper plate voltage of the capacitor is the threshold voltage; When the first signal changes from a low level to a high level and the overcurrent trigger signal is at a low level, the first switch, the second switch, and the third switch are controlled to be turned off, and the fourth switch is controlled to be turned on, and the upper plate voltage of the capacitor is the difference between the threshold voltage and the second voltage; When the first signal is at a high level and the overcurrent trigger signal changes from a low level to a high level, the second switch and the third switch are controlled to be turned off, and the first switch and the fourth switch are controlled to be turned on, so as to charge the capacitor.
10. The timing type valley current protection circuit according to claim 8 or 9, characterized in that: The comparison circuit includes: a first current source, a second current source, a first NMOS, a second NMOS and a third inverter; A first end of the first current source is connected to a power supply voltage, and a second end is connected to the drain of the first NMOS, the energy storage circuit, and the gate of the second NMOS; The gate of the first NMOS is connected to the energy storage circuit, and the source is grounded; A first end of the second current source is connected to a power supply voltage, and a second end is connected to the drain of the second NMOS and one end of the third inverter; The source of the second NMOS is grounded; The other end of the third inverter is connected to the logic circuit; The comparison circuit is specifically used for: When the voltage of the upper plate of the capacitor is greater than the threshold voltage, the output comparison signal is a low level; When the capacitor upper plate voltage is less than the threshold voltage, the output comparison signal is a high level.