A high-reliability low-power lock detector

Abstract

The application relates to the technical field of phase-locked loops, and particularly provides a high-reliability low-power consumption lock detector, which comprises a dead zone pulse processing unit and a lock detection maintaining unit. The dead zone pulse processing unit performs logic operation on a first signal and a second signal output by a frequency discriminator and phase detector to obtain a first decision signal; and performs logic operation on the second signal and the first decision signal to obtain a second decision signal; and the lock detection maintaining unit generates a lock decision signal for judging the lock state of a phase-locked loop based on the second decision signal. The application can always generate an effective pulse signal according to the signals output by the frequency discriminator and phase detector through logic operation, so that the dead zone problem is eliminated, the lock state of the phase-locked loop is judged according to the generated pulse signal, the decision precision of the lock detection circuit for the lock state of the phase-locked loop is improved, and the overall circuit power consumption is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phase-locked loop lock detector, and particularly relates to a high-reliability and low-power lock detector. BACKGROUND

[0002] The lock detection circuit is an important auxiliary module in a phase-locked loop system (PLL), and usually cooperates with core components such as a frequency discriminator, a loop filter and a voltage-controlled oscillator (VCO). As a monitor of the system, the lock detection circuit monitors the phase and frequency relationship between a reference signal and a feedback signal in real time. When the phase-locked loop system (PLL) reaches a locked state, the lock detection circuit outputs a continuously valid logic to indicate the locked state.

[0003] The existing digital lock detection circuit directly compares UP / DN pulses of a frequency discriminator to determine the locked state. This detection method is simple in judgment, and the result of the judgment is only two cases of locked and non-locked. In some conventional applications, the application is good, however, when a VCO is driven with high accuracy, the frequency value of the VCO after frequency division is very close to the frequency value of the reference after frequency division, so that the phase difference between the reference frequency and the feedback frequency detected by the frequency discriminator is very small, and there is a dead zone problem, which causes the frequency discriminator to be unable to generate an effective pulse signal. The phase difference between the reference frequency and the feedback frequency is about 800-900 ps when the phase-locked loop is locked. The existing lock detection circuit has low judgment accuracy, and the lock error is about 1-2 ns. When the lock detection circuit detects, the phase difference between the reference frequency and the feedback frequency detected by the frequency discriminator is less than the lock error of the existing lock detection circuit, so that the lock detection circuit misjudges the phase-locked loop as a locked state due to no pulse input, and thus a false lock signal may be generated. Meanwhile, the existing digital lock detection circuit has high power consumption. SUMMARY

[0004] In view of the above problems, the present application provides a high-reliability and low-power lock detector, which only adds a plurality of logic gate circuits to process the output signal of the frequency discriminator, eliminates the dead zone effect caused by the very small phase difference between the reference frequency and the feedback frequency detected by the frequency discriminator, and further eliminates the false lock signal, improves the judgment accuracy of the lock detection circuit on the locked state of the phase-locked loop system, and has low circuit power consumption.

[0005] To achieve the purpose of the present application, the present application provides the following technical solutions:

[0006] In a first aspect, the present application provides a high-reliability and low-power lock detector, which comprises:

[0007] The dead zone pulse processing unit comprises a first processing circuit and a second processing circuit; the first processing circuit is configured to receive a first signal and a second signal output by a phase frequency detector, and generate a first decision signal based on the first signal and the second signal; the second processing circuit is configured to receive the second signal and the first decision signal, and generate a second decision signal based on the second signal and the first decision signal;

[0008] The lock detection maintaining unit is connected to the output of the dead zone pulse processing unit, configured to receive the second decision signal, and adjust the voltage value of the capacitance of the lock detection maintaining unit based on the second decision signal; when the voltage value is lower than a preset threshold, a lock decision signal is generated.

[0009] In a possible implementation, in the dead zone pulse processing unit, the logical operation performed by the first processing circuit based on the first signal and the second signal is an AND operation; and the logical operation performed based on the second signal and the first decision signal is an XOR operation.

[0010] In a possible implementation, the first processing circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube; the gate of the first PMOS tube and the gate of the first NMOS tube are connected to a first output of a phase frequency detector, configured to receive the first signal; the gate of the second PMOS tube and the gate of the second NMOS tube are connected to a second output of the phase frequency detector, configured to receive the second signal; the drain of the first PMOS tube, the drain of the second PMOS tube and the drain of the first NMOS tube are commonly connected to the gate of the third PMOS tube and the gate of the third NMOS tube; the source of the first NMOS tube is connected to the drain of the second NMOS tube; the drain of the third PMOS tube and the drain of the third NMOS tube are connected to the output of the first processing circuit, configured to output the first decision signal; the source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to a power supply; and the source of the second NMOS tube and the source of the third NMOS tube are grounded.

[0011] In a possible implementation, the second processing circuit includes a fourth PMOS, a fifth PMOS, a sixth PMOS, a seventh PMOS, an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth PMOS, a fourteenth PMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, gates of the fourth NMOS, the fourth PMOS, the eighth PMOS, and the ninth NMOS are connected to a drain of the third PMOS, for receiving the first decision signal; gates of the fifth NMOS, the seventh NMOS, the sixth PMOS, and the seventh PMOS are connected to a second output terminal of the phase-frequency detector, for receiving the second signal; drains of the fourth PMOS and the fourth NMOS are commonly connected to gates of the fifth PMOS and the sixth NMOS; a drain of the fifth NMOS is connected to a source of the sixth NMOS; drains of the fifth PMOS, the sixth PMOS, and the sixth NMOS are commonly connected to gates of the tenth PMOS and the tenth NMOS; drains of the seventh PMOS and the seventh NMOS are commonly connected to gates of the eighth NMOS and the ninth PMOS; a drain of the eighth NMOS is connected to a source of the ninth NMOS; drains of the eighth PMOS, the ninth PMOS, and the ninth NMOS are commonly connected to gates of the eleventh PMOS and the eleventh NMOS; drains of the tenth PMOS and the tenth NMOS are commonly connected to gates of the twelfth PMOS and the thirteenth NMOS; drains of the eleventh PMOS and the eleventh NMOS are commonly connected to gates of the twelfth NMOS and the thirteenth PMOS; a drain of the twelfth PMOS is connected to a source of the thirteenth PMOS; drains of the twelfth NMOS, the thirteenth PMOS, and the thirteenth NMOS are commonly connected to gates of the fourteenth PMOS and the fourteenth NMOS; drains of the fourteenth PMOS and the fourteenth NMOS are commonly connected to an output terminal of the second processing circuit; sources of the fourth PMOS, the fifth PMOS, the sixth PMOS, the seventh PMOS, the eighth PMOS, the ninth PMOS, the tenth PMOS, the eleventh PMOS, the twelfth PMOS, and the fourteenth PMOS are commonly connected to a power supply.The source of the fourth NMOS transistor, the fifth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor and the fourteenth NMOS transistor are grounded.

[0012] In a possible implementation, the lock detection maintaining unit comprises a resistor, a capacitor, a first inverter and a second inverter; the first inverter comprises a fifteenth PMOS transistor and a fifteenth NMOS transistor, the gates of the fifteenth PMOS transistor and the fifteenth NMOS transistor are connected to the output of the lock detection maintaining unit, for receiving the second decision signal; the second inverter comprises a sixteenth PMOS transistor and a sixteenth NMOS transistor, the gates of the sixteenth PMOS transistor and the sixteenth NMOS transistor are connected to the drain of the fifteenth PMOS transistor, one end of the resistor and one end of the capacitor; the other end of the resistor is connected to the drain of the fifteenth NMOS transistor; the drain of the sixteenth PMOS transistor is connected to the drain of the sixteenth NMOS transistor, for outputting the lock decision signal; the sources of the fifteenth PMOS transistor and the sixteenth PMOS transistor are connected to a power supply; the other end of the capacitor and the sources of the fifteenth NMOS transistor and the sixteenth NMOS transistor are grounded.

[0013] In a possible implementation, the generating the lock decision signal based on the second decision signal comprises:

[0014] adjusting the voltage of the capacitor based on the second decision signal, to obtain an adjusted voltage of the capacitor;

[0015] generating the lock decision signal based on the adjusted voltage of the capacitor and a preset threshold.

[0016] In a possible implementation, in the generating the lock decision signal based on the adjusted voltage of the capacitor and a preset threshold, the preset threshold is the flip voltage of the first inverter.

[0017] In a possible implementation, the lock detection maintaining unit further includes a third inverter and a fourth inverter, the third inverter includes a seventeenth PMOS tube and a seventeenth NMOS tube, the gates of the seventeenth PMOS tube and the seventeenth NMOS tube are commonly connected with the drain of the sixteenth PMOS tube, and are configured to receive the lock decision signal; the fourth inverter includes an eighteenth PMOS tube and an eighteenth NMOS tube, the gates of the eighteenth PMOS tube and the eighteenth NMOS tube are commonly connected with the drains of the seventeenth PMOS tube and the seventeenth NMOS tube, the drains of the eighteenth PMOS tube and the eighteenth NMOS tube are connected, and are configured to output the lock decision signal; the sources of the seventeenth PMOS tube and the eighteenth PMOS tube are both connected with a power supply; and the sources of the seventeenth NMOS tube and the eighteenth NMOS tube are both grounded.

[0018] In a possible implementation, the lock detection maintaining unit further includes a nineteenth NMOS tube, the gate of the nineteenth NMOS tube is connected with the drain of the sixteenth PMOS tube, the drain of the nineteenth NMOS tube is connected with the gate of the sixteenth PMOS tube, and the source of the nineteenth NMOS tube is grounded.

[0019] Advantages:

[0020] The application can generate an effective pulse signal according to the signal output by the phase frequency detector, eliminate the dead zone problem, and determine the locking state of the phase-locked loop according to the generated pulse signal, thereby improving the determination accuracy of the locking detection circuit on the locking state of the phase-locked loop, and generating the effective pulse signal through a logic circuit, so that the overall circuit has low power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, illustrate the embodiments of the application, and are used to explain the application, but do not form a limitation on the application;

[0022] Figure 1 A component structure schematic diagram of a high-reliability low-power consumption lock detector provided by the embodiment of the application;

[0023] Figure 2 A component structure schematic diagram of a dead zone pulse processing unit of a high-reliability low-power consumption lock detector provided by the embodiment of the application;

[0024] Figure 3 A component structure schematic diagram of a lock detection maintaining unit of a high-reliability low-power consumption lock detector provided by the embodiment of the application;

[0025] Figure 4 A timing analysis diagram of an unlocked time of a high-reliability low-power lock detector provided for an embodiment of the present application is provided.

[0026] Figure 5 A timing analysis diagram of a locked time of a high-reliability low-power lock detector provided for an embodiment of the present application is provided. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0028] The terms "first", "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features; in the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0029] The high-reliability low-power lock detector of an embodiment of the present application comprises: a dead zone pulse processing unit comprising a first processing circuit and a second processing circuit; the first processing circuit is configured to receive a first signal and a second signal output by a phase discriminator, and generate a first decision signal based on the first signal and the second signal; the second processing circuit is configured to receive the second signal and the first decision signal, and generate a second decision signal based on the second signal and the first decision signal;

[0030] A lock detection maintenance unit, an input end of the lock detection maintenance unit is connected to an output end of the dead zone pulse processing unit, configured to receive the second decision signal, and adjust a voltage value of a capacitance of the lock detection maintenance unit based on the second decision signal, and generate a lock decision signal when the voltage value is lower than a preset threshold.

[0031] The technical solutions of the present application will be described below with reference to the embodiments shown in the drawings:

[0032] As shown in Figure 1 A high-reliability low-power lock detector can comprise:

[0033] The dead zone pulse processing unit 11 comprises a first processing circuit 111 and a second processing circuit 112; the first processing circuit 111 is configured to receive a first signal and a second signal output by the phase detector, and perform logical operation based on the first signal and the second signal to obtain a first decision signal; the second processing circuit 112 is configured to receive the second signal and the first decision signal, and perform logical operation based on the second signal and the first decision signal to obtain a second decision signal;

[0034] The lock detection maintaining unit 12 is connected to the output end of the dead zone pulse processing unit, configured to receive the second decision signal, and generate a lock decision signal based on the second decision signal, wherein the lock decision signal is used to determine the lock state of the phase-locked loop.

[0035] In the embodiment of the present application, the first signal and the second signal are UP signal and DN signal output by the phase detector. When the VCO is driven accurately, the output frequency of the VCO after frequency division is extremely close to the reference frequency after frequency division. The extremely close frequency means that the phase difference between the two is very small. When the phase difference between the reference frequency detected by the phase detector and the feedback frequency is too small, the phase detector cannot correctly phase, thereby causing the phase detector to fail to trigger the output pulse, that is, there is a dead zone problem, which will cause the lock detection circuit to generate a false lock signal. Therefore, the dead zone problem is eliminated by the dead zone pulse processing unit.

[0036] In the embodiment, the reference Figure 2As shown, the dead zone pulse processing unit includes a first processing circuit and a second processing circuit, wherein the first processing circuit includes a first PMOS PM0, a second PMOS PM1, a third PMOS PM2, a first NMOS NM0, a second NMOS NM1 and a third NMOS NM2, the gates of the first PMOS PM0 and the first NMOS NM0 are connected to the first output of the phase-frequency detector for receiving the first signal, the gates of the second PMOS PM1 and the second NMOS NM1 are connected to the second output of the phase-frequency detector for receiving the second signal, the drains of the first PMOS PM0, the second PMOS PM1 and the first NMOS NM0 are commonly connected to the gates of the third PMOS PM2 and the third NMOS NM2, the source of the first NMOS NM0 is connected to the drain of the second NMOS NM1, the drain of the third PMOS PM2 is connected to the drain of the third NMOS NM2 for outputting the first decision signal, the sources of the first PMOS PM0, the second PMOS PM1 and the third PMOS PM2 are connected to the power supply, and the sources of the second NMOS NM1 and the third NMOS NM2 are grounded.

[0037] It can be understood that after the phase-frequency detector outputs the UP signal and the DN signal, the first processing circuit receives the UP signal and the DN signal, and performs AND operation on the UP signal and the DN signal to generate the first decision signal. When the phase-locked loop is not locked, the UP signal and the DN signal are different in frequency and in phase, and after the AND operation on the UP signal and the DN signal, a low level is generated, that is, the first decision signal generated by the first processing circuit when the phase-locked loop is not locked, and the generated first decision signal is input into the second processing circuit for further processing.

[0038] The second processing circuit 112 comprises a fourth PMOS PM3, a fifth PMOS PM4, a sixth PMOS PM5, a seventh PMOS PM6, an eighth PMOS PM7, a ninth PMOS PM8, a tenth PMOS PM9, an eleventh PMOS PM10, a twelfth PMOS PM11, a thirteenth PMOS PM12, a fourteenth PMOS PM13, a fourth NMOS NM3, a fifth NMOS NM4, a sixth NMOS NM5, a seventh NMOS NM6, an eighth NMOS NM7, a ninth NMOS NM8, a tenth NMOS NM9, an eleventh NMOS NM10, a twelfth NMOS NM11, a thirteenth NMOS NM12, and a fourteenth NMOS NM13. The gates of the fourth NMOS NM3, the fourth PMOS PM3, the eighth PMOS PM7, and the ninth NMOS NM8 are connected to the drain of the third PMOS PM2, for receiving the first decision signal. The gates of the fifth NMOS NM4, the seventh NMOS NM6, the sixth PMOS PM5, and the seventh PMOS PM6 are connected to the second output of the phase-frequency detector, for receiving the second signal. The drains of the fourth PMOS PM3 and the fourth NMOS NM3 are connected to the gates of the fifth PMOS PM4 and the sixth NMOS NM5. The drain of the fifth NMOS NM4 is connected to the source of the sixth NMOS NM5. The drains of the fifth PMOS PM4, the sixth PMOS PM5, and the sixth NMOS NM5 are connected to the gates of the tenth PMOS PM9 and the tenth NMOS NM9. The drains of the seventh PMOS PM6 and the seventh NMOS NM6 are connected to the gates of the eighth NMOS NM7 and the ninth PMOS PM8. The drain of the eighth NMOS NM7 is connected to the source of the ninth NMOS NM8. The drains of the eighth PMOS PM7, the ninth PMOS PM8, and the ninth NMOS NM8 are connected to the gates of the eleventh PMOS PM10 and the eleventh NMOS NM10. The drains of the tenth PMOS PM9 and the tenth NMOS NM9 are connected to the gates of the twelfth PMOS PM11 and the thirteenth NMOS NM12. The drains of the eleventh PMOS PM10 and the eleventh NMOS NM10 are connected to the gates of the twelfth NMOS NM11 and the thirteenth PMOS PM12. The drain of the twelfth PMOS PM11 is connected to the source of the thirteenth PMOS PM12.The drain of the twelfth NMOS transistor NM11, the drain of the thirteenth PMOS transistor PM12 and the drain of the thirteenth NMOS transistor NM12 are commonly connected to the gate of the fourteenth PMOS transistor PM13 and the gate of the fourteenth NMOS transistor NM13; the drain of the fourteenth PMOS transistor PM13 and the drain of the fourteenth NMOS transistor NM13 are commonly connected to the input end of the lock detection maintaining unit, for transmitting the second decision signal to the lock detection maintaining unit; the source of the fourth PMOS transistor PM3, the source of the fifth PMOS transistor PM4, the source of the sixth PMOS transistor PM5, the source of the seventh PMOS transistor PM6, the source of the eighth PMOS transistor PM7, the source of the ninth PMOS transistor PM8, the source of the tenth PMOS transistor PM9, the source of the eleventh PMOS transistor PM10, the source of the twelfth PMOS transistor PM11 and the source of the fourteenth PMOS transistor PM13 are commonly connected to a power supply; the source of the fourth NMOS transistor NM3, the source of the fifth NMOS transistor NM4, the source of the seventh NMOS transistor NM6, the source of the eighth NMOS transistor NM7, the source of the tenth NMOS transistor NM9, the source of the eleventh NMOS transistor NM10, the source of the twelfth NMOS transistor NM11, the source of the thirteenth NMOS transistor NM12 and the source of the fourteenth NMOS transistor NM13 are commonly connected to a ground.

[0039] It can be understood that, after the UP signal and the DN signal output by the phase frequency detector, the first processing circuit performs AND operation on the UP signal and the DN signal. When the phase-locked loop system is not locked, the UP signal and the DN signal output by the phase frequency detector are different in frequency and in phase, so that after the AND operation on the UP signal and the DN signal, a low-level signal is generated. Then, the second processing circuit receives the low-level signal and the DN signal, and performs XOR operation thereon, and after the XOR operation, a "0" signal with a certain pulse width is obtained, that is, the dead zone pulse processing unit generates a "0" signal with a certain pulse width when the phase-locked loop system is not locked, which is the second decision signal when the phase-locked loop system is not locked, for the subsequent lock detection maintaining unit to determine the phase-locked loop locking. When the output frequency of the phase-locked loop gradually stabilizes, that is, when the phase-locked loop is close to locking, the UP signal and the DN signal output by the phase frequency detector are close in frequency and in phase, at this time, the UP and DN signals pass through the AND gate unit to generate a high-low level alternating signal, and then pass through the XOR gate and the DN signal to generate a "1" signal with a relatively wide pulse width and a "0" signal with a relatively narrow pulse width alternately. In this way, even if the phase difference between the reference frequency and the feedback frequency detected by the phase frequency detector is too small, the dead zone pulse processing unit can still output an effective pulse signal to trigger a pulse, thereby solving the problem of being unable to trigger an output pulse due to the inability of the phase frequency detector to correctly phase.

[0040] Further, the lock detection maintaining unit in the embodiment adjusts the values of the resistance and the capacitance in the lock detection maintaining unit according to the second decision signal output by the dead zone pulse unit, so as to determine whether the phase-locked loop system is locked, thereby eliminating the false lock signal and improving the decision precision of the lock detector.

[0041] In the embodiment of the present application, referring to Figure 3 As shown in the figure, the lock detection maintaining unit comprises a resistance, a capacitance, a first inverter and a second inverter; the first inverter comprises a fifteenth PMOS tube PM14 and a fifteenth NMOS tube NM14, the gates of the fifteenth PMOS tube PM14 and the fifteenth NMOS tube NM14 are commonly connected to the output end of the dead zone pulse processing unit, for receiving the second decision signal; the second inverter comprises a sixteenth PMOS tube PM15 and a sixteenth NMOS tube NM16, the gates of the sixteenth PMOS tube PM15 and the sixteenth NMOS tube NM16 are commonly connected to the drain of the fifteenth PMOS tube PM14, one end of the resistance and one end of the capacitance; the other end of the resistance is connected to the drain of the fifteenth NMOS tube NM14; the drain of the sixteenth PMOS tube PM15 is connected to the drain of the sixteenth NMOS tube NM16, for outputting the lock decision signal; the sources of the fifteenth PMOS tube PM14 and the sixteenth PMOS tube PM15 are both connected to a power supply; the other end of the capacitance and the sources of the fifteenth NMOS tube NM14 and the sixteenth NMOS tube NM16 are both grounded.

[0042] When the lock detection maintaining unit receives the signal output by the dead zone pulse unit as a "0" signal, the fifteenth PMOS transistor PM14 is turned on, so that the capacitor C1 is charged, and the voltage of the capacitor C1 is raised. When the signal output by the dead zone pulse unit 11 is a "1" signal, the charge accumulated on the capacitor C1 is gradually released through the resistor R1 and the fifteenth NMOS transistor NM14, and the voltage of the capacitor is lowered. Therefore, when the phase-locked loop system is not locked, the signal output by the dead zone pulse unit 11 is a "0" signal with a certain pulse width, at this time, the capacitor C1 is charged, and the voltage of the capacitor C1 is continuously raised, the voltage of the capacitor C1 is maintained at a high level, which is higher than the flip voltage of the first inverter, so the input level of the first inverter is recognized as logic "1", and a low level signal is output. After the second inverter receives the low level signal, the low level signal is inverted, and a high level signal is output, that is, the lock decision signal is a high level signal, indicating that the phase-locked loop system is not locked. When the output frequency of the phase-locked loop is gradually stabilized, that is, when the phase-locked loop is close to being locked, the output of the dead zone pulse processing unit will appear as a relatively wide pulse width "1" signal and a relatively narrow pulse width "0" signal alternately, and the voltage of the capacitor C1 will gradually decrease as a whole. When the voltage of the capacitor C1 is lower than the flip voltage of the first inverter, the input level of the first inverter is recognized as logic "0", the first inverter outputs a high level, and after the second inverter inverts, a low level is output, that is, the lock decision signal is a low level signal, indicating that the phase difference between the two output signals of the frequency discriminator is less than the set value, which is the detectable phase difference, which can reach 500ps through experimental analysis. At this time, it indicates that the PLL has been locked.

[0043] In addition, in the embodiment, the lock detection maintaining unit further includes a third inverter and a fourth inverter. The third inverter includes a seventeenth PMOS transistor PM16 and a seventeenth NMOS transistor NM17, the gates of the seventeenth PMOS transistor PM16 and the seventeenth NMOS transistor NM17 are commonly connected with the drain of the sixteenth PMOS transistor PM15, and are used to receive the lock decision signal. The fourth inverter includes an eighteenth PMOS transistor PM17 and an eighteenth NMOS transistor NM18, the gates of the eighteenth PMOS transistor PM17 and the eighteenth NMOS transistor NM18 are commonly connected with the drains of the seventeenth PMOS transistor PM16 and the seventeenth NMOS transistor NM17, the drains of the eighteenth PMOS transistor PM17 and the eighteenth NMOS transistor NM18 are connected, and are used to output the lock decision signal. The sources of the seventeenth PMOS transistor PM16 and the eighteenth PMOS transistor PM17 are connected with a power supply. The sources of the seventeenth NMOS transistor NM17 and the eighteenth NMOS transistor NM18 are grounded.

[0044] In addition, in the embodiment, the lock detection maintaining unit further comprises a nineteenth NMOS transistor NM15, a gate of the nineteenth NMOS transistor NM15 is connected to a drain of the sixteenth PMOS transistor PM15, a drain of the nineteenth NMOS transistor NM15 is connected to a gate of the sixteenth PMOS transistor PM15, and a source of the nineteenth NMOS transistor NM15 is grounded. The nineteenth NMOS transistor NM15 is connected in parallel with the capacitor C1, and is used for accelerating the charging and discharging speed of the capacitor C1.

[0045] Based on the lock detector provided in the application, simulation experiments are carried out.

[0046] The simulation experiment element of the application adopts the SMIC 55nm CMOS process, and the simulation circuit of the application is built based on the Cadence IC617 simulation experiment platform under the Linux system.

[0047] The simulation of the application adopts the Specture simulation tool to simulate the circuit of the application, and the given power supply voltage VDD is 1.2V, and the working temperature is 27℃.

[0048] Simulation 1: under the above working conditions, the Specture simulation tool is used, corresponding input waveforms (UP and DN signals simulated by the frequency discriminator output) are added to the input end of the dead zone pulse processing unit 11, the UP signal voltage is 0-1.2V, the period is 20ns, the rise time is 10ps, the fall time is 10ps, and the pulse width is 10ns, the DN signal voltage is 0-1.2V, the period is 20.83ns, the delay is 500ps, the rise time is 10ps, the fall time is 10ps, and the pulse width is 10.415ns, the transient simulation of the application is carried out, and the result is as shown in Figure 4 . Figure 4 Fig. 1 is a timing simulation diagram of the application in the unlocked state in simulation 1, wherein the abscissa represents the transient simulation time, the unit is ns, the ordinate is the high and low level of the output signal, the unit is V, and the output signal is high in the unlocked state. Figure 4

[0049] Simulation 2: under the above working conditions, the Specture simulation tool is used, corresponding input waveforms (UP and DN signals simulated by the frequency discriminator output) are added to the input end of the dead zone pulse processing unit 11, the UP signal voltage is 0-1.2V, the period is 20ns, the rise time is 10ps, the fall time is 10ps, and the pulse width is 10ns, the DN signal voltage is 0-1.2V, the period is 20ns, the delay is 500ps, the rise time is 10ps, the fall time is 10ps, and the pulse width is 10ns, the transient simulation of the application is carried out, and the result is as shown in Figure 5 . Figure 5 ​The lock-in post timing simulation chart in the simulation 2, wherein the horizontal coordinate represents the transient simulation time, unit: ns, and the vertical coordinate is the output signal high and low level, unit: V, from Figure 5 It can be seen that the output low level after locking-in.

[0050] The simulation results show that the lock-in detector proposed in the application eliminates the dead zone influence caused by the small phase difference of the input signal of the frequency discriminator and phase detector, thereby eliminating the false lock signal while ensuring low power consumption.

[0051] It should be noted that in the present disclosure, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or apparatus including the element.

[0052] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit it. The present application is not limited to the exact structure described above and illustrated in the drawings, and the specific implementation of the present application should not be limited to the above description. For ordinary skilled persons in the art to which the present application belongs, various changes and modifications made without departing from the concept of the present application should be considered as falling within the scope of protection of the present application.

Claims

1. A highly reliable, low-power locking detector, characterized in that, The lock detector includes: The dead-zone pulse processing unit includes a first processing circuit and a second processing circuit. The first processing circuit is used to receive a first signal and a second signal output by a frequency and phase detector, and perform logical operations based on the first signal and the second signal to obtain a first decision signal. The second processing circuit is used to receive the second signal and the first decision signal, and perform logical operations based on the second signal and the first decision signal to obtain a second decision signal. The logical operation performed by the first processing circuit based on the first signal and the second signal is an AND operation; the logical operation performed based on the second signal and the first decision signal is an XOR operation. A lock detection and maintenance unit, wherein the input terminal of the lock detection and maintenance unit is connected to the output terminal of the dead-zone pulse processing unit, is used to receive the second decision signal and generate a lock decision signal based on the second decision signal, wherein the lock decision signal is used to determine the lock state of the phase-locked loop; The lock detection and maintenance unit includes a resistor, a capacitor, a first inverter, and a second inverter. The first inverter includes a fifteenth PMOS transistor and a fifteenth NMOS transistor, the gates of which are connected to the output of the lock detection and maintenance unit to receive the second decision signal. The second inverter includes a sixteenth PMOS transistor and a sixteenth NMOS transistor, the gates of which are connected to the drain of the fifteenth PMOS transistor, one end of the resistor, and one end of the capacitor. The other end of the resistor is connected to the drain of the fifteenth NMOS transistor. The drain of the sixteenth PMOS transistor is connected to the drain of the sixteenth NMOS transistor to output the lock decision signal. The sources of both the fifteenth and sixteenth PMOS transistors are connected to a power supply. The other end of the capacitor and the sources of both the fifteenth and sixteenth NMOS transistors are grounded.

2. The high-reliability, low-power locking detector according to claim 1, characterized in that, The first processing circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are both connected to the first output terminal of a frequency-phase detector for receiving the first signal. The gates of the second PMOS transistor and the second NMOS transistor are both connected to the second output terminal of the frequency-phase detector for receiving the second signal. The drains of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected to the gates of the third PMOS transistor and the third NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The drains of the third PMOS transistor and the third NMOS transistor are connected to the output terminal of the first processing circuit for outputting the first decision signal. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to a power supply. The sources of the second NMOS transistor and the third NMOS transistor are both grounded.

3. A high-reliability, low-power locking detector according to claim 2, characterized in that, The second processing circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. The gates of the fourth NMOS transistor, the fourth PMOS transistor, the eighth PMOS transistor, and the ninth NMOS transistor are all connected to... The drain of the third PMOS transistor is used to receive the first decision signal; the gates of the fifth NMOS transistor, the seventh NMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are all connected to the second output terminal of the frequency-phase detector to receive the second signal; the drains of the fourth PMOS transistor and the fourth NMOS transistor are connected to the gates of the fifth PMOS transistor and the sixth NMOS transistor; the drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor; the drains of the fifth PMOS transistor, the sixth PMOS transistor, and the sixth NMOS transistor are connected to the gates of the tenth PMOS transistor and the tenth NMOS transistor; the seventh PMOS transistor... The drain of the seventh NMOS transistor is connected to the gates of the eighth NMOS transistor and the ninth PMOS transistor; the drain of the eighth NMOS transistor is connected to the source of the ninth NMOS transistor; the drains of the eighth PMOS transistor, the ninth PMOS transistor, and the ninth NMOS transistor are connected to the gates of the eleventh PMOS transistor and the eleventh NMOS transistor; the drains of the tenth PMOS transistor and the tenth NMOS transistor are connected to the gates of the twelfth PMOS transistor and the thirteenth NMOS transistor; the drains of the eleventh PMOS transistor and the eleventh NMOS transistor are connected to the gates of the twelfth NMOS transistor and the thirteenth PMOS transistor; the... The drain of the 12th PMOS transistor is connected to the source of the 13th PMOS transistor; the drains of the 12th, 13th PMOS, and 13th NMOS transistors are connected to the gates of the 14th PMOS and 14th NMOS transistors; the drains of the 14th PMOS and 14th NMOS transistors are both connected to the output terminal of the second processing circuit; the sources of the 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, and 14th PMOS transistors are all connected to the power supply;The sources of the fourth, fifth, seventh, eighth, tenth, eleventh, twelfth, thirteenth, and fourteenth NMOS transistors are all grounded.

4. A high-reliability, low-power locking detector according to claim 1, characterized in that, The step of generating a locking decision signal based on the second decision signal includes: The voltage of the capacitor is adjusted based on the second decision signal to obtain the adjusted voltage of the capacitor; The locking decision signal is generated based on the adjusted voltage of the capacitor and a preset threshold.

5. A high-reliability, low-power locking detector according to claim 4, characterized in that, In generating the lockout decision signal based on the adjusted voltage of the capacitor and a preset threshold, the preset threshold is the flip-flop voltage of the first inverter.

6. A high-reliability, low-power locking detector according to claim 1, characterized in that, The lock detection and maintenance unit further includes a third inverter and a fourth inverter. The third inverter includes a seventeenth PMOS transistor and a seventeenth NMOS transistor, the gates of which are connected to the drain of the sixteenth PMOS transistor, for receiving the lock decision signal. The fourth inverter includes an eighteenth PMOS transistor and an eighteenth NMOS transistor, the gates of which are connected to the drains of which are connected to the drains of which are connected, for outputting the lock decision signal. The sources of the seventeenth PMOS transistor and the eighteenth PMOS transistor are both connected to a power supply. The sources of the seventeenth NMOS transistor and the eighteenth NMOS transistor are both grounded.

7. A high-reliability, low-power locking detector according to claim 1, characterized in that, The lock detection and maintenance unit further includes a nineteenth NMOS transistor, the gate of which is connected to the drain of the sixteenth PMOS transistor, the drain of which is connected to the gate of the sixteenth PMOS transistor, and the source of which is grounded.

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