Odd-even data weight homogenization method and system

Abstract

The invention discloses a parity data weight homogenization method and system. The method comprises the following steps of: judging whether any one of a plurality of bit values is equal to a weight value, if not, setting an even number initial bit and an odd number initial bit, if so, updating the even number initial bit to be the next even number bit of the previously last shifted even number bit, and if not, updating the odd number initial bit to be the next even number bit; updating the odd number initial bit to the odd number bit next to the odd number bit to which the odd number initial bit is shifted last previously; shifting from the even initial bit to other even bits according to the even number, and shifting from the odd initial bit to other odd bits according to the odd number; and adjusting the even and odd initial bits and the one or more bit values shifted therefrom to be equal to the weight value.

Description

Technical Field

[0001] The present invention relates to a method and system for setting data bit weights, and in particular to a method and system for equalizing odd and even data weights. Background Art

[0002] Data Weighted Averaging (DWA), also known as element rotation, is widely used to overcome process mismatches. Its primary goal is to ensure that multiple components are selected with the same probability during the conversion process. However, in practice, this goal has not yet been effectively achieved. Summary of the Invention

[0003] A method for equalizing the weight of even and parity data of the present invention is executed by a weight equalization circuit and includes the following steps: (a) determining whether an even number set by a weight setting program executed each time is equal to zero, and if so, directly executing step (d); if not, executing steps (b) to (d) in sequence; (b) determining whether any of a plurality of bit values ​​of a plurality of even bits of input data is equal to a first weight value in the weight setting program executed each time, and if not, setting one of the plurality of even bits as an even initial bit, and if so, setting the next even bit after the even bit that was last shifted as the even initial bit, and then resetting the plurality of even bits to be not equal to the first weight value; (c) in the weight setting program executed each time, using the value obtained by subtracting "1" from the even number as an even shift bit number, shifting the even shift bit number from the even initial bit to the other even bits by the even shift bit number, and adjusting the even initial bit and one or more bit values ​​shifted therefrom to be equal to the first weight value; d) determining whether an odd number set by the weight setting procedure in each execution is equal to zero, if so, jumping to step (a) to execute the next weight setting procedure, if not, executing steps (e) to (f) in sequence; (e) in each execution of the weight setting procedure, determining whether any of the multiple bit values ​​of the multiple odd bits of the input data is equal to the first weight value, if not, setting one of the multiple odd bits as an odd initial bit, if so, setting the next odd bit after the previously last shifted odd bit as the odd initial bit, and then resetting the multiple odd bits to be not equal to the first weight value; and (f) in each execution of the weight setting procedure, using the value obtained by subtracting "1" from the odd number as an odd shift bit number, shifting the odd shift bit number from the odd initial bit to the other odd bits, adjusting the odd initial bit and one or more bit values ​​shifted therefrom to be equal to the first weight value, and then jumping to step (a) to execute the next weight setting procedure.

[0004] A parity data weight equalization system of the present invention includes a weight equalization circuit. The weight equalization circuit is configured to execute a weight setting program multiple times. In the first execution of the weight setting program, the weight equalization circuit sets any one of the multiple bit values ​​of multiple even bits of an input data as an even initial bit, and in the other executions of the weight setting program, the next even bit of the even bit that was previously last shifted is set as the even initial bit. When the even number set by the weight setting program executed each time is not equal to zero, the weight equalization circuit uses the value after "1" is subtracted from the even number as an even shift bit number, shifts the even shift bit number from the even initial bit to the other even bits, and adjusts the even initial bit and one or more bit values ​​shifted therefrom to be equal to the first weight value. In the first execution of the weight setting procedure, the weight equalization circuit sets any one of the multiple bit values ​​of the multiple odd bits of the input data as an odd initial bit, and in subsequent executions of the weight setting procedure, the even bit next to the last shifted odd bit is set as the odd initial bit. When the odd number set in each execution of the weight setting procedure is not equal to zero, the weight equalization circuit uses the value obtained by subtracting "1" from the odd number as an odd shift bit number, shifts the odd shift bit number from the odd initial bit to the other odd bits, and adjusts the odd initial bit and the one or more bit values ​​shifted therefrom to equal the first weight value.

[0005] As described above, the present invention provides a method and system for equalizing parity data weights. In the method and system for equalizing parity data weights of the present invention, after executing a weight setting procedure multiple times, multiple bit values ​​of input data (including multiple bit values ​​of multiple even bits and multiple bit values ​​of multiple odd bits) are adjusted multiple times, so that the probabilities of the multiple bit values ​​of the input data being adjusted to equal a first weight value are similar to each other, and are all close to a probability average.

[0006] If the parity data weight equalization method and system of the present invention are applied to the control of multiple components, the multiple bit values ​​of the input data can correspond to multiple components respectively, so that the probability of multiple components being turned on or used is close to an average probability. Because when the components are manufactured, there are usually differences between each individual component due to process variations, and when the signal output passes through these components, it will cause the output signal to be interfered with by these differences, thereby reducing performance. Through the parity data weight equalization method and system of the present invention, the use probability of all components is made close to the same, and the signal error of the output signal caused by the differences of these components is averaged, thereby further improving the overall performance.

[0007] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and illustration and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A process diagram of the steps of setting weight values ​​of multiple even bits of input data in a method for equalizing parity data weights according to an embodiment of the present invention.

[0009] Figure 2 This is a process diagram of the steps of setting weight values ​​of multiple odd bits of input data in a method for equalizing parity data weights according to an embodiment of the present invention.

[0010] Figure 3 This is a process diagram of the steps of initially setting multiple bit values ​​of input data as second weight values ​​in the method for equalizing parity data weights according to an embodiment of the present invention.

[0011] Figure 4 This is a process diagram of controlling a component according to weight values ​​of multiple bits of input data in a method for equalizing parity data weights according to an embodiment of the present invention.

[0012] Figure 5 FIG2 is a process diagram of setting the even number and odd number of the parity data weight equalization method according to an embodiment of the present invention.

[0013] Figure 6 FIG2 is a process diagram of the steps of initially setting the even initial bits in the method for equalizing the weight of parity data according to an embodiment of the present invention.

[0014] Figure 7 FIG2 is a process diagram of the steps of initially setting odd initial bits in the method for equalizing the weight of parity data according to an embodiment of the present invention.

[0015] Figure 8 This is a process diagram of the subsequent steps of setting the even initial bits in the method for equalizing the weight of parity data according to an embodiment of the present invention.

[0016] Figure 9 This is a process diagram of the subsequent steps of setting odd initial bits in the method for equalizing parity data weights according to an embodiment of the present invention.

[0017] Figure 10 Schematic diagram of the weight values ​​outputted by the parity data weight equalization method and system according to an embodiment of the present invention after executing a weight setting procedure on input data.

[0018] Figure 11 Schematic diagram of the weight values ​​outputted by the parity data weight equalization method and system according to an embodiment of the present invention after executing a weight setting procedure on input data.

[0019] Figure 12 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0020] Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0021] Figure 14 1 is a circuit diagram of an even-numbered shift counting circuit and an even-numbered output stage circuit of a parity data weight equalization system according to an embodiment of the present invention.

[0022] Figure 15 1 is a circuit diagram of an odd-numbered shift counting circuit and an odd-numbered output stage circuit of a parity data weight equalization system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following is an explanation of the embodiments of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical content of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0024] See also Figure 1 、 Figure 2 as well as Figures 10 to 13 ,in Figure 1 This is a process diagram of the steps of setting the weight values ​​of multiple even bits of input data in the method for equalizing the weight of parity data according to an embodiment of the present invention. Figure 2 This is a process diagram of setting weight values ​​for a plurality of odd bits of input data in a method for equalizing parity data weights according to an embodiment of the present invention. Figure 10 and Figure 11 Schematic diagram of the weight values ​​output by the method and system for equalizing the weight of parity data according to an embodiment of the present invention after executing a weight setting procedure on input data. Figure 12 Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0025] The parity data weight equalization system of the present invention comprises the following Figure 12 The weight equalization circuit 100 is shown. If necessary, the parity data weight equalization system of the present invention may further include the following Figure 12The output stage circuit 200 is shown. The output stage circuit 200 is connected to the weight equalization circuit 100. The weight equalization circuit 100 can be a processor.

[0026] like Figure 13 As shown, the example weight equalization circuit 100 may include an even bit shift circuit 1011, an even bit shift counter circuit 1012, an odd bit shift circuit 1021, and an odd bit shift counter circuit 1022. The even bit shift counter circuit 1012 is connected to the even bit shift circuit 1011 and the output stage circuit 200, each of which may include one or more digital logic elements, but the invention is not limited thereto. The odd bit shift counter circuit 1022 is connected to the odd bit shift circuit 1021 and the output stage circuit 200. The output stage circuit 200 is connected to a plurality of elements A0 to An-1.

[0027] The method for equalizing the weight of parity data of the present invention can be performed as follows: Figure 12 or Figure 13 The parity data weight equalization system shown in FIG is performed. For the convenience of explanation, Figure 13 The parity data weight equalization system shown is used for illustration, but the present invention is not limited thereto.

[0028] It is worth noting that the method for equalizing the weight of parity data of the present invention includes the following steps: Figure 1 Steps S101 to S110 shown in FIG. Figure 2 Steps S202 to S210 are shown.

[0029] In the parity data weight equalization method of the present invention, the following steps are performed on the input data DT multiple times: Figure 1 Steps S101 to S110 shown in FIG. Figure 2 The weight setting procedure of S202 to S210 shown in the figure is different from the weight setting procedure of other executions. In each execution of the weight setting procedure, the odd weight setting procedure is executed once and the even weight setting procedure is executed once. That is, in the parity data weight equalization method of the present invention, the odd weight setting procedure of steps S101 to S110 is executed multiple times, and the even weight setting procedure of steps S202 to S210 is executed multiple times.

[0030] In step S101, the even-bit shift circuit 1011 of the weight equalization circuit 100 receives an input data DT from an external indication circuit, and receives a plurality of total usage numbers X or receives a total usage number instruction containing a plurality of total usage numbers X, where N is an integer value greater than 1, and the plurality of total usage numbers X are respectively used for weight setting procedures executed multiple times, where each total usage number X includes an even number and an odd number.

[0031] For example, the even bit shift circuit 1011 of the weight equalization circuit 100 is as follows: Figure 10 As shown, input data DT having 16 bits is received, or as shown Figure 11 The received input data DT having 15 bits is shown above for illustration only, and the present invention is not limited thereto.

[0032] For example, the even bit shift circuit 1011 of the weight equalization circuit 100 is as follows: Figure 10 and Figure 11 The total usage quantity instruction received as shown indicates 5 total usage quantities X (which are the quantities of components A0 to An-1 turned on) of 5 weight setting procedures, which are 1, 2, 5, 8, and 13 respectively. This is only an example and the present invention is not limited to this.

[0033] In step S102 , the even bit shift circuit 1011 of the weight equalization circuit 100 enters the even weight setting procedure each time.

[0034] In step S103, the even bit shift circuit 1011 of the weight equalization circuit 100 sets an even number for the current even weight setting procedure based on a total usage number X indicated by a received total usage number instruction, and determines whether the even number set for the current weight setting procedure is equal to zero. The even number set for each execution of the weight setting procedure may be different from the even number set for previous executions of the weight setting procedure.

[0035] If the even number set by the even weight setting procedure included in the currently executed weight setting procedure is equal to zero, the process jumps back to step S102 to execute the next even weight setting procedure (or in practice jumps to the odd weight setting procedure included in the currently executed weight setting procedure). Conversely, if the even number set by the currently executed weight setting procedure is not equal to zero, the process then executes step S104.

[0036] For example, if Figure 10 and Figure 11 As shown, the even number NEVEN set in the five weight setting procedures is 1, 1, 3, 4, and 7, respectively, which are all not equal to zero. This is only an example and the present invention is not limited thereto.

[0037] In step S104, the even bit shift circuit 1011 of the weight equalization circuit 100 determines a plurality of even bits (eg Figure 10 and Figure 11 Whether any of the multiple bit values ​​of the input data DT (the 0th, 2nd, 4th, 6th, 8th, 10th, 12th, and 14th bits) is equal to the first weight value.

[0038] If none of the bit values ​​of the even bits of the input data DT is equal to the first weight value, step S105 is executed. Conversely, if any of the bit values ​​of the even bits of the input data DT is equal to the first weight value, step S106 is executed.

[0039] In step S105 , the even bit shift circuit 1011 of the weight equalization circuit 100 sets one of the even bits of the input data DT (for example, but not limited to, the highest bit among the even bits) as an even initial bit.

[0040] For example, if Figure 10 and Figure 11 As shown, in the first execution of the weight setting procedure (TM=1), the even bit shift circuit 1011 of the first weight equalization circuit 100 sets 14 bits among the multiple bits of the input data DT, which are the most significant bits among the multiple even bits of the input data DT, as even initial bits. An even bit number LPOS of the even initial bit is 14 (step S105).

[0041] In step S106 , the even bit shift circuit 1011 of the weight equalization circuit 100 sets the next even bit (eg, but not limited to, the next lower even bit) of the even bit that was last shifted as an even initial bit.

[0042] For example, if Figure 10 and Figure 11 As shown, in the second execution of the weight setting procedure (TM=2), the even bit shift circuit 1011 of the weight equalization circuit 100 sets the next lower even bit, i.e., the 12th bit, among the 14 bits of the plurality of bits of the input data DT as an even initial bit. The even bit number LPOS of this even initial bit is 12 (step S106).

[0043] In step S107 , the even-numbered shift counting circuit 1012 of the weight equalization circuit 100 adjusts the bit values ​​of all the even-numbered bits of the input data DT to be unequal to the first weight value.

[0044] That is, if the bit value of one or more even bits of the input data DT was adjusted to the first weight value in the last even weight setting procedure, the bit values ​​of all the even bits of the previously adjusted input data DT must first be reset to be not equal to the first weight value (step S107).

[0045] In step S108 , the even bit shift circuit 1011 of the weight equalization circuit 100 uses the value obtained by subtracting “1” from the even number set by the even weight setting procedure executed this time as an even bit shift number.

[0046] In step S109 , the even bit shift circuit 1011 of the weight equalization circuit 100 shifts an even number of bits from an even initial bit to other even bits of the input data DT.

[0047] In step S110 , the even shift counting circuit 1012 of the weight equalization circuit 100 adjusts the even initial bit and one or more bit values ​​shifted therefrom to be equal to the first weight value.

[0048] For example, if Figure 10 and Figure 11 As shown, in the first execution of the weight setting process (TM=1), the even number NEVEN is 1. The even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "1" from the even number NEVEN to obtain a value of "0" as an even bit shift number. Therefore, the weight setting process (TM=1) executed this time does not require even bit shifting. Therefore, the even bit shift counter circuit 1012 of the weight equalization circuit 100 only adjusts the 14th bit of the multiple bits of the input data DT, which serves as an even initial bit in the first execution of the weight setting process (TM=1), to equal the first weight value, such as "1".

[0049] Then, if Figure 10 and Figure 11 As shown, in the second execution of the weight setting process (TM=2), the even number NEVEN is 1. The even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "1" from the even number NEVEN to obtain a value of "0" as an even bit shift number. Therefore, the weight setting process (TM=2) executed this time does not require even bit shifting. Therefore, the even bit shift counter circuit 1012 of the weight equalization circuit 100 only adjusts 12 of the multiple bits of the input data DT that serve as even initial bits in the second execution of the weight setting process (TM=2) to equal the first weight value, such as "1".

[0050] Then, if Figure 10 and Figure 11As shown, in the third execution of the weight setting procedure (TM=3), the even bit shift circuit 1011 of the weight equalization circuit 100 uses the next lower bit after the 12th bit last shifted after the second execution of the weight setting procedure (TM=2), that is, the 10th bit, as an even initial bit. The even bit number LPOS of this even initial bit is 10.

[0051] like Figure 10 and Figure 11 As shown, in the third execution of the weight setting procedure (TM=3), the even number NEVEN is 3. The even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "1" from the even number NEVEN "3" to obtain a value of "2" as the even bit shift number. Accordingly, the even bit shift circuit 1011 of the weight equalization circuit 100 sequentially shifts the even bits from the 10th bit, which is an even initial bit, to the two lower even bits, namely the 8th bit and the 6th bit.

[0052] like Figure 10 and Figure 11 As shown, in the third execution of the weight setting procedure (TM=3), the even shift counting circuit 1012 of the weight equalization circuit 100 adjusts the 10th bit of the multiple bits of the input data DT, which is an even initial bit, and the 8th bit and the 6th bit shifted from the 10th bit to be equal to the first weight value, such as "1".

[0053] Then, if Figure 10 and Figure 11 As shown, in the fourth execution of the weight setting procedure (TM=4), the even bit shift circuit 1011 of the weight equalization circuit 100 uses the next lower bit after the 6th bit last shifted after the third execution of the weight setting procedure (TM=3), that is, the 4th bit, as an even initial bit. The even bit number LPOS of this even initial bit is 4.

[0054] like Figure 10 and Figure 11 As shown, in the fourth execution of the weight setting procedure (TM=4), the number of even bits NEVEN is 4. The even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "1" from the even number NEVEN "4" to obtain a value of "3" as the even bit shift number. Accordingly, the even bit shift circuit 1011 of the weight equalization circuit 100 sequentially shifts the even bits from the 4th bit, which is an even initial bit, to the two lower even bits, namely the 2nd bit and the 0th bit.

[0055] like Figure 10 and Figure 11As shown, when the shifted even bit number "2" is less than the even shift bit number "3" and has been shifted to the lowest bit among the multiple even bits of the input data DT, that is, the 0th bit, the even bit shift circuit 1011 of the weight equalization circuit 100 shifts from the 0th bit to the highest even bit, that is, the 14th bit.

[0056] like Figure 10 and Figure 11 As shown, in the fourth execution of the weight setting procedure (TM=4), the even shift counting circuit 1012 of the weight equalization circuit 100 adjusts the 4th bit of the multiple bits of the input data DT, which is an even initial bit, and the 2nd bit, the 0th bit, and the 14th bit sequentially shifted from the 4th bit to be equal to the first weight value, such as "1".

[0057] Then, if Figure 10 and Figure 11 As shown, in the fifth weight setting procedure (TM=5), the even bit shift circuit 1011 of the weight equalization circuit 100 uses the next lower bit after the 14th bit last shifted after the fourth weight setting procedure (TM=4), that is, the 12th bit, as an even initial bit. The even bit number LPOS of this even initial bit is 12.

[0058] like Figure 10 and Figure 11 As shown, in the fifth execution of the weight setting procedure (TM=5), the number of even bits NEVEN is 7. The even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "1" from the even number NEVEN "7" to obtain a value of "6" as the even bit shift number. Accordingly, the even bit shift circuit 1011 of the weight equalization circuit 100 shifts the even bits from the 12th bit, which is an even initial bit, to the six lower even bits, namely the 10th bit, the 8th bit, the 6th bit, the 4th bit, the 2nd bit, and the 0th bit.

[0059] like Figure 10 and Figure 11 As shown, after executing the weight setting procedure five times (TM=5), each of the multiple bit values ​​of the multiple even bits of the input data DT is adjusted to be equal to the weight value "1" twice. Therefore, the multiple bit values ​​of the multiple even bits of the input data DT are adjusted to be equal to the weight value "1" with equal probability.

[0060] As described above, in this embodiment, the highest-order bit of the multiple even-numbered bits of the input data DT is first set as an initial even-numbered bit. Starting from this initial even-numbered bit, the shift is then directed toward the other even-numbered bits with lower bits. When the shift reaches the lowest-order bit of the multiple even-numbered bits, the shift is then returned to the highest-order bit of the multiple even-numbered bits of the input data DT. Then, starting from this highest-order bit, the shift is again directed toward the other even-numbered bits with lower bits. This process is repeated. However, the above is merely an example and the present invention is not limited thereto. In practice, any one of the multiple even-numbered bits of the input data DT can be selected as an initial even-numbered bit based on actual needs, and the direction of the shift from the initial even-numbered bit can also be adjusted.

[0061] After executing step S101, the weight setting procedure is executed multiple times, and each execution of the weight setting procedure includes the even weight setting procedure of steps S102 to S110 and the odd weight setting procedure of steps S202 to S210, wherein the odd weight setting procedure can be executed simultaneously with the even weight setting procedure, or after or before the even weight setting procedure.

[0062] In step S202 , the odd bit shift circuit 1021 of the weight equalization circuit 100 enters the odd weight setting procedure each time.

[0063] In step S203, the odd bit shift circuit 1021 of the weight equalization circuit 100 sets an odd number for the current odd weight setting procedure based on a total usage number X indicated by a total usage number instruction, and determines whether the odd number set in the current execution of the odd weight setting procedure is equal to zero. The odd number set in each execution of the weight setting procedure may be different from the odd number set in other executions of the weight setting procedure.

[0064] If the odd number set by the currently executed odd weight setting procedure is equal to zero, the process returns to step S202 to execute the next odd weight setting procedure (or in practice jumps to the next even weight setting procedure). Conversely, if the odd number set by the currently executed weight setting procedure is not equal to zero, the process proceeds to step S204.

[0065] In step S204 , the odd-bit shift circuit 1021 of the weight equalization circuit 100 determines whether any of the bit values ​​of the odd bits of the input data DT is equal to the first weight value.

[0066] If none of the bit values ​​of the odd bits of the input data DT is equal to the first weight value, step S205 is executed. Conversely, if any of the bit values ​​of the odd bits of the input data DT is equal to the first weight value, step S206 is executed.

[0067] In step S205 , the odd bit shift circuit 1021 of the weight equalization circuit 100 sets one of the odd bits of the input data DT (for example, but not limited to, the least significant bit) as an odd initial bit.

[0068] In step S206 , the odd bit shift circuit 1021 of the weight equalization circuit 100 sets the next odd bit after the last shifted odd bit as an odd initial bit.

[0069] In step S207 , the odd-numbered shift counting circuit 1022 of the weight equalization circuit 100 adjusts the bit values ​​of all odd-numbered bits of the input data DT to be unequal to the first weight value.

[0070] That is, if the bit value of one or more odd bits of the input data DT was adjusted to the first weight value in the previous execution of the odd weight setting program, before setting the weight values ​​of the multiple bit values ​​of the multiple odd bits in each execution of the weight setting program, the multiple bit values ​​of all the multiple odd bits of the input data DT that were previously adjusted must be reset (step S207).

[0071] In step S208 , the odd shift counting circuit 1022 of the weight equalization circuit 100 uses the value obtained by subtracting “1” from the odd number set by the odd weight setting procedure executed this time as an odd shift bit number.

[0072] In step S209 , the odd shift counting circuit 1022 of the weight equalization circuit 100 shifts an odd number of bits from the odd initial bits to other odd bits of the input data DT.

[0073] In step S210 , the odd shift counting circuit 1022 of the weight equalization circuit 100 adjusts the odd initial bit and one or more bit values ​​shifted therefrom to be equal to the first weight value.

[0074] For example, if Figure 10 and Figure 11 As shown, in the first execution of the weight setting procedure (TM=1), the odd number NODD is 0. Accordingly, in the first execution of the weight setting procedure (TM=1), the odd bit shift circuit 1021 of the weight equalization circuit 100 sets the least significant odd bit of the first bit of the input data DT, i.e., the first bit, as an odd initial bit, and an odd bit number RPOS of this odd initial bit is 1.

[0075] Next, in the second execution of the weight setting process (TM=2), the odd number NODD is 1. The odd bit shift circuit 1021 of the weight equalization circuit 100 subtracts "1" from the odd number NODD to obtain a value of "0" as the odd bit shift number. Therefore, the weight setting process (TM=2) executed this time does not require odd bit shifting. Therefore, the odd bit shift counter circuit 1022 of the weight equalization circuit 100 only adjusts the first bit of the multiple bits of the input data DT, which serves as an odd initial bit in the second execution of the weight setting process (TM=2), to be equal to the first weight value, e.g., "1."

[0076] Then, if Figure 10 and Figure 11 As shown, in the third execution of the weight setting procedure (TM=3), the odd bit shift circuit 1021 of the weight equalization circuit 100 uses the third bit, which is the next higher bit after the first bit of an odd initial bit in the second execution of the weight setting procedure (TM=2), as an odd initial bit. The odd bit number RPOS of this odd initial bit is 3.

[0077] like Figure 10 and Figure 11 As shown, in the third execution of the weight setting process (TM=3), the odd number NODD is 2. The odd bit shift circuit 1021 of the weight equalization circuit 100 subtracts 1 from the odd number NODD "2" to obtain a value of "1" as the odd bit shift number. Accordingly, the odd bit shift circuit 1021 of the weight equalization circuit 100 sequentially shifts the odd bit from the third bit, which is an odd initial bit, to the next higher odd bit, i.e., the fifth bit.

[0078] like Figure 10 and Figure 11 As shown, in the third execution of the weight setting procedure (TM=3), the odd shift counting circuit 1022 of the weight equalization circuit 100 adjusts the third bit of the multiple bits of the input data DT, which is an odd initial bit, and the fifth bit shifted from the third bit to be equal to the first weight value, e.g., "1".

[0079] Then, if Figure 10 and Figure 11 As shown, in the fourth execution of the weight setting procedure (TM=4), the odd bit shift circuit 1021 of the weight equalization circuit 100 uses the next higher bit after the 5th bit shifted in the third execution of the weight setting procedure (TM=3), that is, the 7th bit, as an odd initial bit. The odd bit number RPOS of this odd initial bit is 7.

[0080] In the fourth weight setting process (TM=4), the number of odd bits NODD is 4. The odd bit shift circuit 1021 of the weight equalization circuit 100 subtracts 1 from the number of odd bits NODD (4) to obtain a value of 3 as the number of odd bits to shift. Accordingly, the odd bit shift circuit 1021 of the weight equalization circuit 100 shifts the odd bits from the 7th bit, which is an odd initial bit, to the three higher odd bits, namely the 9th bit, the 11th bit, and the 13th bit.

[0081] like Figure 10 and Figure 11 As shown, in the fourth execution of the weight setting procedure (TM=4), the odd shift counting circuit 1022 of the weight equalization circuit 100 adjusts the 7th bit of the multiple bits of the input data DT, which is an odd initial bit, and the 9th bit, 11th bit, and 13th bit sequentially shifted from the 7th bit to be equal to the first weight value, such as "1".

[0082] Then, if Figure 10 As shown, in the fifth execution of the weight setting procedure (TM=5), the odd bit shift circuit 1021 of the weight equalization circuit 100 uses the next higher bit after the 13th bit shifted in the fourth execution of the weight setting procedure (TM=4), that is, the 15th bit, as an odd initial bit. The odd bit number RPOS of this odd initial bit is 15.

[0083] like Figure 10 As shown, in the fifth weight setting procedure (TM=5), the odd number NODD is 6, and the odd bit shift circuit 1021 of the weight equalization circuit 100 subtracts "1" from the odd number NODD "6" to obtain a value "5" as an odd bit shift number.

[0084] like Figure 10 As shown, when the bit shift has been shifted to the 15th bit, which is the highest odd bit among the multiple odd bits of the input data DT, the odd bit shift circuit 1021 of the weight equalization circuit 100 shifts from the 15th bit, which is the highest odd bit, to the 1st bit, which is the lowest odd bit, and then shifts from the 1st bit to the 3rd bit, the 5th bit, the 7th bit, and the 9th bit in sequence.

[0085] like Figure 10As shown, in the fifth execution of the weight setting procedure (TM=5), the odd shift counting circuit 1012 of the weight equalization circuit 100 adjusts the 15th bit of the multiple bits of the input data DT, which is an odd initial bit, and the 1st bit, 3rd bit, 5th bit, 7th bit and 9th bit sequentially shifted from the 15th bit to be equal to the first weight value, such as "1".

[0086] like Figure 11 As shown, in the fourth weight setting process (TM=4), the most significant bit among the odd bits of the input data DT is the 13th bit. Therefore, in the fifth weight setting process (TM=5), the number of odd bits NODD is 6, and the odd bit shifting circuit 1021 of the weight equalization circuit 100 again uses the least significant bit among the odd bits of the input data DT as an odd initial bit, and shifts the bits sequentially from the first bit to the third bit, the fifth bit, the seventh bit, the ninth bit, and the eleventh bit.

[0087] like Figure 11 As shown, in the fifth execution of the weight setting procedure (TM=5), the odd shift counting circuit 1012 of the weight equalization circuit 100 adjusts the first bit of the multiple bits of the input data DT, which is an odd initial bit, and the third bit, fifth bit, seventh bit, ninth bit, and eleventh bit sequentially shifted from the first bit to be equal to the first weight value, e.g., “1”.

[0088] like Figure 10 and Figure 11 As shown, in the five weight setting procedures (TM=1 to 5) performed, each of the bit values ​​of the odd bits of the input data DT is adjusted to be equal to the weight value "1" once or twice.

[0089] As described above, after the weight setting procedure of the parity data weight equalization method of the present invention is executed multiple times, multiple bit values ​​of the input data DT (including multiple bit values ​​of multiple even bits and multiple bit values ​​of multiple odd bits) are adjusted multiple times, so that the probabilities of the multiple bit values ​​of the input data DT being adjusted to be equal to the first weight value are close to each other and are all close to a probability average value.

[0090] As described above, in this embodiment, the highest-order bit among the odd bits of the input data DT is first set as an initial odd bit. Starting from this initial odd bit, the bits are shifted toward the other odd bits with higher orders, until the highest-order bit among the odd bits is reached. The bits are then shifted back to the lowest-order bit among the odd bits of the input data DT. Then, the bits are shifted again from this lowest-order bit toward the other odd bits with higher orders, and this process is repeated. The above is merely an example, and the present invention is not limited thereto. In practice, any one of the odd bits of the input data DT can be selected as an initial odd bit based on actual needs, and the direction of the shift from the initial odd bit can also be adjusted.

[0091] See also Figure 3 and Figure 13 ,in Figure 3 This is a process diagram of the steps of initially setting multiple bit values ​​of input data to second weight values ​​in the method for equalizing the weight of parity data according to an embodiment of the present invention. Figure 12 and Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0092] The method for equalizing the weight of parity data of the present invention may further include: Figure 3 Steps S301 to S305 are shown.

[0093] In each execution of the weight setting procedure, before setting any one or more of the multiple bit values ​​of the multiple even bits of the input data DT to be equal to the first weight value, such as "1" (steps S108 to S110), the even shift counting circuit 1012 of the weight equalization circuit 100 may initially set or reset each of the multiple even bit values ​​of the input data DT to be equal to the second weight value, such as "0" (step S301).

[0094] Furthermore, when an even initial bit of the input data DT and one or more bit values ​​shifted therefrom are adjusted to be equal to the first weight value (step S110), the even shift counting circuit 1012 of the weight equalization circuit 100 may set the first weight value to "1" and adjust an even initial bit of the input data DT and each bit value shifted therefrom from the second weight value "0" to be equal to the first weight value "1" (step S302).

[0095] On the other hand, in each execution of the weight setting procedure, before setting any one or more of the multiple bit values ​​of the multiple odd bits of the input data DT to be equal to the first weight value, such as "1" (steps S108 to S110), the odd shift counting circuit 1022 of the weight equalization circuit 100 may initially set or reset each of the multiple odd bit values ​​of the input data DT to be equal to the second weight value, such as "0" (step S303).

[0096] Furthermore, when an odd initial bit of the input data DT and one or more bit values ​​shifted therefrom are adjusted to be equal to the first weight value (step S110), the odd shift counting circuit 1022 of the weight equalization circuit 100 can set the first weight value to "1" and adjust an odd initial bit of the input data DT and each bit value shifted therefrom from the second weight value "0" to be equal to the first weight value "1" (step S304).

[0097] like Figure 12 As shown, the weight equalization circuit 100 may use the adjusted input data DT as an adjustment data ENOVRG (step S305). The adjustment data ENOVRG may include a plurality of sub-adjustment data generated in a plurality of weight setting procedures, each sub-adjustment data having the same number of bits as the input data DT.

[0098] like Figure 13 As shown, the even shift counting circuit 1012 of the weight equalization circuit 100 may use the bit values ​​of the multiple even bits of the adjusted input data DT as the bit values ​​of the multiple even bits of the even adjustment data, and may use the bit values ​​of the multiple odd bits of the adjusted input data DT as the bit values ​​of the multiple odd bits of the odd adjustment data (step S305). The adjustment data ENOVRG output after each execution of the weight setting process includes an even adjustment data ENRG and an odd adjustment data OVRG.

[0099] See also Figure 4 and Figure 13 ,in Figure 4 This is a process diagram of a method for equalizing the weight of parity data according to an embodiment of the present invention, which controls the weight values ​​of multiple bits of input data. Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0100] The method for equalizing the weight of parity data of the present invention may further include: Figure 4 Steps S401 to S404 are executed after the step S305 generates an adjustment data ENOVRG (including an even adjustment data ENRG and an odd adjustment data OVRG).

[0101] In step S401, Figure 12 The illustrated weight equalization circuit 100 (which may be based on an external component control command received from an external instruction circuit) sets the bit values ​​of the input data DT to multiple bit numbers 0 through (n-1) corresponding to the multiple components A0 through An-1, respectively. These multiple components A0 through An-1 may be any electronic components, where the bit number "n" represents the number of bits in the input data DT. The weight equalization circuit 100 outputs the multiple bit values ​​of the adjusted data ENOVRG (i.e., the adjusted input data DT) to the corresponding multiple components A0 through An-1.

[0102] In detail, Figure 13 The even bit shift circuit 1011 of the weight equalization circuit 100 sets a plurality of even bits of the input data DT (eg, bit numbers are, for example but not limited to, Figure 10 or Figure 11 The even-numbered bits (A0, A2, A4, A6, A8, A10, A12, and A14) shown correspond to respective ones of the plurality of elements A0 through An-1. The weight equalization circuit 100 outputs the values ​​of the even-numbered bits of the adjusted data ENOVRG (i.e., the adjusted input data DT) to the corresponding plurality of elements A0 through An-1.

[0103] like Figure 13 As shown, the odd bit shift circuit 1021 of the weight equalization circuit 100 sets a plurality of odd bits of the input data DT (for example, the bit numbers are as follows Figure 11 A1, A3, A5, A7, A9, A11, A13 or as shown Figure 10 The odd-numbered bits (A1, A3, A5, A7, A9, A11, A13, and A15) shown correspond to respective ones of the plurality of elements A0 through An-1. The weight equalization circuit 100 outputs the values ​​of the odd-numbered bits of the adjusted data ENOVRG (i.e., the adjusted input data DT) to the corresponding plurality of elements A0 through An-1.

[0104] In step S402 , each of the plurality of components A0 to An- 1 determines whether the one-bit value received from the weight equalization circuit 100 is equal to the first weight value.

[0105] In step S403, if the one-bit value received by any one of the multiple components A0 to An-1 is not equal to the first weight value (and equal to the second weight value), the one or more of the multiple components A0 to An-1 that receive the one-bit value not equal to the first weight value (and equal to the second weight value) are closed.

[0106] In step S404 , if the one-bit value received by any one of the plurality of components A0 to An-1 is equal to the first weight value, one or more of the plurality of components A0 to An-1 that receive the one-bit value equal to the first weight value are turned on.

[0107] In the parity data weight equalization method of the present invention, multiple bit values ​​of adjustment data ENOVRG generated by repeatedly executing a weight setting process on input data DT can be output to components A0 to An-1. This is used to control the components A0 to An-1 so that the components A0 to An-1 are activated or used in a nearly even manner. In other words, the probability of each component A0 to An-1 being activated or used is the same as, or close to, the probability of each of the other components A0 to An-1 being activated or used.

[0108] See also Figure 5 and Figure 13 ,in Figure 5 FIG1 is a process diagram of setting the even number and odd number of steps in the method for equalizing the weight of even and parity data according to an embodiment of the present invention. Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0109] The method for equalizing the weight of parity data of the present invention may further include: Figure 5 Steps S501 to S502 are shown.

[0110] After the weight equalization circuit 100 obtains a total usage quantity X for executing each weight setting process from a total usage quantity instruction (step S101), it enters the weight setting process, including entering the even weight setting process (step S102) and entering the odd weight setting process (step S202).

[0111] Next, the odd bit shift circuit 1021 of the weight equalization circuit 100 unconditionally rounds down the calculated value obtained by dividing the total number of used items X in each weight setting process by 2, and uses the result as an odd number (step S501), which is expressed by the following equation:

[0112] NODD=INT(X / 2),

[0113] Wherein NODD represents an odd number, and X represents a total used number (which is the number of components A0 to An-1 that are turned on).

[0114] Next, in each execution of the weight setting process, the even bit shift circuit 1011 of the weight equalization circuit 100 can be connected to the odd bit shift circuit 1021 to obtain an odd number. Then, the total used number X is subtracted from the odd number, and the resulting value is used as an even number (step S502), which is expressed by the following equation:

[0115] NEVEN=X–NODD,

[0116] Wherein NEVEN represents an even number, NODD represents an odd number, and X represents a total used number (which is the number of components A0 to An-1 that are turned on).

[0117] After executing step S501, the odd weight setting procedure of steps S203 to S210 is executed in sequence. After executing steps S501 to S502 in sequence, the even weight setting procedure of steps S103 to S110 is executed in sequence.

[0118] See also Figure 6 、 Figure 10 、 Figure 11 and Figure 13 ,in Figure 6 FIG1 is a process diagram of the steps of initially setting the even initial bits of the method for equalizing the weight of parity data according to an embodiment of the present invention. Figure 10 and Figure 11 Schematic diagram of the weight values ​​output by the method and system for equalizing the weight of parity data according to an embodiment of the present invention after executing a weight setting procedure on input data. Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0119] The method for equalizing the weight of parity data of the present invention may further include: Figure 6 Steps S601 to S605 are shown.

[0120] After the even-bit shift circuit 1011 of the weight equalization circuit 100 receives an input data DT and a total usage quantity instruction from an external indication circuit in step S101 , step S601 is executed.

[0121] In step S601, the even bit shift circuit 1011 of the weight equalization circuit 100 sequentially numbers a plurality of even bits in the input data DT from the least significant bit LSB to the most significant bit MSB with a plurality of bit numbers (step S601). These plurality of bit numbers are all even values, for example Figure 10 and Figure 11 The numbers shown are 0, 2, 4, 6, 8, 10, 12, and 14 respectively.

[0122] After step S601 is executed, the above steps S102 to S104 are executed in sequence.

[0123] When it is determined in step S104 that none of the bit values ​​of the even bits of the input data DT is equal to the first weight value, the following steps are performed: Figure 6Steps S602 to S605 are shown to implement step S105 of setting a most significant bit among a plurality of even bits of the input data DT as an even initial bit.

[0124] In step S602 , the even-numbered bit shift circuit 1011 of the weight equalization circuit 100 determines whether the number of bits of the input data DT is an even value.

[0125] If the number of bits of the input data DT is an even value, step S603 is executed. On the contrary, if the number of bits of the input data DT is not an even value (but an odd value), step S604 is executed.

[0126] In step S603, the even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "2" from the number of bits of the input data DT, and the resulting value is used as an even initial bit number, which can be expressed as follows:

[0127] LPOS=N–2

[0128] Wherein LPOS represents a bit number of an even initial bit, and N represents the number of bits of the input data DT.

[0129] For example, if Figure 10 As shown, in the first execution of the weight setting process (TM=1), the number of bits of the input data DT is 16, which is an even value. The 16 bits of the input data DT are numbered with a plurality of bit numbers 0 to 15. The even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "2" from the number of bits "16" of the input data DT to obtain a value "14" as an even initial bit number.

[0130] In step S604, the even bit shift circuit 1011 of the weight equalization circuit 100 decrements the number of bits of the input data DT by "1", and the resulting value is used as an even initial bit number, which can be expressed as follows:

[0131] LPOS=N–1,

[0132] Wherein LPOS represents a bit number of an even initial bit, and N represents the number of bits of the input data DT.

[0133] For example, if Figure 11 As shown, in the first execution of the weight setting process (TM=1), the number of bits of the input data DT is 15, which is an even value. The 16 bits of the input data DT are numbered with a plurality of bit numbers 0 to 14. The even bit shift circuit 1011 of the weight equalization circuit 100 subtracts "1" from the number of bits "15" of the input data DT to obtain a value "14" as an even initial bit number.

[0134] In step S605 , the even bit shift circuit 1011 of the weight equalization circuit 100 sets an even bit having a bit number identical to an even initial bit number as an even initial bit.

[0135] When executing step S605, the above steps S107 to S110 are executed in sequence.

[0136] See also Figure 7 、 Figure 10 、 Figure 11 and Figure 13 ,in Figure 7 FIG1 is a process diagram of the steps of initially setting the odd initial bits of the method for equalizing the weight of parity data according to an embodiment of the present invention. Figure 10 and Figure 11 Schematic diagram of the weight values ​​output by the method and system for equalizing the weight of parity data according to an embodiment of the present invention after executing a weight setting procedure on input data. Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0137] The method for equalizing the weight of parity data of the present invention may further include: Figure 7 Steps S701 to S703 are shown.

[0138] In step S701, the odd bit shift circuit 1021 of the weight equalization circuit 100 sequentially numbers a plurality of odd bits in the input data DT from the least significant bit (LSB) to the most significant bit (MSB) with a plurality of bit numbers (step S601). These plurality of bit numbers are all odd values, for example Figure 10 The order shown is 1, 3, 5, 7, 9, 11, 13, 15 or as shown Figure 11 The numbers shown are 1, 3, 5, 7, 9, 11, and 13 respectively.

[0139] After step S701 is executed, the above steps S202 to S204 are executed in sequence.

[0140] When it is determined in step S104 that none of the bit values ​​of the odd bits of the input data DT is equal to the first weight value, the following steps are performed: Figure 7 Steps S702 to S703 are shown to implement step S205 of setting a least significant bit among a plurality of odd bits of the input data DT as an odd initial bit.

[0141] In step S702 , the odd bit shift circuit 1021 of the weight equalization circuit 100 sets an odd initial bit number to 1.

[0142] In step S703 , the odd bit shift circuit 1021 of the weight equalization circuit 100 sets an odd bit having a bit number identical to an odd initial bit number “1” as an odd initial bit.

[0143] For example, if Figure 10 and Figure 11 As shown, the odd number NODD of the second weight setting process (TM=2) is 1 instead of zero (step S203), and none of the odd bits of the input data DT after the first weight setting process (TM=1) has a bit value equal to the first weight value "1" (step S204). In this case, an odd bit having a bit number identical to an odd initial bit number "1" is set as an odd initial bit, and an odd bit number RPOS of this odd initial bit is 1.

[0144] After step S701 is executed, the above steps S207 to S210 are executed in sequence.

[0145] See also Figure 8 、 Figure 10 、 Figure 11 and Figure 13 ,in Figure 8 FIG1 is a process diagram of the subsequent steps of setting the even initial bits in the method for equalizing the weight of parity data according to an embodiment of the present invention. Figure 10 and Figure 11 Schematic diagram of the weight values ​​output by the method and system for equalizing the weight of parity data according to an embodiment of the present invention after executing a weight setting procedure on input data. Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0146] The method for equalizing the weight of parity data of the present invention may further include: Figure 8 Steps S801 to S806 are shown.

[0147] When it is determined in step S104 that any one of the bit values ​​of the even bits of the input data DT is equal to the first weight value, the following steps are executed: Figure 8 Steps S801 to S806 are shown to implement step S106 of setting the next even bit after the even bit that was last shifted as an even initial bit.

[0148] In step S801, the even bit shift circuit 1011 of the weight equalization circuit 100 subtracts twice an even number from the bit number of the even bit that was last shifted to obtain a value as an even initial bit number, which is expressed as:

[0149] LPOS(i)=LPOS(i-1)-2×NEVEN(i-1),

[0150] Wherein LPOS(i) represents an even initial bit number of a weight setting procedure executed for the i-th time (i.e., the bit number of an even initial bit mentioned above), LPOS(i-1) represents an even initial bit number of a weight setting procedure executed for the (i-1)th time (i.e., the bit number of an even initial bit described in this article), i is a positive value, and NEVEN(i-1) represents an even number of a weight setting procedure executed for the (i-1)th time.

[0151] For example, if Figure 10 and Figure 11 As shown, an even initial even bit number LPOS "14" of the first executed weight setting procedure (TM=1) is subtracted from twice the value "2" of an even number NEVEN "1" of the first executed weight setting procedure (TM=1) to obtain a value "12" as an even initial even bit number LPOS in the second executed weight setting procedure (TM=2).

[0152] For example, if Figure 10 and Figure 11 As shown, an even initial even bit number LPOS "12" of the second execution of the weight setting procedure (TM=2) is subtracted from twice the value "2" of an even number NEVEN "1" of the second execution of the weight setting procedure (TM=2) to obtain a value "10" as an even initial even bit number LPOS in the third execution of the weight setting procedure (TM=3).

[0153] For example, if Figure 10 and Figure 11 As shown, an even initial even bit number LPOS "10" of the third execution of the weight setting procedure (TM=3) is subtracted from twice the value "6" of an even number NEVEN "3" of the third execution of the weight setting procedure (TM=3) to obtain a value "4" as an even initial even bit number LPOS in the fourth execution of the weight setting procedure (TM=4).

[0154] In step S802 , the even bit shift circuit 1011 of the weight equalization circuit 100 determines whether an even initial bit number is smaller than zero.

[0155] If the even initial bit number is not less than zero, then step S806 is directly executed. On the contrary, if the even initial bit number is less than zero, then step S803 is executed.

[0156] In step S803 , the even-numbered bit shift circuit 1011 of the weight equalization circuit 100 determines whether the number of bits of the input data DT is an even value.

[0157] If the number of bits of the input data DT is an even value, steps S804 and S806 are executed in sequence. Conversely, if the number of bits of the input data DT is not an even value (but an odd value), steps S805 and S806 are executed in sequence.

[0158] In step S804, the even bit shift circuit 1011 of the weight equalization circuit 100 adds the even initial bit number to the number of bits of the input data DT, which is expressed as follows:

[0159] If LPOS<0, LPOS=LPOS(i)+N,

[0160] Wherein LPOS(i) represents an even-numbered initial bit number obtained each time step S801 is executed, LPOS represents an even-numbered initial bit number obtained each time step S804 is executed, and N represents the number of bits of the input data DT.

[0161] For example, if Figure 10 As shown, the even initial even bit number LPOS "4" of the fourth weight setting procedure (TM=4) is subtracted from the double value "8" of the even number NEVEN "4" of the fourth weight setting procedure (TM=4) to obtain a value "-4" (step S802), which is less than zero. Therefore, the number of bits "16" of the input data DT is added to this value "-4" to obtain a value "12" as the even initial even bit number LPOS of the fifth weight setting procedure (TM=5) (step S804).

[0162] In step S805, the even bit shift circuit 1011 of the weight equalization circuit 100 adds the even initial bit number to the number of bits of the input data DT and then adds 1, which is expressed as:

[0163] If LPOS<0,LPOS=LPOS(i)+(N+1),

[0164] Wherein LPOS(i) represents an even-numbered initial bit number obtained each time step S801 is executed, LPOS represents an even-numbered initial bit number obtained each time step S805 is executed, and N represents the number of bits of the input data DT.

[0165] For example, if Figure 11As shown, the even initial even bit number LPOS "4" of the fourth weight setting procedure (TM=4) is subtracted from the even number NEVEN "4" of the fourth weight setting procedure (TM=4), which is twice the value "8" to obtain a value "-4" (step S802), which is less than zero. Therefore, this value "-4" is added to the number of bits "15" of the input data DT and then added to "1" to obtain a value "12", which is used as the even initial even bit number LPOS of the fifth weight setting procedure (TM=5) (step S805).

[0166] In step S806 , the even bit shift circuit 1011 of the weight equalization circuit 100 sets an even bit having the same bit number as an even initial bit number as an even initial bit.

[0167] After step S806 is executed, the above steps S107 to S110 are executed in sequence.

[0168] See also Figure 9 、 Figure 10 、 Figure 11 and Figure 13 ,in Figure 9 FIG1 is a process diagram of the subsequent steps of setting the odd initial bits in the method for equalizing the weight of parity data according to an embodiment of the present invention. Figure 10 and Figure 11 Schematic diagram of the weight values ​​output by the method and system for equalizing the weight of parity data according to an embodiment of the present invention after executing a weight setting procedure on input data. Figure 13 4 is a block diagram of a parity data weight equalization system according to an embodiment of the present invention.

[0169] The method for equalizing the weight of parity data of the present invention may further include: Figure 9 Steps S901 to S906 are shown.

[0170] When it is determined in step S204 that any one of the bit values ​​of the odd bits of the input data DT is equal to the first weight value, the following steps are executed: Figure 9 Steps S901 to S906 are shown to implement step S206 of setting the next odd bit after the last odd bit shifted as an odd initial bit.

[0171] In step S901, the odd bit shift circuit 1021 of the weight equalization circuit 100 adds twice the odd number to the bit number of the last shifted odd bit to obtain a value as an odd initial bit number, which is expressed as:

[0172] RPOS(i)=RPOS(i-1)-2×NODD(i-1),

[0173] Wherein RPOS(i) represents an odd initial bit number of a weight setting procedure executed for the i-th time (i.e., the bit number of an odd initial bit mentioned above), RPOS(i-1) represents an odd initial bit number of a weight setting procedure executed for the (i-1)th time (i.e., the bit number of an odd initial bit mentioned above), i is a positive value, and NODD(i-1) represents an odd number of a weight setting procedure executed for the (i-1)th time.

[0174] For example, if Figure 10 and Figure 11 As shown, an odd initial odd bit number RPOS "1" of the second execution of the weight setting procedure (TM=2) is added to twice the value "2" of an odd number NODD "1" of the second execution of the weight setting procedure (TM=2) to obtain a value "3" as an odd initial odd bit number RPOS in the third execution of the weight setting procedure (TM=3).

[0175] For example, if Figure 10 and Figure 11 As shown, an odd initial odd bit number RPOS "3" of the third execution of the weight setting procedure (TM=3) is added to twice the value "4" of an odd number NODD "2" of the third execution of the weight setting procedure (TM=3) to obtain a value "7" as an odd initial odd bit number RPOS in the fourth execution of the weight setting procedure (TM=4).

[0176] In step S902 , the odd bit shift circuit 1021 of the weight equalization circuit 100 determines whether an odd initial bit number is greater than a value obtained by subtracting “1” from the number of bits of the input data DT.

[0177] If the odd initial bit number is not greater than the value obtained by subtracting "1" from the number of bits in the input data DT, step S906 is executed directly. Conversely, if the odd initial bit number is greater than the value obtained by subtracting "1" from the number of bits in the input data DT, step S903 is executed next.

[0178] In step S903 , the odd-bit shift circuit 1021 of the weight equalization circuit 100 determines whether the number of bits of the input data DT is an even value.

[0179] If the number of bits of the input data DT is an even value, steps S904 and S906 are executed in sequence. Conversely, if the number of bits of the input data DT is not an even value (but an odd value), steps S905 and S906 are executed in sequence.

[0180] In step S904, the odd bit shift circuit 1021 of the weight equalization circuit 100 subtracts the number of bits of the input data DT from the odd initial bit number, which is expressed as follows:

[0181] If RPOS>(N-1), RPOS=RPOS(i)-N,

[0182] RPOS(i) represents an odd initial bit number obtained each time step S901 is executed, RPOS represents an odd initial bit number obtained each time step S904 is executed, and N represents the number of bits of the input data DT.

[0183] In step S905, the odd bit shift circuit 1021 of the weight equalization circuit 100 subtracts the number of bits of the input data DT from the odd initial bit number and adds "1" to obtain a value, which is expressed as follows:

[0184] If RPOS>(N-1), RPOS=RPOS(i)-N+1,

[0185] RPOS(i) represents an odd initial bit number obtained each time step S901 is executed, RPOS represents an odd initial bit number obtained each time step S905 is executed, and N represents the number of bits of the input data DT.

[0186] For example, if Figure 11 As shown, the number of bits "15" of the input data DT is an odd value. An odd initial odd bit number RPOS "7" of the fourth weight setting procedure (TM=4) is added to twice the odd number NODD "4" of the fourth weight setting procedure (TM=4), which is "8", to obtain a value "15" (step S902). This value is greater than the value "14" obtained by subtracting "1" from the number of bits "15" of the input data DT. Therefore, the number of bits "15" of the input data DT is subtracted from this value "15" and then added to obtain a value "1" as an odd initial odd bit number RPOS in the fifth weight setting procedure (TM=5) (step S904).

[0187] In step S906 , the odd bit shift circuit 1021 of the weight equalization circuit 100 sets an odd bit having the same bit number as an odd initial bit number as an odd initial bit.

[0188] After step S906 is executed, the above steps S207 to S210 are executed in sequence.

[0189] It should be understood that the parity data weight equalization method of the present invention includes the following steps: Figure 1Steps S101 to S110, steps S202 to S210, and Figure 3 Steps S301 to S305 shown in FIG. Figure 4 Steps S401 to S404 shown in FIG. Figure 5 Steps S501 to S502 shown in FIG. Figure 6 Steps S601 to S605 shown in FIG. Figure 7 Steps S701 to S703 shown in FIG. Figure 8 Steps S801 to S806 shown in FIG. Figure 9 The execution order of steps S901 to S906 shown can be adjusted appropriately according to actual needs. The above is only an example and the present invention is not limited thereto. In particular, in practice, the odd-weighted process can be executed simultaneously with the even-weighted process, or before or after the even-weighted process.

[0190] See also Figure 14 , which is a circuit diagram of an even shift counting circuit and an even output stage circuit of an even-odd data weight equalization system according to an embodiment of the present invention.

[0191] like Figure 13 The even shift counting circuit 1012 of the parity data weight equalization system of the embodiment of the present invention shown in FIG. 1 may include a plurality of counting circuits 10121 to 10123, such as but not limited to the following: Figure 14 The D-type flip-flop shown in FIG. 1 can be replaced with other types of flip-flops or other types of circuit components with the same function. The multiple counting circuits 10121 to 10123 can be adjusted according to actual needs and are not limited to the following. Figure 14 Quantity shown.

[0192] The plurality of counting circuits 10121 to 10123 correspond to the plurality of bit values ​​of the plurality of even bits of the input data DT, respectively. Figure 14 The counting circuits 10121 to 10123 shown receive bits from the even bit shift circuit 1011. Figure 13 The one-bit value of the corresponding even bit is shown.

[0193] like Figure 14 Each counting circuit 10121 to 10123 shown outputs one bit value "0" or "1" each time, and the combination of the three-bit values ​​output by multiple counting circuits 10121 to 10123 is converted into a one-bit number whose decimal value is an even-numbered bit that needs to be adjusted to the first weight value "1".

[0194] like Figure 13The output stage circuit 200 of the parity data weight equalization system of the embodiment of the present invention may include a plurality of storage components 2011 to 2013, for example but not limited to a plurality of storage components, but in practice, they may also be replaced with other circuit components with the same function. The plurality of storage components 2011 to 2013 may be adjusted according to actual needs and are not limited to the following. Figure 14 Each storage component 2011 to 2013 can store one or more bit values ​​of one or more even-numbered bits.

[0195] The plurality of storage components 2011 to 2013 may store and output bit values ​​received from the phase connection counting circuits 10121 to 10123 .

[0196] See also Figure 15 , which is a circuit diagram of an odd shift counting circuit and an odd output stage circuit of a parity data weight equalization system according to an embodiment of the present invention.

[0197] like Figure 13 The odd shift counting circuit 1022 of the parity data weight equalization system of the embodiment of the present invention shown in FIG. 1 may include a plurality of counting circuits 10221 to 10223, such as but not limited to the following: Figure 14 The D-type flip-flop shown in FIG. 1 can be replaced with other types of flip-flops or other types of circuit components with the same function. The multiple counting circuits 10221 to 10223 can be adjusted according to actual needs and are not limited to the following. Figure 15 Quantity shown.

[0198] The plurality of counting circuits 10221 to 10223 correspond to the plurality of bit values ​​of the plurality of odd bits of the input data DT, respectively. Figure 15 The counting circuits 10221 to 10223 shown receive the bits from the odd bit shift circuit 1021. Figure 13 The corresponding one or more bit values ​​of the one or more odd bits are shown.

[0199] like Figure 12 The counting circuits 10221 to 10223 shown can be configured to respectively Figure 13 The odd bit shift circuit 1021 adjusts the bit values ​​of an odd initial bit and the odd bits to which the odd initial bit is shifted to be equal to a first weight value, such as “1”, each time executing the odd weight setting procedure.

[0200] like Figure 13 The output stage circuit 200 of the parity data weight equalization system of the embodiment of the present invention shown may include a plurality of storage components 2021 to 2023, for example but not limited to a plurality of, but in practice can also be replaced with other circuit components with the same function. The plurality of storage components 2021 to 2023 can be adjusted according to actual needs and are not limited to, for example Figure 14 Each storage component 2021 to 2023 can store one or more bit values ​​of one or more odd bits.

[0201] In summary, the present invention provides a method and system for equalizing parity data weights. In the method and system of the present invention, after executing a weight setting procedure multiple times, multiple bit values ​​of the input data (including multiple bit values ​​of multiple even bits and multiple bit values ​​of multiple odd bits) are adjusted multiple times, so that the probability of the multiple bit values ​​of the input data being adjusted to equal a first weight value is close to each other, and each is close to a probability average.

[0202] If the parity data weight equalization method and system of the present invention are applied to the control of multiple components, the multiple bit values ​​of the input data can correspond to multiple components respectively, so that the probability of multiple components being turned on or used is close to an average probability. Because when the components are manufactured, there are usually differences between each individual component due to process variations, and when the signal output passes through these components, it will cause the output signal to be interfered with by these differences, thereby reducing performance. Through the parity data weight equalization method and system of the present invention, the use probability of all components is made close to the same, and the signal error of the output signal caused by the differences of these components is averaged, thereby further improving the overall performance.

[0203] The contents disclosed above are only preferred feasible embodiments of the present invention and are not intended to limit the claims of the present invention. Therefore, any equivalent technical changes made using the contents of the present invention's description and drawings are included in the claims of the present invention.

Claims

1. A method for equalizing the weight of odd and even data, characterized in that: The method for equalizing the weight of parity data comprises the following steps performed by a weight equalization circuit: (a) determining whether an even number set by a weight setting procedure executed each time is equal to zero, If yes, proceed directly to step (d); if no, proceed to steps (b) to (d) in sequence; (b) in each execution of the weight setting procedure, determining whether any of a plurality of even-numbered bits of input data has a bit value equal to a first weight value; if not, setting one of the plurality of even-numbered bits as an even initial bit; and if so, setting the even bit next to the even bit that was last shifted as the even initial bit; (c) in each execution of the weight setting procedure, using the value obtained by subtracting "1" from the even number as an even-numbered shift bit number, shifting the even-numbered initial bit to the other even-numbered bits by the even-numbered shift bit number, and adjusting the even-numbered initial bit and one or more bit values ​​shifted from the even-numbered initial bit to be equal to the first weight value; (d) determining whether the odd number set in each execution of the weight setting procedure is equal to zero; if so, skipping to step (a) to execute the next weight setting procedure; if not, executing steps (e) to (f) in sequence; (e) in each execution of the weight setting procedure, determining whether any of a plurality of odd-numbered bits of the input data has a bit value equal to the first weight value; if not, setting one of the plurality of odd-numbered bits as an odd initial bit; and if so, setting the odd-numbered bit next to the last shifted odd bit as the odd initial bit; and (f) in each execution of the weight setting procedure, using the value obtained by subtracting "1" from the odd number as an odd bit shift number, shifting the odd bit shift number from the odd initial bit to the other odd bits, and adjusting the odd initial bit and one or more bit values ​​shifted from the odd initial bit to be equal to the first weight value; Then jump to step (a) to execute the next weight setting procedure.

2. The method for equalizing parity data weights according to claim 1, wherein: The method for equalizing the weight of even and parity data further comprises the following steps, which are performed when it is determined in step (b) that any one of the bit values ​​of the even bits of the input data is equal to the first weight value: Setting each of the plurality of bit values ​​of the input data to be equal to a second weight value; as well as The second weight value is set to be different from the first weight value.

3. The method for equalizing parity data weights according to claim 2, wherein: The method for equalizing the weight of parity data further comprises the following steps: Setting one of the second weight value and the first weight value to 0; and The other of the second weight value and the first weight value is set to 1.

4. The method for equalizing parity data weights according to claim 1, wherein: The method for equalizing the weight of parity data further comprises the following steps performed before step (a): receiving the input data and a total usage quantity instruction; obtaining a plurality of total usage quantities in the weight setting procedures executed multiple times as indicated by the total usage quantity instruction; In each execution of the weight setting procedure, the total used quantity is divided by 2 and the result is rounded down unconditionally to obtain a value as the odd number; and In each execution of the weight setting procedure, the odd number is subtracted from the total usage number to obtain a value as the even number.

5. The method for equalizing parity data weights according to claim 1, wherein: Step (a) comprises: In each execution of the weight setting procedure, it is determined whether any of the multiple bit values ​​of the multiple even bits of the input data is equal to the first weight value. If not, the highest bit is selected from the multiple even bits of the input data as the even initial bit. If so, the even bit that is the next lower bit of the even bit that was previously shifted last is selected as the even initial bit.

6. The method for equalizing parity data weights according to claim 1, wherein: Step (c) comprises: In each execution of the weight setting procedure, it is determined whether any of the multiple bit values ​​of the multiple odd bits of the input data is equal to the first weight value. If not, the lowest bit is selected from the multiple odd bits of the input data as the odd initial bit. If so, the odd bit that is the next higher bit of the odd bit that was previously last shifted is selected as the odd initial bit.

7. The method for equalizing parity data weights according to claim 1, wherein: The method for equalizing the weight of parity data further comprises the following steps performed before step (a): The plurality of odd bits and the plurality of even bits of the input data are sequentially numbered with a plurality of bit numbers from the least significant bit to the most significant bit.

8. The method for equalizing parity data weights according to claim 7, wherein: The method for equalizing the weight of even and parity data further comprises the following steps, which are performed when it is determined in step (a) that none of the bit values ​​of the even bits of the input data is equal to the first weight value: Determining whether the number of bits of the input data is an even value, and if so, using the value obtained by subtracting "2" from the number of bits of the input data as an even initial bit number; if not, using the value obtained by subtracting "1" from the number of bits of the input data as the even initial bit number; and The even bit having the same bit number as the even initial bit number is set as the even initial bit.

9. The method for equalizing parity data weights according to claim 8, wherein: The method for equalizing the weight of even and odd data further comprises the following steps, which are performed when it is determined in step (c) that none of the bit values ​​of the odd bits of the input data is equal to the first weight value: Set an odd initial bit number to 1; as well as The odd bit having the same bit number as the odd initial bit number is set as the odd initial bit.

10. The method for equalizing parity data weights according to claim 9, wherein: The method for equalizing the weight of even and parity data further comprises the following steps, which are performed when it is determined in step (a) that any one of the bit values ​​of the even bits of the input data is equal to the first weight value: Subtracting twice the number of even bits in the previous weight setting procedure from the bit number of the last shifted even bit to obtain a value as the even initial bit number of the weight setting procedure executed this time; and The even-numbered bit having the same bit number as the even-numbered initial bit number is set as the even-numbered initial bit of the weight setting procedure executed this time.

11. The method for equalizing parity data weights according to claim 10, wherein: The method for equalizing the weight of parity data comprises the following steps performed after step (a): Determine whether the even initial bit number is less than zero, if not, do not execute the next step, if yes, execute the next step; and Determine whether the number of bits of the input data is an even value. If so, add the even initial bit number to the number of bits of the input data. If not, add the even initial bit number to the number of bits of the input data and then add 1.

12. The method for equalizing parity data weights according to claim 11, wherein: The method for equalizing the weight of even and odd data further comprises the following steps, which are performed when it is determined in step (c) that any one of the bit values ​​of the odd bits of the input data is equal to the first weight value: Adding twice the odd number of the previous weight setting procedure to the bit number of the last shifted odd bit to obtain a value as the odd initial bit number of the weight setting procedure executed this time; and The odd bit having the same bit number as the odd initial bit number is set as the odd initial bit of the weight setting procedure executed this time.

13. The method for equalizing parity data weights according to claim 12, wherein: The method for equalizing the weight of even and odd data further comprises the following steps performed after step (a): Subtract 1 from the number of bits of the input data to obtain a value as a bit number operation value; Determine whether the odd initial bit number is greater than the bit number calculation value, if not, do not execute the next step, if so, execute the next step; and Determine whether the number of bits of the input data is an even value. If so, subtract the number of bits of the input data from the odd initial bit number. If not, subtract the number of bits of the input data from the odd initial bit number and add 1.

14. The method for equalizing parity data weights according to claim 1, wherein: The method for equalizing the weight of even and odd data further comprises the following steps performed after step (d): Setting the plurality of bit values ​​of the input data to correspond to a plurality of components respectively; and Determine whether the bit value corresponding to each of the components is equal to the first weight value; if not, turn off the components corresponding to each of the bit values ​​equal to the first weight value; if so, turn on the components corresponding to each of the bit values ​​equal to the first weight value.

15. A parity data weight equalization system, characterized in that: The parity data weight equalization system comprises: a weight equalization circuit configured to execute a weight setting procedure multiple times; wherein, in the first execution of the weight setting procedure, the weight equalization circuit sets any one of a plurality of bit values ​​of a plurality of even bits of input data as an even initial bit, and in subsequent executions of the weight setting procedure, sets the next even bit after the last shifted even bit as the even initial bit; When the weight setting procedure is executed each time and the set even number is not equal to zero, the weight equalization circuit uses the value obtained by subtracting "1" from the even number as an even shift bit number, shifts the even shift bit number from the even initial bit to the other even bits, and adjusts the even initial bit and one or more bit values ​​shifted from the even initial bit to equal a first weight value; wherein, in the first execution of the weight setting procedure, the weight equalization circuit sets any one of a plurality of bit values ​​of a plurality of odd bits of the input data as an odd initial bit, and in subsequent executions of the weight setting procedure, the even bit next to the odd bit that was last shifted is used as the odd initial bit; When an odd number set by the weight setting program executed each time is not equal to zero, the weight equalization circuit uses the value obtained by subtracting "1" from the odd number as an odd shift bit number, shifts the odd shift bit number from the odd initial bit to other odd bits, and adjusts the odd initial bit and one or more bit values ​​shifted from the odd initial bit to be equal to the first weight value.

16. The parity data weight equalization system according to claim 15, characterized in that: Before performing the shift in each execution of the weight setting procedure, the weight equalization circuit sets each of the plurality of bit values ​​of the input data to be equal to a second weight value.

17. The parity data weight equalization system according to claim 15, characterized in that: The weight equalization circuit corresponds the adjusted multiple bit values ​​of the input data to multiple components respectively; wherein the weight equalization circuit turns on the components corresponding to the bit values ​​in the adjusted input data that are equal to the first weight value; The weight equalization circuit turns off the components corresponding to the bit values ​​of the adjusted input data that are not equal to the first weight value.

18. The parity data weight equalization system according to claim 15, characterized in that: In each execution of the weight setting procedure, the weight equalization circuit divides the total used number by 2 and rounds down the result unconditionally as the odd number, and subtracts the odd number from the total used number as the even number.

19. The parity data weight equalization system according to claim 15, characterized in that: The weight equalization circuit comprises: an even bit shift circuit configured to set the even initial bit, count and set the even shift bit number, and shift the even shift bit number from the even initial bit to the other even bits; an even-numbered shift counting circuit, connected to the even-numbered bit shift circuit and an output stage circuit, configured to count up the even-numbered initial bit of the input data and one or more bit values ​​shifted from the even-numbered initial bit to the first weight value; an odd bit shift circuit configured to set the odd initial bit, count and set the odd shift bit number, and shift the odd shift bit number from the odd initial bit to the other odd bits; and an odd bit shift counting circuit connected to the odd bit shift circuit and the output stage circuit, configured to count up the odd initial bit of the input data and one or more bit values ​​shifted from the odd initial bit to the first weight value; The output stage circuit stores the adjusted input data.

20. The parity data weight equalization system according to claim 19, wherein: The output stage circuit outputs the adjusted bit values ​​of the input data to a plurality of components respectively.

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