Double-tail comparator circuit for pixel sensor column end ADC and operation method

Abstract

The invention provides a double-tail comparator circuit used for a pixel sensor column end ADC and an operation method, and solves the technical problem that the high kickback noise and the imbalance phenomenon of a comparator cannot be overcome in a high-frequency scene in the prior art. The circuit comprises an input differential pair transistor, and further comprises a latch module and a correction capacitor module, and the latch module is connected with the input differential pair transistor and the correction capacitor module; the input differential pair transistors are used for providing input stage transconductance and rapid noise discharge voltage; the latch module is used for reducing the amplitude of kickback noise and shortening the transient process of the kickback noise; and the correction capacitor module is used for modulating the size of the correction capacitor and compensating the offset of the comparator. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and more specifically, relates to a double-tail comparator circuit and an operating method for a column-side ADC of a pixel sensor. Background Art

[0002] The comparator is a key module in an ADC (analog-to-digital converter). Its function is to compare the voltage amplitudes of two input signals and output the corresponding binary comparison result. Essentially an open-loop, high-gain amplifier, the comparator is crucial to the performance of the SAR-ADC (successive approximation register ADC). Because pixel sensors used for high-energy particle detection must operate at extremely high frame rates, the comparators in their column-level SAR-ADCs must achieve low noise while maintaining high speed operation and minimize circuit area to increase the sensor's effective sensitive area.

[0003] Traditional latch comparators introduce high kickback noise to the input end. This noise is transient noise introduced during the operation of the comparator due to the change in the output voltage coupled by the parasitic capacitance of the MOS tube. If the transient noise cannot be completely reset between two adjacent comparisons of the comparator, it may affect the conversion accuracy of the ADC. The existing Chinese invention patent with application number CN202311676115.8 proposes a comparator, analog-to-digital converter and device for reducing kickback noise, which uses the synergistic effect of the isolation switch module and the neutralization capacitor module to reduce the kickback noise. However, this patent cannot discharge the accumulated charge on the parasitic capacitance of the high-resistance node, and there is a problem of incomplete comparator establishment in high-frequency scenarios. Not only can it not solve the kickback noise of the comparator in high-frequency scenarios, but it can also cause imbalance due to the accumulated charge.

[0004] Existing methods for comparator offset compensation include pre-amplifier compensation and input / output offset storage. These offset compensation methods all require the use of an active amplifier to amplify the input voltage, ensuring the amplifier is fully settled during the comparison process. Comparators operate at extremely high speeds, placing high demands on the amplifier's bandwidth and slew rate. Consequently, existing offset compensation methods are unable to compensate for comparator offset at extremely high frame rates. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a double-tail comparator circuit for a column-side ADC of a pixel sensor, so as to solve the technical problem that the prior art cannot solve the high kick-back noise and offset phenomenon of the comparator in high-frequency scenarios.

[0006] To achieve the above objectives, a first aspect of an embodiment of the present application provides a double-tail comparator circuit for a column-side ADC of a pixel sensor, comprising: an input differential pair transistor, a latch module, and a correction capacitor module, wherein the latch module is connected to the input differential pair transistor and the correction capacitor module; The input differential pair tubes are used to provide input stage transconductance and quickly discharge noise voltage; The latch module is used to reduce the amplitude of the kickback noise and shorten the transient process of the kickback noise; The correction capacitor module is used to modulate the size of the correction capacitor to compensate for the offset of the comparator.

[0007] Preferably, the latch module includes a positive feedback circuit, a time-controlled switch and a connection switch, wherein the connection switch is connected to the positive feedback circuit; The time-controlled switch is used to disconnect the input differential pair tube and the positive feedback circuit to ensure a stable potential during the reset phase; The connection switch is used to be turned on during the reset phase to ensure that the charges on both sides of the branch are consistent during the reset phase.

[0008] Preferably, the correction capacitor module is a variable capacitor of a PMOS tube, the source and drain of the PMOS tube are short-circuited with the substrate, and the plates serving as the variable capacitor are symmetrically mounted on both sides of the positive feedback circuit. The gate of the PMOS tube serves as the other plate of the variable capacitor and is connected to a control voltage switch, which is used to switch between two high and low control voltages VRP and VRN.

[0009] Preferably, the positive feedback circuit includes a zeroth PMOS transistor M0, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a sixth NMOS transistor M6, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth NMOS transistor M12 and a thirteenth NMOS transistor M13. The sources of the zeroth PMOS transistor M0, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the tenth PMOS transistor M10, and the eleventh PMOS transistor M11 are connected to the power supply, the gate of the zeroth PMOS transistor M0 is connected to the comparison clock, the drain of the zeroth PMOS transistor M0 is connected to the gates of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13, the gate of the second PMOS transistor M2 is connected to the gate of the sixth NMOS transistor M6, the drain of the second PMOS transistor M2 is connected to the time-controlled switch, the gate of the first PMOS transistor M1 is connected to the gate of the ninth NMOS transistor M9, the drain of the first PMOS transistor M1 is connected to the time-controlled switch, the gate of the third PMOS transistor M3 is connected to the comparison clock, and the drain of the third PMOS transistor M3 is connected to the gates of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12. The drains of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 are connected to the input voltage VOP, the source of the thirteenth NMOS transistor M13 is grounded to VSS, the drains of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 are connected to the input voltage VON, and the source of the twelfth NMOS transistor M12 is grounded to VSS.

[0010] Preferably, the sixth NMOS transistor M6 and the ninth NMOS transistor M9 are isolation switches, which are used to isolate the kick-back noise introduced by the change of the comparison clock level during the startup phase, and to offset the positive polarity kick-back noise introduced by the comparison clock and the negative polarity kick-back noise caused by the voltage common mode drop.

[0011] Preferably, the time-controlled switch includes a fourth NMOS transistor M4 and an eighth NMOS transistor M8, wherein the gate of the fourth NMOS transistor M4 is connected to the comparison clock, the source of the fourth NMOS transistor M4 is connected to the isolation switch, the drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M2, the gate of the eighth NMOS transistor M8 is connected to the comparison clock, the source of the eighth NMOS transistor M8 is connected to the isolation switch, and the drain of the eighth NMOS transistor M8 is connected to the drain of the first PMOS transistor M1.

[0012] Preferably, the connection switch is turned on only in the reset phase, and the connection switch is the fourteenth NMOS transistor M14. The source of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistors, the gate of the fourteenth NMOS transistor M14 is connected to the comparison clock, and the drain of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistors.

[0013] A second aspect of an embodiment of the present application provides a method for operating a double-tail comparator for a column-side ADC of a pixel sensor, comprising the following steps: inputting a low-level comparison clock to a latch module to reset the latch module, charging a positive feedback circuit coupled on both sides to a high level, and simultaneously maintaining the potentials on both sides of a connected switch consistent; Input the high-level comparison clock to the latch module, and use the difference in discharge speed caused by the input voltage difference to trigger the positive feedback circuit, accelerate the current discharge, and complete the voltage comparison; The modulation correction capacitor module compensates for the offset generated during the comparison process.

[0014] Preferably, the compensation process includes: finding the lowest weight capacitor in the comparison process, the comparator continues to compare, and based on the comparison result and the comparison result before the lowest weight is reset, it is determined whether the mismatched capacitance before the last comparison is greater than the lowest weight capacitor, the lowest weight capacitor is reversed, and the redundant capacitor is connected for search and comparison to determine whether the mismatched capacitance reaches the maximum correction bit number. If so, it ends; otherwise, the comparator continues to compare.

[0015] Preferably, by accelerating the current discharge, both sides of the comparator are made to output VDD and VSS respectively, thereby completing the voltage comparison.

[0016] The beneficial effects of the present application are as follows: the present application provides a double-tail comparator circuit for the column-end ADC of a pixel sensor and an operating method thereof, which overcomes the existing high kickback noise and offset phenomenon of the comparator in high-frequency scenarios through the synergistic effect of the input differential pair tube, the latch module and the correction capacitor module, and reduces the comparison accuracy error caused by the high kickback noise. By providing a higher input stage transconductance through the input differential pair tube, the ability of the amplifier input stage to convert the input differential voltage into the output current is enhanced, so that the noise voltage can be discharged quickly and a fast response is achieved. In the reset stage, the latch module is used to disconnect the input differential pair tube from the positive feedback node in the comparator, ensuring the isolation of the positive feedback node, maintaining a stable potential, reducing the amplitude of the kickback noise, shortening the transient process of the kickback noise, reducing the interference time of the noise on the signal, and ensuring the stability and reliability of the signal. In addition, at the beginning of the comparison, the kickback noise introduced by the level change is effectively isolated by the latch module, so that the positive kickback received by the gate of the input differential pair tube in the comparator is smaller, and the positive kickback noise and the negative kickback noise are offset by each other, thereby effectively suppressing the kickback noise. The correction capacitor module adjusts the initial voltage of the lower plate of the load capacitor by modulating the size of the correction capacitor, and then controls the size of the equivalent capacitance connected to the positive feedback node, realizing compensation for the comparator offset in high-speed scenarios. Using the correction capacitor module instead of the traditional capacitor series method reduces the high power consumption or speed loss that may be introduced by the traditional dynamic comparator offset correction method, and improves the accuracy of the comparator with low area and low power consumption.

[0017] In summary, the present application can effectively solve the kickback noise and offset problems generated by the comparator in the pixel sensor in high-frequency scenarios, and improve the accuracy of the comparator under the premise of low area and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A circuit diagram of a double-tail comparator circuit for a column-side ADC of a pixel sensor provided in one embodiment of the present application; Figure 2 The simulation results of the correction capacitance variation with voltage provided by an embodiment of the present application and its variation with different V P Schematic diagram of equivalent charge load under voltage; Figure 3 A flowchart of a comparator offset correction process according to an embodiment of the present application; Figure 4 A simulation waveform diagram of the comparator correction capacitor module correcting the offset provided in one embodiment of the present application; Figure 5 This is a comparison of simulation results of kickback noise of double-tail comparators with different structures provided in one embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0021] See also Figure 1 , a double-tail comparator circuit for a column-end ADC of a pixel sensor provided in the first aspect of the first embodiment of the present application, includes: an input differential pair tube, a latch module and a correction capacitor module, the latch module is connected to the input differential pair tube and the correction capacitor module.

[0022] The input differential pair tubes are used to provide input stage transconductance and quickly discharge noise voltage; The latch module is used to reduce the amplitude of the kickback noise and shorten the transient process of the kickback noise; The correction capacitor module is used to modulate the size of the correction capacitor to compensate for the offset of the comparator.

[0023] On the one hand, the present application utilizes a latch module and an input differential pair tube to quickly discharge the noise voltage, reduce the amplitude of the kickback noise, shorten the transient process of the kickback noise, and effectively suppress the kickback noise in high-frequency scenarios; on the other hand, the unit correction capacitor size is adjusted according to the reference voltage and delay time to compensate for the offset of the comparator.

[0024] Specifically, the latch module includes a positive feedback circuit, a time-controlled switch, and a connection switch. The time-controlled switch disconnects the input differential pair transistors from the positive feedback circuit to ensure a stable potential during the reset phase. The connection switch turns on during the reset phase to ensure that the charges on both branches are consistent.

[0025] This application reduces the amplitude of kickback noise and shortens its transient state through the following two approaches. Firstly, an isolation switch in the positive feedback circuit is used to offset positive and negative kickback noise, and a time-controlled switch is used to isolate the input differential pair transistors from the positive feedback circuit, thereby reducing the amplitude of the kickback noise. Secondly, the input differential pair transistors are grounded to enhance the driving capability of the discharge path. These measures effectively shorten the transient state of the noise.

[0026] Specifically, the positive feedback circuit includes a zeroth PMOS transistor M0, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a sixth NMOS transistor M6, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth NMOS transistor M12 and a thirteenth NMOS transistor M13. The sources of the zeroth PMOS transistor M0, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the tenth PMOS transistor M10, and the eleventh PMOS transistor M11 are connected to the power supply, the gate of the zeroth PMOS transistor M0 is connected to the comparison clock CLK, the drain of the zeroth PMOS transistor M0 is connected to the gates of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13, the gate of the second PMOS transistor M2 is connected to the gate of the sixth NMOS transistor M6, the drain of the second PMOS transistor M2 is connected to the time-controlled switch, the gate of the first PMOS transistor M1 is connected to the gate of the ninth NMOS transistor M9, the drain of the first PMOS transistor M1 is connected to the time-controlled switch, the gate of the third PMOS transistor M3 is connected to the comparison clock CLK, and the drain of the third PMOS transistor M3 is connected to the gates of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12. The drains of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 are connected to the input voltage VOP, the source of the thirteenth NMOS transistor M13 is grounded to VSS, the drains of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 are connected to the input voltage VON, and the source of the twelfth NMOS transistor M12 is grounded to VSS. The eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 form an inverter on the left, and the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 form an inverter on the right.

[0027] The sixth and ninth NMOS transistors M6 and M9 function as isolation switches, isolating kickback noise introduced by variations in the comparison clock CLK level during the comparator's startup phase. The isolation switches effectively isolate the noise introduced by the comparison clock from the gates of the input differential pair transistors, significantly reducing the positive kickback noise experienced by the gates of the input differential pair transistors. By adjusting the dimensions of the sixth and ninth NMOS transistors M6 and M9, the positive kickback noise introduced by the comparison clock CLK and the negative kickback noise caused by the voltage common-mode drop between the left and right branches of the double-tail comparator during the comparison process can be offset, effectively suppressing the kickback noise. Specifically, the gate of the sixth NMOS transistor M6 is connected to the gate of the second PMOS transistor M2, the source of the sixth NMOS transistor M6 is connected to the input differential pair transistor, the drain of the sixth NMOS transistor M6 is connected to the time-controlled switch, the gate of the ninth NMOS transistor M9 is connected to the gate of the first PMOS transistor M1, the source of the ninth NMOS transistor M9 is connected to the input differential pair transistor, and the drain of the ninth NMOS transistor M9 is connected to the time-controlled switch.

[0028] Furthermore, the present application provides a time-controlled switch to disconnect the input differential pair transistors from the positive feedback circuit, isolating the positive feedback circuit while stabilizing the potential during the reset phase. Specifically, the time-controlled switch includes a fourth NMOS transistor M4 and an eighth NMOS transistor M8. The gate of the fourth NMOS transistor M4 is connected to the comparison clock CLK, the source of the fourth NMOS transistor M4 is connected to the isolation switch, the drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M2, the gate of the eighth NMOS transistor M8 is connected to the comparison clock CLK, the source of the eighth NMOS transistor M8 is connected to the isolation switch, and the drain of the eighth NMOS transistor M8 is connected to the drain of the first PMOS transistor M1.

[0029] To ensure that the charge levels on both sides of the branch circuit are consistent during the reset phase, the present application adds a fourteenth NMOS transistor M14, a connectivity switch that is turned on only during the reset phase, at the drain node of the input differential pair transistors. The source of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistors. The gate of the fourteenth NMOS transistor M14 is connected to the comparison clock CLKB. The drain of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistors.

[0030] The present application retains the grounding characteristic of the input differential pair of transistors in a traditional double-tail comparator, providing a higher input stage transconductance, thereby enabling rapid discharge of noise voltage. Specifically, the input differential pair includes a fifth NMOS transistor M5 and a seventh NMOS transistor M7, wherein the gate of the fifth NMOS transistor M5 is connected to the input voltage VIP, the source of the fifth NMOS transistor M5 is grounded to VSS, the drain of the fifth NMOS transistor M5 is connected to the source of the isolation switch and the drain of the connection switch, the gate of the seventh NMOS transistor M7 is connected to the input voltage VIP, the source of the seventh NMOS transistor M7 is grounded to VSS, and the drain of the seventh NMOS transistor M7 is connected to the source of the isolation switch and the drain of the connection switch.

[0031] This application mounts a correction capacitor module on the positive feedback circuit to compensate for offset to achieve offset calibration. This application directly calibrates the comparator's offset, combining metastable calibration with a varactor diode to finely adjust the size of the correction capacitor, achieving extremely high offset calibration accuracy. This eliminates the need to establish the preamplifier stage during multi-stage comparator calibration, and better compensates for comparator offset in high-speed scenarios.

[0032] Specifically, see Figure 1 In the two parts of the middle frame, the correction capacitor module is a variable capacitor of a PMOS tube. The source, drain and substrate of the PMOS tube are short-circuited together. As one plate of the variable capacitor, it is symmetrically mounted on both sides of the comparator's positive feedback circuit. The gate of the PMOS tube is connected to the modulated control voltage switch as the other plate of the variable capacitor, and then switches between the high and low control voltages VRP and VRN.

[0033] Specifically, since the function of the correction capacitor module is mainly concentrated in the voltage drop process before the positive feedback starts, when the positive feedback starts, the operation of the comparator is dominated by the positive feedback regeneration loop, and the node has no active drive during the voltage drop process, so the charge discharge involved is extremely low, and a very small correction capacitor is required for load adjustment to achieve the required accuracy. However, existing metal capacitors are difficult to meet such small capacitance requirements, and although the required capacitance can be achieved by connecting capacitors in series, it will result in a significant increase in chip area. This application uses PMOS varactor (variable capacitor) as a correction capacitor to compensate for the capacitive load of the comparator's offset. According to the characteristic that the capacitance of the PMOS varactor (variable capacitor) changes with the voltage difference between the two ends, by adjusting the initial voltage of the lower plate of the correction capacitor, the equivalent capacitance size connected to the positive feedback node is controlled to solve the implementation problem of ultra-low capacitance capacitors. During the voltage drop process, the PMOS varactor (variable capacitor diode) changes at different lower plate voltages. The equivalent capacitance value under can be expressed as: ; Where C var (V) is the function of the capacitance across the PMOS varactor and the voltage difference across it, is the equivalent capacitance of the PMOSvaractor, is the power supply voltage, is the lower plate voltage, is the threshold voltage of the PMOS tube.

[0034] The present application utilizes the reference voltage of a PMOS varactor (variable capacitance diode) to modulate the correction capacitor. Specifically, when the PMOS varactor (variable capacitance diode) with the lowest design rule size is selected, C var The function curve of (V) is as follows Figure 2 As shown in the figure, the horizontal axis represents the bias voltage (V), the vertical axis represents the capacitance value (Pf), and the blue solid line represents the capacitance change under different voltages. In this case, the charge discharge amount on the unit load correction capacitor during a comparison process can be adjusted by modulating the PMOS varactor reference voltage to obtain a more precise offset correction capacitor, thereby reducing the single-step size of the offset calibration and achieving a more precise offset calibration.

[0035] This application sets the correction capacitor module to a non-binary weight and leaves a certain amount of redundancy. Even if a bit error occurs, the subsequent capacitor weight can cover the weight of the error bit and leave a certain amount of redundancy (N bits), thereby greatly reducing the impact of the error caused by noise on the correction accuracy. Insert the capacitor of the above redundant bit into the lowest weight capacitor ( ) and then Encode the weight, where i is the current redundant capacitor bit number, i takes a positive integer from 1 to N, and the differential term is set to , in conjunction with the metastable criterion, using a capacitance slightly higher than the minimum value The load capacitance is used to construct a more precise correction capacitor module. In addition, the added comparator metastable state judgment circuit in the correction capacitor module can be used with the delayed clock. The offset size of the delayed clock is judged by the metastable duration of the comparator, thereby more precisely controlling the offset calibration accuracy of the comparator. Among them, the clock delay size is determined by simulation and is taken as the value of the comparator at The judgment delay under mismatch conditions is reduced, and a certain margin is left on this basis to reduce the offset calibration compensation.

[0036] When the input voltages on both sides of the comparator's positive feedback circuit are the same, the lower the input offset voltage, the more consistent the discharge speed levels between the two branches. Therefore, it takes a longer time to amplify the voltage difference between the two branches before the positive feedback regeneration node can start to work, which directly leads to a longer propagation delay of the comparator from the start of comparison to the completion of the comparison output result. During this delay time, the comparator is in a metastable state, and the output results of both ends are 0. Therefore, this application uses the propagation delay of the comparator as a standard to measure the offset voltage in its input correction capacitor module, and adds a comparator delay criterion on the basis of the original calibration timing to dynamically distinguish the input offset voltage of the comparator. This application uses propagation delay as an offset criterion to dynamically monitor and compensate for the comparator offset phenomenon.

[0037] A second aspect of an embodiment of the present application provides a method for operating a double-tailed comparator for a column-side ADC of a pixel sensor, comprising: First, a low-level comparison clock CLK is input to the latch module, placing it in a reset state. The zeroth PMOS transistor M0 and the third PMOS transistor M3 are turned on, charging the mutually coupled positive feedback circuit to a high level. This voltage is then output through the eleventh PMOS transistor M11 and the twelfth NMOS transistor M12 of the left inverter and the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 of the right inverter. The potential of the node below is maintained at the same level by the conductive connection switch, the fourteenth NMOS transistor M14.

[0038] Next, a high-level comparison clock CLK is input to the latch module. The zeroth PMOS transistor M0, the third PMOS transistor M3, and the fourteenth NMOS transistor M14 are turned off, while the gate voltages of the fifth and seventh NMOS transistors M5 and M7 of the input differential pair are different, resulting in different charge discharge rates on both sides. If the input voltage VIP > VIN, the left branch discharges faster than the right. Once the potential at this node in the positive feedback circuit on this side is discharged to the turn-on voltage (VDD - VTHP) of transistors M1 / M2, the positive feedback circuit activates and takes over the subsequent comparison process. At this point, the current discharge rate on the other side decreases due to the lower gate voltage of the ninth NMOS transistor M9. Simultaneously, the first PMOS transistor M1 turns on, charging the right positive feedback node to VDD, causing the left gate voltage to rise. This gate voltage turns off the second PMOS transistor M2 and restores the sixth NMOS transistor M6 to its fully open state, further accelerating current discharge on this side and pulling it down to ground VSS. Finally, the comparator outputs power supply VDD on one end and ground VSS on the other, completing the comparison process.

[0039] Next, adjust the correction capacitor module. P Taking 900mV, we get an equivalent differential load capacitance of 20aF, and an offset calibration step of 600μV. The offset generated during the comparison process is compensated using the modulated correction capacitor module.

[0040] Specifically, see Figure 3 First, connect the two ends of the double-tail comparator input differential pair to the common mode level, and connect the two ends to the maximum calibration capacitor. Input the comparison clock to start the comparator comparison, and perform a binary search of the mismatched capacitance until the lowest weight capacitance comparison is completed. On this basis, the comparator continues to compare once, and based on the comparison result of this comparison and the comparison result before the lowest weight is reset, it is determined whether the mismatched capacitance before the last comparison is greater than (At this time, the mismatch capacitance must be less than ). If the offset capacitance is greater than , then disconnect the lowest weight capacitor and connect the redundant bit to continue searching and comparing. If the offset capacitance is less than , then the lowest weight capacitor is reversed so that its mismatch capacitance is ( , ) and connect redundant capacitors for search and comparison. During the search and comparison process, the comparator metastable time criterion is used to dynamically determine whether the mismatched capacitance meets expectations: if the comparator completes the comparison within the set delay time, it is considered that the comparator still has a large mismatch, and subsequent searches continue; if the comparator does not complete the comparison within the set delay time, and the outputs at both ends are low, the positive end correction load capacitance is reduced to determine whether it has reached the correction bit. If so, it is considered that the comparator has reached the required accuracy, otherwise the comparator continues to compare; if the outputs at both ends are high, the negative end correction load capacitance is reduced to determine whether it has reached the correction bit. If so, it is considered that the comparator has reached the required accuracy, otherwise the comparator continues to compare.

[0041] This application uses 5 weight bits + 3 redundant bits to design the calibration circuit, and the weights of each correction capacitor are shown in Table 1. Under this condition, the simulation results of the comparator correction algorithm process are as follows Figure 4 As shown in the figure. At point ①, calibration begins. Then, at point ②, the comparator performs continuous comparisons and searches for the equivalent mismatched capacitance of the branches on both sides. At point ③, the delayed clock rising edge arrives before the comparator's settling signal, indicating that the offset voltage has met the design criteria. Then, at point ④, the comparator calibration algorithm dynamically ends, completing the comparator calibration.

[0042] Table 1 Correction capacitor array weights

[0043] Specific embodiment 1: a simulation test The double-tail comparator circuit of the present application is compared with the traditional single-tail or double-tail comparator designed with the same aspect ratio device. The comparison simulation results are as follows: Figure 5 shown.

[0044] Depend on Figure 5 Compared to conventional latch comparators and traditional double-tail comparators, the novel double-tail comparator designed in this paper significantly improves both kickback noise amplitude and noise recovery time. In high-frequency scenarios, the kickback noise amplitude is reduced by more than half, and the recovery time is less than 1ns. Using a voltage-modulated correction capacitor, the error calibration step size can be reduced from 2mV to 600μV, achieving more precise error correction. A dynamic comparator offset correction method based on comparator metastability can further reduce the error calibration step size to N times the original value (N is the number of redundant bits in the offset correction capacitor array). Simulations measuring the comparator offset voltage before and after offset correction show that the proposed calibration circuit can reduce the offset voltage from 5.40mV to 0.23mV.

[0045] In summary, the present application can quickly reduce the amplitude of the kickback noise at high frequencies, reduce the calibration step from 2mV to 600μV, significantly improve the calibration time, and achieve more precise offset compensation.

[0046] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0047] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A double-tail comparator circuit for a pixel sensor column-side ADC, comprising an input differential pair of transistors, characterized in that: It also includes a latch module and a correction capacitor module, wherein the latch module is connected to the input differential pair tube and the correction capacitor module; The input differential pair transistors are used to provide input stage transconductance and quickly discharge noise voltage; The latch module is used to reduce the amplitude of the kickback noise and shorten the transient process of the kickback noise; The correction capacitor module is used to modulate the size of the correction capacitor to compensate for the offset of the comparator.

2. The double-tail comparator circuit for a pixel sensor column-side ADC according to claim 1, wherein: The latch module includes a positive feedback circuit, a time-controlled switch and a connection switch, wherein the connection switch is connected to the positive feedback circuit; The time-controlled switch is used to disconnect the input differential pair tube and the positive feedback circuit to ensure a stable potential in the reset phase; The connection switch is used to be turned on during the reset phase to ensure that the charges on both sides of the branch circuit are consistent during the reset phase.

3. The double-tail comparator circuit for a pixel sensor column-side ADC according to claim 2, wherein: The correction capacitor module is a variable capacitor of a PMOS tube. The source and drain of the PMOS tube are short-circuited with the substrate. The plates serving as the variable capacitor are symmetrically mounted on both sides of the positive feedback circuit. The gate of the PMOS tube serves as the other plate of the variable capacitor and is connected to a control voltage switch. The control voltage switch is used to switch between two high and low control voltages VRP and VRN.

4. The double-tail comparator circuit for a pixel sensor column-side ADC according to claim 2, wherein: The positive feedback circuit includes a zeroth PMOS transistor M0, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a sixth NMOS transistor M6, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth NMOS transistor M12 and a thirteenth NMOS transistor M13. The sources of the zeroth PMOS transistor M0, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the tenth PMOS transistor M10 and the eleventh PMOS transistor M11 are connected to a power supply, the gate of the zeroth PMOS transistor M0 is connected to a comparison clock, the drain of the zeroth PMOS transistor M0 is connected to the gates of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13, the gate of the second PMOS transistor M2 is connected to the sixth The gate of the NMOS transistor M6 and the drain of the second PMOS transistor M2 are connected to the time-controlled switch, the gate of the first PMOS transistor M1 is connected to the gate of the ninth NMOS transistor M9, the drain of the first PMOS transistor M1 is connected to the time-controlled switch, the gate of the third PMOS transistor M3 is connected to the comparison clock, the drain of the third PMOS transistor M3 is connected to the gates of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12, the drains of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 are connected to the input voltage VOP, the source of the thirteenth NMOS transistor M13 is grounded VSS, the drains of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 are connected to the input voltage VON, and the source of the twelfth NMOS transistor M12 is grounded VSS.

5. The double-tail comparator circuit for a pixel sensor column-side ADC according to claim 4, wherein: The sixth NMOS transistor M6 and the ninth NMOS transistor M9 are isolation switches, which are used to isolate the kick-back noise introduced by the change of the comparison clock level during the startup phase, and to offset the positive polarity kick-back noise introduced by the comparison clock and the negative polarity kick-back noise caused by the voltage common mode drop.

6. The double-tail comparator circuit for a pixel sensor column-side ADC according to claim 5, wherein: The time-controlled switch includes a fourth NMOS transistor M4 and an eighth NMOS transistor M8. The gate of the fourth NMOS transistor M4 is connected to the comparison clock, the source of the fourth NMOS transistor M4 is connected to the isolation switch, and the drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M2. The gate of the eighth NMOS transistor M8 is connected to the comparison clock, the source of the eighth NMOS transistor M8 is connected to the isolation switch, and the drain of the eighth NMOS transistor M8 is connected to the drain of the first PMOS transistor M1.

7. The double-tail comparator circuit for a pixel sensor column-side ADC according to claim 6, wherein: The connectivity switch is turned on only in the reset phase. The connectivity switch is the fourteenth NMOS transistor M14. The source of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistor. The gate of the fourteenth NMOS transistor M14 is connected to the comparison clock. The drain of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistor.

8. A method for operating a double-tailed comparator for a column-side ADC of a pixel sensor, applied to a double-tailed comparator circuit for a column-side ADC of a pixel sensor according to any one of claims 1 to 7, characterized in that: The following steps are involved: Input a low-level comparison clock to the latch module to reset the latch module, charge the mutually coupled positive feedback circuits on both sides to a high level, and keep the potentials on both sides of the switch consistent. Input the high-level comparison clock to the latch module, and use the difference in discharge speed caused by the input voltage difference to trigger the positive feedback circuit, accelerate the current discharge, and complete the voltage comparison; The modulation correction capacitor module compensates for the offset generated during the comparison process.

9. The method for operating a double-tailed comparator for a column-side ADC of a pixel sensor according to claim 8, wherein: The compensation process includes: finding the lowest weight capacitor in the comparison process, the comparator continues to compare to obtain a comparison result, and based on the comparison result and the comparison result before the lowest weight is reset, it is determined whether the mismatched capacitance before the last comparison is greater than the lowest weight capacitance, the lowest weight capacitance is reversed, and the redundant capacitance is connected for search and comparison to determine whether the mismatched capacitance reaches the maximum correction bit number. If so, the process ends; otherwise, the comparator continues to compare.

10. The method for operating a double-tailed comparator for a column-side ADC of a pixel sensor according to claim 8, wherein: By accelerating the current discharge, both sides of the comparator output VDD and VSS respectively, thereby completing the voltage comparison.

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