Common-mode level adjustment method, SAR ADC architecture and storage medium

Abstract

The invention discloses a common-mode level adjustment method, an SAR ADC architecture and a storage medium, and the method is applied to an analog-to-digital converter, and the method comprises the steps: in a sampling stage, enabling lower electrode plates, used for sampling, in a first capacitor array and a second capacitor array to be connected with respective collected input signals, and enabling upper electrode plates, not used for sampling, in the first capacitor array and the second capacitor array to be connected with a VCM; in the conversion stage, the VCM is disconnected, and connection objects of lower polar plates of split capacitors and non-split capacitors in the first capacitor array and the second capacitor array are adjusted; obtaining a comparison result output by the comparator; and circularly executing the steps of adjusting the connection object of each lower polar plate based on the comparison result and obtaining the comparison result output by the comparator until the conversion is completed. The invention aims to solve the technical problem of how to reduce the cost for maintaining the common-mode level near the VCM.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital converters, and in particular to a common-mode level adjustment method, a SAR ADC architecture, and a storage medium. Background Art

[0002] SAR ADC (Successive Approximation Register Analog to Digital Converter) has a good balance between speed, resolution and power, and therefore occupies a large market share.

[0003] It's understandable that for the comparator in a SAR ADC, maintaining the comparator input common-mode level near the ideal common-mode level, VCM (typically half the full-scale power supply voltage range), maximizes the input dynamic range and minimizes noise and offset voltage. Therefore, maintaining the common-mode level near VCM is essential.

[0004] Currently, the main methods for maintaining the common-mode level near VCM include: switching timing design based on the common-mode level VCM. However, while switching timing based on the common-mode level VCM can maintain the comparator input common-mode level near VCM, this approach requires an additional VCM generation module. This VCM generation module is used during switching during the conversion phase, which requires high speed. Therefore, the implementation area and power consumption of this module are also large. Therefore, traditional methods for maintaining the common-mode level near VCM have the technical problem of high cost. Summary of the Invention

[0005] The main purpose of this application is to provide a common-mode level adjustment method, a SAR ADC architecture, and a storage medium, aiming to solve the technical problem of how to reduce the cost required to maintain the common-mode level near VCM.

[0006] To achieve the above objectives, the present application proposes a common-mode level adjustment method, which is applied to a SAR ADC. The SAR ADC includes a first capacitor array and a second capacitor array, wherein the high-order capacitors in the first capacitor array and the second capacitor array are split capacitors and the low-order capacitors are unsplit capacitors; each of the split capacitors includes a first sub-capacitor and a second sub-capacitor;

[0007] The common mode level adjustment method comprises:

[0008] During the sampling phase, the lower plate in the first capacitor array is connected to the first input signal collected by the first capacitor array, the lower plate in the second capacitor array is connected to the second input signal collected by the second capacitor array, and the upper plates in the first capacitor array and the second capacitor array are connected to VCM;

[0009] During the conversion phase, the VCM is disconnected, the first low-order capacitor from the high-order to the low-order is used as the first low-order capacitor, and the other low-order capacitors except the first low-order capacitor are used as the second low-order capacitor;

[0010] Connecting the lower plate of the first sub-capacitor and the lower plate of the second sub-capacitor to a first preset voltage and a second preset voltage, respectively, and connecting the lower plate of the first low-order capacitor and the lower plate of the second low-order capacitor to the first preset voltage and the second preset voltage, respectively; the first preset voltage and the second preset voltage have opposite polarities;

[0011] Obtaining a comparison result output by a comparator in the SAR ADC;

[0012] The steps of adjusting the connection object of each lower electrode plate based on the comparison result and obtaining the comparison result output by the comparator in the SAR ADC are executed cyclically until the conversion is completed.

[0013] In one embodiment, the step of adjusting the connection object of each of the lower plates based on the comparison result includes:

[0014] determining an array to be adjusted in the first capacitor array and the second capacitor array based on the comparison result;

[0015] determining a capacitance to be adjusted in the array to be adjusted;

[0016] When it is detected that the array to be adjusted includes the first capacitor array and the second capacitor array, connecting the lower plate of the capacitor to be adjusted in the first capacitor array and the lower plate of the capacitor to be adjusted in the second capacitor array to a first preset voltage and a second preset voltage respectively;

[0017] When it is detected that the array to be adjusted is the first capacitor array or the second capacitor array, if it is detected that the current connection object of the capacitor to be adjusted is the first preset voltage, the lower plate of the capacitor to be adjusted is connected to the second preset voltage; if it is detected that the current connection object of the capacitor to be adjusted is the second preset voltage, the lower plate of the capacitor to be adjusted is connected to the first preset voltage.

[0018] In one embodiment, connecting the lower plate of the first sub-capacitor and the lower plate of the second sub-capacitor to the first preset voltage and the second preset voltage, respectively, comprises:

[0019] Connecting the lower plate of the first sub-capacitor to a first preset voltage, and connecting the lower plate of the second sub-capacitor to a second preset voltage;

[0020] or,

[0021] The lower plate of the first sub-capacitor is connected to the second preset voltage, and the lower plate of the second sub-capacitor is connected to the first preset voltage.

[0022] In one embodiment, connecting the lower plate of the first low-level capacitor and the lower plate of the second low-level capacitor to the first preset voltage and the second preset voltage, respectively, comprises:

[0023] Connecting the lower plate of the first low-level capacitor to the first preset voltage, and connecting the lower plate of the second low-level capacitor to the second preset voltage;

[0024] or,

[0025] The lower plate of the first low-level capacitor is connected to the second preset voltage, and the lower plate of the second low-level capacitor is connected to the first preset voltage.

[0026] In one embodiment, the VCM is half of the sum of the first preset voltage and the second preset voltage.

[0027] In addition, to achieve the above objectives, the present application also proposes a SAR ADC architecture, which includes:

[0028] a first capacitor array, wherein sampling capacitors of the first capacitor array include split capacitors and unsplit capacitors, a lower plate of each capacitor in the first capacitor array is connected to a first input signal, a first preset voltage, and a second preset voltage collected by the first capacitor array, and a top plate of each capacitor in the first capacitor array is connected to VCM; the first preset voltage and the second preset voltage have opposite polarities;

[0029] a second capacitor array, wherein the sampling capacitors of the second capacitor array include split capacitors and unsplit capacitors, the lower plates of the capacitors in the second capacitor array are connected to the second input signal, the first preset voltage, and the second preset voltage collected by the second capacitor array, and the upper plates of the capacitors in the first capacitor array are connected to VCM;

[0030] a comparator, wherein a first input terminal of the comparator is connected to the first capacitor array, and a second input terminal of the comparator is connected to the second capacitor array;

[0031] A digital logic circuit, wherein the input end of the digital logic circuit is connected to the output end of the comparator, the first output end of the digital logic circuit is connected to the first capacitor array, the second output end of the digital logic circuit is connected to the second capacitor array, and the third input end of the digital logic circuit is used to output a digital code.

[0032] In one embodiment, the first capacitor array and the second capacitor array both include redundant capacitors, and the connection objects of the lower plates of the redundant capacitors include: the first preset voltage and the second preset voltage; the connection object of the upper plates of the redundant capacitors includes: VCM.

[0033] In one embodiment, the SAR ADC architecture further includes:

[0034] The sampling switch is a bootstrap switch, one end of the sampling switch is connected to the lower plate, and the other end of the sampling switch is connected to a connection object of the lower plate.

[0035] In one embodiment, the SAR ADC architecture further includes:

[0036] a third capacitor array, the third capacitor array being connected to the first capacitor array via a first bridging capacitor; the lower plates of the capacitors in the third capacitor array being connected to the first preset voltage and the second preset voltage; and the upper plates of the capacitors in the third capacitor array being connected to one end of the first bridging capacitor;

[0037] A fourth capacitor array, wherein the fourth capacitor array is connected to the second capacitor array through a second bridging capacitor; the connection object of the lower plate of each capacitor in the fourth capacitor array includes: the first preset voltage and the second preset voltage; the connection object of the upper plate of each capacitor in the fourth capacitor array includes one end of the second bridging capacitor.

[0038] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the steps of the common-mode level adjustment method described above are implemented.

[0039] One or more technical solutions proposed in this application have at least the following technical effects:

[0040] During the sampling phase, the lower plate in the first capacitor array is connected to the first input signal collected by the first capacitor array, the lower plate in the second capacitor array is connected to the second input signal collected by the second capacitor array, and the upper plates in the first capacitor array and the second capacitor array are connected to VCM. The analog signal that needs to be converted into a digital signal can be stored in the first capacitor array and the second capacitor array.

[0041] Then, during the conversion phase, VCM is disconnected, and the first low-order capacitor in the high-to-low direction is used as the first low-order capacitor, and the other low-order capacitors except the first low-order capacitor are used as the second low-order capacitor. The lower plate of the first sub-capacitor and the lower plate of the second sub-capacitor are connected to the first preset voltage and the second preset voltage, respectively, and the lower plate of the first low-order capacitor and the lower plate of the second low-order capacitor are connected to the first preset voltage and the second preset voltage, respectively. The polarity of the first preset voltage and the second preset voltage are opposite, which can ensure that during the first conversion, half of the sampling capacitors of the first capacitor array are connected to the first preset voltage and half are connected to the second preset voltage, which can be equivalently regarded as the sampling capacitors being connected to VCM. Therefore, during the first conversion, the sampling capacitors of the first capacitor array are switched from the first input signal to VCM, and the sampling capacitors of the second capacitor array are switched from the second input signal to VCM, thereby achieving the purpose of maintaining the common mode level near VCM.

[0042] Then, a comparison result output by the comparator in the SAR ADC is obtained to determine the magnitude of the voltage at the two input terminals of the comparator. Then, the steps of adjusting the connection object of each lower plate based on the comparison result and obtaining the comparison result output by the comparator in the SAR ADC are executed in a loop until the conversion is completed. The connection object of the lower plate of the capacitor currently used for signal conversion can be adjusted based on the magnitude of the voltage at the two input terminals of the comparator at the previous moment, so that the comparison result output by the comparator gradually approaches the input signal, and the lower plate of the capacitor currently used for signal conversion can be equivalently connected to VCM.

[0043] It can be seen that this application only involves split capacitors and switch timing, and the plates used for sampling in the capacitor array of this application are only switched to the first preset voltage or the second preset voltage, and are not switched to VCM. Therefore, compared with traditional technologies, this application does not require an additional VCM generation module with speed requirements; thus, this application achieves the purpose of controlling the common mode level of the comparator near VCM under low-cost conditions by combining split capacitors and switch timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 A flowchart of the first embodiment of the common-mode level adjustment method of the present application is provided;

[0047] Figure 2 This is a schematic diagram of the first embodiment of the SAR ADC architecture of the present application;

[0048] Figure 3 Schematic diagram of the change of the common-mode level of the comparator input of the SAR ADC architecture of this application;

[0049] Figure 4 This is a schematic diagram of a second embodiment of the SAR ADC architecture of the present application;

[0050] Figure 5 This is a schematic diagram of a third embodiment of the SAR ADC architecture of the present application;

[0051] Figure 6 This is a schematic diagram of a fourth embodiment of the SAR ADC architecture of the present application;

[0052] Figure 7 This is a schematic diagram of a fifth embodiment of the SAR ADC architecture of the present application;

[0053] Figure 8 This is a schematic diagram of the sixth embodiment of the SAR ADC architecture of the present application.

[0054] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0055] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0056] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0057] It is understandable that the traditional method of maintaining the common mode level near VCM has the technical problem of high cost.

[0058] To solve the above problems, in the sampling stage, the present application connects the lower plates used for sampling in the first capacitor array and the second capacitor array to their respective collected input signals, and connects the upper plates not used for sampling to VCM; in the conversion stage, VCM is disconnected, and the connection objects of the lower plates of the split capacitors and the unsplit capacitors in the first capacitor array and the second capacitor array are adjusted; the comparison results output by the comparator are obtained; and the steps of adjusting the connection objects of each lower plate and obtaining the comparison results output by the comparator based on the comparison results are executed in a loop until the conversion is completed, thereby achieving the purpose of controlling the common mode level of the comparator to be near VCM under low-cost conditions.

[0059] It should be noted that the execution entity of the common-mode level adjustment method of the present application can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, etc., or an electronic device capable of performing the above functions. The following uses a computer as an example to illustrate various embodiments of the common-mode level adjustment method of the present application.

[0060] Based on the above, the present invention provides a method for adjusting the common mode level. Figure 1 , Figure 1 This is a flow chart of the first embodiment of the common-mode level adjustment method of the present application.

[0061] In this embodiment, the common-mode level adjustment method is applied to a SAR ADC, wherein the SAR ADC includes a first capacitor array and a second capacitor array, wherein the high-order capacitors in the first capacitor array and the second capacitor array are split capacitors and the low-order capacitors are unsplit capacitors; each of the split capacitors includes a first sub-capacitor and a second sub-capacitor; and the common-mode level adjustment method includes steps S10 to S50:

[0062] Step S10, in a sampling phase, connecting the lower plate in the first capacitor array to a first input signal collected by the first capacitor array, connecting the lower plate in the second capacitor array to a second input signal collected by the second capacitor array, and connecting the upper plates in the first capacitor array and the second capacitor array to VCM;

[0063] It is understood that the SAR ADC includes a sampling phase and a conversion phase. The sampling phase is used to store the signal to be converted in the first capacitor array and the second capacitor array, and the conversion phase is used to convert the analog signals in the first capacitor array and the second capacitor array into digital signals.

[0064] It should be noted that the first input signal refers to the analog signal collected by the first capacitor array, and the second input signal refers to the analog signal collected by the second capacitor array. For ease of explanation, the first input signal is represented by VIP and the second input signal is represented by VIN.

[0065] Step S20, in the conversion phase, disconnecting the VCM, using the first low-order capacitor from the high-order to the low-order capacitor as the first low-order capacitor, and using the other low-order capacitors except the first low-order capacitor as the second low-order capacitor;

[0066] For example, taking a 7-bit SAR ADC as an example (H1G, H1, H2, H3, H4, H5, H6), if H4, H5, and H6 are all split capacitors, the first low-order capacitor is H3, and the second low-order capacitors are H1G, H1, and H2.

[0067] Step S30: connecting the lower plate of the first sub-capacitor and the lower plate of the second sub-capacitor to a first preset voltage and a second preset voltage, respectively, and connecting the lower plate of the first low-order capacitor and the lower plate of the second low-order capacitor to the first preset voltage and the second preset voltage, respectively; the first preset voltage and the second preset voltage have opposite polarities;

[0068] It should be noted that the VCM is half of the sum of the first preset voltage and the second preset voltage.

[0069] In addition, it should be noted that, in the present embodiment, each split capacitor includes two sub-capacitors (a first sub-capacitor and a second sub-capacitor). For example, the above-mentioned H6 can be split into H6P (a first sub-capacitor) and H6N (a second sub-capacitor). To ensure that the common-mode level of the comparator is near VCM during the conversion phase, the lower plates of the first sub-capacitor and the second sub-capacitor can be connected to two voltages of opposite polarity, respectively. Since VCM is the average value of the two voltages of opposite polarity, by splitting the capacitor and connecting the split capacitors to the two voltages of opposite polarity, respectively, the common-mode level of the comparator input can be equal to VCM during the first conversion.

[0070] In a feasible implementation manner, the above step S30 includes:

[0071] Step S301: connecting the lower plate of the first sub-capacitor to a first preset voltage, and connecting the lower plate of the second sub-capacitor to a second preset voltage;

[0072] Step S302: Connect the lower plate of the first sub-capacitor to a second preset voltage, and connect the lower plate of the second sub-capacitor to the first preset voltage.

[0073] It is understood that when the first preset voltage is VRP and the second preset voltage is VRN, the first sub-capacitor and the second sub-capacitor may be connected in such a manner that the lower plate of the first sub-capacitor is connected to VRP and the lower plate of the second sub-capacitor is connected to VRN. Alternatively, the first sub-capacitor and the second sub-capacitor may be connected in such a manner that the lower plate of the first sub-capacitor is connected to VRN and the lower plate of the second sub-capacitor is connected to VRP.

[0074] In a feasible implementation manner, the above step S30 further includes:

[0075] Step S303: connecting the lower plate of the first low-level capacitor to the first preset voltage, and connecting the lower plate of the second low-level capacitor to the second preset voltage;

[0076] Step S304: connecting the lower plate of the first low-level capacitor to the second preset voltage, and connecting the lower plate of the second low-level capacitor to the first preset voltage.

[0077] It is understandable that the first low-level capacitor and the second low-level capacitor have the following relationship:

[0078] If the highest bit H6 is 32 potential capacitors, then H1G is 1 potential capacitor, H1 is 1 potential capacitor, H2 is 2 potential capacitors, H3 is 4 potential capacitors, H4 is 8 potential capacitors, and H5 is 16 potential capacitors. It can be seen that the number of potential capacitors in H3 is equal to the sum of the number of potential capacitors in H1G to H2. Therefore, H3 and H1G to H2 can be considered as a sampling capacitor as a whole. Therefore, by connecting the lower plate of H3 to either the first preset voltage or the second preset voltage, and then connecting the lower plates of H1G to H2 to the other of the first preset voltage or the second preset voltage, the common-mode level of the comparator input can be ensured to be close to VCM.

[0079] For example, the lower plate of H3 can be connected to VRP, and the lower plates of H1G to H2 can be connected to VRN; or, the lower plate of H3 can be connected to VRN, and the lower plates of H1G to H2 can be connected to VRP.

[0080] Step S40, obtaining a comparison result output by the comparator in the SAR ADC;

[0081] It can be understood that during the conversion phase, the first and second control signals output by the digital logic circuit in the SAR ADC will respectively cause the first and second capacitor arrays to redistribute charge. After charge redistribution, the upper plates of the capacitor arrays will generate new analog signals: the negative comparison signal V- and the positive comparison signal V+. V- and V+ serve as input signals for the comparator, which performs the comparison. The comparison result mentioned above refers to the comparison result of V- and V+.

[0082] Step S50 , looping the steps of adjusting the connection object of each lower electrode plate based on the comparison result and obtaining the comparison result output by the comparator in the SAR ADC until the conversion is completed.

[0083] It is understandable that the above comparison result will also serve as the input of the digital logic circuit in the SAR ADC, and then the digital logic circuit will generate a new first control signal and a new second control signal and a digital code with the highest bit converted according to the result of the comparator output. Then, the new first control signal and the new second control signal will continue to control the second highest bit of the first capacitor array and the second capacitor array, thereby obtaining a new comparison result and generating a digital code with the second highest bit converted. Similarly, when the SAR ADC is 7 bits, a 7-bit digital output can be obtained through 7 comparisons.

[0084] It should be noted that during the conversion process, each comparison requires adjusting the connection destination of the lower plate to ensure a successive approximation of the input signal, while keeping the common-mode voltage at the comparator input close to VCM. Therefore, after obtaining the comparison result from the first comparison, not only is it necessary to derive a digital code based on the first comparison result, but the connection destination of the lower plate in the first capacitor array or the second capacitor array must also be adjusted based on the first comparison result.

[0085] Specifically, when the first capacitor array corresponds to the V- side and the second capacitor array corresponds to the V+ side, since the two sub-capacitors of the split capacitor are connected to VRP and VRN respectively, when comparing the high position represented by the split capacitor, even if the connection object is adjusted, the lower plates of the first capacitor array and the second capacitor array are still equivalently connected to VCM. However, when comparing the low position represented by the low-position capacitor, since the lower plates of the low-position capacitors in the original first capacitor array and the second capacitor array are connected to the same receiving object, the method of adjusting the connection object is mainly "connecting the lower plate of one side originally connected to VRP to VRN" or "connecting the lower plate of one side originally connected to VRN to VRP". Therefore, in the comparison stage corresponding to the low-position capacitor, the common mode level of the comparator input will take VCM as the starting point, showing a trend of first rising and then falling or first falling and then rising, and then falling back to VCM.

[0086] In a feasible implementation manner, the above step S50 includes:

[0087] Step S501, determining an array to be adjusted in the first capacitor array and the second capacitor array based on the comparison result;

[0088] Step S502, determining a capacitance to be adjusted in the array to be adjusted;

[0089] It is understood that the capacitance to be adjusted is the capacitance of the current operating bit in the array to be adjusted. For example, if the operating bit at the last moment was H4, the capacitance of the current operating bit is H3; if the operating bit at the last moment was H3, the capacitance of the current operating bit is H2.

[0090] Step S503: When it is detected that the array to be adjusted includes the first capacitor array and the second capacitor array, connecting the lower plates of the capacitors to be adjusted in the first capacitor array and the lower plates of the capacitors to be adjusted in the second capacitor array to a first preset voltage and a second preset voltage, respectively;

[0091] It can be understood that the connection method between the lower plate and the first preset voltage and the second preset voltage can be: the lower plate of the capacitor to be adjusted in the first capacitor array is connected to the first preset voltage, and the lower plate of the capacitor to be adjusted in the second capacitor array is connected to the second preset voltage; it can also be that the lower plate of the capacitor to be adjusted in the first capacitor array is connected to the second preset voltage, and the lower plate of the capacitor to be adjusted in the second capacitor array is connected to the first preset voltage.

[0092] Step S504: When it is detected that the array to be adjusted is the first capacitor array or the second capacitor array, if it is detected that the current connection object of the capacitor to be adjusted is the first preset voltage, the lower plate of the capacitor to be adjusted is connected to the second preset voltage; if it is detected that the current connection object of the capacitor to be adjusted is the second preset voltage, the lower plate of the capacitor to be adjusted is connected to the first preset voltage.

[0093] It should be noted that the array to be adjusted refers to the array in the first capacitor array and the second capacitor array that needs to adjust the voltage. Among them, the first capacitor array and the second capacitor array in the present application contain both split capacitors and unsplit capacitors. When operating the split capacitors, the first capacitor array and the second capacitor array both need to adjust the voltage. Therefore, at this time, the first capacitor array and the second capacitor array are both arrays to be adjusted. When operating the unsplit capacitors, a capacitor array will be selected from the first capacitor array and the second capacitor array as the array to be adjusted based on the comparison result.

[0094] Exemplarily, when the first capacitor array and the second capacitor array both include H6, H5, H4, H3, H2 and H1 (H6 to H4 are split capacitors), the conversion process will operate H6, H5, H4, H3, H2 and H1 in sequence. Specifically, after the first conversion is completed, H6 will be operated, and then H5 will be operated. In a feasible embodiment, the connection method in the sampling phase is: the lower plates of the two sub-capacitors split from H6 in the first capacitor array, the lower plates of the two sub-capacitors split from H5, and the lower plates of the two sub-capacitors split from H4 are all connected to VIP; the lower plates of the two sub-capacitors split from H6 in the second capacitor array, the lower plates of the two sub-capacitors split from H5, and the lower plates of the two sub-capacitors split from H4 are all connected to VIN; the method of adjusting the lower plate is:

[0095] After the first conversion is completed, the digital logic circuit will output the first control signal and the second control signal. Then, the first control signal and the second control signal will determine which voltage is lower, the negative comparison signal V- or the positive comparison signal V+, based on the result of the comparator output during the first conversion. Then, the two sub-capacitors of H6 on the side with the lower voltage are connected to VRP, and the two sub-capacitors of H6 on the side with the higher voltage are connected to VRN. Since H6 is a split capacitor in the first capacitor array and the second capacitor array, it can be equivalently regarded as connected to VCM. Now one side is connected to VRP and the other side is connected to VRN. Therefore, after adjusting the connection object, the common mode level of the comparator input is still VCM. H5 and H4 are both split capacitors, and their operating principles are similar to H6. This application will not go into details here.

[0096] When the conversion operation reaches the H3 bit, the first and second control signals output by the digital logic circuit will determine which voltage is lower, the negative comparison signal V- or the positive comparison signal V+, based on the previous comparator output result. The lower voltage side will be used as the array to be adjusted. Similarly, when the operation reaches the H2 or H1 bit, the first and second control signals output by the digital logic circuit will determine which voltage is higher, the negative comparison signal V- or the positive comparison signal V+, based on the previous comparator output result. The higher voltage side will be used as the array to be adjusted. At this time, the common-mode level will show a pattern of first rising and then falling.

[0097] In one feasible embodiment, during the first conversion, H3 in the first capacitor array is switched from VIP to VRN during the sampling phase; H2, H1, and H1G in the first capacitor array are switched from VIP to VRP during the sampling phase; and H3 in the second capacitor array is switched from VIN to VRN during the sampling phase; and H2, H1, and H1G in the second capacitor array are switched from VIN to VRP during the sampling phase; when the conversion operation reaches the H3 bit, the first control signal and the second control signal output by the digital logic circuit will determine which voltage is lower, the negative comparison signal V- or the positive comparison signal V+, based on the result of the comparator output at the previous moment, and then switch the lower plate of the capacitor H3 on the side with the lower voltage from VRN to VRP, while the side with the higher voltage remains unchanged (i.e., the lower plate of the capacitor remains connected to VRN). Since H3 in the first and second capacitor arrays was originally connected to VRN, but one side is now connected to VRP, after adjusting the connection object, the common mode level of the comparator input will be slightly greater than VCM.

[0098] Then, the H2 bit can be operated and the connection object of H2 in the array to be adjusted can be adjusted according to the comparison result corresponding to the H3 bit. And so on, until all the bits in the SAR ADC are compared.

[0099] It is understandable that, because the weights of the lower bits in the SAR ADC are small, the deviation from VCM is very small, and the comparator's input common-mode level can still be considered to be maintained near VCM. Furthermore, the final bit comparison is completed, allowing the comparator's input common-mode level to return to VCM. Therefore, this application can achieve the goal of controlling the comparator's common-mode level near VCM.

[0100] In addition, in a feasible embodiment, when sampling through the upper plate, during the conversion phase, the upper plate will only be connected to the output of the comparator, while the lower plate will still be connected to the first preset voltage or the second preset voltage, and the lower plate will also automatically adjust the connected voltage according to the comparison result, thereby achieving the purpose of controlling the common mode level of the comparator to be near VCM, which also falls within the protection scope of this application.

[0101] In this embodiment, the present application only involves split capacitors and switch timing, and the plates used for sampling in the capacitor array of the present application are only switched to the first preset voltage or the second preset voltage, and are not switched to VCM. Therefore, compared with traditional technologies, the present application does not require an additional VCM generation module with speed requirements; thus, the present application achieves the purpose of controlling the common mode level of the comparator near VCM under low-cost conditions by combining split capacitors and switch timing.

[0102] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the common-mode level adjustment method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0103] Furthermore, to solve the above problems, the present application also proposes a SAR ADC architecture, which includes:

[0104] a first capacitor array, wherein sampling capacitors of the first capacitor array include split capacitors and unsplit capacitors, a lower plate of each capacitor in the first capacitor array is connected to a first input signal, a first preset voltage, and a second preset voltage collected by the first capacitor array, and a top plate of each capacitor in the first capacitor array is connected to VCM; the first preset voltage and the second preset voltage have opposite polarities;

[0105] a second capacitor array, wherein the sampling capacitors of the second capacitor array include split capacitors and unsplit capacitors, the lower plates of the capacitors in the second capacitor array are connected to the second input signal, the first preset voltage, and the second preset voltage collected by the second capacitor array, and the upper plates of the capacitors in the first capacitor array are connected to VCM;

[0106] a comparator, wherein a first input terminal of the comparator is connected to the first capacitor array, and a second input terminal of the comparator is connected to the second capacitor array;

[0107] A digital logic circuit, wherein the input end of the digital logic circuit is connected to the output end of the comparator, the first output end of the digital logic circuit is connected to the first capacitor array, the second output end of the digital logic circuit is connected to the second capacitor array, and the third input end of the digital logic circuit is used to output a digital code.

[0108] It can be understood that the common-mode level adjustment method of the present application is mainly used to adjust the connection objects of the lower plates in the first capacitor array and the second capacitor array to achieve the purpose of making the common-mode level of the comparator input terminal close to VCM.

[0109] In addition, in a feasible embodiment, the first capacitor array and the second capacitor array both include redundant capacitors, and the connection objects of the lower plates of the redundant capacitors include: the first preset voltage and the second preset voltage; the connection objects of the upper plates of the redundant capacitors include: VCM.

[0110] It is understandable that in this application, the redundant capacitor can be placed after any binary capacitor. The redundant capacitor can protect the capacitor in front of it and provide a certain range of redundancy for the capacitor in front of it. It can be seen that by providing redundant capacitors in the first capacitor array and the second capacitor array, the present application can achieve the purpose of correction while ensuring that the common mode level is close to VCM.

[0111] For example, please refer to Figure 2 , Figure 2 This is a schematic diagram of the first embodiment of the SAR ADC architecture of this application. Specifically, Figure 2 This is a schematic diagram of a seven-bit SAR ADC architecture with a redundant structure. Figure 2 The DAC capacitor array in Figure 1 is composed of binary capacitors and redundant capacitors. H4R and H1R are redundant capacitors that can be placed after any binary capacitor. The redundant capacitors protect the capacitors in front of them and provide a certain degree of redundancy.

[0112] Figure 2 During the sampling phase, except for the redundant capacitors (H4R and H1R), the remaining capacitors (H6, H5, H4, H3, H2, H1, and H1G) all participate in sampling. At this time, the comparator inputs, namely the upper plates of the first and second capacitor arrays, are connected to VCM through switches. As for the lower plates of the DAC capacitor arrays, the lower plates of the remaining capacitors in the first capacitor array are connected to VIP, and the lower plates of the remaining capacitors in the second capacitor array are connected to VIN. H4R in the first and second capacitor arrays is split into H4RP and H4RN, with the lower plate of H4RP connected to VRP and the lower plate of H4RN connected to VRN. The lower plates of H1R in the first and second capacitor arrays are connected to VRP.

[0113] Figure 2After sampling is complete, the conversion phase begins. For the first conversion, the switches connected to VCM for the comparator inputs, i.e., the upper plates of the first and second capacitor arrays, are disconnected, placing the upper plates of the capacitor arrays in a high-impedance state. The lower plates of the DAC capacitor arrays, H4R and H1R in the first and second capacitor arrays, are connected in the same manner as during the sampling phase. H6 in the first capacitor array is split into H6P and H6N, where the lower plate of H6P is switched from VIP to VRP during the sampling phase, and the lower plate of H6N is switched from VIP to VRN during the sampling phase; the switching mode of the lower plates of H5 and H4 in the first capacitor array is the same as that of H6; H3 in the first capacitor array is switched from VIP to VRN during the sampling phase; H2, H1, and H1G in the first capacitor array are switched from VIP to VRP during the sampling phase; and H6 in the second capacitor array is split into H6P and H6N, where the lower plate of H6P is switched from VIN to VRP during the sampling phase, and the lower plate of H6N is switched from VIN to VRN during the sampling phase; the switching mode of the lower plates of H5 and H4 in the second capacitor array is the same as that of H6; H3 in the second capacitor array is switched from VIN to VRN during the sampling phase; H2, H1, and H1G in the second capacitor array are switched from VIN to VRP during the sampling phase;

[0114] From the above analysis, we can see that during the sampling phase, the capacitors involved in sampling are considered a single entity, and this equivalent entity is called the sampling capacitor. At the end of sampling, during the first conversion phase, for both the first and second capacitor arrays, half of the sampling capacitors are connected to VRP and half to VRN, effectively treating them as if they were connected to VCM. Therefore, during the first conversion, the sampling capacitors of the first capacitor array are switched from VIP to VCM, while the sampling capacitors of the second capacitor array are switched from VIN to VCM.

[0115] Therefore, by Figure 2 As can be seen from the above analysis, the high-order bits of the DAC capacitor array are switched by split capacitor switches. That is, the capacitor in the dotted box in the figure can actually be regarded as a whole capacitor, which is split into two capacitors. When the switch of one capacitor is connected to the positive reference voltage VRP and the switch of the other capacitor is connected to the negative reference voltage VRN, it can be regarded as equivalent to the switch of the whole capacitor being connected to the common mode voltage VCM. The relationship between VRP, VRN and VCM can be shown by formula (1):

[0116]

[0117] Since the working principle of SAR ADC is to use the binary successive approximation method, the capacitor array satisfies the binary relationship. Figure 2 The lowest bit H1 is 1 unit capacitance Cu, then Figure 2The highest bit, H6, has 32 Cus, while H5 has 16 Cus and H4 has 8 Cus. Since H4R is a redundant capacitor, its number of capacitors remains the same as the previous bit, also 8 Cus. The larger the number of capacitors, the longer the required setup time. To ensure that the setup time meets the requirements, the larger the number of capacitors, the smaller the switching impedance needs to be, which means that more switches are required. Considering the overall layout, if a set of switches is assigned for every 4 Cus, subsequent bits with fewer than 4 Cus should also be assigned a set of switches. Therefore, the number of switches required for the first four bits, H6, H5, H4, and H4R, is greater than or equal to 2. Therefore, using split capacitor switching for these four bits does not increase the number of switches or the complexity of the layout wiring. Therefore, using split capacitor switching for these first four bits achieves the equivalent connection of the capacitor's lower plate to the common-mode level, VCM, without any additional cost. Therefore, during the conversion phase, the comparator input common-mode level remains stable at VCM for these first four bits. Because the first few bits carry a significant weight, they significantly impact the comparator input common-mode level. Keeping the comparator input common-mode level stable near VCM improves SAR ADC performance. Therefore, it's crucial to keep the comparator input common-mode level stable at VCM when comparing the first few bits. It's worth noting that the higher bits of the DAC capacitor array can also utilize thermometer coding, resulting in improved differential nonlinearity (DNL) and integral nonlinearity (INL) performance.

[0118] and Figure 2 For the lower bits, due to the smaller number of capacitors, using split-capacitor switching would increase the number of switches and the complexity of the layout wiring. Furthermore, due to their small weights, the lower bits have little impact on the comparator input common-mode level. Therefore, bidirectional switching can be used for the lower bits. Although this technique causes the comparator input common-mode level to deviate from VCM, the smaller weights of the lower bits minimize the deviation, maintaining the comparator input common-mode level near VCM. Furthermore, the final bit comparison completes, allowing the comparator input common-mode level to return to VCM.

[0119] Figure 2 The lower bits of the 1 / 4 bit use a bidirectional switching technology that makes the common mode level rise first and then fall. Figure 2It can be seen that the sampling is completed and the conversion stage begins. The lower plate of the capacitor of H3 is connected to VRN, and the lower plates of the capacitors of H2, H1 and H1 R are all connected to VRP. Therefore, when the conversion operation reaches the position of H3, the first control signal and the second control signal output by the digital logic circuit will judge which voltage is lower, the negative comparison signal V- or the positive comparison signal V+, based on the result of the comparator output at the previous moment, and switch the lower plate of the capacitor of H3 on the side with lower voltage from VRN to VRP, while the side with higher voltage remains unchanged, and the lower plate of the capacitor is still connected to VRN. Since the lower plate of the H3 capacitor on one side is connected from VRN to VRP, the input common mode level of the comparator will increase. Similarly, since the lower plate of the capacitor of H2 is connected to VRP at the beginning, when the operation reaches the position where H2 is located later, only one side can be changed to VRN, so the input common mode level of the comparator will decrease. Therefore, Figure 2 The lower bits of the digits are consistent with the common mode level rising first and then falling.

[0120] Please also refer to Figure 2 and Figure 3 , Figure 3 Schematic diagram of the change of the common-mode level of the comparator input of the SAR ADC architecture of this application. Figure 3 The horizontal axis represents the number of comparisons in the conversion phase ( Figure 2 There are 7 binary capacitors and 2 redundant capacitors, so 9 comparisons are required). The vertical axis represents the normalized comparator common mode level, where 0.5 represents the VCM value. Figure 2 It can be seen that: During the sampling phase, the comparator inputs are all connected to VCM, and the redundant capacitors do not participate in sampling. At this time, the capacitors involved in sampling can be considered as a whole, and this equivalent whole is called the sampling capacitor. At the end of sampling, entering the first conversion of the conversion phase, half of the sampling capacitors are connected to VRP and the other half are connected to VRN. This can be equivalent to the sampling capacitor being connected to VCM. Therefore, in the first conversion, the negative comparison signal V- and the positive comparison signal V+ of the comparator input can be expressed as:

[0121]

[0122] Among them, V -,1 The negative comparison signal for the first conversion, V +,1 is the diagnostic comparison signal for the first conversion, CSAMP represents the sampling capacitor on one side, and CTOT represents the total capacitance on one side. VIP represents the first input signal, and VIN represents the second input signal. Due to the fully differential input, the relationship between VIP, VIN, and VCM can be expressed as follows:

[0123]

[0124] Therefore, the first conversion of the comparator input differential mode level ΔVI,1 and the common-mode level VCM1 can be expressed as:

[0125]

[0126] Among them, VI represents the difference between VIP and VIN. It can be seen that after the first conversion is completed, the comparator input differential mode level is The comparator input common mode level is still VCM. Assuming ΔV I,1 >0, which proves that the positive comparison signal V+ of the comparator input is greater than the negative comparison signal V-. Therefore, in the second conversion, only the capacitor at the position of H6 is operated. At this time, the lower plate of H6N in the capacitor H6 on the V- side is switched from VRN to VRP, and the lower plate of H6P remains connected to VRP; the lower plate of H6P in the capacitor H6 on the V+ side is switched from VRP to VRN, and the lower plate of H6N remains connected to VRN. The above operation can be equivalently regarded as the lower plate of capacitor H6 on the V- side is switched from VCM to VRP, and the lower plate of capacitor H6 on the V+ side is switched from VCM to VRN. Therefore, in the second conversion, the negative comparison signal V- of the comparator input, the positive comparison signal V+, and the comparator input differential mode level ΔV I,2 and the common-mode level VCM2 can be expressed as:

[0127]

[0128] Among them, V -,2 is the negative comparison signal of the second conversion, V +,2 is the positive comparison signal of the second conversion, VR represents the difference between VRP and VRN. It can be seen that after the second conversion is completed, the comparator input differential mode level is The comparator input common mode level is still VCM.

[0129] Similarly, from the third to the fifth conversion, since they are all split capacitor switches, it can be equivalently considered that one side of the capacitor's lower plate switches from VCM to VRP, and the other side switches from VCM to VRN. Therefore, from the third to the fifth conversion, the comparator input common-mode level is still VCM. From the previous analysis, it can be seen that in the sixth conversion, the lower plate of the H3 capacitor will switch from VRN to VRP, while the other side will remain at VRN unchanged. At this time, the comparator input common-mode level will increase, as shown in Figure 1. Figure 3 The sixth segment shows that the common-mode level first rises and then falls. That is, the comparator input common-mode level VCM6 of the sixth conversion is:

[0130]

[0131] Here, CTOT represents the total capacitance on one side. In addition, due to normalization, the value of VCM is 0.5.

[0132] As can be seen from the above formula, the deviation of the comparator input common mode level VCM6 in the sixth conversion is very small and remains close to VCM. Similarly, from the seventh conversion to the ninth conversion, the lower plate of the capacitor will switch from VRP to VRN, while the other side will remain at VRP unchanged. At this time, the comparator input common mode level will decrease, such as Figure 3 As shown in the seventh to ninth segments where the common-mode level first rises and then falls, it can be seen that the input common-mode level of the comparator gradually approaches VCM and eventually returns to VCM.

[0133] In this embodiment, the redundant capacitors in the redundant architecture can be placed after any binary capacitor. The redundant capacitors can protect the capacitors preceding them, providing a certain degree of redundancy for the preceding capacitors. Furthermore, the present application utilizes split capacitors and bidirectional switching technology, which allows the comparator input common-mode level to be maintained near VCM without increasing circuit complexity. Furthermore, in conventional technology, due to the short conversion time during the conversion phase, conversion speed is required. If the lower plate of the capacitor array switches to VCM during this time, an additional VCM generation module is required. Furthermore, if the switch is connected to VCM, a transmission gate, i.e., a switch composed of PMOS and NMOS transistors, is required. This switch has a relatively high impedance, which can affect the settling speed. However, in the present application, the lower plate of the capacitor array only switches to VRP or VRN, not VCM. Therefore, an additional VCM generation module with speed requirements is not required. Furthermore, the switch connected to VRP requires only PMOS transistors, and the switch connected to VRN requires only NMOS transistors. Compared to the aforementioned transmission gate, the impedance can be made very low for the same area, or the area can be made very small for the same impedance. Therefore, this application can save more hardware expenses and have better performance.

[0134] Therefore, compared with the traditional switch switching method, the present application adopts split capacitor plus bidirectional switch switching technology, so that the capacitor array can save half the number of capacitors, that is, save half the area; and the power consumption of the switch switching of the present application will be greatly reduced, and the switching timing will become simpler, which can greatly improve the competitiveness of the present application.

[0135] For further information, please refer to Figure 4 , Figure 4 This is a schematic diagram of the second embodiment of the SAR ADC architecture of the present application.

[0136] It is understandable that Figure 2 The example given in Figure 3 In the common mode, the level rises first and then falls. Figure 4 The example given is Figure 3 The common mode level first decreases and then increases. Specifically, Figure 4 and Figure 2The main difference is that in the sampling phase, H1R is connected to VRN; in the conversion phase, such as the first conversion, H3 is connected to VRP, while H2, H1, H1R, and H1G are all connected to VRN. Therefore, in the sixth conversion, H3 can only switch the lower plate of one side of the capacitor from VRP to VRN, while the other side remains at VRP. Therefore, the common-mode level of the comparator input in the sixth conversion will be reduced, such as Figure 3 The common-mode level first decreases and then increases as shown in the sixth segment; and in the subsequent seventh to ninth transitions, the lower plate of the capacitor switches from VRN to VRP, while the other side remains at VRN unchanged. At this time, the common-mode level of the comparator input increases, as shown in Figure 3 From the seventh to the ninth segments, where the common-mode level first decreases and then increases, it can be seen that the input common-mode level of the comparator gradually approaches VCM and eventually returns to VCM.

[0137] For further information, please refer to Figure 5 , Figure 5 This is a schematic diagram of the third embodiment of the SAR ADC architecture of the present application.

[0138] It is understandable that Figure 2 It can be seen that during the sampling phase, the comparator inputs are all connected to VCM, and the redundant capacitors do not participate in sampling. Since H4R is a split capacitor, its lower plate can be equivalently considered to be connected to VCM during the sampling phase, so H4R does not store charge during the sampling phase. However, the lower plate of H1R is connected to VRP during the sampling phase, so the amount of charge stored by H1R during the sampling phase can be expressed as:

[0139] Q H1R =C H1R (VCM-VRP) = C u (VCM-VRP)# formula (12)

[0140] When the sampling is finished and the conversion phase begins, H1G will be connected to VRP. During the entire conversion phase, H1G is constantly connected to VRP. Figure 3 It can also be seen that when the entire conversion phase is completed, the common-mode voltage of the comparator will return to VCM. Therefore, when the conversion phase is completed, the amount of charge stored in H1G can be expressed as:

[0141] Q H1G =C H1G (VCM-VRP) = C u (VCM-VRP)# formula (13)

[0142] It can be seen from this that the charge stored on H1R during the sampling phase will eventually be transferred to H1G. Therefore, this charge has no effect on the entire conversion process and does not affect the linearity of the ADC output code.

[0143] Assume that H1G is always connected to VRP during the sampling and conversion phases, while H1R participates in sampling during the sampling phase, i.e. the switch on the lower plate of H1R is connected to the input signal VIP or VIN, and H1R follows VRP during the conversion phase. Figure 2 According to this assumption, the amount of charge stored on H1G during the sampling phase is equal to the amount of charge stored during the conversion phase, that is, the amount of charge expressed by equations (12) and (13), and the entire principle derivation is consistent with Figure 2 It is completely consistent. Therefore, the role of H1G is only to store a part of the charge, and it does not play a substantial role in the entire conversion process. Therefore, H1G can be completely removed. When H1G is removed, we can get Figure 5 An extended embodiment of . Figure 5 and Figure 2 The main difference is that H1G is removed. In the sampling phase, H1R will participate in the sampling; in the first conversion, H1R will receive VRP. The whole conversion process is the same as Figure 2 It is worth mentioning that Figure 5 It can also be slightly modified to become a bidirectional switch switching common mode level first drop and then rise structure, which is also within the protection scope of this application.

[0144] Furthermore, based on the above-mentioned embodiments of the SAR ADC architecture of the present application, a fourth embodiment of the SAR ADC architecture of the present application is proposed.

[0145] In this embodiment, the SAR ADC architecture further includes: a sampling switch, which is a bootstrap switch, one end of which is connected to the lower plate, and the other end of which is connected to a connection object of the lower plate.

[0146] It is understandable that if high accuracy is required for the ADC, the sampling switches of the DAC capacitor array can use bootstrap switches. Currently, sampling switches are typically implemented using MOS transistors. However, the amplitudes of the input signals VIP and VIN vary at different sampling times. For conventional MOS transistor switches, if the input signal connected to one end of the switch changes, the gate-source voltage difference VGS of the switch will also change, causing the switch impedance to change. This change in switch impedance, in turn, affects sampling accuracy. Therefore, the sampling switches in this embodiment can use bootstrap switches to improve accuracy.

[0147] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the fourth embodiment of the SAR ADC architecture of the present application. Figure 6In the figure, C1 represents the bootstrap capacitor, M1, M2, through Mn represent the sampling switches, VIN represents the input signal, and the input signal on the other side of the capacitor array is represented by VIP. CB1, CB2, through CBn represent the bottom plate of the capacitor array. During the non-sampling phase, the bootstrap capacitor C1 in the bootstrap switch charges. Its two terminals are connected to the power supply VDD and ground VSS, respectively. Since ground VSS is generally at zero potential, when the bootstrap capacitor C1 is fully charged, the voltage difference across it equals the power supply voltage VDD. At this time, the gates of the sampling switches are both connected to VSS, so the sampling switches are disconnected. During the sampling phase, the switch that originally connected the bootstrap capacitor C1 to VSS is disconnected and connected to one terminal of the sampling switch and the input signal VIN. The switch that originally connected the bootstrap capacitor C1 to VDD is also disconnected and connected to the gate of the sampling switch. Since the voltage across the capacitor does not change suddenly, the voltage difference is still VDD. Therefore, the gate-source voltage VGS of the sampling switch is the voltage across the capacitor and does not change with the change of the input signal VIN. Therefore, the impedance of the sampling switch is stable. And because the gate-source voltage of the sampling switch is the power supply voltage VDD, the impedance of the sampling switch is also small, which can effectively improve the sampling performance. In addition, Figure 6 In the sampling switch embodiment, all sampling switches on a single side of the capacitor array share a bootstrap capacitor C1, which can significantly reduce the hardware cost of the bootstrap switches. In a feasible implementation, if the cost is sufficient, the bootstrap switches can also be configured to use one bootstrap capacitor per sampling switch.

[0148] Furthermore, based on the above-mentioned embodiments of the SAR ADC architecture of the present application, a fifth embodiment of the SAR ADC architecture of the present application is proposed.

[0149] In this embodiment, the SAR ADC architecture further includes:

[0150] a third capacitor array, the third capacitor array being connected to the first capacitor array via a first bridging capacitor; the lower plates of the capacitors in the third capacitor array being connected to the first preset voltage and the second preset voltage; and the upper plates of the capacitors in the third capacitor array being connected to one end of the first bridging capacitor;

[0151] A fourth capacitor array, wherein the fourth capacitor array is connected to the second capacitor array through a second bridging capacitor; the connection object of the lower plate of each capacitor in the fourth capacitor array includes: the first preset voltage and the second preset voltage; the connection object of the upper plate of each capacitor in the fourth capacitor array includes one end of the second bridging capacitor.

[0152] It should be noted that the third capacitor array and the fourth capacitor array both participate in binary operations and have a redundant function. Specifically, when the bridging capacitance is equal to a unit capacitance, all capacitors in the third capacitor array and the fourth capacitor array will participate in binary operations, that is, there will be no redundant capacitance; when the bridging capacitance is greater than a unit capacitance, all capacitors in the third capacitor array and the fourth capacitor array, in addition to the capacitors participating in binary operations, also have some redundant capacitance. This part of the redundant capacitance can be selected as redundant capacitance as needed, and the redundant capacitance can be inserted into the appropriate position in the third capacitor array or the fourth capacitor array to provide a certain range of redundant protection.

[0153] Please refer to Figure 7 , Figure 7 Schematic diagram of the fifth embodiment of the SAR ADC architecture of this application. Figure 2 compared to, Figure 7 exist Figure 2 On the basis of , a 5-bit low-segment capacitor array is added to form a 12-bit resolution SAR ADC architecture. Figure 7 In, originally located Figure 2 The capacitor arrays (the first capacitor array and the second capacitor array) in the are used as high-segment capacitor arrays, and the newly added third capacitor array and fourth capacitor array are used as low-segment capacitor arrays. Figure 7 middle, Figure 7 The low-segment capacitor array does not participate in the sampling operation. Therefore, in the sampling phase, the lower plate of the low-segment capacitor array will be connected to VRP or VRN, and will remain until the conversion phase operates on a certain bit of the low-segment capacitor array, at which point the lower plate switch of the capacitor will be switched. In addition, Figure 7 Due to the large number of capacitors, L5, L4, and L4R of the low-segment capacitor array use split capacitor switching; while L3, L2, L1, and L1R use bidirectional switching. It is worth noting that since the low-segment capacitor array has a small weight and has little impact on the comparator input common-mode level, split capacitor switching can be avoided and bidirectional switching can be used entirely. Furthermore, the low-segment capacitor array can also use unidirectional switching. Unidirectional switching will cause the comparator input common-mode level to monotonically increase or decrease. However, due to the low weight of the low-segment capacitor array, the final deviation of the comparator input common-mode level from VCM will not be too large.

[0154] In addition, in order to allow the low-segment capacitor array to have a certain redundancy range, the bridging capacitance is generally made larger than a unit capacitance, so the low-segment capacitor array will have some redundant capacitance. In most cases, these redundant capacitances are useless. The present application can cleverly utilize some of the redundant capacitances and make them redundant capacitances to participate in the conversion operation of the ADC, so that it can provide a certain range of error correction effects without the need to introduce additional redundant capacitances. In addition, the redundant architecture and switching timing of the present application are applicable to both high-segment capacitor arrays and low-segment capacitor arrays.

[0155] Furthermore, based on the above-mentioned embodiments of the SAR ADC architecture of the present application, a sixth embodiment of the SAR ADC architecture of the present application is proposed.

[0156] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the sixth embodiment of the SAR ADC architecture of the present application. Figure 8 and Figure 2 The difference is: Figure 8 It is a fully differential upper plate sampling SAR ADC architecture. Figure 2 It is a fully differential lower plate sampling SAR ADC architecture; that is, Figure 8 and Figure 2 The main difference is the sampling method. Figure 8 In the sampling phase, the comparator input, i.e., the upper plate of the capacitor array, is connected to VIN and VIP respectively, and the sampling switch connecting VIP, VIN and the upper plate can be a bootstrap switch. Figure 8 and Figure 2 Compared with , the timing is simpler and more power-saving. Figure 2 The lower plate sampling method has a higher accuracy. It can be seen that the redundant architecture and switch timing of the present application are applicable to both lower plate sampling and upper plate sampling.

[0157] It should be noted that the various embodiments of the SAR ADC architecture of the present application can also be arranged and combined to produce other embodiments, which are also within the scope of protection of the present application. In addition, the present application does not limit the resolution of the SAR ADC architecture. It is worth mentioning that in addition to the above-mentioned embodiments, the present application can also be used for pseudo-differential or single-ended SAR ADC architectures. In addition, if the present application is combined with a correction algorithm, it can achieve better performance.

[0158] The SAR ADC architecture provided in this application, employing the common-mode level adjustment method described in the aforementioned embodiments, can address the technical problem of reducing the cost of maintaining the common-mode level near VCM. Compared to the prior art, the beneficial effects of the SAR ADC architecture provided in this application are the same as those of the common-mode level adjustment method described in the aforementioned embodiments. Other technical features of the SAR ADC architecture are the same as those disclosed in the aforementioned embodiments and are not further elaborated here.

[0159] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the common-mode level adjustment method in the above-mentioned embodiment.

[0160] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0161] The above-mentioned computer-readable storage medium may be included in the electronic device that serves as the execution subject of this application; or it may exist independently without being assembled into the electronic device.

[0162] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device: in a sampling phase, connects the lower plate of the first capacitor array to the first input signal collected by the first capacitor array, connects the lower plate of the second capacitor array to the second input signal collected by the second capacitor array, and connects the upper plates of the first capacitor array and the second capacitor array to VCM; in a conversion phase, disconnects VCM, uses the first low-order capacitor in the direction from high to low as the first low-order capacitor, and uses the other low-order capacitors except the first low-order capacitor as the second low-order capacitor; connects the lower plate of the first sub-capacitor and the lower plate of the second sub-capacitor to a first preset voltage and a second preset voltage, respectively, and connects the lower plate of the first low-order capacitor and the lower plate of the second low-order capacitor to the first preset voltage and the second preset voltage, respectively; the first preset voltage and the second preset voltage have opposite polarities; obtains a comparison result output by the comparator in the SAR ADC; and loops through the steps of adjusting the connection object of each lower plate based on the comparison result and obtaining the comparison result output by the comparator in the SAR ADC until the conversion is completed.

[0163] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0164] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0165] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0166] The computer-readable storage medium provided herein stores computer-readable program instructions (i.e., a computer program) for executing the common-mode level adjustment method described above. This computer-readable storage medium addresses the technical problem of reducing the cost of maintaining the common-mode level near VCM. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided herein are similar to those of the common-mode level adjustment method provided in the aforementioned embodiments and are not further elaborated here.

[0167] The present application also provides a computer program product, including a computer program, which implements the steps of the common-mode level adjustment method as described above when the computer program is executed by a processor.

[0168] The computer program product provided in this application can solve the technical problem of how to reduce the cost required to maintain the common-mode level near VCM. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the common-mode level adjustment method provided in the above embodiment, and will not be repeated here.

[0169] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A common mode level adjustment method, characterized in that: The common-mode level adjustment method is applied to a SAR ADC, wherein the SAR ADC includes a first capacitor array and a second capacitor array, wherein high-order capacitors in the first capacitor array and the second capacitor array are split capacitors and low-order capacitors are unsplit capacitors; each of the split capacitors includes a first sub-capacitor and a second sub-capacitor; The common mode level adjustment method comprises: During the sampling phase, the lower plate in the first capacitor array is connected to the first input signal collected by the first capacitor array, the lower plate in the second capacitor array is connected to the second input signal collected by the second capacitor array, and the upper plates in the first capacitor array and the second capacitor array are connected to VCM; During the conversion phase, the VCM is disconnected, the first low-order capacitor from the high-order to the low-order is used as the first low-order capacitor, and the other low-order capacitors except the first low-order capacitor are used as the second low-order capacitor; Connecting the lower plate of the first sub-capacitor and the lower plate of the second sub-capacitor to a first preset voltage and a second preset voltage, respectively, and connecting the lower plate of the first low-order capacitor and the lower plate of the second low-order capacitor to the first preset voltage and the second preset voltage, respectively; the first preset voltage and the second preset voltage have opposite polarities; Obtaining a comparison result output by a comparator in the SAR ADC; The steps of adjusting the connection object of each lower electrode plate based on the comparison result and obtaining the comparison result output by the comparator in the SAR ADC are executed cyclically until the conversion is completed.

2. The common mode level adjustment method according to claim 1, wherein: The step of adjusting the connection object of each lower electrode plate based on the comparison result includes: determining an array to be adjusted in the first capacitor array and the second capacitor array based on the comparison result; determining a capacitance to be adjusted in the array to be adjusted; When it is detected that the array to be adjusted includes the first capacitor array and the second capacitor array, connecting the lower plate of the capacitor to be adjusted in the first capacitor array and the lower plate of the capacitor to be adjusted in the second capacitor array to a first preset voltage and a second preset voltage respectively; When it is detected that the array to be adjusted is the first capacitor array or the second capacitor array, if it is detected that the current connection object of the capacitor to be adjusted is the first preset voltage, the lower plate of the capacitor to be adjusted is connected to the second preset voltage; if it is detected that the current connection object of the capacitor to be adjusted is the second preset voltage, the lower plate of the capacitor to be adjusted is connected to the first preset voltage.

3. The common mode level adjustment method according to claim 1, wherein: Connecting the lower plate of the first low-level capacitor and the lower plate of the second low-level capacitor to the first preset voltage and the second preset voltage respectively includes: Connecting the lower plate of the first low-level capacitor to the first preset voltage, and connecting the lower plate of the second low-level capacitor to the second preset voltage; or, The lower plate of the first low-level capacitor is connected to the second preset voltage, and the lower plate of the second low-level capacitor is connected to the first preset voltage.

4. The common mode level adjustment method according to claim 1, wherein: The VCM is half of the sum of the first preset voltage and the second preset voltage.

5. A SAR ADC architecture, characterized in that: The SAR ADC architecture includes: a first capacitor array, wherein sampling capacitors of the first capacitor array include split capacitors and unsplit capacitors, a lower plate of each capacitor in the first capacitor array is connected to a first input signal, a first preset voltage, and a second preset voltage collected by the first capacitor array, and a top plate of each capacitor in the first capacitor array is connected to VCM; the first preset voltage and the second preset voltage have opposite polarities; a second capacitor array, wherein the sampling capacitors of the second capacitor array include split capacitors and unsplit capacitors, the lower plates of the capacitors in the second capacitor array are connected to the second input signal, the first preset voltage, and the second preset voltage collected by the second capacitor array, and the upper plates of the capacitors in the first capacitor array are connected to VCM; a comparator, wherein a first input terminal of the comparator is connected to the first capacitor array, and a second input terminal of the comparator is connected to the second capacitor array; A digital logic circuit, wherein the input end of the digital logic circuit is connected to the output end of the comparator, the first output end of the digital logic circuit is connected to the first capacitor array, the second output end of the digital logic circuit is connected to the second capacitor array, and the third input end of the digital logic circuit is used to output a digital code.

6. The SAR ADC architecture of claim 5, wherein: The first capacitor array and the second capacitor array both include redundant capacitors, and the connection objects of the lower plates of the redundant capacitors include: the first preset voltage and the second preset voltage; the connection object of the upper plates of the redundant capacitors includes: VCM.

7. The SAR ADC architecture of claim 5, wherein: The SAR ADC architecture further includes: The sampling switch is a bootstrap switch, one end of the sampling switch is connected to the lower plate, and the other end of the sampling switch is connected to a connection object of the lower plate.

8. The SAR ADC architecture of claim 5, wherein: The SAR ADC architecture further includes: a third capacitor array, the third capacitor array being connected to the first capacitor array via a first bridging capacitor; the lower plates of the capacitors in the third capacitor array being connected to the first preset voltage and the second preset voltage; and the upper plates of the capacitors in the third capacitor array being connected to one end of the first bridging capacitor; A fourth capacitor array, wherein the fourth capacitor array is connected to the second capacitor array through a second bridging capacitor; the connection object of the lower plate of each capacitor in the fourth capacitor array includes: the first preset voltage and the second preset voltage; the connection object of the upper plate of each capacitor in the fourth capacitor array includes one end of the second bridging capacitor.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the common-mode level adjustment method according to any one of claims 1 to 4 are implemented.

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