Approximate analog-to-digital converter and analog-to-digital conversion method thereof

Abstract

The invention discloses an approximation type analog-to-digital converter and an analog-to-digital conversion method thereof, and belongs to the technical field of power electronics. The approximation type analog-to-digital converter comprises a preloading capacitor array, a main capacitor array, a comparator and a logic switch controller; the working voltage of the main capacitor array and the working voltage of the preloading capacitor array are # imgabs 0 # times of the comparator; the execution logic of the logic switch controller comprises the following steps: controlling the preloaded capacitor array and the main capacitor array to sample a target analog signal; in the process of performing digital conversion on a target analog signal, an output result of a weight bit capacitor with a negative voltage electric leakage risk in a main capacitor array is quantized by using a preloading capacitor array and a comparator, and the result is assigned to the main capacitor array; and quantizing output results of other weight bit capacitors except for the risk of negative voltage electric leakage in the main capacitor array by using the main capacitor array and a comparator so as to obtain a digital signal corresponding to the target analog signal. By using the architecture, the power consumption and the conversion precision of the approximation type analog-to-digital converter can be balanced.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to an approximation analog-to-digital converter and an analog-to-digital conversion method thereof. Background Art

[0002] The Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is an energy-efficient analog-to-digital converter that is widely used in various application scenarios, such as wireless sensor network nodes, wearable electronic devices, implantable medical electronics, industrial control, and data acquisition.

[0003] Approximation-based analog-to-digital converters (A / D converters) are a popular choice for precision industrial applications due to their speed and energy efficiency. Today, A / D converters are continuously evolving toward higher precision and lower power consumption. To reduce the power consumption of A / D converters, one approach is to split the capacitors, split the capacitors with the highest weight, or change the switching behavior of the capacitor array. However, the power reduction achieved with these methods is limited. Another approach is to reduce the operating voltage of the A / D converter. However, this approach compresses the quantization range of the capacitor array, compromising the A / D converter's conversion accuracy.

[0004] When improving the conversion accuracy of an approximation-type analog-to-digital converter (ADC), each time the effective number of bits of the ADC increases by one, its dynamic range needs to be increased by 6dB. This means that the noise needs to be reduced by 6dB, or the noise power needs to be attenuated to one-fourth of its original value. However, for analog circuits, it is difficult to reduce the noise very low. In this technical context, in order to improve the conversion accuracy of an approximation-type ADC, the most direct approach is to increase the capacitance of the capacitors in the capacitor array by four times or to increase the operating voltage of the capacitor array by four times. However, in this case, if the operating speed of the ADC is to be maintained, its power consumption will increase by four times. Therefore, how to provide an approximation-type ADC with a high accuracy range and low power consumption is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention aims to provide an approximation-type analog-to-digital converter and an analog-to-digital conversion method thereof to solve the problem in the prior art of being unable to balance the power consumption and conversion accuracy of the approximation-type analog-to-digital converter. The specific solution is as follows:

[0006] In order to solve the above technical problems, the present invention provides an approximation type analog-to-digital converter, comprising: a preload capacitor array, a main capacitor array, a comparator and a logic switch controller; the operating voltage of the main capacitor array and the preload capacitor array is a multiple of the operating voltage of the comparator. times, ;

[0007] The execution logic of the logic switch controller includes:

[0008] Controlling the preload capacitor array and the main capacitor array to sample a target analog signal;

[0009] In the process of digitally converting the target analog signal using a successive approximation algorithm, the output results of the weighted capacitors in the main capacitor array with a risk of negative voltage leakage are quantized using the preload capacitor array and the comparator to obtain a target quantization result;

[0010] The target quantization result is assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk, so as to obtain a digital signal corresponding to the target analog signal.

[0011] Preferably, the preload capacitor array and the main capacitor array are both binary weighted capacitor arrays of a differential common mode.

[0012] Preferably, the setting factors of the common mode voltage of the preload capacitor array and the main capacitor array include: the operating voltage of the comparator.

[0013] Preferably, the conversion accuracy of the preload capacitor array is strongly correlated with the number of beats in the main capacitor array that have a risk of negative voltage leakage.

[0014] Preferably, the highest-weighted capacitor in the main capacitor array is a split capacitor array, and the main capacitor array includes two groups of first capacitor array and second capacitor array having the same arrangement structure.

[0015] Preferably, the highest-weighted capacitor in the preload capacitor array is a split capacitor array, and the preload capacitor array includes two groups of capacitor arrays with the same setting structure.

[0016] Preferably, the using the preload capacitor array and the comparator to quantize the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array to obtain the target quantization results includes:

[0017] quantizing output results of the highest-weighted capacitor and the second-highest-weighted capacitor in the main capacitor array that have a risk of negative voltage leakage using the preload capacitor array and the comparator, to obtain a first quantization result and a second quantization result, respectively;

[0018] Accordingly, assigning the target quantization result to the main capacitor array, and using the main capacitor array and the comparator to quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk to obtain a digital signal corresponding to the target analog signal, includes:

[0019] When the conversion accuracy of the main capacitor array is 4 bits, the first quantization result and the second quantization result are assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the lower two weight capacitors in the main capacitor array to obtain a digital signal corresponding to the target analog signal.

[0020] Preferably, assigning the first quantization result and the second quantization result to the main capacitor array, and using the main capacitor array and the comparator to quantize the output results of the lower two weight capacitors in the main capacitor array to obtain a digital signal corresponding to the target analog signal includes:

[0021] When the first capacitor array is the highest-weighted capacitor in the main capacitor array;

[0022] If the first quantization result is 1, the second capacitor array is searched for the second highest weighted capacitor in the main capacitor array to obtain a first screening capacitor, and the first screening capacitor is switched from ground to a reference voltage.

[0023] Preferably, when the first capacitor array is the highest-weighted capacitor in the main capacitor array, the method further includes:

[0024] If the first quantization result is 0, the second highest weighted capacitor in the main capacitor array is searched in the first capacitor array to obtain a second screening capacitor, and the second screening capacitor is switched from the reference voltage to the ground.

[0025] In order to solve the above technical problems, the present invention also provides an analog-to-digital conversion method of an approximation type analog-to-digital converter, which is applied to a logic switch controller in the approximation type analog-to-digital converter; the approximation type analog-to-digital converter includes: a preload capacitor array, a main capacitor array, a comparator and the logic switch controller; the operating voltage of the main capacitor array and the preload capacitor array is the working voltage of the comparator. times, ; The method comprises:

[0026] Controlling the preload capacitor array and the main capacitor array to sample a target analog signal;

[0027] In the process of digitally converting the target analog signal using a successive approximation algorithm, the output results of the weighted capacitors in the main capacitor array with a risk of negative voltage leakage are quantized using the preload capacitor array and the comparator to obtain a target quantization result;

[0028] The target quantization result is assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk, so as to obtain a digital signal corresponding to the target analog signal.

[0029] Beneficial effect: It can be seen that in the approximation type analog-to-digital converter provided by the present invention, a preload capacitor array, a main capacitor array, a comparator and a logic switch controller are provided; wherein the operating voltage of the main capacitor array and the preload capacitor array is 1 / 4 of the operating voltage of the comparator. times, When the approximation type analog-to-digital converter performs analog-to-digital conversion, its internal logic switch controller will first control the preload capacitor array and the main capacitor array to sample the target analog signal. In the process of digitally converting the target analog signal using the successive approximation algorithm, the preload capacitor array and the comparator will be used to quantize the output results of the weighted capacitors in the main capacitor array with negative voltage leakage risk to obtain the target quantization results. Afterwards, the logic switch controller will assign the target quantization results to the main capacitor array, and will use the main capacitor array and the comparator to quantize the output results of the other weighted capacitors in the main capacitor array except for the weighted capacitors with negative voltage leakage risk, thereby obtaining a digital signal corresponding to the target analog signal.

[0030] Compared to the prior art, because the main capacitor array, the preload capacitor array and the comparator operate in different voltage domains, and the operating voltages of the main capacitor array and the preload capacitor array are higher than the operating voltage of the comparator, this is equivalent to reducing the operating voltage of the comparator, thereby reducing the power consumption of the approximation type analog-to-digital converter. At the same time, since the main capacitor array and the comparator operate in different voltage domains, under this setting mode, if the main capacitor array wants to maintain the original conversion accuracy, there will be a risk of negative voltage leakage in the first few beats when executing the successive approximation algorithm. In order to avoid this problem, the present invention uses the preload capacitor array and the comparator to quantize the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array, obtain the target quantization result, and assign the target quantization result to the main capacitor array, so that the main capacitor array and the comparator can quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk according to the target quantization result, and then obtain a digital signal corresponding to the target analog signal, thereby retaining the conversion accuracy of the approximation type analog-to-digital converter while reducing the power consumption of the approximation type analog-to-digital converter. Furthermore, in the process of executing the successive approximation algorithm, the approximation type analog-to-digital converter directly obtains the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array from the preloaded capacitor array. In this way, the main capacitor array does not need to switch the timing switches of the weighted capacitors with negative voltage leakage risk, thereby further reducing the power consumption of the approximation type analog-to-digital converter. In summary, the approximation type analog-to-digital converter provided by the present invention can not only take into account the conversion accuracy of the approximation type analog-to-digital converter, but also reduce the power consumption of the approximation type analog-to-digital converter.

[0031] Correspondingly, the analog-to-digital conversion method of an approximation-type analog-to-digital converter provided by the present invention also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0033] Figure 1 A structural diagram of an approximation-type analog-to-digital converter provided by an embodiment of the present invention;

[0034] Figure 2 A structural diagram of another approximation-type analog-to-digital converter provided by an embodiment of the present invention;

[0035] Figure 3 For the general Figure 2A schematic diagram of a main capacitor array in an approximation-type analog-to-digital converter when the common-mode voltage VCM is set to 2.5V and the successive approximation algorithm is executed;

[0036] Figure 4 For the general Figure 2 Schematic diagram of a main capacitor array in an approximation-type analog-to-digital converter when the common-mode voltage VCM is set to 1.25V and a successive approximation algorithm is executed;

[0037] Figure 5 for Figure 2 A schematic diagram of the main capacitor array in the embodiment of the present invention when executing the successive approximation algorithm without loading the quantized output result of the preloaded capacitor array;

[0038] Figure 6 for Figure 2 A schematic diagram of the main capacitor array in the embodiment of the present invention when executing a successive approximation algorithm when loading the quantized output result of the preloaded capacitor array;

[0039] Figure 7 for Figure 2 Schematic diagram of the main capacitor array in the first step of the successive approximation algorithm;

[0040] Figure 8 for Figure 2 Schematic diagram of the main capacitor array when executing the second step of the successive approximation algorithm when the output result of the highest-weighted capacitor in the main capacitor array is 1;

[0041] Figure 9 for Figure 2 Schematic diagram of the main capacitor array when executing the second step of the successive approximation algorithm when the output result of the highest-weighted capacitor in the main capacitor array is 0;

[0042] Figure 10 The present invention provides a flowchart of an analog-to-digital conversion method of an approximation-type analog-to-digital converter. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] See Figure 1 , Figure 1The structure diagram of an approximation type analog-to-digital converter provided by an embodiment of the present invention includes: a preload capacitor array 11, a main capacitor array 12, a comparator 13 and a logic switch controller 14; the operating voltage of the main capacitor array 12 and the preload capacitor array 11 is the working voltage of the comparator 13. times, ;

[0045] The execution logic of the logic switch controller 14 includes:

[0046] Step 1: Control the preload capacitor array 11 and the main capacitor array 12 to sample the target analog signal;

[0047] Step 2: In the process of digitally converting the target analog signal using the successive approximation algorithm, the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array 12 are quantized using the preload capacitor array 11 and the comparator 13 to obtain the target quantization result;

[0048] Step 3: Assign the target quantization result to the main capacitor array 12, and use the main capacitor array 12 and the comparator 13 to quantize the output results of the other weighted capacitors in the main capacitor array 12 except the weighted capacitors with negative voltage leakage risk, so as to obtain a digital signal corresponding to the target analog signal.

[0049] In this embodiment, a new type of approximation type analog-to-digital converter is provided. The approximation type analog-to-digital converter can not only take into account the conversion accuracy of the approximation type analog-to-digital converter, but also reduce the power consumption of the approximation type analog-to-digital converter. The approximation type analog-to-digital converter is provided with: a preload capacitor array 11, a main capacitor array 12, a comparator 13 and a logic switch controller 14. Among them, the operating voltage of the main capacitor array 12 and the preload capacitor array 11 is 1 / 4 of the operating voltage of the comparator 13. times.

[0050] For the approximation type analog-to-digital converter, the main power consumption sources are the preload capacitor array 11, the main capacitor array 12, the comparator 13 and the logic switch controller 14. The conversion accuracy of the approximation type analog-to-digital converter is mainly determined by the main capacitor array 12. Therefore, when the operating voltage of the main capacitor array 12 and the preload capacitor array 11 is set to the operating voltage of the comparator 13, the operating voltage of the comparator 13 is 1 / 4 of the operating voltage of the comparator 13. When the conversion accuracy of the approximation type analog-to-digital converter is retained, the operating voltage of the comparator 13 is reduced, thereby reducing the power consumption required by the approximation type analog-to-digital converter.

[0051] When the operating voltages of the main capacitor array 12 and the preload capacitor array 11 are set to the operating voltage of the comparator 13 times, the main capacitor array 12, the preload capacitor array 11 and the comparator 13 are equivalent to working in different voltage domains. Since the main capacitor array 12 needs to switch back and forth between different voltage reference points when executing the successive approximation algorithm, if the main capacitor array 12 and the comparator 13 operate in different voltage domains, it may cause the main capacitor array 12 to have a voltage mutation during the timing switching process, thereby causing charge injection. This charge injection may cause the voltage of the main capacitor array 12 to be lower than the lower limit of its operating voltage, thereby causing the main capacitor array 12 to have a negative voltage leakage risk in the first few beats when executing the successive approximation algorithm.

[0052] In this embodiment, in order to avoid the occurrence of the above-mentioned problems, a preload capacitor array 11 is introduced into the approximation type analog-to-digital converter, and the preload capacitor array 11 and the comparator 13 are used to quantify the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array 12. Then, the output results of the preload capacitor array 11 are assigned to the main capacitor array 12, so that the main capacitor array 12 and the comparator 13 complete the digital conversion of the analog signal.

[0053] Specifically, the analog-to-digital conversion process of the approximation type analog-to-digital converter is triggered by the logic switch controller 14. When the logic switch controller 14 triggers the approximation type analog-to-digital converter to perform analog-to-digital conversion, the logic switch controller 14 will first control the preload capacitor array 11 and the main capacitor array 12 to sample the target analog signal. When the preload capacitor array 11 and the main capacitor array 12 have completed sampling the target analog signal, the logic switch controller 14 will use the successive approximation algorithm to perform digital conversion on the target analog signal. During this process, the logic switch controller 14 will first use the preload capacitor array 11 and the comparator 13 to quantize the output results of the weighted capacitors in the main capacitor array 12 that have a risk of negative voltage leakage to obtain the target quantization result.

[0054] It should be noted that the preload capacitor array 11 and the main capacitor array 12 described in this embodiment can be either a binary weighted capacitor array of a differential common model or a single-ended binary weighted capacitor array. As long as the working principle is similar to the working principle of the approximation type analog-to-digital converter provided in this embodiment, the circuit architecture of the approximation type analog-to-digital converter provided in this application can be used to balance the conversion accuracy of the approximation type analog-to-digital converter and the power consumption required. In addition, in different application scenarios, as the operating voltages of the main capacitor array 12, the preload capacitor array 11, and the comparator 13 are set differently, the number of beats of the main capacitor array 12 with the risk of negative voltage leakage when executing the successive approximation algorithm is also different.

[0055] When the preload capacitor array 11 and the comparator 13 quantize the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array 12 and obtain the target quantization results, the target quantization results will be assigned to the main capacitor array 12. After obtaining the target quantization results, the main capacitor array 12 will continue to quantize the output results of the other weighted capacitors in the main capacitor array 12 except for the weighted capacitors with negative voltage leakage risk with the comparator 13 based on the target quantization results, thereby obtaining a digital signal corresponding to the target analog signal.

[0056] Because the approximation-type ADC directly obtains the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array 12 from the preload capacitor array 11 during the execution of the successive approximation algorithm, the main capacitor array 12 does not need to switch the timing switches of the weighted capacitors with negative voltage leakage risk when executing the successive approximation algorithm, thereby further reducing the power consumption of the approximation-type ADC. In addition, under this configuration, the conversion accuracy of the approximation-type ADC is also taken into account.

[0057] Compared to the prior art, because the main capacitor array, the preload capacitor array, and the comparator operate in different voltage domains, and the operating voltages of the main capacitor array and the preload capacitor array are higher than the operating voltage of the comparator, this is equivalent to reducing the operating voltage of the comparator, thereby reducing the power consumption of the approximation type analog-to-digital converter. At the same time, since the main capacitor array and the comparator operate in different voltage domains, under this setting mode, if the main capacitor array wants to maintain the original conversion accuracy, there will be a risk of negative voltage leakage in the first few beats when executing the successive approximation algorithm. In order to avoid this problem, in this embodiment, the preload capacitor array and the comparator are used to quantize the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array, obtain the target quantization result, and assign the target quantization result to the main capacitor array, so that the main capacitor array and the comparator can quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk according to the target quantization result, and then obtain a digital signal corresponding to the target analog signal, thereby retaining the conversion accuracy of the approximation type analog-to-digital converter while reducing the power consumption of the approximation type analog-to-digital converter. Furthermore, when the approximation-type analog-to-digital converter executes the successive approximation algorithm, the main capacitor array directly obtains the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array from the preloaded capacitor array. In this way, the main capacitor array does not need to switch the timing switches of the weighted capacitors with negative voltage leakage risk, thereby further reducing the power consumption of the approximation-type analog-to-digital converter. In summary, the approximation-type analog-to-digital converter provided by this embodiment can not only take into account the conversion accuracy of the approximation-type analog-to-digital converter, but also reduce the power consumption of the approximation-type analog-to-digital converter.

[0058] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the preload capacitor array and the main capacitor array are both binary weighted capacitor arrays of a differential common model.

[0059] From a power consumption perspective, three main factors influence capacitor array power consumption: unit capacitance value, operating voltage, and capacitor switching timing. Smaller unit capacitance values ​​reduce capacitor array power consumption. However, the minimum unit capacitance value is determined by noise and capacitor mismatch, with capacitor mismatch generally playing a major role. A decrease in the capacitor array's operating voltage reduces the array's input voltage quantization range. Furthermore, an excessively low operating voltage increases the on-resistance of the sampling switches, causing them to vary with input voltage, introducing nonlinear distortion. Capacitor array switching timing, from highest to lowest power consumption, primarily includes traditional, Spilt (Split Capacitor Array Switching), set-and-down, and VCM-based switching. The average energy consumption of these four switching methods—traditional, Spilt, set-and-down, and VCM-based—is approximately 15:10:3:2.

[0060] In view of the above factors, in this embodiment, the preload capacitor array and the main capacitor array are set to a binary weighted capacitor array of a common model. In addition, since the binary weighted capacitor array of the differential common model has good anti-interference ability and can provide a higher signal-to-noise ratio under the same power supply voltage. At the same time, by setting the common mode signal, the positive and negative ends of the differential signal in the preload capacitor array and the main capacitor array can respectively charge the capacitor with the common mode signal as the reference, thereby ensuring that the common mode voltage of the preload capacitor array and the main capacitor array is stable. This stable common mode voltage signal can reduce the common mode variation of the comparator input signal and further improve the conversion accuracy of the approximation type analog-to-digital converter. Therefore, in this embodiment, the preload capacitor array and the main capacitor array are both set to a binary weighted capacitor array of a differential common model.

[0061] As a preferred implementation, the setting factors of the common mode voltage of the preload capacitor array and the main capacitor array include: the operating voltage of the comparator.

[0062] It is understood that the comparator can only correctly determine the magnitude of the input signal when the output voltages of the preload capacitor array and the main capacitor array fall within the effective input voltage range of the comparator. If the common-mode voltage of the preload capacitor array and the main capacitor array is set too high or too low, the output voltages of the preload capacitor array and the main capacitor array may exceed the input range of the comparator, thereby causing the comparator to misjudge. Therefore, to improve the accuracy of the comparator output result, the comparator's operating voltage should be considered when setting the common-mode voltage of the preload capacitor array and the main capacitor array.

[0063] As a preferred implementation, the conversion accuracy of the preload capacitor array is strongly correlated with the number of beats in the main capacitor array that have a risk of negative voltage leakage.

[0064] In practical applications, the conversion accuracy of the preload capacitor array is strongly correlated with the number of beats in the main capacitor array with a risk of negative voltage leakage. That is, the conversion accuracy of the preload capacitor array is strongly correlated with the number of weighted capacitor bits in the main capacitor array with a risk of negative voltage leakage.

[0065] In order to enable those skilled in the art to more clearly understand the implementation principle of the present application, the working principle of the approximation type analog-to-digital converter described in the present application is described in detail here by a specific example. Specifically, in the present embodiment, the main capacitor array and the preload capacitor array are both set to a binary weighted capacitor array of a differential common model, and the conversion accuracy of the main capacitor array is set to 4bit, and the conversion accuracy of the preload capacitor array is set to 2bit. That is, when the conversion accuracy of the main capacitor array is 4bit, there is a risk of negative voltage leakage in the first two beats when executing the successive approximation algorithm. Therefore, in the present embodiment, it is necessary to set the conversion accuracy of the preload capacitor array to 2bit.

[0066] In addition, it should be noted that in actual applications, factors such as the setting structure, switching timing, common-mode voltage setting parameters, and setting parameters of its internal capacitance of the main capacitor array will affect the number of beats with negative voltage leakage risk in the main capacitor array. Therefore, when facing the main capacitor array in a specific scenario, the main capacitor array should be specifically analyzed to determine the number of beats with negative voltage leakage risk in the main capacitor array. Only after analyzing the number of beats with negative voltage leakage risk in the main capacitor array can the conversion accuracy of the preload capacitor array be finally determined.

[0067] Generally speaking, if the conversion accuracy of the main capacitor array is 16 bits or lower, the risk of negative voltage leakage in the main capacitor array usually occurs in the first two beats. In other words, if the conversion accuracy of the main capacitor array is 8 bits or 16 bits, the main capacitor array usually has a risk of negative voltage leakage in the first and second beats of the successive approximation algorithm. In this case, the conversion accuracy of the preload capacitor array can be set to 2 bits.

[0068] As a preferred embodiment, the highest-weighted capacitor in the main capacitor array is a split capacitor array, and the main capacitor array includes two groups of first capacitor array and second capacitor array with the same arrangement structure.

[0069] In a traditional binary weighted capacitor array, the area of ​​the highest weight capacitor in the capacitor array is usually very large, because the weight of the highest weight capacitor is twice that of the lowest weight capacitor. , is the number of bits of the main capacitor array. Therefore, in this embodiment, in order to reduce the space volume occupied by the main capacitor array, the highest-weighted capacitor in the main capacitor array is set to a split capacitor array, so that the main capacitor array includes two groups of first capacitor arrays and second capacitor arrays with the same setting structure.

[0070] In other words, in practical applications, the conventional 4-bit main capacitor array is In this embodiment, the highest-weight capacitor 8C in the main capacitor array is split into the same form as the other capacitors in the main capacitor array, that is, 8C = 4C + 2C + 1C + 1C. At this time, the 4-bit main capacitor array will become: In this case, there will be two sets of capacitor arrays with the same configuration in the main capacitor array. and .

[0071] Based on the same setting principle, in this embodiment, the highest weight capacitor in the preload capacitor array is set as a split capacitor array. At this time, two groups of capacitor arrays with the same setting structure will be set in the preload capacitor array.

[0072] That is, in this embodiment, the highest weighted capacitor 2C in the preload capacitor array is split into the same form as the other capacitors in the preload capacitor array, that is, 2C=1C+1C. At this time, the 2-bit preload capacitor array will become: In this case, there will be two sets of capacitor arrays with the same configuration in the preload capacitor array. and .

[0073] See Figure 2 , Figure 2 This is a structural diagram of another approximation type analog-to-digital converter provided by an embodiment of the present invention. Figure 2 The approximation-type analog-to-digital converter shown is provided with: a preload capacitor array 11, a main capacitor array 12, a comparator 13, and a logic switch controller 14. The preload capacitor array 11 and the main capacitor array 12 are both binary-weighted capacitor arrays of a differential common mode. Furthermore, the operating voltage of the comparator 13 is set to 2.5V, the operating voltage of the preload capacitor array 11 and the main capacitor array 12 is set to 5V, and the common mode voltage VCM of the preload capacitor array 11 and the main capacitor array 12 is set to 1.25V.

[0074] In order to enable those skilled in the art to clearly understand the implementation principle of this application, Figure 2 The working principle of the approximation type analog-to-digital converter shown is briefly described. When the approximation type analog-to-digital converter performs analog-to-digital conversion, the preload capacitor array 11 and the main capacitor array 12 will first sample the analog signal and send the sampled analog signal to the comparator 13. At this time, the input end of the comparator 13 loses balance and generates a corresponding sign bit at its output end. The logic switch controller 14 will sample the comparison result and control each capacitor in the main capacitor array 12 according to the sampling result, and connect its switch to the reference voltage VREF or the ground GND according to the output result of the previous weighted capacitor, until the signal at the input end of the comparator 13 converges to the common mode level. In the process of executing the successive approximation algorithm of the approximation type analog-to-digital converter, the output result of the comparator 13 will be latched by its internal latch, and the latched data will be compared and calibrated with the data from the internal memory, and finally a digital signal corresponding to the analog signal will be output.

[0075] Since the preload capacitor array 11, the main capacitor array 12, and the comparator 13 operate in different voltage domains, that is, the preload capacitor array 11 and the main capacitor array 12 operate in the high-voltage domain of 5V, while the comparator 13 operates in the low-voltage domain of 2.5V, in order to take into account the low-voltage operating domain of the comparator 13, the common-mode voltage of the preload capacitor array 11 and the main capacitor array 12 needs to be set to 1.25V. However, a problem will arise at this time: the input voltage range of the main capacitor array 12 is compressed. If the original voltage input range is to be maintained, the main capacitor array 12 will have a risk of negative voltage leakage when executing the first two beats of the successive approximation algorithm. For details, please refer to Figure 3 and Figure 4 , Figure 3 For the general Figure 2 Schematic diagram of the main capacitor array in the approximation type analog-to-digital converter when the common mode voltage VCM is set to 2.5V and the successive approximation algorithm is executed. Figure 4 For the general Figure 2A schematic diagram illustrating a common-mode voltage VCM in FIG. 1 is set to 1.25 V and a main capacitor array in an approximation-type analog-to-digital converter when a successive approximation algorithm is executed.

[0076] To avoid the problem of negative voltage leakage in the main capacitor array of an approximation-type analog-to-digital converter during the first two cycles of executing the successive approximation algorithm, in this embodiment, a preload capacitor array is used to replace the main capacitor array during the first two cycles of executing the successive approximation algorithm, which are at risk of negative voltage leakage.

[0077] See Figure 2 When the target analog signal needs to be sampled, the logic switch controller in the approximation analog-to-digital converter will first close switches SP0, SN0, SP3 and SN3, and open switches SP1, SN1, SP2 and SN2. At this time, the preload capacitor array and the main capacitor array sample the target analog signal at the same time.

[0078] After sampling the target analog signal, the approximation analog-to-digital converter begins digitizing it. At this point, switches SP0, SN0, SP3, SN3, SP1, and SN1 are open, and switches SP2 and SN2 are closed. The logic switch controller controls the preload capacitor array and comparator to quantify the first two cycles of negative voltage leakage risk in the main capacitor array.

[0079] Specifically, the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array are quantized using a preload capacitor array and a comparator to obtain the target quantization results, including:

[0080] quantizing output results of the highest-weighted capacitor and the second-highest-weighted capacitor in the main capacitor array that have a risk of negative voltage leakage using a preload capacitor array and a comparator, to obtain a first quantization result and a second quantization result, respectively;

[0081] Accordingly, the target quantization result is assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the weighted capacitors in the main capacitor array except for the weighted capacitors with negative voltage leakage risk, so as to obtain a digital signal corresponding to the target analog signal, including:

[0082] When the conversion accuracy of the main capacitor array is 4 bits, the first quantization result and the second quantization result are assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the lower two weight capacitors in the main capacitor array to obtain a digital signal corresponding to the target analog signal.

[0083] Please continue to see Figure 2When using the preload capacitor array and comparator to quantify the first two beats of the main capacitor array with a risk of negative voltage leakage, the preload capacitor array converts the sampled analog signal into a 2-bit digital signal, thereby obtaining the output results of the highest-weighted capacitor and the second-highest-weighted capacitor in the main capacitor array with a risk of negative voltage leakage. The output result of the highest-weighted capacitor in the main capacitor array is the first quantization result, and the output result of the second-highest-weighted capacitor in the main capacitor array is the second quantization result.

[0084] After the preload capacitor array completes quantization of the output results of the highest-weighted capacitor and the second-highest-weighted capacitor in the main capacitor array that have a risk of negative voltage leakage, switches SP0, SN0, SP3, SN3, SP2, and SN2 are disconnected, switches SP1 and SN1 are closed, and the comparator disconnects from the preload capacitor array and establishes a connection with the main capacitor array. After the main capacitor array obtains the first quantization result and the second quantization result output by the preload capacitor array, it quantizes the output results of the second-lowest-weighted capacitor and the lowest-weighted capacitor in the main capacitor array with the comparator, thereby obtaining the lower two digital signals corresponding to the target analog signal.

[0085] During this process, if the first quantization result is 1, the highest weighted capacitor 8C in the main capacitor array is connected to VREF. If the first quantization result is 0, the highest weighted capacitor 8C in the main capacitor array is connected to GND. If the second quantization result is 1, the second highest weighted capacitor 4C in the main capacitor array is connected to VREF. If the second quantization result is 0, the second highest weighted capacitor 4C in the main capacitor array is connected to GND, and the same applies to the remaining weighted capacitors.

[0086] It is understandable that after the preload capacitor array quantizes the output results of the highest-weighted capacitor and the second-highest-weighted capacitor in the main capacitor array that have a risk of negative voltage leakage, the output results of the two highest-weighted capacitors in the main capacitor array have been determined. In this case, the main capacitor array will start comparing from the third beat until all weighted capacitors in the main capacitor array are compared.

[0087] See Figure 5 and Figure 6 , Figure 5 for Figure 2 Schematic diagram of the main capacitor array in the process of executing the successive approximation algorithm when the quantized output result of the preloaded capacitor array is not loaded. Figure 6 for Figure 2 Schematic diagram of the main capacitor array in the implementation of the successive approximation algorithm when loading the quantized output results of the preloaded capacitor array. Figure 5 and Figure 6It can be seen that before and after the main capacitor array is loaded with the quantized output result of the preloaded capacitor array, the main capacitor array can avoid the risk of negative voltage leakage during the process of executing the successive approximation algorithm.

[0088] In this embodiment, in order to further reduce the power consumption required by the approximation type analog-to-digital converter, the highest weighted capacitor in the main capacitor array can be set as a split capacitor array, and the switching timing of the main capacitor array when executing the successive approximation algorithm can be improved.

[0089] Specifically, the first quantization result and the second quantization result are assigned to the main capacitor array, and the output results of the lower two weight capacitors in the main capacitor array are quantized using the main capacitor array and the comparator to obtain a digital signal corresponding to the target analog signal, including:

[0090] When the first capacitor array is the highest weighted capacitor in the main capacitor array;

[0091] If the first quantization result is 1, searching the second capacitor array for the second highest weighted capacitor in the main capacitor array to obtain a first screening capacitor, and switching the first screening capacitor from ground to a reference voltage;

[0092] If the first quantization result is 0, the second highest weighted capacitor in the main capacitor array is searched in the first capacitor array to obtain a second screening capacitor, and the second screening capacitor is switched from the reference voltage to the ground.

[0093] In this embodiment, when the highest weighted capacitor in the main capacitor array is set as a split capacitor array, the main capacitor array actually includes two groups of first capacitor arrays and second capacitor arrays with the same configuration. For the convenience of description, we refer to the first capacitor array as the highest weighted capacitor in the main capacitor array. Figure 7 , Figure 7 for Figure 2 The main capacitor array in the diagram is a schematic diagram of the first beat of the successive approximation algorithm. When the main capacitor array compares the first beat, it will compare with 1 / 2VREF. All connected to VREF, the second capacitor array Connect all to GND.

[0094] See Figure 8 and Figure 9 , Figure 8 for Figure 2 Schematic diagram of the main capacitor array executing the second step of the successive approximation algorithm when the output result of the highest-weighted capacitor in the main capacitor array is 1. Figure 9 for Figure 2Schematic diagram of the main capacitor array when executing the second beat of the successive approximation algorithm when the output result of the highest weighted capacitor in the main capacitor array is 0. When the main capacitor array compares the size with 1 / 4VREF during the second beat, if the output result of the highest weighted capacitor in the main capacitor array is 1, the weighted capacitor 4C in the second capacitor array (this capacitor is the first screening capacitor) is switched from ground GND to reference voltage VREF. If the output result of the highest weighted capacitor in the main capacitor array is 0, the weighted capacitor 4C in the first capacitor array (this capacitor is the second screening capacitor) is switched from reference capacitor VREF to ground GND.

[0095] In the traditional switch switching of the approximation type analog-to-digital converter, the first step is to switch from the highest weight capacitor of the capacitor array, that is, to switch from the ground GND to the reference voltage VREF first, and then decide whether the switch of the second highest weight capacitor is kept at the reference voltage VREF or switched to the ground GND according to the output result of the highest weight capacitor. In the process of the main capacitor array executing the successive approximation algorithm, the charge in the main capacitor array must be redistributed. In this case, if the output result of the highest weight capacitor is 0, the switch of the second highest weight capacitor must be switched from the ground GND to the reference voltage VREF, and then from the reference voltage VREF to the ground GND. In the present embodiment, when the main capacitor array is set to two groups of first capacitor arrays and second capacitor arrays with the same structure, if the output result of the highest weight capacitor is 0, it is only necessary to switch the switch of the second highest weight capacitor 4C in the first capacitor array from the reference voltage VREF to the first GND. Compared with the traditional switch switching timing, one switch switching process is less, thereby further reducing the power consumption required by the approximation type analog-to-digital converter.

[0096] See Figure 10 , Figure 10 A flowchart of an analog-to-digital conversion method of an approximation type analog-to-digital converter provided in an embodiment of the present invention, wherein the method is applied to a logic switch controller in the approximation type analog-to-digital converter; the approximation type analog-to-digital converter comprises: a preload capacitor array, a main capacitor array, a comparator, and a logic switch controller; the operating voltage of the main capacitor array and the preload capacitor array is a ratio of the operating voltage of the comparator to the operating voltage of the comparator. times, ; The method comprises:

[0097] Step S11: controlling the preload capacitor array and the main capacitor array to sample the target analog signal;

[0098] Step S12: in the process of digitally converting the target analog signal using the successive approximation algorithm, the output results of the weighted capacitors with negative voltage leakage risk in the main capacitor array are quantized using the preload capacitor array and the comparator to obtain the target quantization result;

[0099] Step S13: Assign the target quantization result to the main capacitor array, and use the main capacitor array and the comparator to quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk to obtain a digital signal corresponding to the target analog signal.

[0100] An analog-to-digital conversion method of an approximation-type analog-to-digital converter provided in an embodiment of the present invention has the beneficial effects of the aforementioned approximation-type analog-to-digital converter.

[0101] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0102] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0103] The above is a detailed introduction to an approximation-type analog-to-digital converter and an analog-to-digital conversion method provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. An approximation-type analog-to-digital converter, characterized in that: include: preload capacitor array, main capacitor array, comparator and logic switch controller; The operating voltage of the main capacitor array and the preload capacitor array is 1 / 4 of the operating voltage of the comparator. times, ; The execution logic of the logic switch controller includes: Controlling the preload capacitor array and the main capacitor array to sample a target analog signal; In the process of digitally converting the target analog signal using a successive approximation algorithm, the output results of the weighted capacitors in the main capacitor array with a risk of negative voltage leakage are quantized using the preload capacitor array and the comparator to obtain a target quantization result; The target quantization result is assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk, so as to obtain a digital signal corresponding to the target analog signal.

2. The approximation type analog-to-digital converter according to claim 1, wherein: The preload capacitor array and the main capacitor array are both binary weighted capacitor arrays of a differential common mode.

3. An approximation type analog-to-digital converter according to claim 1 or 2, characterized in that: The setting factors of the common mode voltage of the preload capacitor array and the main capacitor array include: the operating voltage of the comparator.

4. The approximation type analog-to-digital converter according to claim 1, wherein: The conversion accuracy of the preload capacitor array is strongly correlated with the number of beats in the main capacitor array that have a risk of negative voltage leakage.

5. The approximation type analog-to-digital converter according to claim 1, characterized in that: The highest-weighted capacitor in the main capacitor array is a split capacitor array, and the main capacitor array includes two groups of first capacitor arrays and second capacitor arrays with the same arrangement structure.

6. The approximation type analog-to-digital converter according to claim 5, characterized in that: The highest-weighted capacitor in the preload capacitor array is a split capacitor array, and the preload capacitor array includes two groups of capacitor arrays with the same setting structure.

7. The approximation type analog-to-digital converter according to claim 6, characterized in that: The method of using the preload capacitor array and the comparator to quantize the output results of the weighted capacitors in the main capacitor array that have a risk of negative voltage leakage to obtain a target quantization result includes: quantizing output results of the highest-weighted capacitor and the second-highest-weighted capacitor in the main capacitor array that have a risk of negative voltage leakage using the preload capacitor array and the comparator, to obtain a first quantization result and a second quantization result, respectively; Accordingly, assigning the target quantization result to the main capacitor array, and using the main capacitor array and the comparator to quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk to obtain a digital signal corresponding to the target analog signal, includes: When the conversion accuracy of the main capacitor array is 4 bits, the first quantization result and the second quantization result are assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the lower two weight capacitors in the main capacitor array to obtain a digital signal corresponding to the target analog signal.

8. The approximation type analog-to-digital converter according to claim 7, characterized in that: The step of assigning the first quantization result and the second quantization result to the main capacitor array, and using the main capacitor array and the comparator to quantize the output results of the lower two weight capacitors in the main capacitor array to obtain a digital signal corresponding to the target analog signal includes: When the first capacitor array is the highest-weighted capacitor in the main capacitor array; If the first quantization result is 1, the second capacitor array is searched for the second highest weighted capacitor in the main capacitor array to obtain a first screening capacitor, and the first screening capacitor is switched from ground to a reference voltage.

9. The approximation type analog-to-digital converter according to claim 8, characterized in that: When the first capacitor array is the highest-weighted capacitor in the main capacitor array, the method further includes: If the first quantization result is 0, the second highest weighted capacitor in the main capacitor array is searched in the first capacitor array to obtain a second screening capacitor, and the second screening capacitor is switched from the reference voltage to the ground.

10. An analog-to-digital conversion method of an approximation-type analog-to-digital converter, characterized in that: Logic switch controller used in approximation type analog-to-digital converter; The approximation type analog-to-digital converter comprises: a preload capacitor array, a main capacitor array, a comparator and the logic switch controller; the operating voltage of the main capacitor array and the preload capacitor array is a ratio of the operating voltage of the comparator to the operating voltage of the comparator. times, ; The method comprises: Controlling the preload capacitor array and the main capacitor array to sample a target analog signal; In the process of digitally converting the target analog signal using a successive approximation algorithm, the output results of the weighted capacitors in the main capacitor array with a risk of negative voltage leakage are quantized using the preload capacitor array and the comparator to obtain a target quantization result; The target quantization result is assigned to the main capacitor array, and the main capacitor array and the comparator are used to quantize the output results of the other weighted capacitors in the main capacitor array except the weighted capacitors with negative voltage leakage risk, so as to obtain a digital signal corresponding to the target analog signal.

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