Clock recovery method, device and system

Abstract

The invention provides a clock recovery method, device and system. The method can be applied to optical transport networks. The method comprises: receiving a first optical transport network (OTN) frame data stream, obtaining phase difference information carried by a service layer clock and a second OTN frame from the first OTN frame data stream, and then adjusting a reference clock of the second OTN frame according to the service layer clock and the phase difference information, the reference clock of the second OTN frame being used for recovering the clock of the second OTN frame. According to the clock recovery method provided by the invention, the clock recovery accuracy of the OTN frame can be improved, so that the purpose of improving the system performance is achieved.

Description

[0001] This application is a divisional application. The application number of the original application is 202310601034.5, and the original application date is May 24, 2023. The entire content of the original application is incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of optical transmission technology, and more specifically, to a clock recovery method, device, and system. Background Art

[0003] Optical transport network (OTN), based on wavelength division multiplexing technology, can provide higher transmission rate, higher transmission efficiency and better operations, administration and maintenance (OAM) capabilities, and has become the mainstream technology of backbone transmission networks.

[0004] OTN systems not only transmit multiple types of service data but also the timing information (primarily clock synchronization frequency) corresponding to each service. One of its core technologies is how to map service data of different types and rates into OTN data frames and recover service data and clock information within OTN equipment. Summary of the Invention

[0005] The embodiments of the present application provide a clock recovery method, device, and system, which enable a destination device to accurately recover the service layer clock, thereby achieving the purpose of improving system performance.

[0006] In a first aspect, an embodiment of the present application provides a method for clock recovery. This method can be performed by a destination device or by a component of the destination device (such as a chip or chip system), and this application does not limit this. The method includes: receiving a first optical transport network (OTN) frame data stream. Obtaining a service layer clock from the first OTN frame data stream. Obtaining phase difference information carried by a second OTN frame carried by the first OTN frame data stream from the first OTN frame data stream. The phase difference information is the sum of the phase differences of one or more groups of two adjacent upstream devices among one or more upstream devices of the destination device through which the second OTN frame passes. The phase difference of the one or more groups of two adjacent upstream devices is an integer number of reference clock cycles. The reference clock of the second OTN frame is adjusted based on the service layer clock and the phase difference information, and the reference clock of the second OTN frame is used to recover the clock of the second OTN frame.

[0007] In some embodiments, the period of the overhead area carrying the phase difference information carried by the second OTN frame is less than or equal to 1 / 2 of the period of the second OTN frame. For example, it can be 1 / 4 or 1 / 3.

[0008] Based on the above solution, the destination device adjusts the reference clock of the destination device's second OTN frame by accumulating the phase difference between each two adjacent devices in its upstream device. Compared to using the reference clock of the second OTN frame of each device in the system to adjust the reference clock of the destination device's second OTN frame, this process avoids the process of extracting the reference clock of the second OTN frame of each device in the system, reducing the complexity and high overhead of clock recovery. Because the phase difference accumulation can achieve lossless estimation of the reference clock of the second OTN frame, the solution of the present application can improve the accuracy of the reference clock adjustment of the destination device's second OTN frame, thereby achieving the goal of improving system performance.

[0009] In conjunction with the first aspect, in certain implementations of the first aspect, adjusting the reference clock of the second OTN frame based on the phase difference information and the server layer clock includes: generating a phase difference between the destination device and an adjacent upstream device of the destination device based on the server layer clock, wherein the phase difference between the destination device and the adjacent upstream device of the destination device is an integer number of reference clock periods; generating a frequency deviation based on the phase difference information and the phase difference between the destination device and the adjacent upstream device of the destination device; and adjusting the reference clock of the second OTN frame based on the frequency deviation.

[0010] In combination with the first aspect, in some implementations of the first aspect, a period T for generating a phase difference between the destination device and an upstream device adjacent to the destination device is greater than a period of the overhead area carrying the phase difference information.

[0011] With reference to the first aspect, in certain implementations of the first aspect, a frequency F of the reference clock of the second OTN frame is greater than or equal to a rate of the second OTN frame.

[0012] In combination with the first aspect, in certain implementations of the first aspect, the frequency F and the period T satisfy: (F*T*20ppm)<10.

[0013] Based on the above solution, by limiting the phase difference period T and / or the frequency F of the reference clock of the second OTN frame of each device, the instantaneous phase error introduced during the phase difference accumulation process can be eliminated, thereby improving the accuracy of the phase difference information obtained by the destination device, and further improving the accuracy of the clock recovered in the second OTN frame, thereby achieving the purpose of improving system performance.

[0014] In conjunction with the first aspect, in certain implementations of the first aspect, the period T is greater than 3 ms and less than 6 ms, for example, 4 ms. In some embodiments, the period T is a value around 4 ms, i.e., approximately equal to 4 ms, and can be slightly less than 4 ms or slightly greater than 4 ms, for example, 4.1 ms or 3.9 ms.

[0015] In combination with the first aspect, in some implementations of the first aspect, the frequency F is in a range of 10 MHz to 1 GHz.

[0016] In conjunction with the first aspect, in certain implementations of the first aspect, the period of the overhead area carrying the phase difference information is 3 ms. In some embodiments, the period of the overhead area carrying the phase difference information is approximately 3 ms, i.e., approximately equal to 3 ms, and can be slightly less than 3 ms or slightly greater than 3 ms, for example, 2.1 ms or 3.9 ms.

[0017] In conjunction with the first aspect, in certain implementations of the first aspect, the error of the recovered service layer clock of the second OTN frame is less than or equal to 40 ns. Based on this solution, the phase error introduced in the phase difference calculation in the clock recovery solution provided in the embodiment of the present application can meet the G.813 template.

[0018] In conjunction with the first aspect, in certain implementations of the first aspect, the phase difference information is carried in multiple overhead areas of the second OTN frame. Based on this solution, by using the overhead area of ​​the second OTN frame to carry the phase difference information, the destination device can promptly obtain the phase difference information after receiving the second OTN frame, thereby reducing clock recovery latency.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the number of bytes carrying the phase difference information in each overhead area of ​​the multiple overhead areas is 1.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the second OTN frame is an optical service unit OSU frame.

[0021] In combination with the first aspect, in some implementations of the first aspect, the first OTN frame is an optical data unit (ODU) frame, and the ODU frame is an ODUk frame or an ODUflex frame.

[0022] In conjunction with the first aspect, in certain implementations of the first aspect, the reference clock for the second OTN frame is generated by an oven-controlled crystal oscillator, and the amplitude of the frequency variation of the reference clock for the second OTN frame over time is within a preset range. Based on this solution, the reference clock for the second OTN frame of each device is generated by an oven-controlled crystal oscillator, which can ensure the stability of the reference clock for the second OTN frame, thereby improving the accuracy of clock recovery and further enhancing system performance.

[0023] In combination with the first aspect, in some implementations of the first aspect, adjusting the reference clock of the second OTN frame according to the phase difference information includes: adjusting the reference clock of the second OTN frame according to the phase difference information in a time period T c Adjust the reference clock of the second OTN frame, T c Satisfaction: T c ≥T / (20ppm). Since the phase difference information received by the destination device is the cumulative result of the phase difference between devices, some devices may make errors when calculating the phase difference with adjacent devices. In order to eliminate the error when calculating the phase difference, the destination device does not use instantaneous compensation when recovering the clock based on the phase difference information, but instead uses a phase compensation in the time period T. c In this time period T c All phase difference information received in the system is used to perform slow clock recovery, thereby improving the accuracy of clock recovery.

[0024] In conjunction with the first aspect, in certain implementations of the first aspect, the method further includes: periodically increasing or decreasing the phase difference between the destination device and an adjacent upstream device of the destination device with a first period T1, wherein the first period T1 satisfies: T1 = (F*T*T / D1), where D1 is the phase difference between the destination device and the adjacent upstream device of the destination device. Based on this solution, by having the destination device regulate the phase difference generated by the device with the first period, the jitter of the phase difference can be reduced, thereby improving the accuracy of clock recovery.

[0025] In a second aspect, embodiments of the present application provide a clock recovery method. This method can be performed by a first device or a component of the first device (such as a chip or chip system), and is not limited in this application. The method includes: receiving a first optical transport network (OTN) frame data stream; obtaining a service layer clock from the first OTN frame data stream; generating a phase difference between the first device and an upstream device adjacent to the first device based on the service layer clock; obtaining, from the first OTN frame data stream, first phase difference information carried by a second OTN frame carried by the first OTN frame data stream. The first phase difference information is the sum of the phase differences between one or more groups of two adjacent upstream devices among one or more upstream devices of the first device through which the second OTN frame passes. The phase difference between the one or more groups of two adjacent upstream devices is an integer number of reference clock cycles; generating second phase difference information. The second phase difference information is the sum of the phase difference between the first device and the upstream device adjacent to the first device and the first phase difference information; and transmitting the second phase difference information. The second phase difference information is used to adjust the reference clock of the second OTN frame, and the reference clock of the second OTN frame is used to recover the clock of the second OTN frame.

[0026] It should be noted that the aforementioned first device is a device other than the sending device and the destination device. In other words, the first device is any intermediate device between the sending device and the destination device. It should be understood that when the first device is a downstream intermediate device adjacent to the sending device, since the sending device does not generate a phase difference, the first phase difference information received by the first device is 0. In this case, the value of the second phase difference information sent by the first device corresponds to the phase difference generated by the first device with the sending device.

[0027] It should also be noted that due to the differences in the devices generating the OTN frames, the second OTN frame carrying the first phase difference information received by the first device is different from the second OTN frame carrying the second phase difference information sent by the first device. However, it should be understood that the overhead area of ​​the second OTN frame carrying the first phase difference information and the overhead area of ​​the second OTN frame carrying the first phase difference information are located at the same position in their respective second OTN frames. In other words, in this embodiment of the present application, the position of the overhead area carrying the phase difference information in the second OTN frame is fixed. After the first device extracts the first phase difference information sent by the upstream device from this overhead area, it records the second phase difference information it generates in the overhead area of ​​the new second OTN frame generated by this device at the same position.

[0028] In some embodiments, the period of the overhead area carrying the first phase difference information is the same as the period of the overhead area carrying the second phase difference information of the second OTN frame, the period of the overhead area carrying the first phase difference information of the second OTN frame is less than or equal to 1 / 2 of the period of the second OTN frame, and the period of the overhead area carrying the second phase difference information of the second OTN frame is less than or equal to 1 / 2 of the period of the second OTN frame.

[0029] Based on this solution, the intermediate device calculates the phase difference between itself and the adjacent upstream device, and adds the received first phase difference information to the phase difference information generated by itself to generate and send the second phase difference information used to recover the destination device. That is, the destination device adjusts the reference clock of the destination device's second OTN frame by accumulating the phase differences sent by the intermediate node, avoiding the process of extracting the reference clock of the second OTN frame of each device in the system and reducing the complexity and high overhead of clock recovery. Because phase difference accumulation can achieve lossless estimation of the reference clock of the second OTN frame, the solution of the present application can improve the accuracy of reference clock adjustment of the destination device's second OTN frame, thereby improving the accuracy of the recovered second OTN frame clock, thereby achieving the purpose of improving system performance. In conjunction with the second aspect, in certain implementations of the second aspect, the period T for generating the phase difference between the first device and the upstream device adjacent to the first device is greater than the period of the overhead area that carries the first phase difference information or the second phase difference information.

[0030] With reference to the second aspect, in certain implementations of the second aspect, a frequency F of the reference clock of the second OTN frame is greater than or equal to a rate of the second OTN frame.

[0031] In combination with the second aspect, in certain implementations of the second aspect, the frequency F and the period T satisfy: (F*T*20ppm)<10.

[0032] In conjunction with the second aspect, in certain implementations of the second aspect, the period T is greater than 3 ms and less than 6 ms, for example, 4 ms. In some embodiments, the period T is a value around 4 ms, i.e., approximately equal to 4 ms, and can be slightly less than 4 ms or slightly greater than 4 ms, for example, 3.1 ms or 4.9 ms.

[0033] In combination with the second aspect, in some implementations of the second aspect, the frequency F is in a range of 10 MHz to 1 GHz.

[0034] In combination with the second aspect, in some implementations of the second aspect, the period of the overhead area carrying the first phase difference information of the second OTN frame is 3 ms.

[0035] With reference to the second aspect, in certain implementations of the second aspect, the period of the overhead area carrying the second phase difference information of the second OTN frame is 3 ms. In some embodiments, the period of the overhead area carrying the first phase difference information or the period of the overhead area carrying the second phase difference information is approximately 3 ms, i.e., approximately equal to 3 ms, and can be slightly less than 3 ms or slightly greater than 3 ms, for example, 2.1 ms or 3.9 ms.

[0036] In combination with the second aspect, in certain implementations of the second aspect, the first phase difference information is carried in multiple overhead areas of the second OTN frame.

[0037] In combination with the second aspect, in certain implementations of the second aspect, the second phase difference information is carried in multiple overhead areas of the second OTN frame.

[0038] In combination with the second aspect, in some implementations of the second aspect, the number of bytes of the first phase difference information carried by each overhead area in the multiple overhead areas is 1.

[0039] In combination with the second aspect, in some implementations of the second aspect, the second OTN frame is an optical service unit OSU frame.

[0040] In combination with the second aspect, in certain implementations of the second aspect, the first OTN frame is an ODUk frame or an ODUflex frame.

[0041] With reference to the second aspect, in certain implementations of the second aspect, the reference clock of the second OTN frame is generated by an oven-controlled crystal oscillator, and a frequency variation amplitude of the reference clock of the second OTN frame over time is within a preset range.

[0042] In conjunction with the second aspect, in certain implementations of the second aspect, the method further includes: periodically increasing or decreasing the phase difference between the first device and an upstream device adjacent to the first device with a second period T2, where the second period T2 satisfies: T2 = (F*T*T / D2), where D2 is the phase difference between the first device and the upstream device adjacent to the first device. Based on this solution, by regulating the phase difference generated by the first device with the second period, the jitter of the phase difference can be reduced, thereby improving the accuracy of clock recovery.

[0043] In a third aspect, embodiments of the present application provide a clock recovery method. This method can be performed by a destination device or a component of the destination device (such as a chip or chip system), and this application is not limited thereto. The method includes: receiving a first optical transport network (OTN) frame data stream; obtaining a service layer clock from the first OTN frame data stream; obtaining, from the first OTN frame data stream, first phase difference information carried by a second OTN frame carried by the first OTN frame data stream. The first phase difference information is the sum of the phase differences of one or more groups of two adjacent upstream devices among one or more upstream devices of the destination device through which the second OTN frame passes. The phase difference of the one or more groups of two adjacent upstream devices is an integer number of nominal clock cycles, where the nominal clock cycle is less than or equal to 10 ns. A local phase difference is generated based on the reference clock of the second OTN frame of the destination device and the service layer clock. The local phase difference is added to the first phase difference information to generate second phase difference information. The reference clock of the second OTN frame of the destination device is used to recover the clock of the second OTN frame. The reference clock of the second OTN frame of the destination device is adjusted based on the second phase difference information.

[0044] In conjunction with the third aspect, in certain implementations of the third aspect, adjusting the reference clock of the second OTN frame of the destination device based on the second phase difference information includes: generating a frequency offset based on the second phase difference information, the frequency offset being the product of the number of nominal clocks corresponding to the second phase difference information and the nominal clock; and adjusting the reference clock of the local second OTN frame based on the frequency offset.

[0045] In conjunction with the third aspect, in certain implementations of the third aspect, adjusting the reference clock of the local second OTN frame based on the second phase difference information includes: generating a clock control signal for adjusting the reference clock of the second OTN frame of the destination device based on the second phase difference information, and adjusting the reference clock of the local second OTN frame based on the clock control signal.

[0046] In combination with the third aspect, in some implementations of the third aspect, a period T for generating the local phase difference is greater than a period of an overhead area of ​​the second OTN frame carrying the first phase difference information.

[0047] In combination with the third aspect, in certain implementations of the third aspect, a frequency F of the nominal clock is greater than or equal to a rate of the second OTN frame.

[0048] In combination with the third aspect, in certain implementations of the third aspect, the frequency F and the period T satisfy: (F×T×20ppm)<64.

[0049] In conjunction with the third aspect, in certain implementations of the third aspect, the period T is less than 6 ms, for example, 4 ms. In some embodiments, the period T is a value around 4 ms, i.e., approximately equal to 4 ms, and can be slightly less than 4 ms or slightly greater than 4 ms, for example, 3.1 ms or 4.9 ms.

[0050] In combination with the third aspect, in certain implementations of the third aspect, the frequency F is in the range of 100 MHz-1 GHz.

[0051] In combination with the third aspect, in certain implementations of the third aspect, a period of the overhead area of ​​the second OTN frame carrying the first phase difference information is 3 ms.

[0052] In some embodiments, the period of the overhead area carrying the phase difference information is approximately 3 ms, that is, approximately equal to 3 ms, and may be slightly less than 3 ms or slightly greater than 3 ms, for example, 2.1 ms or 3.9 ms.

[0053] In combination with the third aspect, in certain implementations of the third aspect, an error of the recovered service layer clock of the second OTN frame is less than or equal to 100 ns.

[0054] In combination with the third aspect, in certain implementations of the third aspect, the first phase difference information is carried in multiple overhead areas of the second OTN frame.

[0055] In some implementable embodiments, each of the multiple overhead areas carries the same first phase difference information. When a system experiences bit errors, the first phase difference information carried by some of the multiple overhead areas may be erroneous. Therefore, this solution enables a receiving device to determine the correct first phase difference information based on the multiple received phase difference information when a system error occurs, thereby improving system performance.

[0056] In other feasible methods, when the first phase difference information generated by the upstream device exceeds the maximum capacity of the resources carrying the phase difference information, for example, when the resources carrying the phase difference information is 1 byte, when the first phase difference information cannot be carried by 1 byte, the first phase difference information can be divided into multiple partial phase difference information and carried in different overhead areas (for example, in adjacent overhead areas), that is, each of the multiple overhead areas carries a part of the first phase difference information, that is, the overall phase difference information carried by the multiple overhead areas is the first phase difference information.

[0057] In combination with the third aspect, in certain implementations of the third aspect, the number of bytes carrying the first phase difference information in each overhead area of ​​the multiple overhead areas is 1.

[0058] In conjunction with the third aspect, in certain implementations of the third aspect, multiple bytes in each of the multiple overhead areas carry multiple pieces of first phase difference information. Based on this solution, a device that obtains the multiple pieces of first phase difference information can use an algorithm such as a majority decision algorithm to determine the correct first phase difference information, thereby reducing system bit error rates.

[0059] In combination with the third aspect, in certain implementations of the third aspect, the amplitude of the frequency variation of the reference clock of the second OTN frame of the destination device over time is within a range of ±20 ppm.

[0060] In combination with the third aspect, in some implementations of the third aspect, adjusting the reference clock of the local second OTN frame according to the second phase difference information includes: adjusting the reference clock of the local second OTN frame according to the second phase difference information in the time period T c Adjust the reference clock of the local second OTN frame, T c Satisfaction: T c ≥T / (20ppm).

[0061] In a fourth aspect, embodiments of the present application provide a clock recovery method. This method can be performed by an intermediate device or a component of the intermediate device (such as a chip or chip system), and this application is not limited thereto. The method includes: receiving a first optical transport network (OTN) frame data stream; obtaining a service layer clock from the first OTN frame data stream; obtaining, from the first OTN frame data stream, first phase difference information carried by a second OTN frame carried by the first OTN frame data stream, wherein the first phase difference information is the sum of the phase differences of one or more groups of two adjacent upstream devices among one or more upstream devices of the intermediate device through which the second OTN frame passes, wherein the phase difference of the one or more groups of two adjacent upstream devices is an integer number of nominal clock cycles, wherein the nominal clock cycle is less than or equal to 10 ns; generating a local phase difference based on the clock of the intermediate device and the service layer clock; adding the local phase difference to the first phase difference information to generate second phase difference information; and transmitting the second phase difference information to an adjacent downstream device.

[0062] In combination with the fourth aspect, in certain implementations of the fourth aspect, the method further includes: when the absolute value of the second phase difference information is greater than a preset threshold, splitting the second phase difference information into multiple partial phase difference information, and the multiple partial phase difference information are carried in multiple overhead areas of the second OTN frame sent by the intermediate device.

[0063] Based on the above solution, the second phase difference information generated by the intermediate device is split and added to at least two overhead areas of the bearer. For example, when the second phase difference information exceeds a single range (e.g., one byte), the second phase difference information can be added to multiple overhead areas in multiple steps to ensure that each overhead area does not overflow, thereby reducing phase difference jitter and improving clock recovery accuracy.

[0064] In a fifth aspect, an embodiment of the present application provides a clock recovery method, which can be performed by an intermediate device or by a component of the intermediate device (such as a chip or chip system, etc.), and is not limited in this application. The method includes: receiving a first optical transport network (OTN) frame data stream. Obtaining a service layer clock from the first OTN frame data stream. Obtaining, from the first OTN frame data stream, first phase difference information carried by a second OTN frame carried by the first OTN frame data stream, wherein the first phase difference information is the sum of the phase differences of one or more groups of two adjacent upstream devices in one or more upstream devices of the intermediate device through which the second OTN frame passes, wherein the phase difference of the one or more groups of two adjacent upstream devices is an integer number of nominal clock cycles, wherein the nominal clock cycle is less than or equal to 10ns. A local phase difference is generated based on the clock of the intermediate device and the service layer clock. Generate first information, the first information including second phase difference information or fault information, the second phase difference information being generated by adding the local phase difference to the first phase difference information, the second phase difference information being used to adjust a reference clock of the second OTN frame, the reference clock of the second OTN frame being used to recover a clock of the second OTN frame, and the fault information indicating a clock anomaly in the intermediate device. Send the first information to an adjacent downstream device.

[0065] Based on the above solution, when a device in the system finds that the upstream service layer clock is abnormal, or the local clock of the local device is abnormal when calculating the phase difference information, it will no longer generate new phase difference information, but instead send the fault information to the downstream device, so that the destination device that finally receives the fault information no longer needs to perform clock recovery, avoiding service transmission failures due to clock recovery errors, and improving system performance.

[0066] In combination with the fifth aspect, in certain implementations of the fifth aspect, the generating of the local phase difference based on the clock of the intermediate device and the service layer clock includes: when confirming receipt of the first phase difference information, recording the number of cycles N1 of the nominal clock corresponding to the clock of the intermediate device, and recording the number of cycles N2 of the nominal clock corresponding to the service layer clock; and calculating the difference between N1 and N2 as the local phase difference.

[0067] In combination with the fifth aspect, in certain implementations of the fifth aspect, the confirmation of receipt of the first phase difference information is determined by identifying a frame header of the second OTN frame.

[0068] In combination with the fifth aspect, in certain implementations of the fifth aspect, generating the local phase difference based on the clock of the intermediate device and the service layer clock includes: determining a faster clock, a slower clock, or an average clock as a reference clock based on the speed of the clock of the intermediate device and the service layer clock; and generating the local phase difference based on the reference clock.

[0069] In combination with the fifth aspect, in certain implementations of the fifth aspect, when the moment for triggering the calculation of the local phase difference is met, the number of cycles N1 of the nominal clock corresponding to the clock of the intermediate device and the number of cycles N2 of the nominal clock corresponding to the service layer clock are recorded. The moment for triggering the calculation of the local phase difference is the moment when the number of cycles of the nominal clock corresponding to the clock of the intermediate device and the nominal clock corresponding to the service layer clock is equal to the preset expected period N earlier, or the moment for triggering the calculation of the local phase difference is the moment when the number of cycles of the nominal clock corresponding to the clock of the intermediate device and the nominal clock corresponding to the service layer clock is equal to the preset expected period N later, and the local phase difference is the difference between N1 and N2.

[0070] Based on the above solution, when calculating the local phase difference, by meeting the time that triggers the calculation of the local phase difference, the intermediate device can select a faster second OTN frame reference clock or a slower second OTN frame reference clock as the local reference clock, thereby improving the accuracy of clock recovery.

[0071] In combination with the fifth aspect, in some implementations of the fifth aspect, N=F×T, where F is the frequency of the nominal clock, and T is the period T for generating the local phase difference.

[0072] In combination with the fifth aspect, in certain implementations of the fifth aspect, the method further includes: determining the nominal clock corresponding to the clock of the intermediate device as a reference clock based on the moment of triggering the calculation of the local phase difference, and the reference clock is used to determine the detection period, or determining the nominal clock corresponding to the service layer clock as a reference clock based on the moment of triggering the calculation of the local phase difference.

[0073] In combination with the fifth aspect, in certain implementations of the fifth aspect, the method further includes: when the absolute value of the second phase difference information is greater than a preset threshold, splitting the second phase difference information into multiple partial phase difference information, and the multiple partial phase difference information are carried in multiple overhead areas of the second OTN frame sent by the intermediate device.

[0074] In conjunction with the fifth aspect, in certain implementations of the fifth aspect, the method further includes: obtaining multiple phase difference information carried by multiple bytes in each overhead area of ​​multiple overhead areas of the second OTN frame, and obtaining the first phase difference information based on the multiple phase difference information.

[0075] In conjunction with the fifth aspect, in certain implementations of the fifth aspect, generating fault information includes: recording the number N1 of cycles of the nominal clock corresponding to the clock of the intermediate device; and recording the number N2 of cycles of the nominal clock corresponding to the clock of the service layer. When N1 does not fall within a preset interval and / or N2 does not fall within a preset interval, generating the fault information.

[0076] In combination with the fifth aspect, in certain implementations of the fifth aspect, the preset interval is [N×(1-20ppm), N×(1+20ppm)].

[0077] In conjunction with the fifth aspect, in certain implementations of the fifth aspect, generating the fault information includes: recording the number N1 of cycles of the nominal clock corresponding to the clock of the intermediate device. Recording the number N2 of cycles of the nominal clock corresponding to the clock of the service layer. When the difference between N1 and N2 is not equal to -1, 0, or 1 within a preset time, generating the fault information.

[0078] In conjunction with the fifth aspect, in certain implementations of the fifth aspect, the preset time is T Nominal ×1 / (40ppm), or T Nominal ×25000, T Nominal is the period of the nominal clock.

[0079] In some implementations, the fault information may be generated when the time triggering the calculation of the local phase difference is met. Specifically, when the time triggering the calculation of the local phase difference is met, the values ​​of N1 and N2 are recorded, and the fault information is generated if it is determined that N1 does not fall within a preset interval and / or N2 does not fall within a preset interval. Furthermore, the fault information is generated when the difference between N1 and N2 is not equal to -1, 0, or 1 within a preset time.

[0080] In combination with the fifth aspect, in certain implementations of the fifth aspect, the first information is carried in an overhead area of ​​a second OTN frame sent by the intermediate device, the number of bytes occupied by the first information is at least one byte, and at least one bit in the at least one byte is used to indicate that the information included in the first information is the second phase difference information or the fault information.

[0081] In combination with the fifth aspect, in certain implementations of the fifth aspect, the first information includes fault information, and the fault information includes the number of nodes between the intermediate device where the fault occurs and the destination device.

[0082] In combination with the fifth aspect, in certain implementations of the fifth aspect, the number of nodes from the failed intermediate device to the destination device is carried by at least five bits in at least one byte occupied by the first information.

[0083] In a sixth aspect, an embodiment of the present application provides a system for clock recovery. The system includes a sending device and a destination device. Or the system includes a sending device, a destination device and at least one first device (also called an intermediate device). The purpose is to execute the method as described in the first aspect or any possible implementation thereof, or to execute the method as described in the third aspect or any possible implementation thereof. The first device is used to execute the method as described in the second aspect or any possible implementation thereof, or to execute the method as described in the fourth aspect or any possible implementation thereof, or to execute the method as described in the fifth aspect or any possible implementation thereof.

[0084] In a seventh aspect, embodiments of the present application provide an optical transmission network (OTN) device. The device is configured to perform the method provided in any one of the first to sixth aspects. Specifically, the optical transmission network (OTN) device may include units and / or modules for performing the method provided in the first aspect or any one of the aforementioned implementations of the first aspect. Alternatively, the optical transmission network (OTN) device may include units and / or modules, such as a processing module and a transceiver module, for performing the method provided in the second aspect or any one of the aforementioned implementations of the second aspect. Alternatively, the optical transmission network (OTN) device may include units and / or modules, such as a processing module and a transceiver module, for performing the method provided in the third aspect or any one of the aforementioned implementations of the third aspect. Alternatively, the optical transmission network (OTN) device may include units and / or modules, such as a processing module and a transceiver module, for performing the method provided in the fourth aspect or any one of the aforementioned implementations of the fourth aspect. Alternatively, the optical transmission network (OTN) device may include units and / or modules, such as a processing module and a transceiver module, for performing the method provided in the fifth aspect or any one of the aforementioned implementations of the fifth aspect.

[0085] In one implementation, the optical transport network (OTN) device may include units and / or modules for executing the method provided in the first aspect or any one of the aforementioned implementations of the first aspect, or units and / or modules for executing the method provided in the third aspect or any one of the aforementioned implementations of the third aspect, and is a receiving-end device. The transceiver may be a transceiver or an input / output interface. The processing module may be at least one processor. Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input / output interface may be an input / output circuit.

[0086] Alternatively, the optical transport network (OTN) device may be a chip, chip system, or circuit in a receiving-end device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0087] In another implementation, the optical transport network (OTN) device may include units and / or modules for executing the method provided in the second aspect or any of the aforementioned implementations of the second aspect, or units and / or modules for executing the method provided in the fourth aspect or any of the aforementioned implementations of the fourth aspect, or units and / or modules for executing the method provided in the fifth aspect or any of the aforementioned implementations of the fifth aspect, and is a transmitting device. The transceiver module may be a transceiver or an input / output interface. The processing module may be at least one processor. Alternatively, the transceiver may be a transceiver circuit. Alternatively, the input / output interface may be an input / output circuit.

[0088] Alternatively, the optical transport network (OTN) device may be a chip, chip system, or circuit in a transmitting device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0089] In an eighth aspect, embodiments of the present application provide a processor for executing the methods provided in the above aspects. For operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or unless otherwise inconsistent with its actual function or inherent logic in the relevant description, it can be understood as operations such as processor output, reception, and input, and can also be understood as sending and receiving operations performed by the radio frequency circuit and antenna, and this application does not limit this.

[0090] In a ninth aspect, an embodiment of the present application provides a computer-readable storage medium. The computer-readable storage medium stores program code for execution by a device, the program code including a method for executing any one of the implementations of the first, second, third, fourth, or fifth aspects described above.

[0091] In a tenth aspect, an embodiment of the present application provides a computer program product comprising instructions. When the computer program product is run on a computer, the computer is caused to execute the method provided by any one of the implementations of the first aspect, the second aspect, the third aspect, the fourth aspect, or the fifth aspect.

[0092] In an eleventh aspect, an embodiment of the present application provides a chip. The chip includes a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any one of the implementations of the first, second, third, fourth, or fifth aspects above.

[0093] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instructions are stored, and the processor is used to execute the computer program or instructions stored in the memory. When the computer program or instructions are executed, the processor is used to execute the method provided by any one of the implementation methods of the above-mentioned first aspect, second aspect, third aspect, fourth aspect, or fifth aspect.

[0094] The beneficial effects brought about by the third to eleventh aspects mentioned above can be specifically referred to the description of the beneficial effects in the first, second or fifth aspects, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Figure 1 A schematic diagram of an OTN optical network system applicable to an embodiment of the present application.

[0096] Figure 2 A schematic diagram of a possible network device hardware structure.

[0097] Figure 3 FIG. 4 is a schematic diagram of a frame structure of an OTN frame applicable to an embodiment of the present application.

[0098] Figure 4 A schematic flowchart of a clock recovery method 400 provided in an embodiment of the present application.

[0099] Figure 5 Schematic diagram of the mapping relationship between the first OTN frame and the second OTN frame applicable to the embodiment of the present application.

[0100] Figure 6 A schematic diagram of calculating the phase difference between two adjacent devices provided in an embodiment of the present application.

[0101] Figure 7 This is a schematic diagram of the first second OTN frame structure provided in an embodiment of the present application.

[0102] Figure 8 This is a schematic diagram of a second OTN frame structure provided in an embodiment of the present application.

[0103] Figure 9 This is a schematic diagram of the third second OTN frame structure provided in an embodiment of the present application.

[0104] Figure 10A flowchart of a target device generating a frequency deviation is provided in an embodiment of the present application.

[0105] Figure 11 A schematic diagram of the phase difference information fluctuating over time provided in an embodiment of the present application.

[0106] Figure 12 A schematic diagram of phase difference information received by a destination device under constraints provided in an embodiment of the present application.

[0107] Figure 13 Schematic diagram of the calculation flow of the first frequency deviation calculation module 1021.

[0108] Figure 14 Schematic diagram of the calculation flow of the second frequency deviation calculation module 1022.

[0109] Figure 15 A schematic flowchart of a clock recovery method 1500 provided in an embodiment of the present application.

[0110] Figure 16 A schematic diagram of the processing flow of the intermediate device provided in an embodiment of the present application.

[0111] Figure 17 A schematic diagram of the processing flow of the destination device provided in an embodiment of the present application.

[0112] Figure 18 A schematic flowchart of a clock recovery method 1800 provided in an embodiment of the present application.

[0113] Figure 19 This is a schematic diagram of the structure of the first information when the number of bytes occupied by the first information is one byte.

[0114] Figure 20 A schematic flowchart of a clock recovery method 2000 provided in an embodiment of the present application.

[0115] Figure 21 Schematic diagram of the first process for calculating phase difference.

[0116] Figure 22 Schematic diagram of the second process of calculating the phase difference.

[0117] Figure 23 The simulation comparison results are as follows: all intermediate devices use local clocks as reference clocks and the embodiments of the present application use a unified faster or slower clock as the reference clock.

[0118] Figure 24 The simulation comparison results are as follows: all intermediate devices use local clocks as reference clocks and the embodiments of the present application use a unified faster or slower clock as the reference clock.

[0119] Figure 25 These are the simulation results when a faster or slower clock is used as the reference clock for all intermediate devices at extreme frequency deviations (±20ppm).

[0120] Figure 26 A schematic diagram of the structure of an OTN device 1500 provided in an embodiment of the present application.

[0121] Figure 27 A schematic diagram of the structure of a possible OTN device provided in an embodiment of the present application.

[0122] Figure 28 A schematic diagram of the third process for calculating phase difference provided in an embodiment of the present application.

[0123] Figure 29 for Figure 28 There are three possible types of moments that trigger the calculation of the local phase difference.

[0124] Figure 30 A schematic diagram of the fourth process for calculating phase difference provided in an embodiment of the present application.

[0125] Figure 31 This is the clock performance obtained by simulating a solution in which the intermediate device calculates the phase difference when confirming receipt of the first phase difference information. DETAILED DESCRIPTION

[0126] The technical solution in this application will be described below with reference to the accompanying drawings.

[0127] In order to facilitate understanding of the embodiments of the present application, the following explanations are provided.

[0128] First, the terms "first," "second," and various numbers in the text descriptions or drawings of the embodiments of the present application shown below are merely for convenience of description and are not necessarily used to describe a specific order or sequence, and are not intended to limit the scope of the embodiments of the present application. For example, different phase difference information is used to distinguish different phase difference information.

[0129] Second, the terms "comprises" and any variations thereof in the embodiments of the present application shown below are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products or apparatuses.

[0130] Third, in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. An embodiment or design described as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. The use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0131] Fourth, in the embodiments of this application, service data refers to services that can be carried by an optical transport network. For example, it can be Ethernet services, packet services, wireless backhaul services, etc. Service data can also be referred to as service signals, customer data, or customer service data. It should be understood that the types of service data are not limited in the embodiments of this application.

[0132] Fifth, in this application, "used to indicate" includes direct indication and indirect indication. When describing that a certain information is used to indicate A, it includes whether the information directly indicates A or indirectly indicates A, and does not mean that the information necessarily carries A.

[0133] Sixth, in the embodiments of the present application shown below, only the OTN frame in the optical transport network (OTN) is used as an example to illustrate the embodiments. It should be understood that for other bearer OTN frames, or metropolitan transport network (MTN) frames, or with the development of OTN technology and MTN technology, new types of OTN frames and MTN frames may be defined, which are also applicable to the present application.

[0134] Seventh, in the embodiments of the present application, a device may also be referred to as a node or node device, and a sending device may be referred to as a sending node, a sending end, or a source node. Similarly, a receiving device may be referred to as a receiving end device, a receiving end, a destination device, or a sink node. An intermediate device may be referred to as an intermediate node.

[0135] Eighth, in the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or multiple.

[0136] Ninth, in the embodiments of this application, the preset may include a pre-defined configuration, such as a protocol definition. The "pre-defined configuration" may be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device. This application does not limit the specific implementation method.

[0137] Figure 1 This is a schematic diagram of an OTN optical network system applicable to the embodiment of this application. Generally, an OTN optical network is composed of multiple devices connected by optical fibers, and can be composed of different topology types such as linear, ring and mesh according to specific needs. Figure 1 The OTN 100 shown includes eight OTN devices 101, namely devices AH. 102 indicates an optical fiber used to connect two devices, and 103 indicates a customer service interface used to receive or send customer service data. Figure 1 As shown, OTN 100 is used to transmit service data for customer devices 1-3. Customer devices are connected to OTN devices through customer service interfaces. For example, Figure 1 In the example, customer devices 1-3 are connected to OTN devices A, H, and F respectively. Figure 1 In the example, when customer device 1 needs to communicate with customer device 3, it can send service data through OTN device AF. For example, OTN device A is a sending device, OTN device BE is an intermediate device, and OTN device F is a receiving device.

[0138] Generally speaking, OTN equipment is divided into optical layer equipment, electrical layer equipment and optoelectronic hybrid equipment. Optical layer equipment refers to equipment that can process optical layer signals, such as optical amplifiers (also known as optical line amplifiers) and optical add-drop multiplexers. Optical amplifiers are used to amplify optical signals to support transmission over longer distances while ensuring the specific performance of optical signals. Optical add-drop multiplexers are used to spatially transform optical signals so that they can be output from different output ports (sometimes also called directions). Electrical layer equipment refers to equipment that can process electrical layer signals, such as equipment that can process OTN signals. Optoelectronic hybrid equipment refers to equipment that has the ability to process optical layer signals and electrical layer signals. It should be noted that, depending on specific integration requirements, an OTN device can integrate multiple different functions. The technical solution provided in this application is applicable to OTN equipment of different forms and integration levels that contain electrical layer functions.

[0139] It should be noted that the data frame structure used by the OTN equipment in the embodiments of the present application is an OTN frame, which is used to carry various service data and provide rich management and monitoring functions. The OTN frame can be an optical data unit frame (ODUk), ODUCn, ODUflex, an optical channel transport unit k (OTUk), OTUCn, or a flexible OTN (FlexO) frame. The difference between an ODU frame and an OTU frame is that an OTU frame includes an ODU frame and an OTU overhead. k represents different rate levels, for example, k=1 represents 2.5Gbps, k=4 represents 100Gbps; Cn represents a variable rate, specifically a rate that is a positive integer multiple of 100Gbps. Unless otherwise specified, an ODU frame refers to any of ODUk, ODUCn, or ODUflex, and an OTU frame refers to any of OTUk, OTUCn, or FlexO. As OTN technology develops, new types of OTN frames may be defined, which are also applicable to this application.

[0140] Figure 2 A possible diagram of the hardware structure of a network device is shown below. For example, Figure 1 Specifically, the OTN device 200 includes a tributary board 201, a cross board 202, a line board 203, an optical layer processing board ( Figure 2 201) and system control and communication boards 204. Network devices may contain different types and quantities of boards depending on needs. For example, a network device serving as a core node may not have a tributary board 201. Another example is a network device serving as an edge node that may have multiple tributary boards 201 or no optical cross-connect board 202. Furthermore, a network device that only supports electrical layer functions may not have an optical layer processing board.

[0141] The tributary board 201, cross-connect board 202, and line board 203 are used to process OTN electrical layer signals. The tributary board 201 is used to receive and transmit various customer services, such as SDH services, packet services, Ethernet services, and fronthaul services. Furthermore, the tributary board 201 can be divided into a client-side optical transceiver module and a signal processor. The client-side optical transceiver module, also known as an optical transceiver, is used to receive and / or transmit service data. The signal processor is used to map and demap service data into data frames. The cross-connect board 202 is used to switch data frames, completing the exchange of one or more types of data frames. The line board 203 primarily processes line-side data frames. Specifically, the line board 203 can be divided into a line-side optical module and a signal processor. The line-side optical module, also known as an optical transceiver, is used to receive and / or transmit data frames. The signal processor is used to multiplex and demultiplex, or map and demap, line-side data frames. The system control and communication board 204 is used to implement system control. Specifically, information can be collected from different boards, or control instructions can be sent to the corresponding board. It should be noted that, unless otherwise specified, the specific components (such as signal processors) can be one or more, and this application does not impose any restrictions. It should also be noted that this application does not impose any restrictions on the types of boards included in the device, as well as the functional design and quantity of the boards. It should be noted that, in a specific implementation, the above two boards may also be designed as one board. In addition, the network equipment may also include a power supply for backup, a fan for heat dissipation, etc.

[0142] Figure 3 Schematic diagram of the frame structure of the OTN frame applicable to the embodiment of the present application. Figure 3 As shown, the OTN frame is a 4-row, multi-column frame structure, including an overhead area and a payload area. In one possible example, the payload area of ​​the OTN frame is divided into multiple payload blocks (PBs). Each PB occupies a fixed length (also called size) in the payload area, for example, 128 bytes. Figure 3 In the OTN frame structure shown, the first four rows and 16 columns are the OTU / ODU / optical payload unit (OPU) overhead area (used to carry ODUk overhead, OPU overhead, etc.), followed by the OPU payload area. For more details on the OTN frame structure, refer to the relevant description in the current protocol and will not be repeated here.

[0143] The optical service unit (OSU), a key technology in OTN, is primarily used to carry customer services at rates ranging from 10M to 100Gbps. Carrying low-speed, small-granularity service signals through the OSU and then mapping the OSU into the ODUk / ODUflex reduces service transmission latency, resolving the low efficiency of carrying low-speed, small-granularity services in existing OTN technology. The recovery of correct service layer clock information by the destination device in the OTN system relies on the correct mapping and demapping process between the OTN data frame and the service. At the same time, the division of low-speed, small-granularity services has led to a surge in the number of ports carrying services in the OTN system. Directly recovering the service data carried in each OSU data frame and regenerating the clock information corresponding to each intermediate device would introduce extremely high processing complexity and significant overhead. Therefore, simplifying clock recovery for OSU services is a technical issue that needs to be addressed.

[0144] To address these issues, this application proposes a clock recovery method that uses phase difference information (PD) generated by accumulating the phase differences between adjacent devices to recover the clock of the OTN frame at the destination device. This method avoids the need to extract clock information from each device in the communication link, simplifies the clock recovery process, and achieves highly reliable clock recovery.

[0145] The clock recovery method provided by the present application is described in detail below with reference to the accompanying drawings.

[0146] Figure 4 4 is a schematic flow chart of a clock recovery method 400 provided in an embodiment of the present application. Figure 4 As shown, method 400 is a schematic flowchart from the perspective of device interaction, wherein the sending device can be an OTN device, or be executed by a component of an OTN device (such as a chip or a chip system). The receiving device can be an OTN device, or be executed by a component of an OTN device (such as a chip or a chip system).

[0147] It should be understood that in the clock recovery method provided in the embodiment, there can be one or more intermediate devices, and of course, in some scenarios, there can be no intermediate device. For simplicity of explanation, the following description of the clock recovery method provided in the embodiment of the present application uses one intermediate device (i.e., intermediate device #1) as an example.

[0148] Specifically, Figure 4 The illustrated method 400 includes the following steps.

[0149] S410: A sending device sends a first OTN frame data stream.

[0150] Specifically, when a sending device wants to transmit service data to a destination device, the sending device sends a first OTN frame data stream to the destination device. The first OTN frame data stream carries the first phase difference information carried by the second OTN frame. The first OTN frame data stream refers to a data stream whose frame format is the OTN frame format.

[0151] For example, the first OTN frame is an ODU frame, for example, an ODUk frame or an ODUflex frame. The second OTN frame is an OSU frame. Figure 5 As shown, n OSU frames are interleaved and mapped in the payload area of ​​an ODU frame. When each OSU frame includes 4N bytes, any time slot of the ODU frame is used to carry partial information from n OSU frames. For example, the first time slot of the ODU frame can be used to carry the information carried by the first byte of each of the n OSU frames. The information carried by each byte of the OSU frame can be service data or padding.

[0152] It should be noted that, in the embodiment of the present application, the phase difference information carried by the second OTN frame (including the first phase difference information and the second phase difference information hereinafter) refers to the sum of the phase differences of one or more groups of two adjacent devices among all the devices passed by the second OTN frame.

[0153] In one achievable approach, the phase difference between two adjacent devices (hereinafter, a first device and a second device are used as examples for illustration, where the first device is the upstream device adjacent to the second device) is obtained by subtracting the number of cycles of the reference clocks of the second OTN frames of the two adjacent devices. It should be understood that when the phase difference is obtained in this manner, the phase difference is an integer, representing an integer number of cycles of the deviation between the reference clocks of the second OTN frames of the two adjacent devices, and can be a positive integer, a negative integer, or 0. For example, when the second device calculates the phase difference with the first device, the second device can obtain the number of cycles of the reference clock of the second OTN frame of the first device and the number of cycles of the reference clock of the local second OTN frame, and then subtract the number of cycles of the reference clock of the second OTN frame of the first device from the number of cycles of the reference clock of the local second OTN frame to obtain the phase difference.

[0154] It should be noted that in this embodiment of the present application, the frequency interval used when calculating the number of reference clock cycles of the second OTN frame is called a nominal clock. This refers to the frequency that the reference clock of the second OTN frame passes through each time the number of reference clock cycles of the second OTN frame increases by 1. For example, this nominal clock can be 10 MHz, 78.125 MHz, 100 MHz, or 300 MHz. It should be understood that this nominal clock is the same for each device.

[0155] For example, the reference clock of the second OTN frame of the first device obtained by the second device is obtained by dividing the server layer clock by a fixed multiplier X. This fixed multiplier X can be preset in each device and is the same for each device. In other words, for each device, the ratio of the server layer clock corresponding to the first OTN frame data stream it transmits to the local reference clock of the second OTN frame is the same fixed multiplier, i.e., they are in direct proportion. Therefore, after receiving the first OTN frame data stream from the first device, the second device can obtain the server layer clock based on the first OTN frame data stream and divide the obtained server layer clock by the fixed multiplier X to obtain the second OTN reference clock of the first device. The reference clock of the second OTN frame of the second device obtained by the second device can be a local crystal oscillator clock or the ratio of the local crystal oscillator clock to a fixed multiplier Y. For example, when the local crystal oscillator clock and the reference clock of the second OTN frame are of the same order of magnitude, the reference clock of the second OTN frame of the second device obtained by the second device can be the local crystal oscillator clock. It should be understood that since the phase difference between adjacent devices is obtained by subtracting the number of cycles of their reference clocks, the reference clocks of the second OTN frames of the adjacent devices are of the same order of magnitude, for example, the same order of magnitude as the nominal clock. In this case, the fixed magnification X can be obtained by the magnification relationship between the server layer clock and the nominal clock. Similarly, the fixed magnification Y can be obtained by the magnification relationship between the local crystal oscillator clock of the second device and the nominal clock.

[0156] It should be noted that the service layer clock corresponding to the first OTN frame data flow refers to the sending period or sending frequency of the first OTN frame data flow.

[0157] It should be understood that for first OTN frames of different rates, the corresponding service layer clocks of the first OTN frame data streams are different. Therefore, when compared with the reference clock of the same locally configured second OTN frame, different fixed multiples will be generated.

[0158] It should be understood that the number of cycles of the reference clocks of the second OTN frames of the first device and the second device is calculated relative to the same preset time period. Figure 6 As shown, after obtaining the server layer clock, the second device calculates the number of reference clock cycles n1 of the second OTN frame of the first device within a preset time. Simultaneously, it calculates the number of reference clock cycles n2 of the local second OTN frame within the same time. The phase difference between n1 and n2 is then calculated to obtain the phase difference between the second device and the first device. The phase difference between the second device and the first device can be n1-n2 or n2-n1, which is not limited in this application.

[0159] However, it should be understood that the phase difference calculation rule is unified for any device that the second OTN frame passes through. That is, when calculating the phase difference between itself and the adjacent upstream device, each device subtracts the number of cycles of the reference clock of the second OTN frame of the adjacent upstream device from the number of cycles of the reference clock of the second OTN frame of the own device. Alternatively, when calculating the phase difference between itself and the adjacent upstream device, each device subtracts the number of cycles of the reference clock of the second OTN frame of the adjacent upstream device from the number of cycles of the reference clock of the second OTN frame of the own device.

[0160] It should be noted that the above-mentioned preset time can be understood as the period T during which the second device generates the phase difference with the first device or the period T during which the second device calculates the phase difference, which can be called the phase difference calculation period T or the phase difference generation period T. In other words, the second device generates or calculates the phase difference once every period T.

[0161] Furthermore, it should be noted that, in order to ensure a relatively stable frequency of the reference clock for the second OTN frame of each device, in the embodiment of the present application, the reference clock for the second OTN frame of each device is generated by an oven-controlled crystal oscillator. It should be understood that a stable frequency of the reference clock for the second OTN frame generated by the oven-controlled crystal oscillator means that the amplitude of the frequency variation of the reference clock for the second OTN frame generated by the oven-controlled crystal oscillator over time is within a preset range.

[0162] Optionally, the phase difference information carried by the second OTN frame is carried in an overhead area of ​​the second OTN frame. For example, when the second OTN frame is an OSU frame, the phase difference information is carried in the overhead area of ​​the OSU frame and occupies at least one byte in the overhead area of ​​the OSU frame. For example, the phase difference information can be carried in a rate adjustment control (JC) overhead in the OSU frame, occupying one or more bytes of the JC overhead.

[0163] It should be understood that when the phase difference information carried by the second OTN frame occupies multiple bytes, these multiple bytes carry the same phase difference information, and these multiple bytes can be consecutive or non-consecutive. In some embodiments, when the phase difference information carried by the second OTN frame occupies multiple bytes, the receiving device can determine the phase difference information sent by the upstream device based on the multiple phase difference information using an algorithm such as majority decision. This solution enables correction of phase difference information when bit errors occur in the system, thereby improving the system's error tolerance.

[0164] It should be understood that, for the transmitting device, since it is the device that sends the first OTN frame data stream, it does not generate a phase difference. Accordingly, the overhead area in the second OTN frame used to carry phase difference information does not carry any information. In other words, when the transmitting device sends the first OTN frame, the first phase difference information carried in the first OTN frame can be understood as 0.

[0165] In some embodiments, the period of the overhead area carrying the phase difference information carried by the second OTN frame is less than or equal to 1 / 2 of the period of the second OTN frame. For example, the period of the overhead area carrying the phase difference information carried by the second OTN frame can be 1 / 2, 1 / 3, or 1 / 4 of the period of the second OTN frame, etc., which is not limited in this application. In other words, a second OTN frame can contain multiple discontinuous overhead areas for phase difference information, and the time interval between two adjacent overhead areas can be referred to as an overhead area period. The period of the overhead area carrying the phase difference information carried by the second OTN frame can be referred to as the overhead area period of the second OTN frame, or the phase difference information period. This can be understood as the period during which a device that obtains the phase difference information carried by the second OTN frame obtains the phase difference information carried by the second OTN frame in the overhead area of ​​the second OTN frame, etc.

[0166] Figure 7 This is a schematic diagram of the first second OTN frame structure provided by the embodiment of the present application, wherein the period of the overhead area of ​​the second OTN frame is equal to 1 / 2 of the period of the second OTN frame. Figure 7 As shown, the transmission period of the second OTN frame is 2n time slots. After the second OTN frame sends the first overhead area, it sends the second overhead area after n time slots. It should be understood that Figure 7 The fact that the second OTN frame transmission period includes two overhead areas is only an example and not a limitation. That is, the present application does not limit the number of overhead areas included in the second OTN frame transmission period.

[0167] Figure 8 This is a schematic diagram of the second OTN frame structure provided in the embodiment of the present application, wherein the period of the overhead area of ​​the second OTN frame is equal to 1 / 3 of the period of the second OTN frame. Figure 8 As shown, the transmission period of the second OTN frame is 3n time slots. After the second OTN frame sends the first overhead area, it sends the second overhead area after n time slots. It should be understood that Figure 8 The number of overhead areas included in the transmission period of the second OTN frame shown is for illustration only and is not limiting.

[0168] Figure 9 This is a schematic diagram of the third second OTN frame structure provided by the embodiment of the present application, wherein the period of the overhead area of ​​the second OTN frame is equal to 1 / 4 of the period of the second OTN frame. Figure 9 As shown, the transmission period of the second OTN frame is 4n time slots. After the second OTN frame sends the first overhead area, it sends the second overhead area after n time slots. It should be understood that Figure 9 The number of overhead areas included in the transmission period of the second OTN frame shown is for illustration only and is not limiting.

[0169] Furthermore, in the embodiments of the present application, service data refers to services that can be carried by the OTN, including but not limited to constant bit rate (CBR) services and variable bit rate (VBR) services. CBR is encoded using a constant bit rate. By way of example and not limitation, CBR services may include but are not limited to multimedia streaming services, such as video streaming services, virtual reality (VR) services, and augmented reality (AR) services. VBR is a bit rate that is determined in real time based on the complexity of the service data. By way of example and not limitation, VBR services may include voice services and / or video services.

[0170] S420, the intermediate device #1 obtains the first phase difference information of the service layer clock and the second OTN frame from the first OTN frame data stream.

[0171] Specifically, after intermediate device #1 receives the data stream from the first OTN frame, it obtains the service layer clock from the sending device from the payload area of ​​the first OTN frame, obtains the second OTN frame through demapping, and obtains the first phase difference information sent by the sending device from the overhead area of ​​the second OTN frame. The first phase difference information is 0.

[0172] Specifically, the above-mentioned service layer clock can be that the sending device reads the service data stream according to the service layer clock at the sending device, and then encapsulates the read service data stream into the OTN frame payload area according to the service layer clock. When the intermediate device #1 receives the first OTN frame data stream, it obtains the service layer clock from the first OTN frame.

[0173] It should be understood that when there are multiple intermediate devices in a system, for other intermediate devices, such as intermediate device #N (N is not equal to 1), the first OTN frame data stream received by intermediate device #N comes from an upstream intermediate device adjacent to intermediate device #N. In this case, intermediate device #N obtains the service layer clock sent by the upstream device adjacent to it and simultaneously obtains the phase difference information of the second OTN frame. The phase difference information of the second OTN frame obtained by intermediate device #N is the sum of the phase differences of one or more groups of two adjacent upstream devices from one or more upstream devices upstream of intermediate device #N. For example, when intermediate device #N is intermediate device #3, intermediate device #1 and intermediate device #2 are located between the sending device and intermediate device #3. Therefore, the first OTN frame data stream received by intermediate device #3 comes from intermediate device #2, and the service layer clock obtained is the service layer clock sent by intermediate device #2. The phase difference information obtained by intermediate device #3 is the sum of the phase difference between intermediate device #1 and the sending device, and the phase difference between intermediate device #2 and intermediate device #1.

[0174] S430 , the intermediate device # 1 generates a phase difference between the intermediate device # 1 and the sending device according to the server layer clock.

[0175] Specifically, intermediate device #1 calculates the reference clock of the second OTN frame of the sending device based on the server layer clock, and generates a phase difference between the reference clock of the second OTN frame of the sending device and the reference clock of the local second OTN frame. The method for generating the phase difference can refer to the relevant description in S410 above, for example, using the difference in the number of cycles to calculate the phase difference between intermediate device #1 and the sending device.

[0176] It should be understood that when there are multiple intermediate devices in the system, for other intermediate devices #N (N is not equal to 1), when the intermediate device #N calculates the phase difference with its adjacent upstream device, it also calculates the reference clock of the second OTN frame with the adjacent upstream device based on the service layer clock, and uses the difference such as the number of reference clock cycles to calculate the phase difference.

[0177] S440: The intermediate device #1 generates second phase difference information.

[0178] Specifically, the intermediate device #1 obtains the first phase difference information, calculates the phase difference between the intermediate device #1 and the sending device, and then adds the first phase difference information and the phase difference between the intermediate device #1 and the sending device to obtain the second phase difference information.

[0179] It should be understood that when the first phase difference information is carried in the overhead area of ​​the second OTN frame, the second phase difference information generated by the intermediate device #1 is also carried in the overhead area of ​​the second OTN frame.

[0180] It should also be understood that when there are multiple intermediate devices in the network, for other intermediate devices #N (N is not equal to 1), intermediate device #N calculates the phase difference between intermediate device #N and the upstream device adjacent to it, adds the phase difference information obtained from the first OTN frame data stream to obtain new phase difference information, and carries the new phase difference information through the second OTN frame (for example, carried in the overhead area of ​​the second OTN frame) and sends it to the downstream device of intermediate device #N.

[0181] S450: Intermediate device #1 sends a first OTN frame data stream.

[0182] Specifically, when the intermediate device #1 generates the second phase difference information, it carries the second phase difference information in the second OTN frame, maps the second OTN frame into the first OTN frame, and sends the first OTN frame data stream to the destination device (i.e., the downstream device of the first intermediate device #1).

[0183] It should be noted that because intermediate device #1 processes the information carried in the first OTN frame data stream, for example, the phase difference information carried in the second OTN frame carried in the first OTN frame data stream sent by intermediate device #1 is the phase difference information updated from the phase difference information carried in the second OTN frame carried in the first OTN frame data stream sent by the sending device in S410. Therefore, the data content carried in the first OTN frame data stream sent by intermediate device #1 and the first OTN frame data stream sent by the sending device is different, but the frame format of the corresponding first OTN frames is the same. Similarly, the second OTN frame carrying the first phase difference information is different from the second OTN frame carrying the second phase difference information, but the frame format is the same, both using the second OTN frame format.

[0184] It should be understood that when the second phase difference information is carried in the overhead area of ​​the second OTN frame, the period of the overhead area carrying the second phase difference information of the second OTN frame is less than or equal to 1 / 2 of the period of the second OTN frame.

[0185] After the destination device receives the first OTN data stream from intermediate device #1, the destination device adjusts the reference clock of the second OTN frame according to the second phase difference information obtained from the first data stream and the server layer clock obtained from the first OTN data stream.

[0186] S460: The destination device obtains the second phase difference information of the server layer clock and the second OTN frame from the first OTN frame data stream.

[0187] Specifically, after the destination device receives the first OTN frame data stream sent by the intermediate device #1, it obtains the service layer clock from the first OTN frame data stream, obtains the second OTN frame through demapping, and obtains the second phase difference information from the second OTN frame (for example, the overhead area of ​​the second OTN frame).

[0188] S470: The destination device adjusts the reference clock of the second OTN frame according to the server layer clock and the second phase difference information.

[0189] Specifically, after the destination device obtains the service layer clock, it first calculates the reference clock of the second OTN frame of the intermediate device #1 based on the service layer clock, calculates the phase difference between the reference clock of the second OTN frame of the intermediate device #1 and the reference clock of the second OTN frame of the destination device, and then sums the obtained second phase difference information with the calculated phase difference (which can be called third phase difference information). The reference clock of the second OTN frame is adjusted according to the third phase difference information, so that the reference clock of the second OTN frame after adjustment of the destination device and the reference clock of the second OTN frame sent by the sending device are within a preset error range.

[0190] The destination device may calculate the phase difference with the intermediate device #1 by subtracting the number of cycles of the reference clock of the second OTN frame of the intermediate device #1 from the number of cycles of the reference clock of the second OTN frame of the destination device within a preset time.

[0191] It should be understood that when the reference clock of the second OTN frame adjusted by the destination device and the reference clock of the second OTN frame sent by the sending device are within the above-mentioned preset error range, it can be considered that the destination device adjusts the reference clock of the second OTN frame to be consistent with the reference clock of the second OTN frame sent by the sending device.

[0192] Exemplarily, when the destination device adjusts the reference clock of the second OTN frame of the destination device according to the phase difference information (including the second phase difference information and the third phase difference information), the destination device first generates a frequency deviation according to the phase difference information, and adjusts the reference clock of the second OTN frame according to the frequency deviation.

[0193] In a possible implementation, the flow chart of the target device generating the frequency deviation is as follows: Figure 10As shown in the figure, PD calculation module 101, frequency calculation module 102, and summation module 103 are modules in the destination device. Specifically, the PD calculation module is used to input the service layer clock obtained by the destination device from the first OTN frame and output the phase difference between the destination device and intermediate device #1. Summation module 103 is used to sum the phase difference between the destination device and intermediate device #1 output by PD calculation module 101 with the second phase difference information obtained by the destination device from the second OTN frame, and output third phase difference information. Frequency calculation module 102 is used to calculate the frequency deviation based on the second phase difference information or the third phase difference information.

[0194] For example, it is assumed that the period during which the destination device calculates the phase difference between the destination device and intermediate device #1 based on the obtained service layer clock (that is, the period during which the destination device generates the phase difference) is the first period. At the same time, the period during which the destination device obtains the second phase difference information (for example, the period of the overhead area of ​​the second OTN frame carrying the second phase difference information) is the second period. When the second period is less than the first period, there will be times when the frequency deviation calculation module 102 of the destination device only obtains the second phase difference information when calculating the frequency deviation. At this time, it can be considered that the phase difference calculated by the destination device is 0, that is, the third phase difference information input by the frequency deviation calculation module 102 is the sum of the second phase difference information and 0. When the frequency deviation calculation module 102 obtains the second phase difference information and the phase difference between the destination device and intermediate device #1 at the same time, the frequency deviation calculation module 102 simultaneously inputs the second phase difference information and the phase difference between the destination device and intermediate device #1. Alternatively, when the frequency deviation calculation module 102 of the destination device only obtains the second phase difference information when calculating the frequency deviation, it can be considered that the frequency deviation calculation module 102 calculates the frequency deviation based only on the second phase difference information.

[0195] It should be understood that when the calculation module 102 calculates the frequency deviation according to the second phase difference information or the third phase difference information, it is obtained by multiplying the second phase difference information or the third phase difference information by the nominal clock.

[0196] Based on the above solution, the clock recovery method provided in the embodiment of the present application adjusts the reference clock of the second OTN frame of the destination device by calculating the phase difference between each device instead of the frequency difference between adjacent devices, thereby recovering the second OTN frame clock. The solution of the present application can achieve lossless estimation of the reference clock of the second OTN frame through phase difference accumulation, thereby improving the accuracy of adjusting the reference clock of the second OTN frame of the destination device, and further improving the accuracy of the recovered second OTN frame clock, thereby achieving the purpose of improving system performance.

[0197] It should be noted that as the transmission time of the business data flow accumulates, such as Figure 11As shown, the third phase difference information generated at the destination device approaches 0, that is, the sum of the phase differences of the upstream devices received by the destination device tends to 0 over time. However, it can be observed that the local PD has uneven fluctuations. These fluctuations mean that there is systematic low-frequency noise in the sum of the accumulated phase differences, that is, when the above phase information is used to recover the clock, there is systematic phase jitter. In order to eliminate these systematic noises, the embodiments of the present application uniformly design the parameters of each device, so that the destination device can eliminate this systematic noise and phase jitter in the sum of the phase differences of the upstream devices obtained.

[0198] In one achievable manner, the frequency F of the reference clock of the second OTN frame of each device in the system is set to be greater than or equal to the rate of the second OTN frame, for example, 10 MHz to 1 GHz. For example, when the second OTN frame is an OSU frame, the frequency F of the reference clock of the second OTN frame of each device can be set to a minimum of 10 MHz.

[0199] In another possible implementation, the period T of the phase difference information in the system is set to be greater than the period of the second OTN frame, for example, 3ms-6ms. That is, the period T of the phase difference information generated by each device with its upstream device is greater than the period of the second OTN frame. For example, when the second OTN frame is an OSU frame, the period T of the phase difference information generated by each device with its upstream device can be set to approximately 4ms. The period T of the phase difference information can be found in the above description and is not further elaborated here.

[0200] In yet another implementable manner, the frequency F of the reference clock of the second OTN frame of each device in the system and the period T of the phase difference information are set to satisfy the following relationship:

[0201] (F*T*20ppm)<10.

[0202] Here, ppm stands for parts per million.

[0203] Figure 12 This is a phase difference distribution diagram under parameter constraints provided by the embodiment of the present application. Figure 12 As shown in the figure, when the frequency F of the reference clock of the second OTN frame of each device is at least 10 MHz, the period T of the phase difference information is 4 ms, and the period of the overhead area carrying the phase difference information is 3 ms, the phase difference information jitters in a symmetrical and sparse manner. That is, the above constraint parameters can regularize the systematic phase difference jitter, so that the systematic noise can be optimized through natural phase correction.

[0204] In one possible implementation, to eliminate systematic phase jitter, Figure 10 The module of the destination device shown, Figure 13 FIG. 1 is a schematic diagram of the calculation flow of the first frequency deviation calculation module 1021. Figure 13 As shown, after the frequency deviation calculation module 102 receives the input phase difference information, it can divide the phase difference information into two paths. One path uses a moving average (MA) algorithm to absorb the instantaneous phase difference fluctuations caused by quantization error and natural recovery. The other path first accumulates (accumulates, ACC) the phase difference information, for example, through an accumulator to generate a final phase difference value, and then uses a sliding average algorithm to eliminate the fluctuations caused by the accumulated phase difference. The frequency deviation output by the frequency deviation calculation module 102 is the result obtained by multiplying the two output results by the corresponding coefficients (including α and β) and superimposing them.

[0205] It should be noted that the length of the sliding average algorithm and the values ​​of the corresponding coefficients of the two paths can be designed to meet the target template specification, such as the G.813 template specification.

[0206] In one achievable approach, Figure 14 FIG. 1 is a schematic diagram of the calculation flow of the second frequency deviation calculation module 1022. Figure 14 As shown, the frequency deviation calculation module 1022 first performs a nonlinear (NL) processing process on the input phase difference information. This process can reduce the nonlinear noise carried by the phase difference information. The result of the nonlinear noise reduction process is then divided into two paths. One path uses a sliding average algorithm to absorb the instantaneous phase difference fluctuations caused by quantization error and natural recovery; the other path first accumulates the phase difference information (for example, through an accumulator) to generate a final phase difference value, and then uses a sliding average algorithm to eliminate the fluctuations caused by the accumulated phase difference. The frequency deviation output by the frequency deviation calculation module 102 is the result obtained by multiplying the two output results by the corresponding coefficients and adding them together.

[0207] Optionally, the NL processing process can be to constrain each phase difference information in the phase difference information to a maximum absolute value N. For example, when N is 10, if the phase difference is a negative number, the phase difference is limited to be less than 0 and greater than -10. If the phase difference is a positive number, the phase difference is limited to be greater than 0 and less than 10. For example, assuming that the phase difference information received by the destination device is 20, -19, 5, 0, and 11, the constrained phase difference information obtained after the nonlinear processing process is 10, -10, 5, 0, and 10.

[0208] Exemplarily, N may be set with the goal of minimizing the clock recovery error, for example, making the error of the recovered service layer clock of the second OTN frame less than or equal to 40 ns.

[0209] Based on the above solution, by nonlinearly processing the phase difference information and limiting the maximum or minimum value of each phase difference, the system nonlinear noise carried in the phase difference information can be reduced, thereby improving the accuracy of clock recovery.

[0210] It should be noted that, when calculating the phase difference between the intermediate device and the adjacent device, errors may occur in the process of calculating the phase difference, but such errors will not last long. Therefore, in order to eliminate the jitter of the phase difference, in the embodiment of the present application, the destination device can use slow compensation to eliminate such errors. For example, in the time period T c Adjust the reference clock of the second OTN frame, where T c Satisfaction: T c ≥T / (20ppm). For example, assuming that the period of the reference clock of the second OTN frame is 100ns, when the phase difference information received by the destination device is 1, the destination device can divide the period of the reference clock corresponding to the phase difference information of 1 into n equally spaced small periods, and the intervals of the n small periods are divided by T c / 100, that is, the destination device can c / 100ns compensates the received phase difference information once.

[0211] In addition, in order to reduce the jitter of the phase difference, in the embodiment of the present application, the intermediate device or the destination device can generate the phase difference with a certain period T i Increase or decrease periodically. The period T i Meet T i =(F*T*T / D i ), where i is equal to 1 or 2. When i is equal to 1, T1 corresponds to the period of the destination device, and D1 is the phase difference generated by the destination device with the adjacent upstream device. When i is equal to 2, T2 corresponds to the period of any intermediate device, and D2 is the phase difference generated by the arbitrary intermediate device with the adjacent upstream device. Exemplarily, the process is described by taking any intermediate device as an example. Assuming that the phase difference generated by the arbitrary intermediate device is 11, the intermediate device can first divide 11 into 10+1, and when generating the phase difference information, use 10 to generate the phase difference information sent to its downstream device, and then send 1 to its downstream device every period T2. After sending n times, 1 will no longer be sent in the subsequent n*T2 time.

[0212] Figure 15 1500 is a schematic flow chart of a clock recovery method provided in an embodiment of the present application. Figure 15As shown, the method 1500 is a schematic flowchart shown from the perspective of device interaction, wherein the sending device, the intermediate device (including any one of the intermediate devices #1 to the intermediate device #N) and the destination device can all be OTN devices or executed by components of the OTN device (such as a chip or a chip system, etc.).

[0213] Specifically, Figure 15 The illustrated method 1500 includes the following steps.

[0214] S1501: A sending device sends a first OTN frame data stream.

[0215] Specifically, when the sending device wants to transmit service data to the destination device, the sending device sends a first OTN frame data stream to the destination device, wherein the first OTN frame data stream refers to a data stream whose frame format is the first OTN frame format.

[0216] S1502: Intermediate device #1 obtains first phase difference information of a service layer clock and a second OTN frame from the first OTN frame data stream.

[0217] Specifically, the intermediate device #1 receives a first OTN frame data stream sent from the sending device, and obtains the first phase difference information between the service layer clock and the second OTN frame from the first OTN frame data stream.

[0218] The service layer clock refers to the transmission period or frequency of the first OTN frame data stream. Specifically, the transmitting device reads the service data stream according to the service layer clock, then encapsulates the read service data stream into the first OTN frame payload area according to the service layer clock, and sends the first OTN frame data stream to intermediate device #1. After receiving the first OTN frame data stream, intermediate device #1 can obtain the service layer clock from the first OTN frame data stream. Simultaneously, after receiving the first OTN frame data stream, intermediate device #1 demaps the second OTN frame and obtains the first phase difference information from the second OTN frame.

[0219] In some embodiments, the first phase difference information is carried in at least one overhead area of ​​the second OTN frame. For example, when the second OTN frame includes multiple overhead areas, each of the multiple overhead areas may carry one piece of first phase difference information. The first phase difference information carried in the multiple overhead areas may be the first phase difference information sent by the transmitting device at the same time, or the phase difference information sent by the transmitting device at different times. If the first phase difference information carried in the multiple overhead areas is the first phase difference information sent by the transmitting device at the same time, the transmitting device may carry the first phase difference information generated at the same time in different overhead areas sent at different times. In this case, intermediate device #1 can use an algorithm such as a majority decision algorithm to more accurately determine the first phase difference information from the first phase difference information carried in the overhead areas of multiple consecutively received second OTN frames. Furthermore, the multiple bytes may be non-consecutive bytes to further improve the system's error-resistance performance. If the first phase difference information carried by the multiple overhead areas is phase difference information sent by the transmitting device at different times, since the multiple overhead areas of the second OTN frame are sent by the transmitting device to the intermediate device #1 at different times, the transmitting device can carry the first phase difference information generated at different times in the overhead areas sent at different times, so that the intermediate device #1 obtains the first phase difference information sent by the transmitting device at different times in the overhead areas of the second OTN frames received at different times.

[0220] In some other embodiments, the first phase difference information may occupy at least one byte in the overhead area of ​​the second OTN frame, that is, the first phase difference information is carried in multiple bytes in the overhead area of ​​the second OTN frame.

[0221] Exemplarily, if the number of bytes occupied by the first phase difference information is 1, the first phase difference information can occupy at least one byte in the overhead area of ​​the second OTN. This means that one byte can be used to carry one piece of first phase difference information, or multiple bytes can be used to carry multiple identical pieces of first phase difference information. When multiple bytes are used to carry multiple pieces of first phase difference information, the same piece of first phase difference information can be repeatedly transmitted using multiple bytes in at least one overhead area of ​​the second OTN frame, allowing intermediate device #1 to obtain multiple pieces of first phase difference information from a single overhead area of ​​the second OTN frame. This multiple retransmission method can prevent the situation where intermediate device #1 obtains inaccurate first phase difference information when a bit error occurs in the system. Exemplarily, intermediate device #1 uses an algorithm such as a majority decision algorithm to determine the more accurate first phase difference information from the multiple pieces of first phase difference information obtained from a single overhead area of ​​the second OTN frame.

[0222] If the first phase difference information occupies multiple bytes, the first phase difference information may occupy at least one byte in the overhead area of ​​the second OTN, which may mean that multiple bytes are used to carry one first phase difference information or that multiple bytes are used to carry multiple identical first phase difference information. Using multiple bytes to carry one first phase difference information may mean that the number of bytes carrying the first phase difference information in one overhead area is agreed to be multiple.

[0223] Specifically, the first phase difference information is the sum of the phase differences of one or more groups of adjacent two upstream devices in one or more upstream devices of the intermediate device #1 through which the second OTN frame passes, wherein the phase difference of one or more groups of adjacent two upstream devices is an integer number of nominal clock cycles, and the nominal clock cycle is less than or equal to 10ns.

[0224] It should be understood that since the upstream device of intermediate device #1 is only a sending device, there is no sum of the phase differences of one or more groups of two adjacent upstream devices in one or more upstream devices of intermediate device #1. At this time, the first phase difference information can be considered to be 0.

[0225] In some embodiments, when the first phase difference information is carried in the overhead area of ​​the second OTN, the transmitting device may record 0 in the overhead area of ​​the second OTN and send it to the intermediate device #1, or the transmitting device may not record any phase difference information in the overhead area of ​​the second OTN.

[0226] S1503 , the intermediate device # 1 generates a local phase difference based on the clock of the intermediate device # 1 and the service layer clock.

[0227] Specifically, the intermediate device records the number of cycles N1 of the nominal clock corresponding to the clock of the intermediate device #1 and the number of cycles N2 of the nominal clock corresponding to the service layer clock, and obtains the local phase difference by subtracting N1 from N2.

[0228] It should be noted that intermediate device #1 has a physical crystal oscillator clock, which serves as its clock and is also called its local clock. After acquiring the upstream server layer clock, intermediate device #1 uses the nominal clock period as the time interval to calculate the time it takes for the local clock period to reach the expected period N. It also calculates the number of server layer clock periods within this time interval and subtracts the two obtained period numbers to obtain the local phase difference. The expected period N is a preset number of periods.

[0229] S1504: Intermediate device #1 adds the local phase difference to the first phase difference information to generate second phase difference information.

[0230] Specifically, the intermediate device #1 sums the generated local phase difference and the acquired first phase difference information to obtain the second phase difference information.

[0231] S1505 , intermediate device # 1 sends a first OTN frame data stream to an adjacent downstream intermediate device.

[0232] Specifically, when the intermediate device #1 generates the second phase difference information, it carries the second phase difference information in the second OTN frame, maps the second OTN frame into the first OTN frame, and sends the first OTN frame data stream to the adjacent downstream device of the first intermediate device #1.

[0233] It should be noted that intermediate device #1 processes the information carried in the received first OTN frame data stream. Therefore, the first OTN frame data stream sent by intermediate device #1 is not identical to the first OTN frame data stream sent by the sending device. That is, the data content carried in the two data streams differs, but the corresponding first OTN frames have the same frame format. Similarly, the second OTN frame carried in the first OTN frame data stream sent by the sending device is different from the second OTN frame carried in the first OTN frame data stream sent by intermediate device #1. The former carries the first phase difference information, while the latter carries the second phase difference information. In other words, the two second OTN frames carry different content but the same frame format: the second OTN frame format.

[0234] It should be understood that when the first phase difference information is carried in the overhead area of ​​the second OTN frame, the second phase difference information generated by the intermediate device #1 is also carried in the overhead area of ​​the second OTN frame.

[0235] It should be understood that in S1502, intermediate device #1 obtains the first phase difference information between the service layer clock and the second OTN frame from the first OTN frame data stream only to illustrate that the information the intermediate device needs to obtain from the first OTN frame data stream includes the first phase difference information between the service layer clock and the second OTN frame, and does not mean that the first phase difference information between the service layer clock and the second OTN frame is obtained simultaneously. Similarly, in S1503, intermediate device #1 generates the local phase difference based on its local clock and the service layer clock. This can occur before or after intermediate device #1 obtains the first phase difference information of the second OTN frame, and this is not limited in this application.

[0236] S1506: Intermediate device #N receives a first OTN frame data stream from an adjacent upstream intermediate device.

[0237] S1507 , the intermediate device #N obtains the first phase difference information of the service layer clock and the second OTN frame from the first OTN frame data stream.

[0238] It should be understood that the service layer clock obtained by intermediate device #N is the transmission period or frequency of the first OTN frame data stream sent by the adjacent upstream intermediate device of intermediate device #N. The first phase difference information of the second OTN frame obtained by intermediate device #N is the first phase difference information carried in the second OTN frame carried in the first OTN frame data stream sent by the adjacent upstream intermediate device of intermediate device #N. This first phase difference information is the sum of the phase differences of multiple groups of adjacent two upstream devices of all upstream devices of intermediate device #N, including the phase difference calculated by intermediate device #1 with the sending device (also known as the local phase difference of intermediate device #1), the phase difference calculated by intermediate device #2 with intermediate device #1 (also known as the local phase difference of intermediate device #2), the phase difference calculated by intermediate device #3 with intermediate device #3 (also known as the local phase difference of intermediate device #3), and finally the phase difference calculated by intermediate device #(N-1) with intermediate device #(N-2) (also known as the local phase difference of intermediate device #(N-1)). It should be understood that the phase difference of these multiple groups of adjacent two upstream devices is an integer number of nominal clock periods. The nominal clock period is less than or equal to 10ns.

[0239] S1508: The intermediate device #N generates a local phase difference based on the clock of the intermediate device #N and the service layer clock.

[0240] S1509: The intermediate device #N accumulates the local phase difference to the first phase difference information to generate second phase difference information.

[0241] S1510: Intermediate device #N sends a first OTN frame data stream to a destination device.

[0242] It should be noted that the overhead area of ​​the second OTN frame carried in the first OTN frame data flow sent by the intermediate device #N to the destination device carries the second phase difference information generated by the intermediate device #N.

[0243] In some embodiments, the second phase difference information is carried in at least one overhead area of ​​the second OTN frame, that is, the second phase difference information is carried in multiple overhead areas of the second OTN frame. For example, when the second OTN frame includes multiple overhead areas, each of the multiple overhead areas may carry a piece of second phase difference information. The second phase difference information carried in the multiple overhead areas may be the second phase difference information sent by intermediate device #N at the same time, or the second phase difference information sent by intermediate device #N at different times. If the second phase difference information carried in the multiple overhead areas is the second phase difference information sent by intermediate device #N at the same time, intermediate device #N may carry the second phase difference information generated at the same time in different overhead areas sent at different times. In this case, the destination device may use an algorithm such as a majority decision algorithm to determine a more accurate second phase difference information based on the second phase difference information carried in the overhead areas of multiple consecutively received second OTN frames. If the second phase difference information carried by the multiple overhead areas is the phase difference information sent by the intermediate device #N at different times, the intermediate device #N can carry the second phase difference information generated at different times in the overhead areas sent at different times, so that the destination device obtains the second phase difference information sent by the intermediate device #N at different times in the overhead areas of the second OTN frames received at different times.

[0244] In other embodiments, the second phase difference information may occupy at least one byte in the overhead area of ​​the second OTN frame. For example, if the number of bytes occupied by the second phase difference information is one, the second phase difference information may occupy at least one byte in the overhead area of ​​the second OTN frame, which means that one byte may be used to carry one piece of second phase difference information, or multiple bytes may be used to carry multiple pieces of the same second phase difference information. When multiple bytes are used to carry multiple pieces of second phase difference information, the same piece of second phase difference information may be repeatedly transmitted using multiple bytes in at least one overhead area of ​​the second OTN frame. This allows the destination device to obtain multiple pieces of second phase difference information from a single overhead area of ​​the second OTN frame. This multiple retransmission method can prevent the destination device from obtaining inaccurate second phase difference information when a bit error occurs in the system. For example, the destination device uses an algorithm such as a majority decision algorithm to determine the more accurate second phase difference information from the multiple pieces of second phase difference information obtained from a single overhead area of ​​the second OTN frame. Furthermore, the multiple bytes may be non-consecutive, further improving the system's bit error resilience. If the second phase difference information occupies multiple bytes, the second phase difference information can occupy at least one byte in the overhead area of ​​the second OTN. This means that when the second phase difference information cannot be fully carried in a single byte, multiple bytes in at least two adjacent overhead areas are used to carry the second phase difference information. This means that the destination device needs to continuously receive multiple overhead areas to obtain the complete second phase difference information. This is because as the phase difference information accumulates, the absolute value of the second phase difference information increases, making it impossible for the byte originally used to carry the correct second phase difference information because the absolute value of the second phase difference information exceeds a preset threshold. In this case, intermediate device #N can split the second phase difference information into multiple partial phase difference information components and use multiple bytes in one overhead area to carry the complete second phase difference information. This means that the second phase difference information can occupy at least one byte in the overhead area of ​​the second OTN, i.e., the second phase difference information can be carried in multiple overhead areas within the overhead area of ​​the second OTN frame. It should be understood that multiple overhead areas can also be used to carry multiple pieces of second phase difference information occupying multiple bytes at the same time or at different times.

[0245] It should be understood that other relevant descriptions of S1507-S1510 can refer to the above S1502 to S1505 and will not be repeated here.

[0246] S1511: The destination device obtains first phase difference information of a server layer clock and a second OTN frame from the first OTN frame data stream.

[0247] Specifically, after receiving the first OTN frame data stream sent by the intermediate device #N, the destination device obtains the first phase difference information of the service layer clock and the second OTN frame from the first OTN frame data stream.

[0248] It should be understood that the service layer clock obtained by the destination device is the transmission period or frequency of the first OTN frame data stream sent by intermediate device #N. The first phase difference information of the second OTN frame obtained by the destination device is the first phase difference information carried in the second OTN frame carried in the first OTN frame data stream sent by intermediate device #N. This first phase difference information is the sum of the phase differences of multiple groups of adjacent upstream devices of all upstream devices of intermediate device #N, including the phase difference calculated by intermediate device #1 with the sending device (also known as the local phase difference of intermediate device #1), the phase difference calculated by intermediate device #2 with intermediate device #1 (also known as the local phase difference of intermediate device #2), the phase difference calculated by intermediate device #3 with intermediate device #3 (also known as the local phase difference of intermediate device #3), and finally the phase difference calculated by intermediate device #N with intermediate device #(N-1) (also known as the local phase difference of intermediate device #N). It should be understood that the phase difference of these multiple groups of adjacent upstream devices is an integer number of nominal clock cycles. The nominal clock cycle is less than or equal to 10ns.

[0249] Other related descriptions of S1511 can refer to the above S1502 respectively, and will not be repeated here.

[0250] S1512: The destination device generates a local phase difference according to the reference clock of the second OTN frame of the destination device and the service layer clock.

[0251] For related descriptions of this process, please refer to S1503 or S1508 above, which will not be repeated here. The reference clock of the second OTN frame of the destination device can be called the local reference clock of the second OTN frame of the destination device, which can be obtained through the local clock of the destination device.

[0252] It should be understood that the intermediate device generates its own phase difference using its local clock, which distinguishes the services of the second OTN frame. In other words, when the intermediate device generates its own local phase difference, one phase difference corresponds to all second OTN frames within the first OTN frame. However, when performing clock recovery, the destination device needs to recover the clock of each second OTN frame. Therefore, when calculating the local phase difference, the destination device needs to use the reference clock of the destination device's second OTN frame. This reference clock is implemented digitally, for example, by dividing the destination device's local crystal oscillator clock into different clocks for different second OTN frames.

[0253] S1513: The destination device adds the local phase difference to the first phase difference information to generate second phase difference information.

[0254] For the relevant description of this process, please refer to the above S1504, or refer to the above S1509, which will not be repeated here.

[0255] S1514: The destination device adjusts the clock control signal of the reference clock of the second OTN frame of the destination device according to the second phase difference information.

[0256] Specifically, when the destination device adjusts the reference clock of the second OTN frame of the destination device, it adjusts the reference clock of the second OTN frame of the destination device to be consistent with the reference clock of the second OTN frame of the sending device (which can be understood as being within a preset range). When the reference clock of the second OTN frame of the destination device is adjusted to be consistent with the reference clock of the second OTN frame of the sending device, the second phase difference information should be 0. Therefore, the destination device can determine the offset of the reference clock of the second OTN frame of the destination device based on the second phase difference information and generate a control signal in the opposite direction of the offset. For example, when the second phase difference information is a positive number, such as 1, it indicates that the reference clock of the second OTN frame of the destination device is faster than the reference clock of the second OTN frame of the sending device. In this case, the control signal is -1.

[0257] S1515: The destination device adjusts the reference clock of the second OTN frame according to the clock control signal.

[0258] Specifically, the destination device adjusts the reference clock of the second OTN frame through the clock control signal, so that the reference clock of the second OTN frame adjusted by the destination device and the reference clock of the second OTN frame sent by the sending device are within a preset error range.

[0259] It should be understood that when the reference clock of the second OTN frame adjusted by the destination device and the reference clock of the second OTN frame sent by the sending device are within the above-mentioned preset error range, it can be considered that the destination device adjusts the reference clock of the second OTN frame to be consistent with the reference clock of the second OTN frame sent by the sending device.

[0260] It should be noted that in the embodiment of the present application described in the above method 1500, the first phase difference information can be understood as the phase difference information received by any device other than the transmitting device or the phase difference information sent by the transmitting device, and the second phase difference information can be understood as the phase difference information generated by any device other than the transmitting device. It should be understood that for different devices, the first phase difference information received is different, and the second phase difference information generated is also different. That is, when understanding the first phase difference information and the second phase difference information in the embodiment of the present application, it is necessary to understand them in combination with the device receiving the first phase difference information and the device generating the second phase difference information.

[0261] It should also be noted that for Figure 15 The processing procedures of other intermediate devices not shown in the figure can refer to the processing procedures of the above-mentioned intermediate device #1 or intermediate device #N, and will not be repeated here.

[0262] It should be understood that in the embodiments of the present application, when any intermediate device or destination device calculates the local phase difference, the service layer clock it obtains is the service layer clock sent by the adjacent upstream device. That is, the service layer clock used to calculate the local phase difference is the upstream service layer clock. When the intermediate device generates second phase difference information and transmits it to the downstream device via the first OTN frame data stream, the service data stream sent to the first OTN frame is encapsulated into the first OTN frame using the local service layer clock of the intermediate device that generated the second phase difference information. In other words, for any intermediate device, the service layer clock corresponding to the first OTN frame data stream it inputs is different from the service layer clock corresponding to the first OTN frame data stream it transmits.

[0263] It should be noted that, in an embodiment of the present application, the overhead area used to carry the phase difference information (including the first phase difference information and the second phase difference information) can be the reserved bytes in the original overhead area in the multiplexed second OTN frame, or the bytes divided in the original payload area in the second OTN frame for carrying the phase difference information.

[0264] In some embodiments, the first OTN frame may be an ODU frame, for example, an ODUk frame or an ODUflex frame. The second OTN frame may be an OSU frame.

[0265] Figure 16 A schematic diagram of the processing flow of the intermediate device provided for an embodiment of the present application. Specifically, the intermediate device receives the ODU data stream from the upstream adjacent device, demaps the OSU from the ODU data stream, and obtains the service layer clock and the first phase difference information. The intermediate device calculates the number of cycles of the nominal clock corresponding to the service layer clock and the clock of the intermediate device respectively, and subtracts the number of cycles of the nominal clock corresponding to the calculated service layer clock from the number of cycles of the nominal clock corresponding to the clock of the intermediate device to obtain the local phase difference. At the same time, the intermediate device sums the first phase difference information and the local phase difference to obtain the second phase difference information, and records it in the OSU frame after the exchange. Subsequently, the intermediate device maps the OSU frame of the recorded second phase difference information to the ODU frame, generates an ODU frame data stream, and sends it to the adjacent downstream device.

[0266] Figure 17A schematic diagram of the processing flow of the destination device provided in an embodiment of the present application. Specifically, the destination receives the ODU frame data stream from the upstream adjacent device, demaps the OSU frame from the ODU frame data stream, and obtains the service layer clock and the first phase difference information. The destination device calculates the number of cycles of the nominal clock corresponding to the service layer clock and the reference clock of the OSU frame of the destination device (obtained through the local clock of the destination device), and subtracts the number of cycles of the nominal clock corresponding to the calculated service layer clock from the number of cycles of the nominal clock corresponding to the OSU frame reference clock of the destination device to obtain the local phase difference. At the same time, the destination device sums the first phase difference information and the local phase difference to obtain the second phase difference information. Subsequently, the destination device generates a control signal based on the second phase difference information, and uses the control signal to perform clock recovery on each OSU frame service data stream in the ODU frame data stream, and outputs the OSU frame data stream. Among them, the OSU frame data stream output by the destination device can be understood as the data information of the OSU frame, including service data and overhead.

[0267] In the clock recovery method provided in the embodiments of the present application, the intermediate device only needs to record phase difference information representing the local clock offset of the intermediate device and transmit this phase difference information to the destination device. The destination device then uses the obtained phase difference information to adjust the reference clock of the second OTN frame, thereby achieving the purpose of recovering the clock of the second OTN frame. This solution does not require the intermediate device to recover the clock of the second OTN frame. At the same time, by quantizing the clock offset using the phase difference information, it can avoid errors that cannot be corrected when using frequency quantization of the clock offset (this error is caused by the fact that only real numbers can be transmitted when the frequency difference is transmitted). Therefore, the clock recovery method provided in the embodiments of the present application can simplify the clock recovery process and improve the accuracy of the reference clock adjustment of the second OTN frame, thereby achieving the purpose of improving system performance.

[0268] In some scenarios, when a sudden anomaly occurs in the reference clock of an OTN device in a system, it can lead to errors in the calculation of phase difference information. To ensure the accuracy of phase difference information and avoid wasting resources due to the transmission of erroneous phase difference information, embodiments of the present application propose a clock recovery method. When a device in the system discovers an anomaly in the service clock it obtains or its local clock when calculating phase difference information, it no longer generates new phase difference information. Instead, it sends the fault information to the downstream device via the overhead area of ​​the second OTN frame. This prevents the destination device that ultimately receives the fault information from performing clock recovery, thus avoiding service transmission failures caused by clock recovery errors and improving system performance. This method is executed by an intermediate device in the system or by a component of the intermediate device.

[0269] The following, combined Figure 18 , and Figure 15The clock recovery method 1800 provided by the embodiment of the present application is described in detail. The clock recovery method 1800 is executed by any intermediate device in the system. The following description takes intermediate device #1 as an example. Figure 18 As shown, the method includes the following steps.

[0270] S1801: Receive a first OTN frame data stream.

[0271] S1802: Obtain first phase difference information between the server layer clock and the second OTN frame from the first OTN frame data stream.

[0272] S1803: Generate a local phase difference based on the clock of the intermediate device #1 and the service layer clock.

[0273] Specifically, intermediate device #1 records the number of cycles N1 of the nominal clock corresponding to the clock of intermediate device #1, and at the same time, intermediate device #1 records the number of cycles N2 of the nominal clock corresponding to the service layer clock, and calculates the difference between N1 and N2 as the local phase difference.

[0274] For other related instructions in S1801 to S1803 above, please refer to Figure 15 S1501 to S1503 in the method 1500 shown are not repeated here.

[0275] S1804: Generate first information.

[0276] The first information includes second phase difference information or fault information.

[0277] Specifically, when the number of cycles N1 of the nominal clock corresponding to the clock of the intermediate device #1 and the number of cycles N2 of the nominal clock corresponding to the service layer clock recorded by the intermediate device #1 fall within a preset interval, and when the difference between N1 and N2 is equal to -1, 0, or 1 within a preset time, the intermediate device #1 accumulates the local phase difference to the first phase difference information to generate the second phase difference information. When the intermediate device #1 determines that the number of cycles N1 of the nominal clock corresponding to the clock of the intermediate device #1 does not fall within the preset interval, the number of cycles N2 of the nominal clock corresponding to the service layer clock recorded by the intermediate device #1 does not fall within the preset interval, and the difference between N1 and N2 is not equal to at least one of -1, 0, or 1 within the preset time, the intermediate device #1 generates a fault message. The preset interval is:

[0278] [N×(1-20ppm), N×(1+20ppm)],

[0279] The preset time is T Nominal ×1 / (40ppm), or T Nominal ×25000, T Nominalis the period of the nominal clock.

[0280] It should be noted that in an OTN network, the actual frequency deviation of a device is usually ±20ppm. The above preset interval is used to detect abnormal frequency deviations outside the ±20ppm range of the system, and the preset time is used to detect sudden frequency deviations of the device.

[0281] S1805, sending the first information.

[0282] It should be noted that when intermediate device #1 detects that no fault has occurred, the first information is the second phase difference information. When intermediate device #1 detects that a fault has occurred, the first information is the fault information. It should be understood that the first information is carried in at least one overhead of the second OTN frame. The number of bytes occupied by the first information is at least one byte, wherein at least one bit in the at least one byte is used to indicate that the information included in the first information is the second phase difference information or the fault information. For example, Figure 19 This is a schematic diagram of the structure of the first information when the number of bytes occupied by the first information is one byte. When the most significant bit of the one byte is 0, it indicates that the first information includes second phase difference information, which is carried on the other seven bits. When the most significant bit is 1, it indicates that the first information includes fault information.

[0283] Optionally, when the first information is fault information, the fault information includes the number of devices that have failed, that is, the number of nodes from the failed intermediate device #1 to the destination device. The number of devices that have failed can be indicated by multiple bits of the remaining 7 bits, such as Figure 19 As shown, it can be indicated by the lower 5 bits. For example, when the intermediate device #1 determines that the clock of the intermediate device #1 is abnormal, it generates fault information, and in the indication field for indicating the number of devices that have failed (such as the above Figure 19 The device then records 1 in the 5 bits of the fault field (in the 5 bits of the fault field) and sends a fault message to the downstream device, which records the number of faulty devices. Upon receiving the fault message, the downstream device can sequentially count the number of faulty devices in the indicator field. This allows the destination device to locate the faulty intermediate device #1 based on the number recorded in the indicator field after receiving the fault message.

[0284] Optionally, when the first information may further include confirmation information, the confirmation information is used to instruct the downstream device to confirm that the first information is fault information. Figure 19As shown, the second higher bit can be used to indicate the fault. For example, when a downstream intermediate device of intermediate device #1, such as intermediate device #2, receives fault information from intermediate device #1, it can reconfirm that the OTN system has experienced a fault by calculating whether there is system frequency deviation or sudden device frequency deviation, and then fill the second bit with 1. This double confirmation avoids false alarms caused by recoverable abnormal jitter in the OTN system, thereby ensuring stable system performance.

[0285] Similarly, when the first information is the second phase difference information, the multiple first information can be carried in multiple bytes in the overhead area of ​​the second OTN. When the multiple bytes are continuous or non-continuous, the system's error resistance performance can be improved.

[0286] It should be understood that Figure 19 This is only an example and not a limitation. In the embodiment of the present application, the number of bits occupied by the fault indication, confirmation information, and the number of faulty devices is not limited to Figure 19 Others in Figure 19 Simple changes based on the example shown, such as using the last bit to indicate that the first information includes the second phase difference information or fault information, etc., are all within the protection scope of the present application.

[0287] Furthermore, the above method 1800 is described using only intermediate device #1 as an example. It should be understood that for other intermediate devices, the second phase difference information is the sum of the local phase difference and the acquired first phase difference. The number of devices experiencing a failure included in the fault information is the number of devices from the intermediate device to the destination device.

[0288] Based on the above solution, when the phase difference information calculated by the intermediate device does not meet the preset conditions, the fault information is sent through the intermediate device, which avoids the downstream device from calculating the wrong phase difference information, saves system resources, and improves system performance.

[0289] It should be noted that in the clock recovery methods provided in the above embodiments of the present application, the calculation is performed based on the local clock of the device, that is, the time elapsed when the nominal clock corresponding to the local clock reaches the preset expected number of cycles is first calculated, and the number of cycles of the nominal clock corresponding to the upstream service layer clock within the same time is calculated. Then, the expected number of cycles is subtracted from the number of cycles of the nominal clock corresponding to the upstream service layer clock to obtain the local phase difference. However, in some scenarios, such as when there are some intermediate devices in the network system with large frequency deviations, the phase difference information obtained by the destination device will have slow low-frequency phase drift. This low-frequency phase drift cannot be eliminated by the clock recovery loop, and will eventually reduce the performance of the clock recovery, so that it cannot meet the requirements of the current standard template (G.813). To solve the above problem, the embodiment of the present application proposes a clock recovery method 2000. This method sets the trigger time for calculating the local phase difference, so that all intermediate devices always select a faster reference clock or a slower reference clock to reduce the error caused by using the local clock as the reference clock, thereby achieving a more accurate clock recovery effect.

[0290] The following, combined Figure 20 , and Figure 15 Taking the intermediate device #1 in the example, the clock recovery method 2000 provided in the embodiment of the present application is described in detail. Figure 20 As shown, the method includes the following steps.

[0291] S2001: Receive a first OTN frame data stream.

[0292] S2002: Acquire first phase difference information of a server layer clock and a second OTN frame from a first OTN frame data stream.

[0293] The above S2001-S2002 can be referred to Figure 15 S1501-S1502 in the method 1500 shown are not repeated here.

[0294] S2003: When the time for triggering calculation of the local phase difference is met, a local phase difference is generated according to the local clock of the intermediate device and the service layer clock.

[0295] Specifically, when the moment for triggering the calculation of the local phase difference is met, the intermediate device #1 records the number of cycles N1 of the nominal clock corresponding to the local clock of the intermediate device #1, and at the same time, the intermediate device #1 records the number of cycles N2 of the nominal clock corresponding to the service layer clock, and calculates the difference between N1 and N2 as the local phase difference.

[0296] When the faster of the local and server clocks is selected as the reference clock, the time to trigger the calculation of the local phase difference is when the number of cycles of the nominal clock corresponding to the local clock first equals the expected period, or when the number of cycles of the nominal clock corresponding to the server clock first equals the expected period, that is, when the number of cycles of the nominal clock corresponding to the local clock or the number of cycles of the nominal clock corresponding to the server clock first equals the expected period. For example, if the preset expected period is N, the time elapsed when N1 equals N is the first time interval, and the time elapsed when N2 equals N is the second time interval, then when the local clock is faster than the server clock, that is, the first time interval is less than the second time interval, in other words, the number of cycles of the nominal clock corresponding to the local clock will first step to the expected period, at which point intermediate device #1 will trigger the process of calculating the local phase difference. Alternatively, when the server clock is faster than the local clock, that is, the second time interval is less than the first time interval, the number of cycles of the nominal clock corresponding to the server clock will first step to the expected period, at which point intermediate device #1 will trigger the process of calculating the local phase difference. The desired period can be set by N=F×T, where F is the frequency of the nominal clock and T is the period for generating the local phase difference.

[0297] Similarly, when the slower of the local clock and the service layer clock is selected as the reference clock, the time to trigger the calculation of the local phase difference is the time when the later of the number of cycles of the nominal clock corresponding to the local clock and the number of cycles of the nominal clock corresponding to the service layer clock is equal to the expected period. For example, when the local clock is slower than the service layer clock, that is, when the first time interval is greater than the second time interval, the number of cycles of the nominal clock corresponding to the local clock advances to the expected period later than the nominal clock corresponding to the service layer. Therefore, when the number of cycles of the nominal clock corresponding to the local clock is equal to the expected period, intermediate device #1 will trigger the process of calculating the local phase difference. Alternatively, when the service layer clock is slower than the local clock, that is, when the second time interval is greater than the first time interval, the nominal clock corresponding to the service layer clock advances to the expected period later than the nominal clock corresponding to the local clock. Therefore, when the number of cycles of the nominal clock corresponding to the service layer clock is equal to the expected period, intermediate device #1 will trigger the process of calculating the local phase difference.

[0298] In one possible implementation, Figure 21 The first method of calculating the phase difference is shown in the figure. Figure 21 As shown, counter A and counter B respectively count the number of cycles of the nominal clock corresponding to the local clock and the number of cycles of the nominal clock corresponding to the server layer clock of the sending device, where N is the expected number of cycles.

[0299] For example, in one scenario, assuming a faster clock is used as the reference clock, if the number of cycles of the nominal clock corresponding to the local clock of intermediate device #1 reaches the desired period N first, that is, if A = N & PD ≥ 0 first holds, the OR gate is triggered, and the AB subtractor calculates the phase difference at this time as N minus the number of cycles B recorded by counter B. At this time, the reference clock of intermediate device #1 is set as the local clock. Alternatively, if the number of cycles of the nominal clock corresponding to the server layer clock reaches the desired period N first, that is, if B = N & PD < 0 first holds, the OR gate is triggered, and the AB subtractor calculates the phase difference at this time as AN recorded by counter A. At this time, the server layer clock is set as the reference clock of intermediate device #1.

[0300] For example, in another scenario, assuming a slower clock is used as the reference clock, when the number of cycles of the nominal clock corresponding to the local clock of intermediate device #1 reaches the desired period N first, that is, when A = N & PD ≥ 0 first holds, the OR gate is not triggered. Instead, the OR gate is triggered when the number of cycles of the nominal clock corresponding to the server layer clock reaches the desired period N. The AB subtractor calculates the phase difference at this time as the number of cycles AN recorded by counter A. At this point, the reference clock of intermediate device #1 is set as the server layer clock. Alternatively, when the number of cycles of the nominal clock corresponding to the local clock of intermediate device #1 reaches the desired period N later than the number of cycles of the nominal clock corresponding to the server layer clock, that is, when A = N & PD ≥ 0 holds, the OR gate is triggered, and the AB subtractor calculates the phase difference at this time as N - the number of cycles B recorded by counter B. At this point, the local clock of intermediate device #1 is set as the reference clock of intermediate device #1.

[0301] After the AB subtractor calculates the phase difference, the phase difference calculation result is stored in the PD register (also called the phase detection register), and the counter A and the counter B are reset (for example, an indication information is sent to the counter A and the counter B to instruct the counter A and the counter B to return to zero). At the same time, the PD register feeds back the calculated phase difference to the two condition modules (including A=N&PD≥0 and B=N&PD<0).

[0302] In one possible implementation, Figure 22 This is a flow chart of the second method for calculating the phase difference. Figure 22 As shown, counter A and counter B respectively count the number of cycles of the nominal clock corresponding to the local clock and the number of cycles of the nominal clock corresponding to the service layer clock, where N is the expected number of cycles.

[0303] For example, in one scenario, assuming that a faster clock is used as the reference clock, when the number of cycles of the nominal clock corresponding to the local clock of the intermediate device #1 reaches the expected period N first, that is, A=A RegWhen +N is established first, the OR gate is triggered, and the AB subtractor calculates the phase difference at this time as N-the number of cycles recorded by counter B. At the same time, counter A and counter B store the values ​​of A and B at that moment, which are A Reg and B Reg At this time, the reference clock of the intermediate device #1 is set to the local clock. Or, when the number of cycles of the nominal clock corresponding to the server layer clock reaches the expected period N first, that is, B=B Reg When +N is established first, the OR gate is triggered, and the AB subtractor calculates the phase difference at this time as the number of cycles AN recorded by counter A. At the same time, counter A and counter B store the values ​​of A and B at that moment, which are A and B respectively. Reg and B Reg At this point, the server layer clock is set to the reference clock of intermediate device #1.

[0304] For example, in another scenario, assuming that a slower clock is used as the reference clock, when the number of cycles of the nominal clock corresponding to the local clock of the intermediate device #1 reaches the expected period N first, that is, A=A Reg When the number of cycles of the nominal clock corresponding to the server clock reaches the expected period N, the OR gate is not triggered. The AB subtractor calculates the phase difference at this time as the number of cycles AN recorded by counter A. At this time, the reference clock of the intermediate device #1 is set as the server clock. Alternatively, when the number of cycles of the nominal clock corresponding to the local clock of the intermediate device #1 reaches the expected period N later than the number of cycles of the nominal clock corresponding to the server clock, that is, when A=A Reg When N+N is established, the OR gate is triggered. The AB subtractor calculates the phase difference at this time as N-the number of cycles B recorded by counter B. At the same time, counter A and counter B store the values ​​of A and B at that moment, which are A Reg and B Reg At this time, the local clock of intermediate device #1 is set as the reference clock of intermediate device #1.

[0305] After the AB subtractor calculates the phase difference, the phase difference calculation result is stored in the PD register (also called the phase detection register).

[0306] It should be understood that for each calculation process A Reg and B Reg The values ​​of A and B recorded by counter A and counter B during the previous phase difference calculation.

[0307] It should be noted that in the embodiments of the present application, the reference clock can be understood as a clock used to determine the detection period (also called the detection window). For example, when a faster clock is used as the reference clock, the process can be understood as selecting the time elapsed when the nominal clock corresponding to the faster clock reaches the expected number of cycles N from the local clock of the intermediate device or the upstream service layer clock as the detection period, and calculating the number of cycles of the nominal clock corresponding to another relatively slower clock within the detection period.

[0308] It should also be noted that due to Figure 22 In the calculation process shown, there is no need to reset the counter, thus achieving the effect of simplifying the calculation process. However, counter A and counter B have limited bit widths, that is, counter A and counter B have a maximum storage capacity. When counter A and counter B reach the maximum countable value, counter A and counter B will recount. At this time, a sudden error will be introduced in the difference between the calculated cycle numbers A and B. In order to solve this problem, there are two implementation methods. In one feasible method, a PD correction module can be introduced before the PD memory. When the absolute value of the phase difference calculated by the AB subtractor is greater than the threshold, the phase difference is corrected to the difference between the threshold and the absolute value of the phase difference. The threshold is a preset range of the counter period, for example, it can be half of the counter period (that is, the maximum value that the counter can store). For example, if the storage limit of counters A and B is 10,000, when the calculation of the local phase difference is triggered, since the period A recorded by counter A is greater than 10,000, the recount of counter A is 2, while the period B recorded by counter B is 9,998. At this time, the absolute value of the phase difference calculated by the AB subtractor is 9,996, which exceeds 5,000. Therefore, the phase difference is corrected to 10,000-9,996=4. In another implementation, the nature of bit arithmetic itself can be used to solve the problem of counter overflow. Counters A and B need to be represented by signed bit sequences. Assuming that the counter bit sequence width is one byte, when A counts to 127 (01111111), assuming that B counts to 120 (01111000), A continues to count and overflows to -128 (10000000), and B is (01111001). At this time, the result of AB is 7 (10000000-01111001=00000111), which is still the correct value. In fact, as long as the target counting period is less than half the size of the counter value range, this method is always legal.

[0309] Based on this solution, the phase difference can be corrected after the counter reaches the counter cycle, thereby ensuring the accuracy of phase difference calculation and further improving the accuracy of clock recovery.

[0310] Figure 23 The simulation comparison results are as follows: the intermediate devices all use local clocks as reference clocks and the embodiments of the present application provide a unified faster or slower clock as the reference clock. Among them, the simulation parameters are set as follows: the destination device is an open-loop setting at the host end, the period of the overhead area carrying the phase difference information is 3.435ms, the nominal clock frequency is 78.125MHz, and the frequency deviations of the 11 devices are: [0, 9.05, -0.005, 18.23, -8.59, -9.58, -3.46, 12.99, -6.36, -19.01, 0] ppm. The vertical coordinate PD_ACC represents the phase difference information received by the destination device from the overhead area. Figure 23 As shown, when all intermediate devices use their local clocks as reference clocks, the phase difference information recorded by the destination device exhibits slow drift. This low-frequency drift cannot be eliminated by the clock recovery loop, ultimately degrading clock recovery performance to the point where it fails to meet template requirements. However, the solution provided by the embodiments of this application effectively removes low-frequency phase offsets, significantly reducing the phase error of clock recovery and thus improving clock recovery performance.

[0311] Figure 24 The simulation comparison results are as follows: the intermediate devices all use local clocks as reference clocks and the embodiments of the present application use a unified faster or slower clock as the reference clock. The simulation parameters are set as follows: the loop bandwidth of the destination device is about 1Hz, the period of the overhead zone carrying the phase difference information is 3.435ms, the nominal clock frequency is 78.125MHz, and the frequency deviations of the 11 devices are: [0, 9.05, -0.005, 18.23, -8.59, -9.58, -3.46, 12.99, -6.36, -19.01, 0]ppm. The vertical axis is the difference between the recovered clock of the destination device and the clock sent by the sending device, which can represent the performance of the clock recovery. Figure 24 As shown, when all intermediate devices use their local clocks as the reference clock, the clock recovered by the destination device has jitter of approximately 50ns and local high-frequency oscillations, failing to meet the requirements of the clock template. However, the solution provided by the embodiments of the present application significantly reduces the phase error of clock recovery, improves clock recovery performance, and meets the G.813 clock performance template under conditions of a relatively high sink loop bandwidth.

[0312] Figure 25The following are simulation results when all intermediate devices are at extreme frequency deviation (±20ppm) and use a unified faster or slower clock as the reference clock. The simulation parameters are set as follows: the loop bandwidth of the destination device is approximately 1Hz, the period of the overhead area carrying phase difference information is 3.435ms, the nominal clock frequency is 78.125MHz, and the frequency deviations of the 11 devices are: [-20, 20, -20, 20, -20, 20, -20, 20, -20, 20, -20]ppm. Figure 22 As shown in FIG, since all intermediate devices always select a reference clock in one direction to eliminate the difference in the basic clock, the phase deviation after clock recovery is reduced to 0.

[0313] In order to reduce the frequency offset jitter of the intermediate device and achieve a more accurate clock recovery effect, in another implementation, an average clock can be always selected for all intermediate devices to reduce the error caused by using the local clock as the reference clock. In some embodiments, the average clock is any time interval between the first time interval and the second time interval. Similarly, the first time interval is the time elapsed when the record N1 is equal to N, and the second time interval is the time elapsed when the record N2 is equal to N, where N is a preset expected period (also called the expected number of periods). For example, when the first time interval is 3ms and the second time interval is 3.00006ms, the average clock period can be an integer number of clock periods corresponding to 3.00003ms. In other embodiments, the average clock period is the average value of the first time interval and the second time interval, and the method of rounding the average value can be, for example, rounding down, rounding up, or rounding up. For example, when the average value of the first time interval and the second time interval is 3.00003ms, the average clock period can be determined to be 3ms by rounding down. Alternatively, when the average of the first time interval and the second time interval is 3.50000 ms, the average clock period can be determined to be 4 ms by rounding. When both the local clock of the intermediate device and the service layer clock have passed the period of the average clock, the integer number of periods of the difference between the nominal clock corresponding to the local clock and the nominal clock corresponding to the service layer clock is calculated as the local phase difference.

[0314] Figure 28 The third method for calculating the phase difference is provided in the embodiment of the present application. Figure 28 In the example, counter A and counter B respectively count the number of cycles of the nominal clock corresponding to the local clock and the number of cycles of the nominal clock corresponding to the server layer clock of the sending device. Storage unit A Reg and B RegThey are used to store the number of cycles recorded by counter A and counter B each time the local phase difference is calculated, so as to obtain the difference in the number of cycles that counter A and counter B have stepped since the previous trigger when the local phase difference is calculated next time. Specifically, when the time for triggering the calculation of the local phase difference is met, the subtractor calculates the difference in the number of cycles that counter A and counter B have stepped since the previous trigger, i.e. (AA Reg ) and (BB Reg ). At the same time, the subtractor enables storage unit A Reg and B Reg The period values ​​of counter A and counter B at this moment are stored respectively, that is, storage unit A Reg Update the stored period value to the value of trigger time counter A, storage unit B Reg The stored period value is updated to the value of the trigger time counter B. After the subtractor calculates the phase difference, the generated phase difference is corrected by the PD correction module and then stored in the PD memory.

[0315] Figure 29 for Figure 28 There are three possible types of moments that trigger the calculation of the local phase difference. Specifically, Figure 29 The time when the local phase difference is triggered can be expressed as A≥A Reg +M. Among them, M can be selected according to the corresponding rules. Specifically, when a faster clock is selected as the reference clock, M is expressed as Figure 29 Type 1 in; when a slower clock is selected as the reference clock, M is expressed as Figure 29 Type 2 in; when the average clock is selected as the reference clock, M is expressed as Figure 29 Type 3 in the equation. Type 1, type 2, and type 3 are expressed as follows:

[0316]

[0317] It should be noted that in Figure 29 In the triggering moment of calculating the local phase difference shown in FIG, only the monitoring counter A is used to determine whether the triggering moment of calculating the local phase difference is satisfied. It can be understood that the triggering moment of calculating the local phase difference can also be replaced by B≥B Reg +M. In addition, Figure 29 The average clock in the figure only shows a form of rounding down. For example, rounding up or rounding up may also be adopted, which is not limited in this application.

[0318] Combine Figure 28 and Figure 29 It can be seen that when using Figure 29When the time for triggering calculation of the local phase difference is shown, it is possible to monitor whether the corresponding time for triggering calculation of the local phase difference is met only for the number of cycles currently recorded by counter A or the number of cycles recorded by counter B. Figure 21 or Figure 22 For monitoring the period values ​​of two counters at the same time, this process is simpler and more reliable.

[0319] In one possible implementation, Figure 30 This is a schematic diagram of the fourth method for calculating the phase difference provided in the embodiment of the present application. Figure 30 As shown, counter A and counter B respectively count the number of cycles of the nominal clock corresponding to the local clock and the number of cycles of the nominal clock corresponding to the service layer clock.

[0320] Specifically, in Figure 30 In the illustrated scenario, when the intermediate device confirms receipt of the first phase difference information, it triggers the calculation of the current local phase difference. In some embodiments, when the data frame carrying the first phase difference information is a second OTN frame, the intermediate device confirms receipt of the first phase difference information by identifying the header of the second OTN frame. In this case, when the intermediate device identifies the header of the second OTN frame carrying the first phase difference information, or once the intermediate device identifies the header of the second OTN frame carrying the first phase difference information, the intermediate device triggers the process of calculating the local phase difference.

[0321] It is understandable that since the process of the intermediate device obtaining the first phase difference information from the second OTN frame takes time, in other embodiments, the moment when the intermediate device triggers the calculation of the local phase difference can be understood as any moment between the moment when the frame header of the second OTN frame is identified and the moment when the first phase difference information carried in the overhead area of ​​the second OTN frame is obtained.

[0322] Specifically, the process of calculating the local phase difference by the intermediate device is the same as the above Figure 28 The process is the same, that is, when the intermediate device triggers the calculation, the intermediate device records the current values ​​of counter A and counter B, and combines them with the A stored in the storage unit after the previous local phase difference calculation. Reg and B Reg , calculate the step value of the number of cycles of the nominal clock corresponding to the local clock and the number of cycles of the nominal clock corresponding to the service layer clock since the last local phase difference calculation, that is, (AA Reg ) and (BB Reg ), the local phase difference is calculated by the step value of counter A and counter B. At the same time, the subtractor enables storage unit A Reg and B Reg The period value at that moment is stored for the next calculation, that is, storage unit A RegUpdate the stored period value to the value of trigger time counter A, storage unit B Reg The stored period value is updated to the value of the trigger time counter B. After the subtractor calculates the phase difference, the generated phase difference is corrected by the PD correction module and stored in the PD memory. Figure 23 The schematic diagram is Figure 30 A special case of , that is, the faster clock between the local clock and the server layer clock is always selected as the reference clock, that is, the time when the local phase difference calculation is triggered is the time when either the local clock or the server layer clock counts to the expected period first.

[0323] Figure 31 The clock performance obtained by simulating a scheme in which an intermediate device performs phase difference calculation upon confirming receipt of the first phase difference information is used. The simulation parameters are set as follows: the destination device is a closed-loop setting of a phase-locked loop (PLL) at the destination end, the period of the overhead area carrying the phase difference information is 3.2768ms, the nominal clock frequency is 312.5MHz, and the frequency deviations of the 21 intermediate devices are randomly distributed within the range of ±20ppm. The simulation results of the maximum time interval error (MTIE) and time deviation (TDEV) show that the scheme provided in the embodiment of the present application can achieve good clock recovery performance and meet the G.813 clock performance template under the condition of a higher destination loop bandwidth.

[0324] Table 1 shows possible values ​​of various parameters provided by an embodiment of the present application when the first OTN frame is ODU2.

[0325] Table 1

[0326]

[0327] Specifically, in Table 1, F is the frequency of the nominal clock, fODU2 is the frequency of ODU2 (10.0372739240506 GHz), Tnominal is the period of the nominal clock, N is the number of nominal clock periods within the 3.188 ms measurement time T, and ΔN is the deviation of N at a ±20 ppm deviation. In some embodiments, when the calculation of the local phase difference is triggered by confirming receipt of the first phase difference information, T is the period of the overhead area carrying the first phase difference information (or the time interval of the overhead area carrying the first phase difference information), for example, approximately 3 ms.

[0328] Considering that each overhead area carries one byte of the phase difference information, and that at least one bit indicates whether the first information includes the second phase difference information or the fault information, there are seven bits available for recording ΔN. Therefore, the range of ΔN needs to be controlled within ±63. Therefore, F needs to be within 1000 MHz (or 1 GHz).

[0329] Considering that the G.813 clock template requires clock phase drift to be within approximately 100ns, the use of different reference clocks by different nodes may result in an error in the nominal clock period. The smaller the nominal clock period, the smaller the error. Considering that a link can have approximately ten devices (nodes), the nominal clock period needs to be less than or equal to 10ns (nanoseconds).

[0330] Based on the above two points, the nominal clock frequency F needs to be in the range of 100 MHz to 1 GHz.

[0331] If the nominal number of clock cycles within the phase difference measurement time period is assumed to be N equal to 1000000, the service layer clock frequency, the local clock frequency of each device, the nominal clock frequency, the nominal clock period, the phase difference measurement time period, and the OSU frame period can be designed to the following values.

[0332] Server layer clock frequency: fserver = fODU2 = 10.0372739240506 GHz

[0333] Local clock frequency: flocal = fODU2 / 32 = 313.6648 MHz

[0334] Nominal clock frequency: F = fODU2 / 32 = 313.6648 MHz

[0335] Nominal clock period: Tnominal = 1 / fnominal = 3.1881166ns

[0336] Nominal number of clock cycles within the phase difference measurement time period: N = F·T = 1,000,000

[0337] Phase difference measurement time period: T = N·Tnominal = 3.1881166ms

[0338] OSU frame period: 11.7533ms

[0339] The period of the overhead area carrying the phase difference information is 1 / 4 of the OSU frame period, i.e., 2.9383 ms, where period T is greater than the period of the overhead area carrying the phase difference information. When the confirmation of receipt of the first phase difference information is used as the trigger for calculating the local phase difference, T is the period of the overhead area carrying the first phase difference information (or the time interval of the overhead area carrying the first phase difference information), for example, approximately 3 ms.

[0340] Figure 26 This is a schematic block diagram of an OTN device 1500 provided in an embodiment of the present application. The device 1500 includes a receiving module 1501, which can be used to implement corresponding receiving functions. The receiving module 1501 can also be called a receiving unit.

[0341] The apparatus 1500 further includes a processing module 1502 , which can be used to implement corresponding processing functions.

[0342] The device 1500 further includes a sending module 1503 , which can be used to implement a corresponding sending function. The sending module 1503 can also be referred to as a sending unit.

[0343] Optionally, the device 1500 also includes a storage unit, which can be used to store at least one of instructions, data and other configuration parameters. The processing unit 1502 can read the content stored in the storage unit so that the device implements the actions of the relevant devices in the aforementioned method embodiments.

[0344] The apparatus 1500 can be used to execute the actions performed by the destination device, sending device, or intermediate device in each of the above method embodiments. In this case, the apparatus 1500 can be a component of the destination device, sending device, or intermediate device, the receiving module 1501 is used to execute the reception-related operations of the destination device, sending device, or intermediate device in the above method embodiments, the processing module 1502 is used to execute the processing-related operations of the destination device, sending device, or intermediate device in the above method embodiments, and the sending module 1503 is used to execute the transmission-related operations of the destination device, sending device, or intermediate device in the above method embodiments.

[0345] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0346] Figure 27 FIG1 is a structural diagram of a possible OTN device 1150, which is a destination device, a sending device, or an intermediate device. Figure 27As shown, the device 1150 includes a processor 1151, an optical transceiver 1152, and a memory 1153. Memory 1153 is optional. Device 1150 can be applied to both a sending-side device (e.g., a sending device) and a receiving-side device (e.g., the destination device described above).

[0347] When applied to a transmitting side device, the processor 1151 and the optical transceiver 1152 are used to implement Figure 4 The method is performed by the transmitting device or intermediate device shown in the figure. During implementation, each step of the processing flow can be completed by hardware integrated logic circuits or software instructions in processor 1151 to complete the method performed by the transmitting device in the above figure. Optical transceiver 1152 is used to receive, process and transmit OTN frames for transmission to the peer device (also called the receiving device).

[0348] When applied to a receiving side device, the processor 1151 and the optical transceiver 1152 are used to implement Figure 4 The method is performed by the destination device or intermediate device shown. During implementation, each step of the processing flow can be accomplished by hardware integrated logic circuits or software instructions in processor 1151 to complete the method performed by the receiving-side device described in the preceding figures. Optical transceiver 1152 is used to receive OTN frames sent by the peer device (also known as the transmitting device) and send them to processor 1151 for subsequent processing.

[0349] The memory 1153 is used to store instructions to enable the processor 1151 to perform the steps mentioned in the above figures. Alternatively, the memory 1153 can also be used to store other instructions to configure the parameters of the processor 1151 to implement corresponding functions.

[0350] It should be noted that the processor 1151 and the memory 1153 are Figure 2 In the network device hardware structure diagram, the processor 1151 and the memory 1153 may be located in a branch board or a single board that combines the branch and the line. Alternatively, the processor 1151 and the memory 1153 may include multiple processors, which are located in the branch board and the line board respectively, and the two boards cooperate to complete the above method steps.

[0351] It should be noted that Figure 27 The device can also be used to execute the method steps involved in the embodiment variations shown in the aforementioned figures, which will not be described in detail here.

[0352] Based on the above embodiments, embodiments of the present application further provide a computer-readable storage medium. This storage medium stores a software program that, when read and executed by one or more processors, can implement the methods provided in any one or more of the above embodiments. The computer-readable storage medium may include any medium capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0353] Based on the above embodiments, embodiments of the present application further provide a chip. This chip includes a processor configured to implement the functions described in any one or more of the above embodiments, such as acquiring or processing OTN frames described in the above methods. Optionally, the chip also includes a memory configured to store program instructions and data necessary for execution by the processor. This chip can be comprised of a single chip or include a chip and other discrete components.

[0354] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

[0355] It should be understood that the processor mentioned in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0356] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory and / or a non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM). For example, RAM can be used as an external cache. By way of example and not limitation, RAM may include the following forms: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0357] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0358] Those skilled in the art will appreciate that the units and steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application; such implementations should not be considered to exceed the scope of protection of this application.

[0359] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0360] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)). For example, the aforementioned available medium may include, but is not limited to, various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0361] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A clock recovery method, characterized in that: Applied to target devices, including: Receiving a first optical transport network OTN frame data stream; Obtaining a service layer clock from the first OTN frame data stream; Acquire, from the first OTN frame data stream, first phase difference information carried by a second OTN frame carried by the first OTN frame data stream, where the first phase difference information is a sum of phase differences of multiple groups of two adjacent upstream devices of the destination device through which the second OTN frame passes; generating a local phase difference according to a reference clock of the second OTN frame of the destination device and the server layer clock, wherein the reference clock of the second OTN frame of the destination device is used to recover a clock of the second OTN frame; Accumulating the local phase difference to the first phase difference information to generate second phase difference information; The reference clock of the second OTN frame of the destination device is adjusted according to the second phase difference information.

2. The method according to claim 1, characterized in that The phase difference between the multiple groups of two adjacent upstream devices is an integer number of nominal clock cycles, wherein the nominal clock cycle is less than or equal to 10ns.

3. The method according to claim 1 or 2, characterized in that The adjusting the reference clock of the second OTN frame of the destination device according to the second phase difference information includes: generating a frequency deviation according to the second phase difference information, where the frequency deviation is a product of the number of the nominal clocks corresponding to the second phase difference information and the nominal clock; A reference clock of the second OTN frame of the destination device is adjusted according to the frequency deviation.

4. The method according to claim 1, wherein The period T for generating the local phase difference is greater than the period of the overhead area of ​​the second OTN frame carrying the first phase difference information.

5. The method according to claim 4, characterized in that The period T is less than 6 ms.

6. The method according to claim 2, characterized in that The frequency F of the nominal clock ranges from 100 MHz to 1 GHz.

7. The method according to any one of claims 1 to 6, characterized in that The first phase difference information is carried in multiple overhead areas of the second OTN frame.

8. The method according to claim 7, characterized in that The number of bytes of the first phase difference information carried by each overhead area in the multiple overhead areas is 1.

9. The method according to claim 7, characterized in that Multiple bytes in the multiple overhead areas carry multiple identical first phase difference information.

10. The method according to any one of claims 1 to 9, characterized in that The first OTN frame is an optical data unit ODUk frame or an ODUflex frame.

11. A clock recovery method, characterized in that: Applied to at least one intermediate device, including: Receiving a first optical transport network OTN frame data stream; Obtaining a service layer clock from the first OTN frame data stream; Acquire, from the first OTN frame data stream, first phase difference information carried by the second OTN frame carried by the first OTN frame data stream, where the first phase difference information is a sum of phase differences between multiple groups of two adjacent upstream devices of the intermediate device through which the second OTN frame passes; generating a local phase difference based on a clock of the intermediate device and a clock of the server layer; Accumulating the local phase difference to the first phase difference information to generate second phase difference information; The second phase difference information is sent to an adjacent downstream device.

12. The method according to claim 11, characterized in that The phase difference between the multiple groups of two adjacent upstream devices is an integer number of nominal clock cycles, wherein the nominal clock cycle is less than or equal to 10ns.

13. The method according to claim 11, characterized in that The period T for generating the local phase difference is greater than the period of the overhead area of ​​the second OTN frame carrying the first phase difference information.

14. The method according to claim 13, characterized in that The period T is less than 6 ms.

15. The method according to claim 12, characterized in that The frequency F of the nominal clock ranges from 100 MHz to 1 GHz.

16. The method according to any one of claims 11 to 15, characterized in that The first phase difference information is carried in multiple overhead areas of the second OTN frame.

17. The method according to claim 16, characterized in that The number of bytes of the first phase difference information carried by each overhead area in the multiple overhead areas is 1.

18. The method according to claim 16, characterized in that The period of the overhead area carrying the first phase difference information is 1 / 4 of the second OTN frame period.

19. The method according to claim 16, wherein The multiple bytes in the multiple overhead areas carry multiple identical first phase difference information.

20. The method according to any one of claims 11 to 19, characterized in that The first OTN frame is an optical data unit (ODU) frame, and the ODU frame is an ODUk frame or an ODUflex frame.

21. An optical transmission network (OTN) device, characterized in that: include: a memory for storing instructions; A processor, wherein the processor is configured to call and execute the instructions from the memory, so that the apparatus performs the method according to any one of claims 1 to 20.

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