Channel equalization method, receiving device, storage medium and program product

Abstract

The application relates to the fields of communication technology and artificial intelligence technology, and provides a channel equalization method, a receiving device, a storage medium and a program product, wherein the method comprises the following steps: acquiring a to-be-equalized signal, and dividing the to-be-equalized signal into a plurality of subblocks, each of which comprises a plurality of symbols; regarding all the symbols and channel estimation data in each subblock as an integral element, and mapping the integral element to a high-dimensional feature space to obtain mapped subblock data; and performing context correlation processing on the mapped subblock data to obtain an equalized signal. According to the application, all the symbols in a subblock are regarded as an integral element and can be mapped to a feature space with a larger dimension for processing, which is beneficial to fully exert the computing power advantage of an AI chip and improve the utilization rate of computing power resources. According to the application, each subblock data instead of all the symbols is correlated with each other, so that the calculation amount is greatly reduced, and the efficiency of channel equalization processing is improved.

Description

Technical Field

[0001] This invention relates to the fields of communication technology and artificial intelligence technology, and in particular to a channel equalization method, receiving device, storage medium and program product. Background Technology

[0002] In wireless communication, signals inevitably encounter numerous problems such as multipath interference and energy loss when propagating through the air via electromagnetic waves, leading to signal distortion. To ensure communication quality, employing channel equalization algorithms at the receiving end to recover distorted signals is crucial. Channel equalization algorithms are mainly divided into two categories: traditional algorithms and AI-based channel equalization algorithms.

[0003] Traditional channel equalization algorithms primarily rely on channel estimation results to recover distorted signals. However, with the continuous development of communication technology and the increasing complexity of communication environments, traditional algorithms have gradually revealed their limitations in handling signal distortion under complex channel conditions. AI-based channel equalization algorithms offer a new approach to solving this problem. Among them, the Transformer, as a revolutionary deep learning architecture, has achieved great success in the field of natural language processing thanks to its core self-attention mechanism. The Transformer's sequence processing capabilities are consistent with the underlying logic of inter-carrier interference and inter-symbol interference in Orthogonal Frequency Division Multiplexing (OFDM) systems, thus researchers have begun to explore its application for channel equalization in OFDM systems.

[0004] While AI-based channel equalization algorithms have advantages, applying the Transformer architecture for channel equalization results in wasted computing resources due to the mismatch between computational granularity and mapping space dimensions. Furthermore, the computational load is enormous and latency is high, making it difficult to meet the low latency requirements of communication systems and limiting their widespread application. Summary of the Invention

[0005] This invention provides a channel equalization method, receiving device, storage medium, and program product to address the shortcomings of related technologies that utilize the Transformer architecture for channel equalization processing, such as wasted computing resources, huge computational load, and high computational latency.

[0006] This invention provides a channel equalization method, comprising:

[0007] The signal to be equalized is acquired and divided into multiple sub-blocks, each sub-block including multiple symbols;

[0008] All symbol and channel estimation data within each sub-block are treated as a whole element, and this whole element is mapped to a high-dimensional feature space to obtain the mapped sub-block data.

[0009] The mapped sub-block data is then subjected to context association processing to obtain the equalized signal.

[0010] According to a channel equalization method provided by the present invention, the step of acquiring the signal to be equalized includes:

[0011] The subcarrier direction is determined as the grouping direction;

[0012] The received signal from at least one user is divided into multiple groups according to the grouping direction to obtain multiple groups of signals for each user;

[0013] The multiple sets of signals from each user are merged in the batch dimension to obtain the signal to be balanced.

[0014] According to a channel equalization method provided by the present invention, the step of dividing the received signal of at least one user into multiple groups according to the grouping direction to obtain multiple groups of signals for each user includes:

[0015] The number of packets is determined based on the number of processing units and the number of user signals;

[0016] Based on the number of groups, the two-dimensional plane composed of subcarriers and symbols in the signal of any user is divided into multiple groups according to the grouping direction, thereby obtaining multiple groups of signals for the user.

[0017] According to a channel equalization method provided by the present invention, dividing the signal to be equalized into multiple sub-blocks includes:

[0018] The target size of the sub-block is determined based on the number of subcarriers, symbols, and channels of the signal to be equalized.

[0019] Based on the target size, the two-dimensional plane composed of subcarriers and symbols in the signal to be equalized is uniformly divided into multiple sub-blocks of the same size.

[0020] According to a channel equalization method provided by the present invention, determining the target size of a sub-block based on the number of subcarriers, the number of symbols, and the number of channels of the signal to be equalized includes:

[0021] Based on the number of subcarriers and the number of symbols of the signal to be equalized, determine the initial size set;

[0022] Based on a preset threshold range for the number of sub-blocks, the initial size set is filtered to obtain a candidate size set;

[0023] Performance evaluation is performed on each size in the candidate size set, and the target size is determined from the candidate size set based on the evaluation results.

[0024] According to a channel equalization method provided by the present invention, the step of performing context association processing on the mapped sub-block data to obtain the equalized signal includes:

[0025] The position of each sub-block data is encoded to obtain the encoded sub-block data;

[0026] The encoded sub-block data is subjected to context association processing using an attention mechanism to obtain context-associated feature representations.

[0027] The feature representation is input into a feedforward neural network for processing to obtain an equalized signal.

[0028] According to a channel equalization method provided by the present invention, mapping the overall elements to a high-dimensional feature space includes:

[0029] The dimension of the feature space is determined based on the number of symbols in each sub-block and the number of channels of the signal to be equalized.

[0030] The overall elements are mapped to a high-dimensional feature space of the specified dimension through an embedding layer.

[0031] The present invention also provides a channel equalization device, comprising:

[0032] The segmentation module is used to acquire the signal to be equalized and segment the signal to be equalized into multiple sub-blocks, each sub-block including multiple symbols;

[0033] The mapping module is used to treat all symbol and channel estimation data in each sub-block as a whole element, and map the whole element to a high-dimensional feature space to obtain the mapped sub-block data.

[0034] The processing module is used to perform context association processing on the mapped sub-block data to obtain the equalized signal.

[0035] The present invention also provides a receiving device, including a memory, an artificial intelligence chip, and a computer program stored in the memory and running on the artificial intelligence chip, wherein the artificial intelligence chip implements the channel equalization method as described above when executing the computer program.

[0036] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the channel equalization method as described above.

[0037] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements any of the channel equalization methods described above.

[0038] The channel equalization method, receiving device, storage medium, and program product provided by this invention first divide the signal to be equalized into multiple sub-blocks, then treats all symbols within each sub-block and the channel estimation data as a whole element, and maps it to a high-dimensional feature space for processing. This differs from traditional methods that only map individual symbols; this invention maps a whole element containing more symbols, thus requiring mapping to a feature space with a larger dimension. This larger-dimensional feature space can accurately match the computational granularity of AI chips, allowing AI chips to fully utilize their powerful computing capabilities when processing data, avoiding wasted computing power due to mismatched computational granularity, and effectively improving the utilization rate of computing resources. Furthermore, after obtaining the mapped sub-block data, this invention performs contextual association processing on the sub-block data, rather than associating all symbols with each other. This greatly reduces the computational load, enabling the entire channel equalization process to be completed in a shorter time, effectively meeting the low-latency requirements of communication systems and ensuring the real-time performance and efficiency of communication. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram illustrating channel equalization processing using the Transformer architecture in related technologies;

[0041] Figure 2 This is a flowchart illustrating the channel equalization method provided by the present invention;

[0042] Figure 3 This is a schematic diagram of channel equalization processing using the Transformer architecture provided by the present invention;

[0043] Figure 4 This is a schematic diagram of the channel equalization device provided by the present invention;

[0044] Figure 5 This is a schematic diagram of the receiving device provided by the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0046] In the ongoing evolution of wireless communication, the global competition for 6G technology has entered a critical stage. Building high-performance, energy-efficient, and highly flexible computing infrastructure has become a strategic high ground supporting future network development. 6G networks address complex scenarios such as full-area coverage, the Internet of Things, and digital twins, requiring breakthroughs in computing power to achieve their goals. This places significant demands on the computing power, energy efficiency, and multi-tasking adaptability of hardware platforms.

[0047] Against this backdrop, building a heterogeneous hardware platform centered on a general-purpose computing on graphics processing units (GPGPU) and integrating a central processing unit (CPU) and a field-programmable gate array (FPGA) demonstrates key strategic value. By leveraging the core advantages of GPGPUs in high-performance parallel computing and artificial intelligence acceleration, combined with the general-purpose processing capabilities of CPUs and the hardware programmability of FPGAs, this platform can effectively address the comprehensive challenges brought by 6G in areas such as ultra-high frequency communication, intelligent network management and control, and massive data processing and integration.

[0048] Artificial Intelligence Radio Access Network (AI-RAN) is an inevitable technological evolution direction driving the generational leap of 6G networks and meeting the needs of future intelligent societies. The fundamental breakthrough of the AI-RAN architecture lies in deeply embedding artificial intelligence capabilities into the core functional units of the network access layer, realizing a historic shift in network function paradigm from primarily "connectivity-enabled" to possessing native "intelligent endogenous" characteristics. By constructing a closed-loop intelligent system with comprehensive perception, real-time decision-making, and precise execution, it achieves visibility, analysis, controllability, and optimization of network status, bringing entirely new development ideas and technical architectures to 6G communication networks.

[0049] In the field of communications, OFDM technology has always been a key technology. It divides high-speed data streams into multiple mutually orthogonal narrowband subcarriers for parallel transmission, effectively combating multipath fading and improving spectrum utilization. This makes it the physical layer foundation technology for modern wireless systems such as Wi-Fi, 4G, 5G, and even 6G mobile communications and digital broadcasting. However, OFDM systems face many challenges in practical operation. Inter-carrier interference (ICI) and inter-symbol interference (ISI) in OFDM symbols are essentially sequence correlation problems, which poses a challenge to channel equalization techniques. When the channel is interfered with, it affects different subcarriers, leading to ICI; interference may also occur at different times, resulting in ISI. Therefore, channel equalization algorithms are needed at the receiver to recover distorted signals and ensure communication quality. It should be understood that subcarriers are the frequency-dimensional resources in an OFDM system, with each subcarrier carrying a portion of data; symbols are the time-dimensional resources in an OFDM system.

[0050] Channel equalization algorithms are mainly divided into two categories: traditional algorithms and AI-based channel equalization algorithms. Traditional channel equalization algorithms recover distorted signals based on channel estimation results. They construct corresponding models by measuring and analyzing channel characteristics, and then use these models to compensate and correct the received distorted signals. However, with the development of communication technology and the increasing complexity of communication environments, traditional algorithms are gradually becoming inadequate in handling signal distortion problems under complex channel conditions.

[0051] AI-based channel equalization algorithms offer a new approach to solving this problem. These algorithms learn a nonlinear mapping function from the distorted signal to the original signal by training on a large amount of distorted data, thereby achieving signal recovery. In AI-RAN architecture, the deep integration of artificial intelligence technology has brought about a revolutionary change to communication systems. Relying on advanced algorithms such as machine learning and deep learning, communication systems can achieve real-time, high-precision prediction and modeling of complex time-varying channel characteristics, enabling AI-based channel equalization algorithms to better adapt to complex and ever-changing communication environments.

[0052] As a revolutionary deep learning architecture, Transformer has achieved tremendous success in natural language processing thanks to its core self-attention mechanism, laying the foundation for today's large language models. The self-attention mechanism allows each element in a sequence (such as a word) to simultaneously attend to all other elements in the sequence and dynamically calculate weights based on their correlations, thus accurately capturing long-range dependencies. This powerful sequence processing capability has led to explorations into its application in the field of communications. Inter-carrier interference and inter-symbol interference in OFDM symbols are essentially sequence correlation problems, which aligns with the underlying logic of Transformer's processing of language sequences. Therefore, researchers have begun to consider applying the Transformer architecture to OFDM systems for channel equalization, hoping to leverage its powerful sequence processing capabilities to better address interference problems in OFDM systems and improve channel equalization performance.

[0053] Figure 1 This is a schematic diagram illustrating channel equalization processing using the Transformer architecture in related technologies, such as... Figure 1 As shown, during the communication process between the terminal and the base station, the base station acts as the signal receiver and can process signals from two user terminals simultaneously (i.e., the number of users is 2). Each user's signal is divided into 1664 subcarriers for parallel transmission (i.e., the number of subcarriers is 1664), and 27 symbols are transmitted on each subcarrier (i.e., the number of symbols is 27). Simultaneously, the channel equalization module utilizes four channels (i.e., the number of channels is 4) to complete the signal transmission and processing tasks.

[0054] When the receiver performs channel equalization using the Transformer architecture, it directly uses the number of users (2) as the batch size and multiplies the number of subcarriers (1664) and the number of symbols (27) to map the sequence length dimension of the Transformer architecture. At this time, the sequence length dimension is 1664×27. For the construction of input data, since the channel equalization module uses 4 channels, each channel will receive signal-related information. Therefore, each symbol on each channel and the corresponding channel estimation data are used together as an element (i.e., token). Here, channel estimation data refers to the data obtained by the receiver in order to accurately recover the original signal sent by the transmitter by estimating the channel characteristics, such as channel gain and phase offset. That is to say, a token integrates the original information of the symbol under a specific channel and the channel characteristic information experienced by the symbol during transmission. Next, these tokens containing multi-channel information are mapped to a 32-dimensional word vector space (also called the feature space, with a feature dimension of 32) through an embedding layer. Through this mapping, the symbol and channel information carried by each token are transformed into a 32-dimensional vector, which can be more effectively understood and processed by the Transformer architecture. After obtaining the vector of each token, an attention mechanism is used to contextually associate the vectors of all tokens.

[0055] In the aforementioned processing methods, since the information of a single symbol is only the real and imaginary coordinates of the complex plane, it is relatively simple and usually mapped to a small feature space (e.g., 32 dimensions). However, in large language models, to better understand a word, it is usually mapped to a feature space of 512 dimensions or even larger. Yet, AI chips typically have a fixed, large computational granularity (e.g., 64, 128, etc.) when calculating matrix multiplication. This leads to a significant waste of computational power in the computation of attention mechanisms and feedforward neural networks. For example, assuming the AI ​​chip's computational granularity is 64, but the mapped feature space dimension is 32, this means that half of the computational resources are wasted, greatly reducing the efficiency of computational resource utilization.

[0056] Furthermore, when using the attention mechanism to contextualize the vectors of all tokens, the computational cost of the attention mechanism is proportional to the square of the sequence length (the number of tokens in the sequence). Each token vector corresponds to a symbol, meaning the computational cost of the attention mechanism is proportional to the square of the total number of symbols. Due to the excessively large number of symbols processed (1664 × 27), exceeding 40,000, the computational cost of the attention mechanism is exceptionally high, essentially accounting for 99.9% of the model's total computation. This enormous computational burden makes the Transformer model difficult to apply in practical communication systems, failing to meet the low latency requirements of such systems. Especially in the 6G AI-RAN architecture, where millisecond-level real-time perception and joint modeling, as well as rapid decision generation and adaptive reconfiguration and execution, are required, the computational latency problem of traditional methods becomes even more pronounced, severely limiting their further promotion and application in the field of channel equalization.

[0057] Although channel equalization algorithms based on the Transformer architecture have great theoretical potential, the waste of computing power and computational latency are major obstacles to their development in existing communication systems. There is an urgent need to find effective solutions to overcome these bottlenecks and promote the further development of channel equalization technology.

[0058] To address the shortcomings of the aforementioned channel equalization techniques, this invention provides a channel equalization method. This method divides the two-dimensional plane composed of the frequency and time domains in the OFDM system into fixed-size resource blocks (also called sub-blocks) before inputting them into a standard Transformer encoder. By processing multiple symbols within a sub-block as a single element, compared to traditional methods that process individual symbols, although the complexity increases, it requires mapping to a larger-dimensional feature space, for example, increasing the feature space from 32 dimensions to 512 dimensions. Adding this dimension leverages the computing power of the tensor core in AI chips, meeting the high-performance computing requirements of 6G networks.

[0059] Moreover, this invention correlates sub-block data rather than all symbols, reducing the sequence length dimension of the attention mechanism computation by two orders of magnitude, significantly decreasing the model's computational load. This improvement aligns with the goals of high efficiency, intelligence, and low latency in the 6G AI-RAN architecture, effectively addressing the computational waste and latency issues of traditional channel equalization techniques while meeting the demands of complex 6G communication scenarios, thus providing a superior solution for channel equalization in 6G communication networks. It should be noted that the channel equalization method provided by this invention is not only applicable to 6G communication networks but also to 4G, 5G, and other communication network environments. The technical solution provided by this invention will be described in detail below.

[0060] Figure 2 This is a flowchart illustrating the channel equalization method provided by the present invention, as follows: Figure 2 As shown, the method includes:

[0061] Step 210: Obtain the signal to be equalized and divide the signal to be equalized into multiple sub-blocks, each sub-block including multiple symbols.

[0062] Specifically, the signal to be equalized refers to the signal received by the receiver during communication that has been distorted by channel interference (such as path loss, multipath effect, noise, etc.). It needs to be processed by channel equalization to eliminate the influence of the channel and recover the original transmitted signal.

[0063] When the antenna array at the receiving end (such as the receiving equipment on the base station side) receives a wireless signal from the transmitting end (such as a user terminal), the signal is an analog signal and is affected by the wireless channel, resulting in distortion due to amplitude attenuation, phase shift, multipath effects, etc., and may also be mixed with noise and interference. Therefore, a series of preprocessing operations can be performed on this signal, such as amplification, analog-to-digital conversion, synchronization, and frequency domain conversion, to obtain a two-dimensional planar signal composed of all symbols in the frequency and time domains, i.e., the signal to be equalized. At this point, the signal is still affected by the channel, exhibiting amplitude and phase distortion, and further channel equalization processing is required to recover the original signal.

[0064] After obtaining the signal to be equalized, it can be uniformly divided into multiple sub-blocks of the same size according to a fixed dimension. Here, a sub-block refers to a small region obtained by uniformly dividing the signal to be equalized (i.e., a two-dimensional planar signal composed of all symbols in the frequency and time domains) according to a certain size, which usually includes a certain number of consecutive symbols. It should be understood that in an OFDM system, each symbol in a sub-block can be a modulation symbol on a subcarrier.

[0065] Step 220: Treat all symbols and channel estimation data within each sub-block as a whole element, and map the whole element to a high-dimensional feature space to obtain the mapped sub-block data.

[0066] Specifically, for each sub-block obtained from the segmentation, all symbols and channel estimation data within that sub-block can be treated as a single element (i.e., a token) to map this token to a high-dimensional feature space for processing. Here, a single element (i.e., a token) refers to a data unit formed by combining all symbols within the sub-block and the corresponding channel estimation data. For example, in a sub-block, multiple symbols are transmitted on subcarriers, and there is also channel estimation data for the sub-block's channel. Combining these symbols and channel estimation data constitutes a single element, i.e., a token. It should be understood that in a wireless communication system, channel estimation data refers to the data obtained by the receiver in estimating channel characteristics, such as channel gain and phase offset, to accurately recover the original signal transmitted by the transmitter.

[0067] Understandably, after dividing the data into sub-blocks, all symbol data within a sub-block and the corresponding channel characteristic data obtained through channel estimation can be extracted and combined to form a token. For example, if a sub-block contains 48 symbols, combining these 48 symbols with the corresponding channel estimation data will yield a token.

[0068] After obtaining the token corresponding to each sub-block, each token can be mapped to a high-dimensional feature space through an embedding layer. Here, the embedding layer acts as a transformer, converting the input token into a vector representation in the high-dimensional feature space. In traditional channel equalization methods, individual symbols are directly mapped to the feature space. Since the information of a single symbol is relatively simple, it is usually mapped to a feature space with a smaller dimension (such as 32 dimensions).

[0069] In this embodiment of the invention, all symbols and channel estimation data within each sub-block are treated as a single token. Due to the increased complexity of the token, it needs to be mapped to a larger-dimensional word vector space (also known as the feature space). For example, the dimension of the feature space is increased from 32 to 512. After inputting the token containing all symbols and channel estimation data within the sub-block into the embedding layer, the embedding layer outputs a 512-dimensional vector. This vector is the representation of the token in the high-dimensional feature space, i.e., the mapped sub-block data.

[0070] Here, the mapped sub-block data refers to the high-dimensional vector data obtained after the overall element (token) is mapped to a high-dimensional feature space through the embedding layer. This high-dimensional vector data retains the feature information of the symbols and channel estimation data within the sub-block and exists in a form more suitable for subsequent model processing. For example, the token corresponding to a sub-block, after being mapped by the embedding layer, yields a 512-dimensional vector; this vector is the mapped sub-block data, which can then be input into modules such as the attention mechanism of the Transformer architecture for further processing.

[0071] In this embodiment of the invention, by taking all symbol and channel estimation data in each sub-block as a token and mapping it to a high-dimensional feature space, it is possible not only to better capture the complex features and relationships of the data and provide richer information representation for subsequent model processing, but also to increase the dimension of the feature space from the original 32 dimensions to 512 dimensions, which is beneficial to make full use of the computing power resources of AI chips.

[0072] Step 230: Perform context association processing on the mapped sub-block data to obtain the equalized signal.

[0073] Specifically, for each sub-block corresponding to a token, after mapping to obtain the vector of each token (i.e., sub-block data), the attention mechanism in the Transformer architecture can be used to perform contextual correlation processing on each sub-block data. Here, contextual correlation processing refers to utilizing the contextual information between data (i.e., the sequential relationships or correlation features of data in dimensions such as time domain and frequency domain) to mine the inherent connections between different sub-block data, thereby more accurately understanding the overall characteristics of the signal and its influence by the channel. In communication signal processing, the changes of the signal at different subcarriers and symbol positions are interrelated; contextual correlation processing can capture these correlations, helping the model to better recover the original signal.

[0074] Specifically, the context association processing of the mapped sub-block data can be achieved through the following steps: First, position encoding is performed on each sub-block data to preserve its relative position information in the frequency and time domains. Since the order and position of the signal on different subcarriers and symbols are crucial for understanding signal characteristics, position encoding provides the model with clues to this positional order. Then, an attention mechanism is used to perform context association on the position-encoded sub-block data. This mechanism allows the model to automatically focus on other sub-block data most relevant to the currently processed sub-block data, determining the degree of association between them by calculating the attention weights between different sub-block data. Finally, the context-associated feature representation is input into a feedforward neural network, such as an MLP (Multilayer Perceptron), for processing. The feedforward neural network can further extract and transform the feature representation through multiple nonlinear transformations to more accurately recover the original signal. After MLP processing, the output is the equalized signal. Here, the equalized signal refers to the signal obtained after channel equalization, which eliminates or minimizes the effects of inter-carrier and inter-symbol interference, making it closer to the original signal transmitted by the transmitter.

[0075] It is understandable that, due to the continuity and correlation of signals during transmission, there are often inherent connections between adjacent sub-blocks. This embodiment of the invention, by performing contextual association processing on the mapped sub-block data, can fully utilize this signal continuity characteristic. While ensuring processing effectiveness, it greatly reduces the amount of associated data that needs to be processed, thereby significantly reducing computational load and improving the efficiency of channel equalization processing.

[0076] The method provided in this invention first divides the signal to be equalized into multiple sub-blocks, then treats all symbols and channel estimation data within each sub-block as a whole element, and maps it to a high-dimensional feature space for processing. This differs from traditional methods that only map individual symbols; this invention maps a whole element containing more symbols, thus requiring mapping to a feature space with a larger dimension. This larger-dimensional feature space can precisely match the computational granularity of AI chips, allowing them to fully leverage their powerful computing capabilities when processing data, avoiding wasted computing power due to mismatched computational granularity, and effectively improving the utilization rate of computing resources. Furthermore, after obtaining the mapped sub-block data, this invention performs contextual association processing on the sub-block data, rather than associating all symbols with each other. This significantly reduces the computational load, enabling the entire channel equalization process to be completed in a shorter time, effectively meeting the low-latency requirements of communication systems and ensuring real-time and efficient communication.

[0077] Based on any of the above embodiments, step 210, obtaining the signal to be equalized, includes:

[0078] Step 211: Determine the subcarrier direction as the grouping direction.

[0079] It should be noted that after receiving the wireless signal from the transmitter (such as a signal sent by a user terminal, also known as a user signal), the receiver performs a series of preprocessing operations on the signal to obtain a two-dimensional planar signal composed of all symbols in the frequency and time domains. In OFDM systems, to efficiently utilize spectrum resources and resist multipath interference, the entire communication band is divided into multiple mutually orthogonal subcarriers, each of which can independently carry a portion of the modulated signal. The signal is transmitted discretely in time, in units of symbols. Therefore, combining the frequency domain subcarriers and the time domain symbols forms a two-dimensional planar signal, where the frequency domain dimension corresponds to the subcarrier direction and the time domain dimension corresponds to the symbol direction.

[0080] Considering that AI chips typically have multiple processing units, two-dimensional planar signals can be grouped to better utilize their parallel computing capabilities. Here, the subcarrier direction can be used as the grouping direction because the computing power and resource allocation of processing units are often adapted to frequency domain processing. By selecting the subcarrier direction as the grouping direction, each processing unit can be responsible for processing signals on different subcarrier groups, thereby achieving parallel computing and improving processing efficiency.

[0081] Step 212: Divide the received signal from at least one user into multiple groups according to the grouping direction to obtain multiple groups of signals for each user.

[0082] Specifically, for each received user signal, after preprocessing, it can be segmented according to a determined grouping direction (i.e., subcarrier direction) to obtain multiple signal groups corresponding to each user (or user terminal). Here, the multiple signal groups for each user refer to the multiple signal groups obtained by segmenting each user's preprocessed signal (i.e., two-dimensional plane signal) according to the subcarrier direction. For example, in a communication system, multiple users communicate simultaneously, and each user's signal is allocated to multiple subcarriers for transmission. After these subcarriers are divided into several groups according to certain rules, each user corresponds to multiple signal groups, and each signal group contains a certain number of subcarriers and their symbol information.

[0083] Furthermore, step 212 specifically includes:

[0084] Step 2121: Determine the number of packets based on the number of processing units and the number of user signals;

[0085] Step 2122: Based on the number of groups, divide the two-dimensional plane composed of subcarriers and symbols in the signal of any user into multiple groups according to the grouping direction to obtain multiple groups of signals for the user.

[0086] Specifically, before grouping each user signal (i.e., the two-dimensional planar signal obtained after preprocessing), it is necessary to determine not only the grouping direction but also the number of groups. Here, the number of groups can be calculated based on the number of processing units and the number of user signals. It should be understood that a processing unit is the basic unit on a chip that performs computational tasks, and the number of processing units refers to the number of cores or computing units in the AI ​​chip capable of performing computational operations in parallel. The number of user signals refers to the number of user signals that the AI ​​chip needs to process simultaneously.

[0087] Understandably, the number of processing units determines the number of signal groups that an AI chip can process simultaneously. To fully utilize the chip's parallel processing capabilities, the number of groups should match the number of processing units to ensure that each processing unit is allocated a group of signals for processing, avoiding idle processing units. The number of groups can typically be determined based on the ratio of the number of processing units to the number of user signals, for example, number of groups = number of processing units / number of user signals (rounded up), or adjusted according to the specific circumstances.

[0088] For example, assuming there are 16 processing units on the AI ​​chip and 2 user signals that need to be processed simultaneously, the number of groups is calculated according to the ratio of the number of processing units to the number of user signals: 16 / 2 = 8 groups. After the two user signals are grouped, there are 16 groups of signals, which exactly matches the number of processing units. Each processing unit can be responsible for processing one group of signals, thereby making full use of the chip's parallel processing capabilities.

[0089] After determining the grouping direction and number of groups, the two-dimensional plane composed of subcarriers and symbols in each user signal can be divided according to the subcarrier direction based on the number of groups. The specific steps are as follows: First, calculate the number of subcarriers in each group based on the number of groups and the total number of subcarriers. For example, if a user signal has a total of 1664 subcarriers and 8 groups, then each group contains 1664 / 8 = 208 subcarriers. Then, along the subcarrier direction, the two-dimensional plane signal of the user signal is divided according to the calculated number of subcarriers in each group. Specifically, starting from the first subcarrier, 208 subcarriers and their corresponding symbol information are selected sequentially as a group, until all subcarriers are assigned to their corresponding groups. For example, the first group contains subcarriers 1-208 and their corresponding 27 symbols, the second group contains subcarriers 209-416 and their corresponding 27 symbols, and so on, until the last group.

[0090] Through the above steps, the user signal can be divided into multiple groups according to the subcarrier direction, providing suitable input data for subsequent signal processing.

[0091] Step 213: Merge the multiple sets of signals from each user in the batch dimension to obtain the signal to be balanced.

[0092] It's important to note that when an AI chip needs to process signals from multiple users simultaneously, after obtaining multiple sets of signals from each user, these signals can be merged at the batch level to obtain the signal to be equalized. This allows the entire batch to be processed using the same signal processing methods and parameters. For example, AI chips typically have multiple processing units. By combining signals from different users into a batch, multiple samples within that batch can be processed in parallel. This not only fully leverages the parallel computing advantages of the hardware but also simplifies the processing flow and improves efficiency.

[0093] Specifically, batch dimension is a commonly used concept in machine learning and signal processing. It refers to combining multiple samples (i.e., signal groups from different users) together to form a batch for processing. In the batch dimension, each sample has the same structure and dimensions, facilitating uniform computation and processing. For example, suppose an AI chip needs to process signals from two users simultaneously. Each user's signal can be represented as (1, 1664 × 27, 4), where 1 represents the batch size (only one user signal), 1664 represents the number of subcarriers, 27 represents the number of symbols, and 4 represents the number of channels. Each user signal is divided into 8 groups according to the subcarrier direction, and each group contains 208 subcarriers. Therefore, the grouped user signal can be represented as (8, 208 × 27, 4), where the batch size becomes 8, meaning each user's signal is divided into 8 groups. When merging in the batch dimension, the 8 groups of signals from the first user and the 8 groups of signals from the second user are combined to form a single batch. Therefore, the merged signal to be equalized can be represented as (16,208×27,4), with a batch size of 16. This means that there are a total of 16 groups of signals in this batch, and these 16 groups of signals can be input as a whole into the subsequent signal processing module for parallel processing.

[0094] Based on any of the above embodiments, step 210, dividing the signal to be equalized into multiple sub-blocks, includes:

[0095] Step 214: Determine the target size of the sub-block based on the number of subcarriers, symbols, and channels of the signal to be equalized.

[0096] Specifically, before segmenting the signal to be equalized, the target size of the sub-blocks needs to be determined first, and then the two-dimensional plane in the signal to be equalized is segmented according to the target size. Here, the target size of the sub-blocks can be determined based on information such as the number of subcarriers, the number of symbols, and the number of channels of the signal to be equalized. For example, in the example above where the signal to be equalized is (16, 208 × 27, 4), the number of subcarriers is 208, the number of symbols is 27, and the number of channels is 4.

[0097] Furthermore, step 214 specifically includes:

[0098] Step 2141: Determine the initial size set based on the number of subcarriers and the number of symbols of the signal to be equalized;

[0099] Step 2142: Based on a preset threshold range for the number of sub-blocks, the initial size set is filtered to obtain a candidate size set;

[0100] Step 2143: Perform performance evaluation based on each size in the candidate size set, and determine the target size from the candidate size set based on the evaluation results.

[0101] Specifically, when determining the target size of a sub-block, the possible sub-block sizes can be initially determined based on the number of subcarriers and symbols of the signal to be equalized, through different combinations, thus obtaining an initial size set. Here, the initial size set refers to the set of possible sub-block sizes for dividing the signal to be equalized, initially determined based on the number of subcarriers and symbols. For example, if the number of subcarriers is 208 and the number of symbols is 27, different combinations of the number of subcarrier segments and symbol segments can be tried. For instance, dividing the subcarriers into 13 segments with 16 subcarriers per segment and the symbols into 9 segments with 3 symbols per segment results in a sub-block size of 16×3; or dividing the subcarriers into 26 segments with 8 subcarriers per segment and the symbols into 3 segments with 9 symbols per segment results in a sub-block size of 8×9, etc. These possible sizes are combined to form the initial size set.

[0102] After determining the initial size set, the sizes of each sub-block within this set can be further filtered. First, considering that the computational cost of the attention mechanism is proportional to the square of the sequence length when processing sequences using the Transformer architecture, the sequence length needs to be minimized to reduce computational cost. In this embodiment, the attention mechanism is used to correlate the data of each sub-block, meaning that the computational cost of the attention mechanism is proportional to the square of the number of sub-blocks. Therefore, after segmenting the signal to be equalized, the number of sub-blocks is mapped to the sequence length dimension. To minimize the sequence length, when filtering the sizes of each sub-block in the initial size set, larger sub-block sizes can be selected. This results in fewer sub-blocks after segmenting the two-dimensional plane composed of subcarriers and symbols in the signal to be equalized according to this size. Fewer sub-blocks mean less computation, as the computational cost is proportional to the square of the sequence length (i.e., the number of sub-blocks). At the same time, the larger the size of the sub-block, the more symbols it contains and the more complex the features. Therefore, it can be mapped to a larger-dimensional word vector space (i.e., feature space) for processing, which can better utilize the computing power of AI chips.

[0103] However, the size of the sub-blocks cannot be too large, because AI chips typically have a fixed computational granularity (e.g., 64) in the sequence length when processing sequence data. If the sequence length (i.e., the number of sub-blocks) is too small, it will lead to a waste of computing resources. Therefore, when using the Transformer architecture for channel equalization, it is necessary to ensure that the size of the signal to be equalized mapped to in the sequence length dimension (i.e., the number of sub-blocks) is appropriate. It cannot be too large, nor can it be smaller than the chip's computational granularity in the sequence length dimension. Based on this, a suitable threshold range can be pre-set for the number of sub-blocks. The size of each sub-block in the initial size set can then be filtered according to this threshold range to ensure that the number of sub-blocks obtained after dividing according to these sizes meets the pre-set threshold range.

[0104] After filtering the initial size set, a candidate size set can be obtained. Here, the candidate size set is the set of sub-block sizes obtained by filtering the initial size set according to a preset threshold range for the number of sub-blocks. These sizes are more suitable for the chip's processing capabilities and the model's requirements, improving processing efficiency and model performance. After obtaining the candidate size set, for each size in this set, the impact of sub-block segmentation according to that size on the communication system's performance can be further evaluated in the communication system. This is because if the sub-block size is too large, it may make the granularity of the correlation analysis too coarse, resulting in poor noise reduction performance of the model.

[0105] When conducting performance evaluation, simulation tools (such as Senna) can be used to build a communication system simulation environment to simulate actual wireless channel conditions and signal transmission processes. In the simulation environment, the signal to be equalized is segmented and processed using each size from the candidate size set, and the processed signal quality metrics, such as bit error rate (BER), signal-to-noise ratio (SNR), and signal distortion, are recorded. The signal quality metrics under different sizes are compared and analyzed to evaluate the impact of each size on the communication system performance. For example, a lower BER indicates better signal recovery quality, and the system performance under that size is superior. Finally, based on the evaluation results of each size, the size that performs best in the performance evaluation is selected as the final target size. For example, if a certain size has the lowest BER and the lowest signal distortion, it means that using that size to segment and process the signal to be equalized can achieve the best performance for the communication system, and this size is then determined as the target size.

[0106] It is understandable that the target size refers to the optimal sub-block size determined from the candidate size set based on the evaluation results of the communication system performance. Using this size to divide the signal to be equalized and perform subsequent processing can enable the communication system to achieve optimal performance, such as the lowest bit error rate and the best signal recovery quality, while meeting the chip processing capabilities and model requirements.

[0107] Step 215: Based on the target size, the two-dimensional plane composed of subcarriers and symbols in the signal to be equalized is uniformly divided into multiple sub-blocks of the same size.

[0108] Specifically, the target size determines the exact size of the sub-block in both the subcarrier and symbol directions. For example, a target size of 16×3 means that each sub-block contains 16 subcarriers (i.e., a size of 16 in the subcarrier direction) and 3 symbols (i.e., a size of 3 in the symbol direction). Therefore, once the target size is determined, the two-dimensional plane composed of subcarriers and symbols in the signal to be equalized can be uniformly divided into multiple sub-blocks of the same size according to this size.

[0109] Specifically, when segmenting according to the target size, the process begins with the first subcarrier in the two-dimensional plane of the signal to be equalized. Subcarriers are then selected sequentially according to their dimensions in the target size's subcarrier direction. For example, assuming the signal to be equalized is represented as (16, 208 × 27, 4), with 208 subcarriers and a target size subcarrier direction of 16, subcarriers 1-16 are selected first, subcarriers 17-32 are selected second, and so on, until all subcarriers are selected, resulting in 208 / 16 = 13 subcarrier segments. Similarly, starting with the first symbol in the two-dimensional plane of the signal to be equalized, symbols are selected sequentially according to their dimensions in the target size's symbol direction, resulting in 27 / 3 = 9 symbol segments.

[0110] After the above subcarrier direction and symbol direction division, each segmented subcarrier segment and symbol segment combination forms a sub-block, and finally the two-dimensional plane of the signal to be equalized is evenly divided into 13×9=117 sub-blocks of the same size.

[0111] Based on any of the above embodiments, step 220, mapping the overall elements to a high-dimensional feature space, includes:

[0112] Step 221: Determine the dimension of the feature space based on the number of symbols in each sub-block and the number of channels of the signal to be equalized;

[0113] Step 222: Map the overall elements to a high-dimensional feature space of the specified dimension through an embedding layer.

[0114] Specifically, after dividing the signal to be equalized into multiple sub-blocks, for each sub-block, all symbols within that sub-block and their corresponding channel estimation data can be treated as a single element (i.e., a token) and mapped to a high-dimensional feature space to obtain a corresponding vector representation. Here, when mapping each token to the high-dimensional feature space, the appropriate dimension of the feature space can be selected based on the number of symbols within each sub-block and the number of channels in the signal to be equalized. For example, assuming each sub-block has a size of 16×3, this means each sub-block contains 48 symbols. Since the number of channels in the signal to be equalized is 4, the information in the channel estimation data will also be more abundant. This means that the complexity of the token increases, requiring mapping to a larger-dimensional feature space. Therefore, the dimension of the feature space can be increased from the original 32 dimensions to 512 dimensions to better capture the complex features and relationships of the data.

[0115] Once the appropriate dimensionality is determined, each token can be mapped to a high-dimensional feature space of the predetermined dimensionality through an embedding layer. Here, a high-dimensional feature space refers to a space with dimensions significantly higher than the original data dimensions. In this space, data can be represented using higher-dimensional vectors, better capturing the complex features and relationships of the data. For example, mapping a token with a lower dimensionality to a 512-dimensional space creates a high-dimensional feature space, which provides richer information representation for subsequent model processing.

[0116] Based on any of the above embodiments, step 230 specifically includes:

[0117] Step 231: Perform position encoding on each sub-block data to obtain encoded sub-block data;

[0118] Step 232: Use an attention mechanism to perform context association processing on the encoded sub-block data to obtain the context-associated feature representation;

[0119] Step 233: Input the feature representation into the feedforward neural network for processing to obtain the equalized signal.

[0120] Specifically, before using the attention mechanism to perform context association on the data of each sub-block, positional encoding can be performed on the data of each sub-block to preserve the relative positional information of each sub-block in the frequency and time domains. Because the order and position of the signal on different subcarriers and symbols are important for understanding signal characteristics, positional encoding can provide the model with clues to this positional order. For example, in the example above, after cutting the two-dimensional plane of the signal to be equalized into 117 sub-blocks, a combination of sine and cosine functions can be used to generate a position-related encoded vector for each sub-block. This vector is then added to the high-dimensional vector mapped to the corresponding token, ensuring that the sub-block data carries positional information when input into subsequent modules.

[0121] After location encoding is completed, these vectors carrying location information can be input into the encoder of a standard Transformer, where an attention mechanism is used for context association processing. Specifically, for each encoded sub-block vector (i.e., each sub-block data), attention scores are obtained by performing operations such as dot products with other sub-block vectors, and then normalization is performed to obtain attention weights. Then, a weighted sum of all sub-block vectors based on these weights is performed to obtain the context-associated feature representation.

[0122] The context-associated feature representation is input into a feedforward neural network (such as a Multi-Level Processing Network) for processing. The feedforward neural network can further extract and transform the feature representation through multiple layers of nonlinear transformations to more accurately recover the original signal. For example, after the Transformer encoder output (i.e., the context-associated feature representation output by the attention calculation) is obtained through an attention mechanism, it is input into an MLP. The MLP calculates and transforms the input features through its internal neurons and activation functions, such as through multiple fully connected layers and activation functions (such as ReLU), gradually adjusting the distribution and expression of the features. After processing by the MLP, the output is the equalized signal. This signal, after considering factors such as the signal's context information and channel effects, is as close as possible to the original transmitter signal.

[0123] Based on any of the above embodiments, this invention provides a channel equalization method based on the Transformer architecture. This method can be applied to intelligent receiving devices equipped with AI chips, such as GPGPU, GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), etc. These AI chips can utilize the Transformer architecture to perform channel equalization processing on signals, thereby achieving the recovery of distorted signals.

[0124] Figure 3 This is a schematic diagram of channel equalization processing using the Transformer architecture provided by the present invention, as shown below. Figure 3 As shown, taking the example of a receiving device simultaneously processing two signals from user terminals (i.e., two users), assuming each user's signal is divided into 1664 subcarriers for parallel transmission (i.e., 1664 subcarriers), and each subcarrier transmits 27 symbols (i.e., 27 symbols). Simultaneously, the channel equalization module utilizes four channels (i.e., four channels) to complete the signal transmission and processing tasks. In this scenario, the signal that the receiving device needs to process can be represented as (2, 1664 × 27, 4), where the batch size is 2, indicating that two user signals need to be processed simultaneously. In traditional processing methods, the number of subcarriers and the number of symbols (i.e., 1664 × 27) are directly multiplied and mapped to the sequence length dimension. Due to the excessively large sequence length, the computational load becomes exceptionally large.

[0125] To address the issues of poor model performance caused by excessively long sequence lengths and small feature space dimensions in traditional processing methods, this invention first divides the two-dimensional plane composed of subcarriers and symbols in the signal into 8 groups according to the subcarrier direction, and combines this with the number of users to obtain the batch dimension (i.e., 2×8). Then, the two-dimensional plane is divided into sub-blocks, each with a size of 16×3, resulting in 13×9=117 sub-blocks. The 48 symbols and channel estimation data within each sub-block are treated as a token. Due to increased complexity (i.e., the token contains richer information), it needs to be mapped to a larger-dimensional word vector space (i.e., feature space), thus increasing the dimension from 32 to 512 (i.e., 512 feature dimensions) for understanding. The 117 sub-blocks in the two-dimensional space are then context-associated using an attention mechanism. By dividing the two-dimensional plane, the sequence length is reduced from over 40,000 to 117, a decrease of two orders of magnitude, significantly reducing the computational load of the model.

[0126] By optimizing the model architecture using the methods described above, the computational cost of the Attention component was reduced by more than 1000 times, and the overall computational cost of the model was reduced by approximately 700 times. Simulations using the Senna platform validated the model's performance (accuracy) in a communication system. Although the computational cost was significantly reduced, the bit error rate remained essentially unchanged, meeting the requirements of the communication system.

[0127] The method provided in this invention processes multiple symbols within a sub-block as a single element, increasing complexity compared to the original single symbol approach. This requires mapping to a larger feature space, and adding this dimension leverages the computational power of the tensor core in AI chips. Furthermore, associating sub-blocks rather than all symbols reduces the sequence length dimension by two orders of magnitude, significantly decreasing the model's computational load. Moreover, testing the optimized model on a simulation platform shows that while computational load is greatly reduced, communication performance remains essentially unchanged, meeting the requirements of the communication system.

[0128] The channel equalization device provided by the present invention is described below. The channel equalization device described below can be referred to in correspondence with the channel equalization method described above.

[0129] Based on any of the above embodiments Figure 4 This is a schematic diagram of the channel equalization device provided by the present invention, as shown below. Figure 4 As shown, the device includes:

[0130] The segmentation module 410 is used to acquire the signal to be equalized and segment the signal to be equalized into multiple sub-blocks, each sub-block including multiple symbols;

[0131] The mapping module 420 is used to treat all symbol and channel estimation data in each sub-block as a whole element, and map the whole element to a high-dimensional feature space to obtain the mapped sub-block data.

[0132] The processing module 430 is used to perform context association processing on the mapped sub-block data to obtain the equalized signal.

[0133] The apparatus provided in this invention first divides the signal to be equalized into multiple sub-blocks, then treats all symbols and channel estimation data within each sub-block as a whole element, and maps it to a high-dimensional feature space for processing. This differs from traditional methods that only map individual symbols; this invention maps a whole element containing more symbols, thus requiring mapping to a feature space with a larger dimension. This larger-dimensional feature space can precisely match the computational granularity of the AI ​​chip, allowing the AI ​​chip to fully utilize its powerful computing capabilities when processing data, avoiding wasted computing power due to mismatched computational granularity, and effectively improving the utilization rate of computing resources. Furthermore, after obtaining the mapped sub-block data, this invention performs contextual association processing on the sub-block data, rather than associating all symbols with each other. This significantly reduces the computational load, enabling the entire channel equalization process to be completed in a shorter time, effectively meeting the low-latency requirements of communication systems and ensuring the real-time performance and efficiency of communication.

[0134] Based on any of the above embodiments, the segmentation module 410 includes an acquisition unit, the acquisition unit comprising:

[0135] The direction determination subunit is used to determine the subcarrier direction as the grouping direction;

[0136] A grouping subunit is used to divide the received signal from at least one user into multiple groups according to the grouping direction, thereby obtaining multiple groups of signals for each user.

[0137] The merging subunit is used to merge multiple sets of signals from each user in the batch dimension to obtain the signal to be equalized.

[0138] Based on any of the above embodiments, the grouping subunit is specifically used for:

[0139] The number of packets is determined based on the number of processing units and the number of user signals;

[0140] Based on the number of groups, the two-dimensional plane composed of subcarriers and symbols in the signal of any user is divided into multiple groups according to the grouping direction, thereby obtaining multiple groups of signals for the user.

[0141] Based on any of the above embodiments, the segmentation module 410 includes a segmentation unit, the segmentation unit comprising:

[0142] The size determination subunit is used to determine the target size of the sub-block based on the number of subcarriers, the number of symbols, and the number of channels of the signal to be equalized;

[0143] The segmentation subunit is used to uniformly divide the two-dimensional plane composed of subcarriers and symbols in the signal to be equalized into multiple sub-blocks of the same size based on the target size.

[0144] Based on any of the above embodiments, the size determination subunit is specifically used for:

[0145] Based on the number of subcarriers and the number of symbols of the signal to be equalized, determine the initial size set;

[0146] Based on a preset threshold range for the number of sub-blocks, the initial size set is filtered to obtain a candidate size set;

[0147] Performance evaluation is performed on each size in the candidate size set, and the target size is determined from the candidate size set based on the evaluation results.

[0148] Based on any of the above embodiments, the processing module 430 is specifically used for:

[0149] The position of each sub-block data is encoded to obtain the encoded sub-block data;

[0150] The encoded sub-block data is subjected to context association processing using an attention mechanism to obtain context-associated feature representations.

[0151] The feature representation is input into a feedforward neural network for processing to obtain an equalized signal.

[0152] Based on any of the above embodiments, the mapping module 420 is specifically used for:

[0153] The dimension of the feature space is determined based on the number of symbols in each sub-block and the number of channels of the signal to be equalized.

[0154] The overall elements are mapped to a high-dimensional feature space of the specified dimension through an embedding layer.

[0155] Figure 5 An example is a schematic diagram of the structure of a receiving device, such as... Figure 5 As shown, the receiving device may include: an artificial intelligence chip 510, a communication interface 520, a memory 530, and a communication bus 540. The artificial intelligence chip 510, communication interface 520, and memory 530 communicate with each other via the communication bus 540. The artificial intelligence chip 510 can call logic instructions in the memory 530 to execute a channel equalization method. This method includes: acquiring the signal to be equalized and dividing the signal into multiple sub-blocks, each sub-block including multiple symbols; treating all symbols and channel estimation data within each sub-block as a whole element and mapping the whole element to a high-dimensional feature space to obtain mapped sub-block data; and performing context association processing on the mapped sub-block data to obtain the equalized signal.

[0156] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0157] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the channel equalization method provided by the above methods. The method includes: acquiring a signal to be equalized and dividing the signal to be equalized into multiple sub-blocks, each sub-block including multiple symbols; treating all symbols and channel estimation data in each sub-block as a whole element and mapping the whole element to a high-dimensional feature space to obtain mapped sub-block data; and performing context association processing on the mapped sub-block data to obtain the equalized signal.

[0158] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the channel equalization method provided by the above methods. The method includes: acquiring a signal to be equalized and dividing the signal to be equalized into multiple sub-blocks, each sub-block including multiple symbols; treating all symbols and channel estimation data within each sub-block as a whole element and mapping the whole element to a high-dimensional feature space to obtain mapped sub-block data; and performing context association processing on the mapped sub-block data to obtain the equalized signal.

[0159] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0160] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A channel equalization method, characterized in that, include: The signal to be equalized is acquired and divided into multiple sub-blocks, each sub-block including multiple symbols; All symbol and channel estimation data within each sub-block are treated as a whole element, and this whole element is mapped to a high-dimensional feature space to obtain the mapped sub-block data. Context association processing is performed on the mapped sub-block data to obtain the equalized signal; The step of performing context association processing on the mapped sub-block data to obtain the equalized signal includes: The position of each sub-block data is encoded to obtain the encoded sub-block data; The encoded sub-block data is subjected to context association processing using an attention mechanism to obtain context-associated feature representations. The feature representation is input into a feedforward neural network for processing to obtain an equalized signal.

2. The channel equalization method according to claim 1, characterized in that, The acquisition of the signal to be equalized includes: The subcarrier direction is determined as the grouping direction; The received signal from at least one user is divided into multiple groups according to the grouping direction to obtain multiple groups of signals for each user; The multiple sets of signals from each user are merged in the batch dimension to obtain the signal to be balanced.

3. The channel equalization method according to claim 2, characterized in that, The step of dividing the received signal from at least one user into multiple groups according to the grouping direction to obtain multiple groups of signals for each user includes: The number of packets is determined based on the number of processing units and the number of user signals; Based on the number of groups, the two-dimensional plane composed of subcarriers and symbols in the signal of any user is divided into multiple groups according to the grouping direction, thereby obtaining multiple groups of signals for the user.

4. The channel equalization method according to claim 1, characterized in that, The step of dividing the signal to be equalized into multiple sub-blocks includes: The target size of the sub-block is determined based on the number of subcarriers, symbols, and channels of the signal to be equalized. Based on the target size, the two-dimensional plane composed of subcarriers and symbols in the signal to be equalized is uniformly divided into multiple sub-blocks of the same size.

5. The channel equalization method according to claim 4, characterized in that, Determining the target size of the sub-block based on the number of subcarriers, symbols, and channels of the signal to be equalized includes: Based on the number of subcarriers and the number of symbols of the signal to be equalized, determine the initial size set; Based on a preset threshold range for the number of sub-blocks, the initial size set is filtered to obtain a candidate size set; Performance evaluation is performed on each size in the candidate size set, and the target size is determined from the candidate size set based on the evaluation results.

6. The channel equalization method according to any one of claims 1 to 5, characterized in that, The step of mapping the overall elements to a high-dimensional feature space includes: The dimension of the feature space is determined based on the number of symbols in each sub-block and the number of channels of the signal to be equalized. The overall elements are mapped to a high-dimensional feature space of the specified dimension through an embedding layer.

7. A receiving device, comprising a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip, characterized in that, When the artificial intelligence chip executes the computer program, it implements the channel equalization method as described in any one of claims 1 to 6.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the channel equalization method as described in any one of claims 1 to 6.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the channel equalization method as described in any one of claims 1 to 6.

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