Read-write verification method and device, electronic equipment and computer readable storage medium
By performing read and write signal verification and shadow mapping table update independently of the timing relationship in the UVM network chip verification test, the coupling problem of table entry read and write operations is solved, and the versatility and reusability of verification are improved.
Patent Information
- Application Number
- CN202510702381.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2025-09-12
AI Technical Summary
In UVM-based network chip verification testing, the correctness check of table entry read and write operations is restricted by timing relationships, which increases the coupling between the module to be tested and the test model, reducing the versatility and reusability of the verification.
By obtaining the read and write signals of the module to be tested and verifying them according to the preset operations of the test model, the shadow mapping table is updated after the write signal verification is successful to keep it consistent with the read and write operation table, independent of the timing relationship.
It reduces the coupling between the module to be tested and the test model, improves the versatility and reusability of verification, and reduces the verification workload.
Smart Images
Figure CN120639660A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of testing technology, and in particular to a read-write verification method, device, electronic device, and computer-readable storage medium. Background Art
[0002] In the network chip verification test based on UVM (Universal Verification Methodology), the correctness check problem of table entry read and write operations is often encountered.
[0003] In related technologies, when verifying the read and write operations of the table items of the module to be tested, it is often necessary to perform a timing comparison between the module to be tested and the test model, and trigger the test model to work through the trigger signal in the module to be tested, so that the read and write operations of the test model are consistent with the module to be tested, thereby allowing the verification to proceed smoothly.
[0004] However, this approach is limited by timing relationships, which increases the coupling between the module to be tested and the test model, thereby reducing the versatility and reusability of verification and increasing the verification workload. Summary of the Invention
[0005] In view of this, the purpose of this application is to provide a read-write verification method, device, electronic device and computer-readable storage medium to get rid of the limitations of timing relationships, reduce the coupling between the module to be tested and the test model, thereby reducing the verification workload and improving the versatility and reusability of verification.
[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:
[0007] In a first aspect, the present application provides a read-write verification method, which is applied to an electronic device, wherein the electronic device is provided with a module to be tested and a test model, the module to be tested is provided with a read-write operation table, and the test model stores a shadow mapping table corresponding to the read-write operation table, the method comprising:
[0008] Obtaining a read / write signal of the module under test for the read / write operation table;
[0009] If the read / write signal is a read signal, performing a read operation verification on the read signal according to a preset read operation in the test model;
[0010] If the read-write signal is a write signal, the write operation is verified on the write signal according to the preset write operation in the test model, and if the write signal verification is successful, the shadow mapping table is updated according to the write signal to make the shadow mapping table consistent with the read-write operation table.
[0011] In an optional embodiment, the preset read operation includes a preset read address, and the read signal includes a read address and read data; and performing read operation verification on the read signal according to the preset read operation in the test model includes:
[0012] Performing address verification on the read address according to the preset read address;
[0013] If the read address verification passes, inputting the read data as first read data corresponding to the test model into the test model for read data processing, and acquiring second read data corresponding to the test model from the shadow mapping table according to the read address;
[0014] Data verification is performed on the read data according to a read data processing result corresponding to the first read data and the second read data.
[0015] In an optional embodiment, the preset write operation includes a preset write address and preset write data, the write signal includes a write address and write data, and the performing write operation verification on the write signal according to the preset write operation in the test model includes:
[0016] Performing write address verification on the write address according to the preset write address;
[0017] The write data is verified according to the preset write data.
[0018] In an optional embodiment, the method further comprises:
[0019] Determining whether there is a read-write conflict in the module to be tested according to the read-write signal;
[0020] In the case where there is a read-write conflict in the module to be tested, storing a write signal in the read-write signal as a pre-stored write signal in a preset write queue;
[0021] The performing a read operation verification on the read signal according to a preset read operation in the test model includes:
[0022] Acquire a pre-stored write signal stored in the write queue, and perform read-write conflict processing on the pre-stored write signal;
[0023] A read operation verification is performed on the read signal according to the pre-stored write signal after the read-write conflict is processed, and if the read operation verification is successful, the shadow mapping table is updated according to the pre-stored write signal after the read-write conflict is processed.
[0024] In a second aspect, the present application provides a read-write verification device, which is applied to an electronic device, wherein the electronic device is provided with a module to be tested and a test model, the module to be tested is provided with a read-write operation table, and the test model stores a shadow mapping table corresponding to the read-write operation table, the device comprising:
[0025] An acquisition module, configured to acquire a read / write signal of the module to be tested for the read / write operation table;
[0026] a verification module, configured to, if the read / write signal is a read signal, perform a read operation verification on the read signal according to a preset read operation in the test model;
[0027] The verification module is also used to perform write operation verification on the write signal according to the preset write operation in the test model if the read-write signal is a write signal, and to update the shadow mapping table according to the write signal if the write signal verification is successful, so that the shadow mapping table is consistent with the read-write operation table.
[0028] In an optional embodiment, the preset read operation includes a preset read address, and the read signal includes a read address and read data; the verification module is further used to perform read address verification on the read address based on the preset read address; if the read address verification passes, the read data is input into the test model as the first read data corresponding to the test model for read data processing, and the second read data corresponding to the test model is obtained from the shadow mapping table according to the read address; and the read data is verified based on the read data processing result corresponding to the first read data and the second read data.
[0029] In an optional embodiment, the preset write operation includes a preset write address and preset write data, the write signal includes a write address and write data, and the verification module is further used to perform write address verification on the write address according to the preset write address; and perform write data verification on the write data according to the preset write data.
[0030] In an optional embodiment, the verification module is further used to determine whether there is a read-write conflict in the module to be tested based on the read-write signal; if there is a read-write conflict in the module to be tested, the write signal in the read-write signal is stored as a pre-stored write signal in a preset write queue; the pre-stored write signal stored in the write queue is obtained, and the pre-stored write signal is processed for the read-write conflict; the read operation is verified on the read signal based on the pre-stored write signal after the read-write conflict processing, and if the read operation verification is successful, the shadow mapping table is updated based on the pre-stored write signal after the read-write conflict processing.
[0031] In a third aspect, the present application provides an electronic device comprising a processor and a memory, wherein the memory stores a computer program that can be executed by the processor, and the processor can execute the computer program to implement the method described in any one of the aforementioned embodiments.
[0032] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any one of the aforementioned embodiments.
[0033] The read / write verification method, device, electronic device, and computer-readable storage medium provided in the embodiments of the present application are such that, when the read / write signal is a write signal, the write signal is verified according to a preset write operation in the test model. If the write signal verification is successful, the shadow mapping table is updated according to the write signal. Since the verification operation and the table update action are independent of each other, the timing constraints can be eliminated, and the coupling between the module to be tested and the test model can be reduced. In addition, since the shadow mapping table is updated according to the write signal only when the write signal verification is successful, the shadow mapping table can be guaranteed to be consistent with the read / write operation table in the module to be tested. On this basis, the read operation verification of the read signal of the module to be tested is directly performed according to the preset read operation in the test model. There is no need to pay attention to the timing issue, thus eliminating the timing constraints and reducing the coupling between the module to be tested and the test model, thereby reducing the verification workload and improving the versatility and reusability of the verification.
[0034] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.
[0036] Figure 1 A schematic diagram of a write operation verification process in the related art is shown;
[0037] Figure 2 Another schematic diagram of a write operation verification process in the related art is shown;
[0038] Figure 3 A block diagram of an electronic device provided in an embodiment of the present application is shown;
[0039] Figure 4A flowchart of a read-write verification method provided by an embodiment of the present application is shown;
[0040] Figure 5 An example diagram of read operation verification is shown;
[0041] Figure 6 An example diagram of write operation verification is shown;
[0042] Figure 7 A functional module diagram of a read-write verification device provided in an embodiment of the present application is shown.
[0043] Icon: 100 - memory; 110 - processor; 120 - communication module; 200 - acquisition module; 210 - verification module. DETAILED DESCRIPTION
[0044] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.
[0045] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present application.
[0046] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.
[0047] In the network chip verification test based on UVM (Universal Verification Methodology), the correctness check problem of table entry read and write operations is often encountered.
[0048] Currently, when verifying the read and write operations of the module to be tested, it is necessary to first ensure that the write data is accurate. On this basis, the read operation is assumed to be correct to ensure the correct verification. In this process, the write operation order in the module to be tested and the test model needs to be consistent.
[0049] See Figure 1 , which is a schematic diagram of the write operation verification process in the related art. The device under test (DUT) performs write operations 1 to 3 on the read and write operation table in a serial order. The test model (Model) is consistent with the module under test and also performs write operations 1 to 3 on the shadow mapping table (Shadow) in a serial order. In this case, the scoreboard can compare the write address and write data in the DUT with the write address and write data in the Model, for example, comparing write operation 1 in the DUT with write operation 1 in the Model.
[0050] However, in the actual testing process, since the modules to be tested are generally written in hardware circuit languages such as Verilog, their execution is mostly parallel, for example, the reading and writing of table entries are executed in parallel at the same time, while the UVM-based test model is generally written in hardware design and verification languages such as SystemVerilog, and its execution process is serial. Therefore, sequence errors often occur during verification.
[0051] See Figure 2 , is another schematic diagram of the write operation verification process in the related art. The module under test (DUT) can perform write operations 1 to 3 on the read-write operation table in parallel, but the test model (Model) can only perform write operations 1 to 3 on the shadow mapping table in a serial order. The two cannot maintain a consistent order. This will also cause the shadow mapping table to be inconsistent with the read-write operation table, resulting in a verification error. For example, when the Scoreboard obtains write operation 3 in the DUT for verification, the corresponding write operation in the Model may be write operation 1. Obviously, the read-write operation table in the DUT has been updated by write operation 3, but the shadow mapping table in the Model has not been updated by write operation 3. At this time, a sequence error will occur, resulting in a verification error.
[0052] To solve this problem, the relevant technology can perform timing comparison between the test model and the module to be tested, and trigger the test model to work through the trigger signal in the module to be tested, so that the read and write operations of the test model are consistent with the module to be tested, thereby allowing the verification to proceed smoothly.
[0053] However, although this method solves the consistency problem during table entry reading and writing verification, it is subject to the limitations of timing relationships, which increases the coupling between the module to be tested and the test model. Sometimes it is even necessary to change the code structure of the test model to adapt it to the timing of the module to be tested, thereby reducing the versatility and reusability of the verification and increasing the verification workload.
[0054] Based on this, embodiments of the present application provide a read-write verification method, device, electronic device, and computer-readable storage medium to solve the above problems.
[0055] Figure 3 For a block diagram of an electronic device provided in an embodiment of the present application, see Figure 3 The electronic device includes a memory 100, a processor 110, and a communication module 120. The memory 100, processor 110, and communication module 120 are electrically connected to each other directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines.
[0056] The memory 100 is used to store computer programs or data that can be executed by the processor. The memory 100 can be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.
[0057] The processor 110 is used to read / write data or computer programs stored in the memory and execute the computer program to implement the read-write verification method provided in the embodiment of the present application.
[0058] The communication module 120 is used to establish a communication connection between the electronic device and other communication terminals through a network, and to send and receive data through the network.
[0059] It should be understood that Figure 3 The structure shown is only a schematic diagram of the structure of the electronic device. The electronic device may also include Figure 3 More or fewer components than shown, or with Figure 1 Different configurations shown. Figure 3 Each component shown in the figure can be implemented by hardware, software or a combination thereof.
[0060] Optionally, the electronic device may be provided with a module to be tested and a test model, the module to be tested is provided with a read-write operation table, and the test model stores a shadow mapping table corresponding to the read-write operation table.
[0061] In this embodiment, the module to be tested may be a chip to be tested, and the test model refers to a software verification platform built based on UVM, which is used to simulate and verify the behavior of the DUT.
[0062] It is understandable that in order to facilitate read and write verification of the module to be tested, the test model needs to maintain a shadow mapping table corresponding to the read and write operation table.
[0063] Next, the above Figure 3 The electronic device in the embodiment is the execution subject, and the read-write verification method provided in the embodiment of the present application is exemplarily introduced in combination with the flow chart.
[0064] Specifically, Figure 4 A flow chart of the read-write verification method provided in this application embodiment is shown in FIG. Figure 4 , the method comprising:
[0065] Step S20: obtaining the read and write signals of the module to be tested with respect to the read and write operation table.
[0066] Step S21 : If the read / write signal is a read signal, a read operation verification is performed on the read signal according to a preset read operation in the test model.
[0067] Optionally, the preset read operation is a read operation pre-edited in the test model, and the read operation should be consistent with the read operation of the module to be tested.
[0068] It can be understood that when the shadow mapping table in the test model is consistent with the read and write operation table in the module to be tested, even if the read signal obtained at this time includes multiple parallel read signals, for example, three parallel read signals, these three parallel read signals can be verified according to the three preset read signals that currently need to be executed continuously in the test model, without paying attention to the timing issues between the test model and the module to be tested.
[0069] Step S22: If the read / write signal is a write signal, the write operation is verified on the write signal according to the preset write operation in the test model, and if the write signal verification is successful, the shadow mapping table is updated according to the write signal to keep the shadow mapping table consistent with the read / write operation table.
[0070] Optionally, the preset write operation is a write operation pre-edited in the test model, and the write operation should be consistent with the write operation of the module to be tested.
[0071] Optionally, in order to get rid of the limitations of timing relationships as much as possible and ensure the independence between the module to be tested and the test model, the write operation process in the test model can be made different from the write operation in the module to be tested. Instead, the write operation of the test model is first verified according to the preset write operation. If the write operation verification is successful, the shadow mapping table is updated with the write operation, so that the data maintenance process of the shadow mapping table and the write operation verification process are independent of each other. At the same time, it can also ensure that the shadow mapping table in the test model is consistent with the read and write operation table in the module to be tested.
[0072] For example, if the write signal is a plurality of parallel write signals, the electronic device can also perform verification based on the multiple write signals that need to be executed continuously at present, and if the verification passes, update the shadow mapping table as a whole based on the write data results of the multiple write signals.
[0073] The read / write verification method provided in the embodiment of the present application performs an operation verification on the write signal according to a preset write operation in the test model when the read / write signal is a write signal. If the write signal verification is successful, the shadow mapping table is updated according to the write signal. Since the verification operation and the table update action are independent of each other, the timing constraints can be eliminated, and the coupling between the module under test and the test model can be reduced. In addition, since the shadow mapping table is updated according to the write signal only when the write signal verification is successful, the shadow mapping table can be kept consistent with the read / write operation table in the module under test. On this basis, the read operation verification of the read signal of the module under test is directly performed according to the preset read operation in the test model, and there is no need to pay attention to the timing issue, thus eliminating the timing constraints and reducing the coupling between the module under test and the test model, thereby reducing the verification workload and improving the versatility and reusability of the verification.
[0074] Optionally, considering that the shadow mapping table is consistent with the read and write operation table in the module to be tested, if the read address verification of the module to be tested is successful, then its corresponding read data should also be verified successfully. Therefore, the read address comparison can be performed first when performing read operation verification.
[0075] Specifically, the preset read operation may include a read address, and the read signal includes the read address and read data.
[0076] In this embodiment, the electronic device can perform address verification on the read address according to a preset read address. If the read address verification passes, the read data is input into the test model as the first read data corresponding to the test model for read data processing, and the second read data corresponding to the test model is obtained from the shadow mapping table according to the read address. The read data is then verified based on the read data processing result corresponding to the first read data and the second read data.
[0077] Optionally, the electronic device can compare the preset read address of the test model with the read address of the module to be tested. If the two are consistent, it can be determined that the read address verification is successful. Otherwise, if the two are inconsistent, it can be determined that the read address verification has failed, and data verification is not required at this time.
[0078] It is understandable that if the read address verification fails, the specific error location may be located in the module to be tested, such as an execution logic error in the module to be tested.
[0079] Optionally, if the read address verification passes, it can be considered that the read data of the module to be tested should be consistent with the read data of the test model. Therefore, the read data of the module to be tested can be directly used as the read data of the test model for other processing, such as using the read data for data analysis, comparing the read data with the read data of the test model, etc.
[0080] It can be understood that if the read data of the module to be tested is correct, the read data processing result should also be correct. If there is an error in the read data processing result, it means that the read data of the module to be tested is wrong and the data verification fails. At this time, the specific error location can be located in the read and write operation table item corresponding to the module to be tested.
[0081] Optionally, the electronic device may also obtain second read data from the shadow mapping table of the test model according to the read address of the module to be tested for inspection, such as comparing the second read data with the read data of the module to be tested.
[0082] It can be understood that if the read data of the module to be tested is correct and the shadow mapping table is also correct, then the second read data should be consistent with the read data of the module to be tested. If the second read data verification fails, it means that the read data of the module to be tested is wrong or the shadow mapping table is wrong.
[0083] It can be understood that the read-write verification method provided in the embodiment of the present application can also locate the error position in real time during the read operation verification process so that the user can follow up and handle it.
[0084] In one example, Figure 5 For a read operation verification example diagram, see Figure 5 , Scoreboard can obtain the read address in the DUT and the read address in the Model for address verification. If the address verification passes, the read data in the DUT is input into the Model as the first read data in the Model for data processing, and the second read data is obtained from the shadow mapping table (Shadow) in the Model according to the read address in the DUT, thereby performing data verification.
[0085] Optionally, when performing write operation verification, the write data and the write address need to be verified separately.
[0086] Specifically, the preset write operation may include a preset write address and preset write data, and the write signal includes the write address and the write data.
[0087] In this embodiment, the electronic device may perform write address verification on the write address according to the preset write address, and perform write data verification on the write data according to the preset write data.
[0088] Optionally, the electronic device compares and verifies the write address of the module to be tested according to the preset write address of the test model, and compares and verifies the write data of the module to be tested according to the preset write data of the test model.
[0089] It is understandable that if the write address and write data verification fails, the specific error location can be located, which may be in the execution logic of the module under test. Therefore, the error location can also be located in real time during the write operation, which is convenient for users to follow up.
[0090] In one example, Figure 6 For a write operation verification example diagram, see Figure 6 , Scoreboard can obtain the write address and write data in DUT respectively, compare them with the write address and write data in Model, and if the verification passes, update the shadow mapping table (Shadow) in Model according to the write address and write data in DUT.
[0091] Optionally, considering that there may be a situation where multiple parallel writes are performed on the same address, in order to ensure that the shadow mapping table is consistent with the read-write operation table, the multiple parallel write data can be stored in a queue first. After the write operations are verified, based on the multiple parallel write operations, it is determined whether to merge and update the data at the corresponding address in the shadow mapping table based on multiple write data, or update it after corresponding processing, etc.
[0092] Optionally, considering that read-write conflicts may occur during multi-path parallel reading and writing, it is also necessary to handle the read-write conflicts.
[0093] Optionally, based on the logic of read-write verification, it is often necessary to obtain the latest data in the test model for verification when performing read operation verification. Therefore, in this embodiment, the read-write conflict of reading first and writing later is mainly handled.
[0094] In this embodiment, the read-write conflict may include a situation where a read or write operation is performed on the same address at the same time, or a situation where a write operation is performed on the address within a read operation hysteresis time range.
[0095] In this embodiment, the electronic device can determine whether there is a read-write conflict in the module to be tested based on the read-write signal, and if there is a read-write conflict in the module to be tested, the write signal in the read-write signal is stored as a pre-stored write signal in a preset write queue. When performing a read operation verification, the pre-stored write signal stored in the write queue can be obtained, and the pre-stored write signal can be processed for the read-write conflict. The read operation is verified on the read signal based on the pre-stored write signal after the read-write conflict processing. If the read operation verification is successful, the shadow mapping table is updated based on the pre-stored write signal after the read-write conflict processing.
[0096] Optionally, the write queue may be FIFO (First In First Out).
[0097] Optionally, the write queue can be set in the model to be tested, which may include two verification operations, one of which is used to perform write operation verification, and the other is used to perform read operation verification. When the write operation verification detects a read-write conflict, the shadow mapping table may not be updated to prevent errors, and the write signal may be pre-stored in the write queue.
[0098] The other read operation verification also performs read-write conflict detection. If a read-write conflict is detected, in order to obtain the latest data, a pre-stored write signal can be obtained from the write queue.
[0099] Optionally, considering that a read-write conflict has occurred, the obtained pre-stored write signal can be processed according to the read-write conflict situation to obtain a complete write signal, and then the processed pre-stored write signal is sent to the read signal of the module to be tested for read operation verification.
[0100] It can be understood that if the read operation verification is successful, it can indirectly indicate that there is no problem with the pre-stored write signal. Therefore, the shadow mapping table can be updated according to the pre-stored write signal after processing to ensure that after the read-write conflict, the shadow mapping table in the test model can also be consistent with the read-write operation table of the module to be tested.
[0101] In order to execute the corresponding steps in the above embodiments and various possible methods, a read-write verification device is provided below. Figure 7 , Figure 7 This is a functional block diagram of a read / write verification device provided in an embodiment of the present application. It should be noted that the basic principles and technical effects of the read / write verification device provided in this embodiment are the same as those in the aforementioned embodiments. For the sake of brevity, any details not mentioned in this embodiment are referenced to the corresponding content in the aforementioned embodiments. The read / write verification device includes an acquisition module 200 and a verification module 210.
[0102] The acquisition module 200 is used to acquire the read and write signals of the module under test with respect to the read and write operation table.
[0103] It is understandable that the acquisition module 200 can also be used to execute the above step S20.
[0104] The verification module 210 is configured to perform a read operation verification on the read signal according to a preset read operation in the test model if the read / write signal is a read signal.
[0105] It is understandable that the verification module 210 can also be used to execute the above step S21.
[0106] The verification module 210 is also used to verify the write operation of the write signal according to the preset write operation in the test model if the read-write signal is a write signal, and if the write signal verification is successful, update the shadow mapping table according to the write signal to make the shadow mapping table consistent with the read-write operation table.
[0107] It is understandable that the verification module 210 can also be used to execute the above step S22.
[0108] Optionally, the preset read operation includes a preset read address, and the read signal includes a read address and read data; the verification module 210 is also used to perform read address verification on the read address according to the preset read address; if the read address verification passes, the read data is input into the test model as the first read data corresponding to the test model for read data processing, and the second read data corresponding to the test model is obtained from the shadow mapping table according to the read address; and the read data is verified based on the read data processing result corresponding to the first read data and the second read data.
[0109] Optionally, the preset write operation includes a preset write address and preset write data, the write signal includes the write address and write data, and the verification module 210 is further used to perform write address verification on the write address according to the preset write address; and perform write data verification on the write data according to the preset write data.
[0110] Optionally, the verification module 210 is also used to determine whether there is a read-write conflict in the module to be tested based on the read-write signal; if there is a read-write conflict in the module to be tested, the write signal in the read-write signal is stored as a pre-stored write signal in a preset write queue; the pre-stored write signal stored in the write queue is obtained, and the pre-stored write signal is processed for the read-write conflict; the read operation is verified on the read signal based on the pre-stored write signal after the read-write conflict processing, and if the read operation verification is successful, the shadow mapping table is updated based on the pre-stored write signal after the read-write conflict processing.
[0111] The read / write verification device provided in an embodiment of the present application performs an operation verification on the write signal according to a preset write operation in the test model when the read / write signal is a write signal. If the write signal verification is successful, the shadow mapping table is updated according to the write signal. Since the verification operation and the table update action are independent of each other, the timing constraints can be eliminated, reducing the coupling between the module under test and the test model. In addition, since the shadow mapping table is updated according to the write signal only when the write signal verification is successful, the shadow mapping table can be kept consistent with the read / write operation table in the module under test. On this basis, the read operation verification of the read signal of the module under test is directly performed according to the preset read operation in the test model, without having to pay attention to the timing issue, eliminating the timing constraints, reducing the coupling between the module under test and the test model, thereby reducing the verification workload and improving the versatility and reusability of the verification.
[0112] Optionally, the above modules can be stored in the form of software or firmware. Figure 3 The memory shown in FIG. 1 or the operating system (OS) of the electronic device may be fixed therein and may be Figure 3 Meanwhile, the data and program codes required to execute the above modules may be stored in the memory.
[0113] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the read-write verification method provided in the embodiment of the present application can be implemented.
[0114] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a portion of code, and the module, program segment, or a portion of code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.
[0115] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0116] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0117] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.
Claims
1. A read-write verification method, characterized in that: Applied to an electronic device, the electronic device is provided with a module to be tested and a test model, the module to be tested is provided with a read-write operation table, and the test model stores a shadow mapping table corresponding to the read-write operation table, the method comprising: Obtaining a read / write signal of the module under test for the read / write operation table; If the read / write signal is a read signal, performing a read operation verification on the read signal according to a preset read operation in the test model; If the read-write signal is a write signal, the write operation is verified on the write signal according to the preset write operation in the test model, and if the write signal verification is successful, the shadow mapping table is updated according to the write signal to make the shadow mapping table consistent with the read-write operation table.
2. The method according to claim 1, characterized in that The preset read operation includes a preset read address, and the read signal includes a read address and read data; and performing read operation verification on the read signal according to the preset read operation in the test model includes: Performing address verification on the read address according to the preset read address; If the read address verification passes, inputting the read data as first read data corresponding to the test model into the test model for read data processing, and acquiring second read data corresponding to the test model from the shadow mapping table according to the read address; Data verification is performed on the read data according to a read data processing result corresponding to the first read data and the second read data.
3. The method according to claim 1, characterized in that The preset write operation includes a preset write address and preset write data, the write signal includes a write address and write data, and performing write operation verification on the write signal according to the preset write operation in the test model includes: Performing write address verification on the write address according to the preset write address; The write data is verified according to the preset write data.
4. The method according to claim 1, wherein The method further comprises: Determining whether there is a read-write conflict in the module to be tested according to the read-write signal; In the case where there is a read-write conflict in the module to be tested, storing a write signal in the read-write signal as a pre-stored write signal in a preset write queue; The performing a read operation verification on the read signal according to a preset read operation in the test model includes: Acquire a pre-stored write signal stored in the write queue, and perform read-write conflict processing on the pre-stored write signal; A read operation verification is performed on the read signal according to the pre-stored write signal after the read-write conflict is processed, and if the read operation verification is successful, the shadow mapping table is updated according to the pre-stored write signal after the read-write conflict is processed.
5. A read-write verification device, characterized in that: Applied to an electronic device, the electronic device is provided with a module to be tested and a test model, the module to be tested is provided with a read-write operation table, the test model stores a shadow mapping table corresponding to the read-write operation table, and the device includes: An acquisition module, configured to acquire a read / write signal of the module to be tested for the read / write operation table; a verification module, configured to, if the read / write signal is a read signal, perform a read operation verification on the read signal according to a preset read operation in the test model; The verification module is also used to perform write operation verification on the write signal according to the preset write operation in the test model if the read-write signal is a write signal, and to update the shadow mapping table according to the write signal if the write signal verification is successful, so that the shadow mapping table is consistent with the read-write operation table.
6. The device according to claim 5, characterized in that The preset read operation includes a preset read address, and the read signal includes a read address and read data; the verification module is further configured to perform read address verification on the read address according to the preset read address; If the read address verification passes, the read data is input into the test model as the first read data corresponding to the test model for read data processing, and the second read data corresponding to the test model is obtained from the shadow mapping table according to the read address; and the read data is read verified according to the read data processing result corresponding to the first read data and the second read data.
7. The device according to claim 5, characterized in that The preset write operation includes a preset write address and preset write data, the write signal includes a write address and write data, and the verification module is further used to perform write address verification on the write address according to the preset write address; and perform write data verification on the write data according to the preset write data.
8. The device according to claim 5, characterized in that The verification module is further configured to determine whether a read-write conflict exists in the module to be tested based on the read-write signal; if a read-write conflict exists in the module to be tested, store the write signal in the read-write signal as a pre-stored write signal in a preset write queue; Acquire a pre-stored write signal stored in the write queue, and perform read-write conflict processing on the pre-stored write signal; A read operation verification is performed on the read signal according to the pre-stored write signal after the read-write conflict is processed, and if the read operation verification is successful, the shadow mapping table is updated according to the pre-stored write signal after the read-write conflict is processed.
9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program that can be executed by the processor, and the processor can execute the computer program to implement the method according to any one of claims 1 to 4.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.