Vehicle-mounted Ethernet PHY chip interconnection and intercommunication test system
Through the test system based on FPGA and host computer program, the complexity and inefficiency of in-vehicle Ethernet PHY chip testing are solved, and an efficient, flexible and scalable test method is implemented, which is suitable for multi-protocol and multi-channel in-vehicle Ethernet PHY chip testing.
Patent Information
- Application Number
- CN202510863707.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-09-12
AI Technical Summary
Existing automotive Ethernet PHY chip testing methods have numerous test items, complex environments, low efficiency, and lack of a managed test case library and host software platform, making them unable to meet the testing requirements of multiple protocols and multiple channels.
The test system based on FPGA and host computer program is adopted, including FPGA module, host computer software module and test case library module, which realizes the analysis, data processing and test signal generation of various communication protocols, supports automated testing, and provides rich preset test cases and custom functions.
It achieves efficient, flexible and scalable testing with a wide coverage, and can accurately test in-vehicle Ethernet PHY chips in a simulated real vehicle environment, improving test efficiency and accuracy and reducing costs.
Smart Images
Figure CN120639675A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor chip testing, and in particular relates to an interconnection and interoperability (IOP) testing system for an on-board Ethernet PHY chip based on FPGA and a host computer program. Background Art
[0002] Amidst the technological revolution in intelligent connected vehicles, automotive Ethernet, with its high-speed data transmission, millisecond-level response times, and flexible and scalable network architecture, is gradually replacing traditional bus technologies and becoming a key communications hub for autonomous driving, multi-screen entertainment, and information exchange among various in-vehicle modules. As the foundational physical layer of this network system, the performance of PHY chips (such as anti-interference capabilities, signal integrity, and protocol compatibility) directly determines the stability of vehicle data transmission and the efficiency of system collaboration. Its reliability and real-time performance are core elements of intelligent vehicle networks.
[0003] However, IOP testing based on microcontroller development boards or network testers is not yet mature and widely commercialized in the automotive PHY chip field. Most references and experience come from foreign companies. In addition, the testing of existing automotive Ethernet PHY chips faces many challenges:
[0004] (1) Numerous test items: Onboard PHY chips need to meet multiple communication protocols and standards, such as CAN, LIN, FlexRay, etc. Customized tests are required for different protocols, and the test items are complex and diverse, which is not conducive to management.
[0005] (2) Complex test environment: The vehicle-mounted PHY chip needs to be tested under conditions that simulate the real vehicle environment, such as temperature, channel type, electromagnetic interference, etc. The test environment is complex and troublesome to set up, and the test platform based on the development board or network tester cannot be used in such a complex environment.
[0006] (3) Low test efficiency: Traditional testing methods usually use a single test device, which cannot meet the testing requirements of multiple protocols and multiple channels. In addition, there is no managed test case library and host computer software platform, and pipeline testing cannot be performed, resulting in very low test efficiency.
[0007] It is necessary to improve the existing IOP testing method with high coverage, high accuracy and high efficiency at a low cost. Summary of the Invention
[0008] The present invention aims to address the shortcomings of existing automotive Ethernet PHY chip testing methods by providing an IOP testing system for automotive Ethernet PHY chips based on an FPGA and a host computer program, enabling efficient, flexible, and scalable testing. This testing system utilizes automated technology to automatically test 100 / 1000BASE-T1 automotive Ethernet physical layer chips from different manufacturers for compliance with IEEE 802.3 protocol specifications.
[0009] The technical solution of this invention is to perform IOP testing on the functions of the in-vehicle Ethernet PHY chip based on an FPGA platform and a host computer program. This test system mainly involves interoperability testing of 100BASE-T1 and 1000BASE-T1, including LinkStatus, Link Up Time, Signal Quality Level, Cable Diagnostics, and TC10 tests. The test system mainly includes the following three modules:
[0010] (1) FPGA module: This test system uses FPGA as the core control module, which can implement the parsing and data processing of multiple communication protocols, as well as the generation and control of test signals. It provides specific transceiver packets and test signals to the PHY chip under test (DUT), and also acts as a link partner (LP) to the DUT.
[0011] (2) Host computer software module: The host computer software is used to manage test projects, analyze test data, generate test reports, and communicate with and control the FPGA module.
[0012] (3) Test case library module: It provides a wealth of pre-set test cases, which are convenient for users to quickly call for testing, and supports users to create, edit, delete and save test cases according to specific needs.
[0013] In order to achieve the above-mentioned technical solution adopted by the present invention is:
[0014] The first aspect proposes the design of an FPGA hardware platform, using high-performance FPGA chips, such as the Xilinx Zynq series or the Intel Cyclone series, to meet the needs of high-speed data processing and support for multiple protocols. As the LP of the DUT, the FPGA needs to be programmed to implement all the functions of the 100 / 1000BASE-T1 PHY chip, and its MDI interface and the DUT are used to reliably transmit data through a single twisted pair. The FPGA can read and write registers of the DUT through MDIO to verify whether the status information of the DUT meets the protocol specification requirements. The FPGA should implement the MAC layer function, send specific frame data to the DUT through the MII interface according to the module part to be tested, or send test instructions to the LP and DUT through MDIO, and analyze the test data to further verify whether the DUT chip meets the protocol specification. Design the internal logic circuit of the FPGA to implement the following functions:
[0015] (1) Communication protocol analysis: supports analysis and data processing of various vehicle communication protocols such as CAN, LIN, and FlexRay.
[0016] (2) Link with DUT: As the link partner of the device under test, it is necessary to implement the complete protocol functions of the 100 / 1000BASE-T1 physical layer chip on the FPGA and establish a reliable data communication link with the DUT through a single twisted pair cable.
[0017] (3) Test signal generation and control: Generate various test signals according to test requirements, such as analog signals, digital signals, pulse signals, etc., and be able to control parameters such as amplitude, frequency, and phase of the test signals.
[0018] (4) Test result analysis: Collect test data and perform real-time analysis, such as waveform display, statistical analysis, etc., and provide test results in a timely manner.
[0019] (5) Communication with the host computer: Communicate with the host computer through the USB or Ethernet interface, receive control instructions from the host computer and send test data.
[0020] The second aspect is the design of the host computer software platform, which uses a graphical interface to facilitate user management of test projects, analysis of test data, and generation of test reports. Users only need to perform simple operations on the host computer software to test the specified modules and functions, which simplifies the test process, reduces test time, and reduces test costs. The main functions of the host computer software include:
[0021] (1) Test project management: define the test project, including the test project name, test project parameters, test cases, etc.
[0022] (2) Test data processing: Display test data, including waveform graph, numerical display, test results, etc.
[0023] (3) Test result analysis: Analyze the test results, determine whether the test passes, and generate a test report.
[0024] (4) Control FPGA: Send control instructions to FPGA to control the generation of test signals and test process.
[0025] Thirdly, the present invention also proposes a managed test case library based on Vivado, which provides a rich set of pre-set test cases, covering various interconnection test functions such as Link Status, Link Up Time, Signal Quality Level, Cable Diagnostics, and TC10 testing. It can also be further expanded according to different user needs. Its specific functions are as follows:
[0026] (1) Pre-set test cases: The test case library contains the current mainstream IOP test cases, which is convenient for users to quickly call for testing.
[0027] (2) Customized test cases: Supports users to customize test cases according to specific needs to meet different test scenarios.
[0028] (3) Manage test cases: Provide convenient test case management functions to facilitate users to create, edit, delete and save test cases.
[0029] The present invention adopts the above technical solution, and compared with the prior art, its significant technical effects are as follows:
[0030] (1) The present invention has rich test functions and a wide range of test items, covering all IOP test cases, supporting multiple vehicle communication protocols, and meeting different test requirements.
[0031] (2) The test environment of the present invention is flexible and can simulate the real vehicle environment to improve the accuracy of the test.
[0032] (3) The present invention has high testing efficiency and adopts FPGA hardware platform and host computer software module to realize automated testing, thereby improving testing efficiency.
[0033] (4) The present invention has strong scalability and can expand test functions and test modules as needed to adapt to different test requirements, such as consistency testing, EMC testing, etc. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 : Schematic diagram of the overall architecture of the present invention
[0035] Figure 2 :System test flow chart
[0036] Figure 3 : Cable status determination diagram DETAILED DESCRIPTION
[0037] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.
[0038] The present invention proposes a vehicle Ethernet PHY chip interconnection and interoperability testing system, such as Figure 1 As shown, it consists of an FPGA platform, host computer software, a chip under test (DUT), an AWGN transmitter, and a signal adapter board. The system uses an FPGA platform to assume the dual roles of a link partner (Link Partner) and a test case library: when acting as a link partner, the FPGA needs to be programmed to implement the functions of the 100 / 1000BASE-T1 physical layer protocol and establish a single-pair twisted pair physical layer communication with the DUT through the MDI interface; when acting as a test case library, it contains preset interoperability test cases and supports user-defined test cases. The host computer software can configure test items, including test item names, test item parameters, test channel types, etc. The test program is started through the host computer software, and the FPGA generates test signals according to the test item configuration and tests the 100M or 1G vehicle-mounted PHY chip. The host computer software also uses a graphical interface. Users only need to perform simple operations to test the specified modules and functions, determine whether the test passes, and generate corresponding test reports. The AWGN transmitter and signal adapter board can add noise to the channel to simulate a real vehicle environment. The specific test flow chart is as follows Figure 2 shown.
[0039] Example 1: Select the Gigabit Link Status test case on the host computer software. This test case ensures that when the DUT and LP establish an Active Link, they can immediately transmit valid data to each other.
[0040] In this embodiment, after the DUT establishes an Active Link with the LP, the specific test steps are as follows:
[0041] (1) First, the FPGA should set an internal counter variable to 0. When the FPGA reads the DUT's PHY through the MDIO interface and indicates Active Link, it immediately sends a data frame containing the count value to the DUT through the Serdes interface.
[0042] (2) Every 1ms, the FPGA should increase its count value and send a frame with the new count value to the DUT.
[0043] (3) After receiving the data frame, the DUT returns the received data frame to the FPGA through the MDI interface.
[0044] (4) Repeat steps (2) and (3) until the FPGA receives the first frame of data from the DUT or the link is disconnected, then the FPGA stops sending data frames.
[0045] (5) If the first frame data value received by the FPGA is 0 and the link remains Linked during the test, the test passes; otherwise, the test fails.
[0046] Example 2: Select the Gigabit Link Up Time test case on the host computer software. This test case should ensure that within the given time limit, the DUT's PHY or LP's PHY can establish an Active Link after reset and reconfiguration. The Link Up process can be analyzed by capturing Reset, MDIO, and LED waveforms. The time from MDIO initialization completion to Link Up establishment (LED light signal jump) is usually calculated as T Link_up time.
[0047] In this embodiment, after the DUT establishes an Active Link with the LP, the specific test steps are as follows:
[0048] (1) First, the DUT should reset and reconfigure its PHY, or the LP should reset and reconfigure its PHY.
[0049] (2) The moment the reconfiguration operation is completed, the FPGA starts the timer.
[0050] (3) When the FPGA reads the DUT's PHY through the MDIO interface and indicates Active Link, it stops counting.
[0051] (4) The DUT should monitor the link status to see if it remains Active Link for at least 750ms after the initial connection.
[0052] (5) If the counter value Timer is less than or equal to 100ms and the link remains Linked within 750ms after the initial connection, the test passes; otherwise, the test fails.
[0053] Example 3: Select the Gigabit Signal Quality Level test case on the host computer software. This test case should ensure that the signal quality (SQI value) of the PHY decreases as the channel quality decreases and increases as the channel quality increases.
[0054] In this embodiment, after the DUT establishes an Active Link with the LP, taking the test case of channel quality degradation as an example, the specific test steps are as follows:
[0055] (1) Eliminate any artificial channel noise to ensure the highest signal quality in the channel between the DUT and LP.
[0056] (2) Measure the SQI value of the DUT’s PHY at least 100 times and store the minimum and maximum readings.
[0057] (3) Increase the artificial noise level by one step, that is, increase the noise amplitude by 100mV using the AWGN noise generator.
[0058] (4) Repeat steps (2) and (3) until the DUT and LP can no longer establish a valid link.
[0059] (5) If both the minimum and maximum values of the SQI decrease as the noise amplitude increases, and the link remains Linked when the SQI is greater than 0 during the test, the test passes; otherwise, the test fails.
[0060] Example 4: Select the Gigabit Cable Diagnostics test case on the host computer software. This test case should ensure that the DUT can detect the normal, open, and short states of the cable.
[0061] In this embodiment, the DUT connected to the FPGA test system is the YT8011A test board. The YT8011A supports the cable diagnostic function, referred to as CSD, which can detect the cable status. The bit14 and bit13 of its extended register 0x9090 display the diagnosis results. The cable status is determined as follows: Figure 3 As shown. Taking the cable open circuit test case as an example, the specific test steps are as follows:
[0062] (1) The DUT should soft reset and reconfigure its PHY.
[0063] (2) FPGA writes CSD instruction to DUT through MDIO interface, that is, writes 0x9090
[15] =1'b1, to start the cable diagnostic function of its PHY.
[0064] (3) The DUT should wait for the PHY to complete the cable diagnosis, that is, 0x9090
[15] is cleared, indicating that the CSD test is completed.
[0065] (4) FPGA reads the cable diagnosis results of DUT through the MDIO interface.
[0066] (5) If 0x9090[14:13]=2'b10, the test passes; otherwise, the test fails.
[0067] Example 5: Select the Gigabit TC10 test case in the host computer software. This test case should ensure that the DUT's PHY chip sleep and wakeup functions are normal. The TC10 test includes a sleep function test and a wakeup function test. The sleep function test verifies whether the DUT can enter sleep mode within a given time after receiving a sleep command, while the wakeup function test ensures that the DUT exits sleep and enters normal operation mode within a given time after receiving a wakeup command.
[0068] In this embodiment, when the DUT enters Sleep mode and the link is down, taking the remote wake-up test case as an example, the specific test steps are as follows:
[0069] (1) Trigger a wake-up request on the link partner LP and start the counter Timer at the same time.
[0070] (2) FPGA reads the register of DUT through MDIO interface, waits for DUT to exit Sleep mode, and reads the value of the counter at this time, which is recorded as T Wake_up .
[0071] (3) After the DUT exits Sleep mode, the DUT’s PHY needs to be reconfigured to Gigabit mode and the counting must be restarted.
[0072] (4) FPGA reads the register of DUT through MDIO interface, waits for DUT to indicate link up, and reads the value of the counter at this time, which is recorded as T Link_up。
[0073] (5) The DUT should monitor the link status to see if it remains Active Link for at least 750ms after the initial connection.
[0074] (6) If T Wake_up <=17ms、T Link_up If the link duration is less than or equal to 100ms and the link remains Linked within 750ms after the initial connection, the test passes; otherwise, the test fails.
[0075] This patent provides a convenient testing system that can be used to conduct test cases for OPEN Alliance certification. It is suitable for interoperability testing or consistency testing of 100M and 1G automotive Ethernet physical layer PHY chips. It can accelerate developers' software and hardware development and verification of automotive Ethernet-related equipment, thereby shortening software and hardware development time, improving development efficiency, and saving development costs.
[0076] The above-described embodiments merely represent several implementation methods of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A vehicle Ethernet PHY core interoperability test system, characterized in that: The test system includes: an FPGA module, a host computer software module, a test case library module and a system expansion module. The FPGA module, as the core control module, is used to implement the link partner (LP) function of the PHY chip under test (DUT), support 100 / 1000BASE-T1 protocol communication, and establish a single twisted pair physical layer link with the DUT through the MDI interface; The host computer software module is used for test project management, test data analysis and report generation, and interacts with the FPGA module through a communication interface to control instructions and data; The test case library module contains preset interoperability test cases and supports the creation, editing and management of user-defined test cases. The system expansion module includes an AWGN generator, a signal adapter board, a multi-channel converter, etc., which is used to simulate real channel noise, channel attenuation and physical layer signal conversion.
2. The test system according to claim 1, wherein: The FPGA module further includes the following functional units: a communication protocol parsing unit that supports parsing and data processing of multiple in-vehicle communication protocols such as CAN, LIN, and FlexRay; The link partner functional unit implements the 100 / 1000BASE-T1 physical layer protocol through programming and establishes a stable data link with the DUT; Test signal generation unit, which can generate analog signals, digital signals and pulse signals, and dynamically adjust signal amplitude, frequency and phase parameters; The communication interface unit transmits commands and interacts with the host computer module via USB or Ethernet.
3. The test system according to claim 1, wherein: The host computer software module further has the following functions: Graphical interface supports users to configure test project parameters, including test name, channel type and protocol standard; Automated test process control, one-click start of the test program and real-time monitoring of the test status; Test data visualization, showing test results in the form of waveform graphs and numerical tables; The test report generation function automatically determines whether the test has passed and outputs a standard test report.
4. The test system according to claim 1, wherein: The test case library module further supports: A collection of pre-built test cases, including Link Status, Link up Time, Signal Quality Level, Cable Diagnostics, and TC10 tests; Custom test case function allows users to design new test cases according to their needs; Use case management function supports batch import, export, classification and version control of use cases.
5. The test system according to claim 1, wherein: The in-vehicle Ethernet PHY chip IOP testing method comprises the following steps: Select test cases and configure test parameters through the host computer software; The FPGA module generates test signals according to the configuration and establishes a communication link with the DUT; Collect DUT response data in real time and transmit it to the host computer software; The host computer software analyzes the data and generates a test report to determine whether the test has passed.
6. The test according to claim 1, characterized in that The system's test cases are used to verify that 100 / 1000BASE-T1 automotive Ethernet physical layer chips from different manufacturers comply with the IEEE 802.3bw and IEEE 802.3bp protocol specifications, including: Example 1: Link Status test, verifying the timeliness and stability of link establishment by sending specific data frames; Example 2: Link up Time test, using dual timers to monitor the time from PHY reset to link activation; Example 3: SQI test, verifying the signal quality attenuation and enhancement characteristics through AWGN stepped noise injection; Example 4: Cable Diagnostics test, based on CSD analysis of cable normal, open and short circuit status; Example 5: TC10 test, measuring the sleep mode switching time and wake-up link reestablishment time.
7. The system expansion module according to claim 1, characterized in that: The AWGN generator uses a programmable Gaussian white noise generation circuit, supports noise injection in the 0-1GHz frequency band, and has a noise amplitude adjustment step accuracy of 1mV. The timing and intensity of noise injection are controlled by the host computer software to simulate the impact of electromagnetic interference (such as motor noise and wireless signal crosstalk) in the vehicle environment on the PHY chip. The signal adapter board integrates an impedance matching circuit and a fault injection unit to simulate cable impedance mismatch, poor contact, and signal attenuation scenarios through physical jumpers or host computer commands to verify the fault tolerance of the DUT under channel attenuation. The multi-channel converter provides multiple independent test channels, supports simultaneous connection of multiple DUTs for parallel testing, and the AWGN noise parameters and signal attenuation configuration of each channel can be set independently, and multi-device test management can be achieved through the host computer software.
8. The test system according to claim 1, wherein: The system supports interoperability testing of 100BASE-T1 and 1000BASE-T1 protocols and is compatible with the OPEN Alliance certification test standards.
9. The scalability of the system test module according to claim 1 is characterized by: The test system can expand the consistency test module, including PCS test, PMA test, PHY Control consistency test, etc., and supports IEEE 802.3bw / bp protocol compatibility verification; The test system can expand the EMC test module to realize the automated testing of electromagnetic radiation emission and conducted sensitivity; The test system can expand the test interface of CAN FD and in-vehicle TSN protocols, supporting the extended verification of future communication standards.