Audio signal processing method and system

Abstract

The invention discloses an audio signal processing method and system, and the method comprises the following steps: constructing a dual Buffer RAM processing unit on an FPGA hardware platform, the dual Buffer RAM comprising an RAM1 and an RAM2; the method comprises the following steps: distributing a unique StreamID and a unique Audio ID for each group of SDI streams and each audio channel, and generating an address StreamID + Audio ID; and controlling the working mode of the double Buffer RAMs based on the framing calculation period: reading historical data from the RAM1 by using the address, calculating the historical data with the current input data, and outputting a calculation result by the RAM2. According to the invention, by optimizing the hardware architecture and the computational logic, the occupation of hardware resources is reduced, and the processing efficiency of the multi-channel audio signal is improved.

Description

Technical Field

[0001] The present invention relates to the field of broadcasting and television technology, and in particular to an audio signal processing method and system. Background Art

[0002] In the broadcast and television industry, FPGA-based, all-hardware platforms are often used to collect, analyze, and process IP media stream data for real-time processing, display, and monitoring of 8K / 4K ultra-high-definition signals. Existing technologies require independent processing of each frame of data to avoid blockage or delays that could affect the display, placing high demands on the platform's computational efficiency.

[0003] For audio and video signals containing multiple channels (usually 16 channels), the traditional FPGA processing method allocates an independent audio processing unit to each audio channel. Figure 1 As shown in the figure, the processing flow for a single channel includes: storing the audio input in a ring buffer, calculating the instantaneous maximum value (Max), minimum value (Min), peak level (PeakdBFS), and RMS level (RMSdBFS) of the current frame through frame processing, updating the global extreme value, and outputting the monitoring results. The calculations that need to be completed include:

[0004] 1. Instantaneous maximum value (Max): The maximum positive / negative value of the sample value in the current processing frame.

[0005] 2. Maximum value of the current frame: Max = max (sampling value 0, sampling value 1, ..., sampling value N).

[0006] 3. Instantaneous minimum value (Min): The minimum positive / negative value of the sampling value in the current processing frame (usually the negative peak value).

[0007] 4. Minimum value of the current frame: Min = min (sampling value 0, sampling value 1, ..., sampling value N).

[0008] 5. Peak level (Peak dBFS): The decibel value based on the maximum absolute value.

[0009] 6. Peak dBFS (based on the absolute value of the maximum value):

[0010]

[0011] 7.RMS level (RM SdBFS): decibel value based on effective value.

[0012] 8.RM SdBFS (based on effective value):

[0013]

[0014] If the device inputs N SDI streams, each stream contains 16 channels, then N×16 audio processing units (Audio_ch_Cal_unit) need to be called. The entire processing architecture of the device is as follows: Figure 2 shown.

[0015] The defects of the existing solution are:

[0016] 1. High hardware resource usage: When processing multiple ultra-high-definition signals, the equipment needs to integrate multiple functions such as signal scaling, encoding, and monitoring. The extensive use of independent audio computing modules will significantly consume FPGA logic resources.

[0017] 2. Limited processing efficiency: The architecture of independent calculation for each channel cannot adapt to the performance requirements of highly integrated devices, limiting the overall processing efficiency of the system. Summary of the Invention

[0018] In view of the deficiencies in the prior art, the present invention provides an audio signal processing method and system, which reduces hardware resource usage and improves the processing efficiency of multi-channel audio signals by optimizing hardware architecture and computing logic.

[0019] The present invention discloses an audio signal processing method, comprising the following steps:

[0020] Constructing a dual-buffer RAM processing unit on an FPGA hardware platform, wherein the dual-buffer RAM includes RAM1 and RAM2;

[0021] Assign a unique Stream_ID and Audio_ch_ID to each SDI stream and each audio channel, and generate the address Stream_ID+Audio_ch_ID;

[0022] The working mode of the double buffer RAM is controlled based on the frame calculation cycle: the historical data is read from RAM1 using the address and calculated with the current input data, and RAM2 outputs the calculation result.

[0023] As a further improvement of the present invention, the calculation includes:

[0024] Calculate the instantaneous maximum value Max and minimum value Min of the current frame sampling value;

[0025] Calculate the peak level Peak dBFS based on Max and Min;

[0026] The RMS level RM SdBFS is calculated based on the effective value of the sampled values.

[0027] As a further improvement of the present invention, when processing N SDI streams, each SDI stream containing M channels, only one dual RAM processing unit is called, and the calculation of N×M channels is completed through Stream_ID+Audio_ch_ID address addressing.

[0028] The present invention also discloses an audio signal processing system, comprising: constructing a dual Buffer RAM processing unit on an FPGA hardware platform, wherein the dual Buffer RAM processing unit is used to implement the above-mentioned audio signal processing method.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention solves the problem in the original audio processing unit solution where each channel occupies an independent hardware computing unit. Multi-signal, multi-channel audio analysis calculation and output can be completed using a single audio computing unit, greatly reducing the hardware resources of the integrated chip. At the same time, the program is easy to maintain, saving logic resources, and fundamentally improving the overall performance of the signal processing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is an existing single-channel audio processing flow chart;

[0032] Figure 2 This is a diagram of the existing audio channel audio processing architecture;

[0033] Figure 3 This is an architectural diagram of the audio signal processing system disclosed in the present invention;

[0034] Figure 4 Flowchart of the audio signal processing method disclosed in the present invention;

[0035] Figure 5 This is a schematic diagram of the actual calling of the audio signal processing system disclosed in the present invention. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0037] The present invention is described in further detail below with reference to the accompanying drawings:

[0038] The present invention provides an audio signal processing method based on a full hardware platform using an FPGA. Two RAMs are designed for the audio processing unit within the FPGA hardware resources. At any given moment, one RAM performs calculations while the other reads the calculation results externally. Furthermore, a new audio calculation algorithm is designed based on the audio processing unit's dual-buffer RAM architecture. This algorithm assigns an ID number to each SDI stream and each audio channel, and calculates each channel's audio by identifying the Stream_ID and Audio_ch_ID. One RAM performs cyclic calculations based on the unique ID values ​​of multiple channels in a multi-channel signal, obtaining the calculation results for the corresponding channels. The other RAM then outputs these calculation results sequentially.

[0039] like Figure 4 As shown, the specific implementation method includes:

[0040] 1) Construct a dual Buffer RAM processing unit on the FPGA hardware platform, wherein the dual Buffer RAM includes RAM1 and RAM2, as well as Buffer1 connected to RAM1 and Buffer2 connected to RAM2. Figure 3 As shown;

[0041] 2) Assign a unique Stream_ID and Audio_ch_ID to each SDI stream and each audio channel, generate the address Stream_ID + Audio_ch_ID, and calculate the audio of each channel by identifying the Stream_ID and Audio_ch_ID;

[0042] 3) The calculation cycle of each frame is obtained through frame calculation, and the calculation cycle is used to control the working mode of the double buffer RAM, controlling RAM1 to perform audio processing calculations and RAM2 to output the calculation results to the outside.

[0043] 4) Before writing to RAM, perform a RAM read operation. The RAM read and write address is stream_ID + audio_ch_ID, that is, each address corresponds to the calculated value of an audio channel; the read data is calculated with the data to be written. The calculation method is consistent with the existing method, and the calculation is repeated in sequence.

[0044] The present invention also discloses an audio signal processing system, comprising: constructing a dual Buffer RAM processing unit on an FPGA hardware platform, wherein the dual Buffer RAM processing unit is used to implement the above-mentioned audio signal processing method.

[0045] The present invention provides an audio signal processing system, comprising: a dual-Buffer RAM processing unit constructed on an FPGA hardware platform, wherein the dual-Buffer RAM processing unit is used to implement the above-mentioned audio signal processing method.

[0046] Example:

[0047] When processing 10 SDI streams, each containing 16 channels, only one dual RAM processing unit is used to complete the calculation of 10×16 channels through Stream_ID+Audio_ch_ID address addressing. For example, Figure 5 shown.

[0048] The advantages of the present invention are:

[0049] The present invention solves the problem in the original audio processing unit solution where each channel occupies an independent hardware computing unit. Multi-signal, multi-channel audio analysis calculation and output can be completed using a single audio computing unit, greatly reducing the hardware resources of the integrated chip. At the same time, the program is easy to maintain, saving logic resources, and fundamentally improving the overall performance of the signal processing device.

[0050] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for processing an audio signal, characterized in that: The following steps are involved: Constructing a dual-buffer RAM processing unit on an FPGA hardware platform, wherein the dual-buffer RAM includes RAM1 and RAM2; Assign a unique Stream_ID and Audio_ch_ID to each SDI stream and each audio channel, and generate the address Stream_ID+Audio_ch_ID; The working mode of the double buffer RAM is controlled based on the frame calculation cycle: the historical data is read from RAM1 using the address and calculated with the current input data, and RAM2 outputs the calculation result.

2. The audio signal processing method according to claim 1, wherein: The calculations include: Calculate the instantaneous maximum value Max and minimum value Min of the current frame sampling value; Calculate the peak level Peak dBFS based on Max and Min; The RMS level RM SdBFS is calculated based on the effective value of the sampled values.

3. The audio signal processing method according to claim 1, wherein: When processing N SDI streams, each with M audio channels, only one dual-RAM processing unit is used to complete the calculation of N × M audio channels through Stream_ID + Audio_ch_ID address addressing.

4. An audio signal processing system, characterized in that: include: A dual-Buffer RAM processing unit is constructed on an FPGA hardware platform, and the dual-Buffer RAM processing unit is used to implement the audio signal processing method according to any one of claims 1 to 3.

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