Method and system for processing signals in multiple video formats

Abstract

The invention discloses a multi-video format signal processing method and system, and the method comprises the steps: receiving an SDI stream signal, and extracting the effective region data (SAV, effective region and EAV) of the SDI stream signal; storing the effective area data into a cache; determining the data volume W written in each row of active area; the duration time Tactive of the active area is determined, Tactive = W / fwrite, and fwrite is the write-in clock frequency; in the active area time, the reading end continuously reads data with a free clock, and the read data volume R is R = Tactive * free; calculating the amount of data increased in the cache during the active area as W-R, and determining the minimum depth of the cache according to the increased amount of data; and reading the data from the cache according to the synchronized fread clock. The method can improve the processing efficiency of input signals in different video formats, is simple to implement, is easy to maintain programs, and saves logic resources.

Description

Technical Field

[0001] The present invention relates to the field of broadcasting and television technology, and in particular to a method and system for processing signals in multiple video formats. Background Art

[0002] Currently, full hardware platforms are typically built on FPGAs with high computing power and stable clocks to implement real-time conversion and processing of multi-channel, multi-format media signals, as well as display scaling. To avoid the impact of video signal blockage or delay on display results, the input processing of streaming data in various media formats requires high computational efficiency from the FPGA platform.

[0003] For video input processing, it is usually necessary to remap SDI streams of different formats to the 1080p50 format. The input is SDI signals of various formats, but they need to be uniformly output to the 1080p50 format under the 148.5MHz pixel clock. For example, Figure 1 As shown in the figure, when the input is HD1080i50, the input pixel clock is 74.25MHz, with 2640 pixels per line, of which 1920 are valid; after mapping, the clock is doubled to 148.5MHz, with 5280 pixels per line, but the valid area still maintains 1920 pixels.

[0004] Specifically, regardless of the input format, the ratio of the input to output clocks needs to be calculated (input pixel clock / 148.5MHz), and then this ratio is used to scale various parameters on the input side, such as total pixels, effective pixels, sync position, etc. For example, if the input is 720p60 (clock 74.25MHz), the ratio is 0.5, then the total input pixels of 1650 will be mapped to the output of 3300 pixels, while the effective pixels of 1280 remain unchanged and only need to be repositioned on the time axis.

[0005] However, this implementation has some drawbacks: the algorithm is complex and consumes significant hardware logic resources. Specifically, attention must be paid to the precise mapping of timing parameters (such as the position of the synchronization pulse), the management of the memory buffer (using the input clock for writes and the output clock for reads), and the possible need for interpolation (if the ratio is not an integer multiple). Storing the valid area in the cache hinges on address calculation: write addresses are based on the input timing, read addresses are based on the output timing, and the two are aligned using the converted pixel position, a cumbersome process. Summary of the Invention

[0006] In view of the deficiencies in the prior art, the present invention provides a method and system for processing signals in multiple video formats to improve the processing efficiency of input signals in different video formats. The method is simple to implement, easy to maintain the program, and saves logic resources.

[0007] The present invention discloses a method for processing signals in multiple video formats, comprising the following steps:

[0008] Receive an SDI stream signal and extract valid area data therein; wherein the valid area data includes SAV (start of valid video), valid area and EAV (end of valid video);

[0009] Storing the extracted valid area data in a cache;

[0010] Determine the amount of data W (unit: number of words) written to each row of the active area;

[0011] Determine the duration of the active area T_active (unit: seconds), T_active = W / f_write, where f_write is the write clock frequency;

[0012] During the active zone, the reader continuously reads data at the f_read clock. The amount of data read is R = T_active * f_read.

[0013] Calculate the amount of data increased in the cache during the active area as WR, and determine the minimum depth of the cache according to the increased amount of data;

[0014] Read data from the cache according to the synchronized f_read clock.

[0015] As a further improvement of the present invention, the processing method constructs a full hardware platform based on FPGA.

[0016] As a further improvement of the present invention, f_read is 148.5 MHz.

[0017] As a further improvement of the present invention, the formats of the SDI stream signal include one or more of 2160p50, 59.94, 60, 100, 120; 1080p50, 59.94, 60; 1080i, 50, 59.94, 60.

[0018] As a further improvement of the present invention, the minimum depth of the cache is not less than the absolute value of the amount of data increased in the cache during the active area.

[0019] The present invention also discloses a multi-video format signal processing system, comprising:

[0020] An extraction module is used to receive an SDI stream signal and extract valid area data therein; wherein the valid area data includes SAV (start of valid video), valid area and EAV (end of valid video);

[0021] a cache module, configured to store the extracted valid area data;

[0022] A calculation module is configured to determine the amount of data W (in words) written to each row of the active area and the duration of the active area, T_active (in seconds), where T_active = W / f_write, where f_write is the write clock frequency. During the active area, the reader continuously reads data at the f_read clock, and the amount of data read, R, is R = T_active * f_read. The amount of data added to the cache during the active area is calculated as WR, and the minimum depth of the cache is determined based on the amount of data added.

[0023] The read module is used to read data from the cache according to the synchronized f_read clock.

[0024] As a further improvement of the present invention, the processing system constructs a full hardware platform based on FPGA.

[0025] As a further improvement of the present invention, f_read is 148.5 MHz.

[0026] As a further improvement of the present invention, the formats of the SDI stream signal include one or more of 2160p50, 59.94, 60, 100, 120; 1080p50, 59.94, 60; and 1080i, 50, 59.94, 60.

[0027] As a further improvement of the present invention, the minimum depth of the cache is not less than the absolute value of the amount of data increased in the cache during the active area.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] Based on the requirement of only processing the active effective pixel area, the present invention stores the SAV+effective area+EAV of the received SDI stream into the cache, calculates the minimum cache depth and reads the data according to the f_read (148.5MHz) clock synchronized as needed, and has a simple implementation method. At the same time, the program is easy to maintain and does not require complex algorithms and address calculations. It saves logic resources and reduces the occupation of hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The existing HD1080i50 input SDI signal is unified into a 1080p50 output SDI signal with a 148.5MHz pixel clock.

[0031] Figure 2 Flowchart of the method for processing multiple video format signals disclosed in the present invention;

[0032] Figure 3 This is a framework diagram of the multiple video format signal processing system disclosed in the present invention. DETAILED DESCRIPTION

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0034] The present invention is described in further detail below with reference to the accompanying drawings:

[0035] like Figure 2 As shown, the present invention provides a method for processing signals of multiple video formats based on a full hardware platform, comprising the following steps:

[0036] Step 1: Receive an SDI stream signal and extract valid area data therefrom; wherein the valid area data includes SAV (Start of Active Video), valid area, and EAV (End of Active Video); the formats of the SDI stream signal include one or more of 2160p50, 59.94, 60, 100, 120; 1080p50, 59.94, 60; 1080i, 50, 59.94, 60.

[0037] Step 2: storing the extracted valid area data into a cache;

[0038] Step 3: Determine the amount of data W (unit: number of words) written into each row of the active area;

[0039] Step 4: Determine the duration of the active area T_active (unit: seconds), T_active = W / f_write, where f_write is the write clock frequency;

[0040] Step 5: During the active zone, the reader continuously reads data using the f_read clock. The amount of data read, R, is R = T_active * f_read, where f_read is 148.5 MHz.

[0041] Step 6: Calculate the amount of data added to the cache during the active zone as WR, and determine the minimum depth of the cache based on the amount of data added; wherein the minimum depth of the cache is not less than the absolute value of the amount of data added to the cache during the active zone;

[0042] Step 7: Read data from the cache according to the synchronized f_read clock.

[0043] For input signals of various SDI video formats, the processing method of the present invention has a fixed reading clock of 148.5 MHz, although the number of clock cycles of the line active area (SAV+effective pixels+EAV) of each format is different.

[0044] like Figure 3 As shown, the present invention provides a multi-video format signal processing system based on a full hardware platform, including:

[0045] Extraction module, used to implement the above step 1;

[0046] Cache module, used to implement the above step 2;

[0047] A calculation module, used to implement steps 3 to 6 above;

[0048] The reading module is used to implement the above step 7.

[0049] In this embodiment, processing of an SDI stream in 720p60 format is taken as an example for description.

[0050] First, receive the 720p60 SDI stream signal. The total number of pixels per line in this format is about 1650, and the effective pixels are 1280. The active area includes SAV(4) + effective area (1280 / 2=640, because it is 4:2:2, 2 pixels per cycle) + EAV(4), so the total number of words in the active area W=4+640+4=648.

[0051] The write clock f_write is 74.25MHz, and the duration of the active area T_active = W / f_write = 648 / 74.25×10 -6 ≈8.727×10 -6 Second.

[0052] The reading end clock f_read is 148.5MHz, and the amount of data read during the active area time is R = T_active * f_read = 8.727 × 10 -6 ×148.5×10^6≈1296.

[0053] During the active area, the amount of data added to the cache is WR=648-1296=-648, which means that during the active area, the amount of data read is greater than the amount of data written, so the minimum depth of the cache should be at least 648 to avoid data overflow.

[0054] Then, data is read from the cache according to the synchronized 148.5MHz clock to obtain a video signal that complies with the 1080p50 format.

[0055] For other SDI formats, such as 1080i60 / 1080p30 and 1080p60, the processing steps are similar. You only need to calculate the minimum cache depth based on the number of words in the corresponding active area and the write clock frequency.

[0056] 1080i60 / 1080p30: Total pixels per row 2200, effective pixels 1920, active area = 4 + 960 + 4 = 968 (4:2:2).

[0057] 1080p60: Total number of pixels per line is 2200, and the active area is also 968.

[0058] The advantages of the present invention are:

[0059] Based on the requirement of only processing the active effective pixel area, the present invention stores the SAV+effective area+EAV of the received SDI stream into the cache, calculates the minimum cache depth and reads the data according to the f_read (148.5MHz) clock synchronized as needed, and has a simple implementation method. At the same time, the program is easy to maintain and does not require complex algorithms and address calculations. It saves logic resources and reduces the occupation of hardware resources.

[0060] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for processing signals in multiple video formats, characterized in that: The following steps are involved: Receive an SDI stream signal and extract valid area data therein; wherein the valid area data includes SAV, valid area and EAV; Storing the extracted valid area data in a cache; Determine the amount of data W written to each row of the active area; Determine the duration of the active area T_active, T_active = W / f_write, where f_write is the write clock frequency; During the active zone, the reader continuously reads data at the f_read clock. The amount of data read is R = T_active * f_read. Calculate the amount of data increased in the cache during the active area as WR, and determine the minimum depth of the cache according to the increased amount of data; Read data from the cache according to the synchronized f_read clock.

2. The method for processing multiple video format signals according to claim 1, wherein: This processing method builds a full hardware platform based on FPGA.

3. The method for processing multiple video format signals according to claim 1, wherein: f_read is 148.5MHz.

4. The method for processing multiple video format signals according to claim 1, wherein: The formats of the SDI stream signal include one or more of 2160p50, 59.94, 60, 100, 120; 1080p50, 59.94, 60; 1080i, 50, 59.94, 60.

5. The method for processing multiple video format signals according to claim 1, wherein: The minimum depth of the cache is not less than the absolute value of the amount of data added to the cache during the active period.

6. A multi-video format signal processing system, characterized in that: include: An extraction module is used to receive an SDI stream signal and extract valid area data therein; wherein the valid area data includes SAV, valid area and EAV; a cache module, configured to store the extracted valid area data; A calculation module is configured to determine the amount of data W written to each row of the active area and the duration of the active area, T_active, where T_active = W / f_write, where f_write is the write clock frequency. During the active area, the reader continuously reads data at the f_read clock, and the amount of data read, R, is R = T_active * f_read. The amount of data added to the cache during the active area is calculated as WR, and the minimum depth of the cache is determined based on the amount of data added. The read module is used to read data from the cache according to the synchronized f_read clock.

7. The multi-video format signal processing system according to claim 6, wherein: The processing system is built on a full hardware platform based on FPGA.

8. The multi-video format signal processing system according to claim 6, wherein: f_read is 148.5MHz.

9. The multi-video format signal processing system according to claim 6, wherein: The formats of the SDI stream signal include one or more of 2160p50, 59.94, 60, 100, 120; 1080p50, 59.94, 60; and 1080i, 50, 59.94, 60.

10. The multi-video format signal processing system according to claim 6, wherein: The minimum depth of the cache is not less than the absolute value of the amount of data added to the cache during the active period.

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