Bias voltage self-calibration method of BLE demodulation circuit pulse width reducer
The pulse width reducer is calibrated through the bias voltage self-calibration method, which solves the problems of high power consumption and poor stability in traditional BLE demodulation technology, realizes stable signal demodulation in low-power IoT devices, and expands the scope of application.
Patent Information
- Application Number
- CN202510677689.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-26
- Publication Date
- 2025-09-12
AI Technical Summary
Traditional BLE demodulation technology has problems such as high power consumption, high circuit complexity, and poor stability, and is particularly not suitable for low-power IoT devices.
The pulse width reducer is calibrated by the bias voltage self-calibration method. The stable demodulation of the GFSK signal is achieved by combining nonlinear elements, bandpass filters, pulse width reducers and pulse width extenders, avoiding off-chip adjustment.
It achieves stable signal demodulation under ultra-low power consumption, supports a wide range of low-power application scenarios, reduces chip area and power consumption, and improves circuit stability and applicability.
Smart Images
Figure CN120640263A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits and wireless communications, and in particular to a bias voltage self-calibration method for a pulse width reducer in a BLE demodulation circuit. Background Art
[0002] BLE (Bluetooth Low Energy) is increasingly used in wireless communication applications. Compared to traditional wireless communication protocols like Bluetooth and Wi-Fi, BLE boasts extremely low average power consumption, making it ideally suited for today's ultra-low-power IoT applications (such as smart homes, smart cars, and wearables). Furthermore, many applications only require intermittent communication of small amounts of data, requiring low communication rates and small amounts of data, making it a more suitable fit for the BLE protocol. While traditional BLE signal receiving systems have low average power consumption, inherent factors such as circuit architecture design and demodulation principles still result in peak power consumption in the milliwatt range. This high power consumption is increasingly unable to meet the IoT's strategic requirements for low cost, zero maintenance, and environmental friendliness. While the industry has explored lower-power architectures, these still suffer from poor stability and applicability, making them of limited practical value.
[0003] Example 1: Traditional BLE coherent demodulation technology [1] uses a mixer to directly down-convert the frequency to obtain the IQ signal, and then uses the phase change corresponding to the IQ signal to judge the baseband signal. Since the mixer down-conversion requires an RF IQ signal, the circuit that generates this signal consumes a lot of power, and the phase judgment of the down-converted IQ signal requires a high-precision ADC, which increases the complexity of the circuit.
[0004] Example 2: Traditional BLE demodulation technology also often uses a demodulation method based on zero-crossing detection technology [2]. Similarly, due to the use of low-noise amplifiers and down-conversion mixers, the circuit has high power consumption. In addition, this technology also requires a DC offset cancellation circuit and a set of specific timing control clocks to assist in signal judgment, requiring high clock accuracy and design precision.
[0005] Example 3: Traditional BLE non-coherent demodulation technology [3] uses nonlinear elements to down-convert the signal, amplifies the signal to full amplitude through a limiting amplifier, and then uses a pulse width reducer and a pulse width extender to demodulate the signal, greatly reducing the power consumption of the circuit. However, since the operation of the pulse width reducer and pulse width extender is greatly affected by the control current, manufacturing process, voltage fluctuations, and ambient temperature, off-chip adjustment is required to achieve normal demodulation, resulting in poor circuit stability and low applicability.
[0006] In summary, traditional BLE demodulation technology has the following drawbacks: ① The circuit consumes too much power and is too complex, making it unsuitable for low-voltage, low-power IoT devices. ② The circuit design and operating clock accuracy requirements are too high. ③ The circuit operation is severely affected by the PVT environment, requiring off-chip regulation and poor circuit stability.
[0007] The shortcomings of existing ultra-low-power BLE demodulation technology are: 1. The operation of the pulse width reducer and pulse width extender is significantly affected by factors such as the manufacturing process, operating voltage, and ambient temperature, resulting in poor stability. 2. Off-chip adjustment is required to ensure the demodulation circuit operates in different scenarios, resulting in limited applicability. Summary of the Invention
[0008] In response to the shortcomings of the prior art, the present invention aims to provide a bias voltage self-calibration method for a pulse width reducer in a BLE demodulation circuit. The calibration circuit greatly improves the stability of the demodulation circuit, avoids off-chip adjustment work, and achieves stable demodulation of GFSK modulated signals transmitted by BLE transmitters in various low-power application scenarios, giving the circuit a wider range of applications. To achieve the above-mentioned purpose and other advantages of the present invention, a bias voltage self-calibration method for a pulse width reducer in a BLE demodulation circuit is provided, comprising:
[0009] An antenna, a nonlinear element connected to the antenna signal, a bandpass filter connected to the nonlinear element signal, a pulse width reducer connected to the bandpass filter signal, a pulse width reducer calibration circuit connected to the pulse width reducer signal, and a pulse width extender connected to the pulse width reducer signal;
[0010] The bandpass filter includes a low-pass filter connected to the nonlinear element signal and a limiting amplifier connected to the low-pass filter signal. The bandpass filter is used to filter the signal after entering the nonlinear element and retain the difference frequency component in the signal.
[0011] Compared with the prior art, the present invention offers the following advantages: Through an automatic calibration circuit for a pulse width reducer, the circuit can calibrate the bias voltage (current) of the pulse width reducer to a value that just eliminates the center frequency pulse width of a GFSK intermediate frequency signal, thus achieving automatic calibration of the pulse width reducer. This calibration circuit significantly improves the stability of the demodulation circuit, avoids off-chip adjustment, and enables stable demodulation of GFSK-modulated signals transmitted by BLE transmitters in various low-power application scenarios, broadening the application range of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 A circuit diagram and a demodulation process waveform diagram of a bias voltage self-calibration method for a pulse width reducer in a BLE demodulation circuit according to the present invention;
[0013] Figure 2 This is a test scenario diagram of the bias voltage self-calibration method of the BLE demodulation circuit pulse width reducer according to the present invention;
[0014] Figure 3 Figure 1 shows the demodulation function test results (left) and bit error rate test results (right) of the bias voltage self-calibration method for the BLE demodulation circuit pulse width reducer according to the present invention;
[0015] Figure 4 This is a diagram showing an application example of a specific implementation of the bias voltage self-calibration method for a pulse width reducer in a BLE demodulation circuit according to the present invention. DETAILED DESCRIPTION
[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0017] Reference Figure 1 , a bias voltage self-calibration method for a pulse width reducer of a BLE demodulation circuit, comprising:
[0018] An antenna, a nonlinear element connected to the antenna signal, a bandpass filter connected to the nonlinear element signal, a pulse width reducer connected to the bandpass filter signal, a pulse width reducer calibration circuit connected to the pulse width reducer signal, and a pulse width extender connected to the pulse width reducer signal; the principle of the nonlinear element to achieve mixing is to utilize the secondary operation in the nonlinear operation.
[0019] The bandpass filter includes a low-pass filter connected to the nonlinear element signal and a limiting amplifier connected to the low-pass filter signal. The bandpass filter is used to filter the signal after entering the nonlinear element and retain the difference frequency component in the signal. The BLE data packet signal and the BLE de-whitening signal entering from the antenna enter the nonlinear element and undergo a secondary operation, which will mix out the DC component, the difference frequency component and the high-frequency component. After filtering by the bandpass filter composed of the low-pass filter and the high-pass characteristics of the limiting amplifier, only the difference frequency component in the signal is left, which is equivalent to the BLE data packet signal being down-converted to the frequency difference between the two RF signals in the spectrum. The signal is amplified by the limiting amplifier to obtain a full-swing intermediate frequency GFSK signal. Assume that the frequency difference between the two signals is f IF , the maximum modulation frequency deviation of the BLE data packet signal is f offset , then the signal frequency of the full-swing intermediate frequency GFSK is f IF ±f offse.
[0020] Furthermore, the pulse width reducer reduces the pulse width of the intermediate frequency GFSK signal. The pulse width reducer includes four inverters connected in series and limits the charging current of the second inverter to delay its rising edge, thereby reducing the pulse width.
[0021] Furthermore, the pulse width extender includes four inverters connected in series, and by limiting the discharge current of the second inverter, the falling edge is extended, thereby extending the pulse width. The pulse width extender connects pulses with a frequency lower than fIF, and its output is converted into a bit stream through the inverter.
[0022] Furthermore, the pulse width reducer calibration circuit includes three inverters connected in series, a first power supply connected in series with the third inverter, a first capacitor connected in series with the first power supply, and a reset switch connected in parallel with the first capacitor. The pulse width reducer calibration circuit's input is a clock pulse with a frequency equal to the center frequency fIF of the intermediate frequency GFSK signal. Its structure is similar to that of a pulse width reducer, but its output serves as a switching level to control the charging current, which is used to charge the capacitor at the bias voltage node of the calibration circuit. The calibration process is as follows: before operation, the bias voltage is reset to zero. When the output of the pulse width reducer calibration circuit is charged to the point where there are no high-frequency pulses, charging stops, the voltage stabilizes, and calibration is complete. Connecting this bias voltage to the bias voltage of the pulse width reducer eliminates pulses with frequencies higher than fIF in the intermediate frequency GFSK signal, while retaining pulses with frequencies lower than fIF. The pulse width reducer calibration circuit includes three inverters connected in series, a first PMOS transistor with its source connected to the power supply terminal of the first inverter, a first capacitor connected to the output of the second inverter, a second PMOS transistor with its gate connected to the output of the third inverter, a first current source connected to the source of the second PMOS transistor, a second capacitor connected to the drain of the second PMOS transistor, and a reset switch connected in parallel with the second capacitor. Furthermore, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor.
[0023] In summary, the ultra-low power consumption BLE demodulation circuit with calibration function of the present invention occupies a chip area of 0.028mm2, supports demodulation of GFSK and FSK signals, and the demodulation rate supports 1Mb / s specified by the BLE protocol physical layer, with a peak power consumption of only 1.4μW. The test scenario of the chip is as follows Figure 2 As shown, the test results ( Figure 3) shows that the invention can correctly demodulate BLE data packets, and the sensitivity reaches -37.4dBm, -34.4dBm, and -26.6dBm when the received BLE de-whitening signal strength is -20dBm, -15dBm, and -10dBm. The above data shows that the invention can complete BLE signal demodulation of a certain strength with extremely low power consumption. If equipped with energy harvesting technology, it can achieve passive communication, which is of great significance for the deployment of ultra-low-power near-field communication networks for the Internet of Things.
[0024] Furthermore, the present invention can be used to receive and demodulate BLE standard radio frequency signals by communication devices in ultra-low-power IoT systems. By aiding in the transmission of de-whitened BLE signals by BLE devices, devices equipped with the present invention can demodulate BLE data packets sent from any device in the system that supports the BLE communication protocol (such as mobile phones, tablets, computers, and some wearable devices and smart homes that support BLE communication), achieving low-power reception of BLE data.
[0025] Specific implementation method Figure 4 As shown, BLE data packets from various nodes of the low-power Internet of Things and some commonly used communication devices are received by the device equipped with the present invention. With the assistance of the BLE de-whitening signal, the present invention can demodulate the data packets stably with much lower power consumption than traditional BLE demodulation devices.
[0026] The number of devices and processing scales described herein are intended to simplify the description of the present invention, and the application, modification, and variation of the present invention will be apparent to those skilled in the art. Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiment. They can be applied to various fields suitable for the present invention. For those skilled in the art, additional modifications can be easily implemented. Therefore, the present invention is not limited to the specific details and illustrations shown and described herein without departing from the general concept defined by the claims and their equivalents.
Claims
1. A bias voltage self-calibration method for a pulse width reducer in a BLE demodulation circuit, characterized in that: include: An antenna, a nonlinear element connected to the antenna signal, a bandpass filter connected to the nonlinear element signal, a pulse width reducer connected to the bandpass filter signal, a pulse width reducer calibration circuit connected to the pulse width reducer signal, and a pulse width extender connected to the pulse width reducer signal; The bandpass filter includes a low-pass filter connected to the nonlinear element signal and a limiting amplifier connected to the low-pass filter signal. The bandpass filter is used to filter the signal after entering the nonlinear element and retain the difference frequency component in the signal.
2. The bias voltage self-calibration method of the BLE demodulation circuit pulse width reducer according to claim 1, wherein: The pulse width reducer includes four inverters connected in series, and limits the charging current of the second inverter to delay its rising edge, thereby achieving the function of reducing the pulse width.
3. The bias voltage self-calibration method of the BLE demodulation circuit pulse width reducer according to claim 1, wherein: The pulse width extender includes four inverters connected in series, and by limiting the discharge current of the second inverter, the falling edge is extended, thereby extending the pulse width.
4. The bias voltage self-calibration method of the BLE demodulation circuit pulse width reducer according to claim 1, wherein: The pulse width reducer calibration circuit includes three inverters connected in series, a first power supply connected in series with the third inverter, a first capacitor connected in series with the first power supply, and a reset switch connected in parallel with the first capacitor.
5. The bias voltage self-calibration method of the BLE demodulation circuit pulse width reducer according to claim 4, characterized in that: The calibration process of the pulse width reducer calibration circuit is as follows: Before operation, the bias voltage is reset to zero; when charging is completed until there is no high-frequency pulse at the output of the pulse width reducer calibration circuit, charging stops, the voltage stabilizes, and calibration is completed; By connecting this bias voltage to the bias voltage of the pulse width reducer, pulses with frequencies higher than fIF in the intermediate frequency GFSK signal can be eliminated, while pulses with frequencies lower than fIF can be retained.