Semiconductor device and data storage system including same

Abstract

The invention provides a semiconductor device and a data storage system including the same. The semiconductor device includes: a gate electrode stacked in a first region to form a first stacked structure and a second stacked structure; the channel structure penetrates through the first stacking structure and the second stacking structure; a first molded structure in the second region; an alignment key structure penetrating the first molding structure; and a second molded structure on the first molded structure and the alignment key structure. The second molding structure includes a first interlayer insulating layer, a first horizontal sacrificial layer, a second interlayer insulating layer, and a second horizontal sacrificial layer sequentially stacked on an upper surface of the first molding structure, the first interlayer insulating layer and the first horizontal sacrificial layer being spaced apart from the alignment key structure in a horizontal direction, and the second interlayer insulating layer covers a part of the side surface and the upper surface of the alignment key structure.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0034728 filed on March 12, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0003] In data storage systems requiring data storage, semiconductor devices capable of storing high-capacity data are desired. Therefore, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, semiconductor devices including memory cells arranged three-dimensionally rather than two-dimensionally have been proposed. Summary of the Invention

[0004] An aspect of the present disclosure is to provide a semiconductor device having improved reliability.

[0005] An aspect of the present disclosure is to provide a data storage system including a semiconductor device having improved reliability.

[0006] According to one aspect of the present disclosure, a semiconductor device includes: a semiconductor layer; a plurality of first gate electrodes disposed in a first region of the semiconductor device, wherein the plurality of first gate electrodes are spaced apart from each other in a first direction perpendicular to an upper surface of the semiconductor layer and stacked to form a first stack structure; a plurality of second gate electrodes stacked in the first direction to form a second stack structure, wherein the second stack structure is disposed on the first stack structure; a channel structure including a first channel structure and a second channel structure penetrating the first stack structure and the second stack structure, respectively, wherein the first channel structure includes an upper end contacting a lower end of the second channel structure and a lower end contacting the semiconductor layer; a first molding structure disposed in the second region A semiconductor device according to the present invention is provided wherein the second region is spaced apart from the first region in a first horizontal direction parallel to the upper surface of the semiconductor layer; an alignment key structure is provided that penetrates the first mold structure and contacts the semiconductor layer; and a second mold structure is provided on the first mold structure and the alignment key structure and includes a plurality of interlayer insulating layers and a plurality of horizontal sacrificial layers alternately stacked in a first direction, wherein the second mold structure includes a first interlayer insulating layer among the plurality of interlayer insulating layers, a first horizontal sacrificial layer among the plurality of horizontal sacrificial layers, a second interlayer insulating layer among the plurality of interlayer insulating layers, and a second horizontal sacrificial layer among the plurality of horizontal sacrificial layers sequentially stacked in the first direction on the upper surface of the first mold structure. When viewed in a plan view, the first interlayer insulating layer and the first horizontal sacrificial layer are spaced apart from the alignment key structure in the horizontal direction. The second interlayer insulating layer covers a portion of the side surface and the upper surface of the alignment key structure.

[0007] According to one aspect of the present disclosure, a semiconductor device includes: a semiconductor layer; a plurality of gate electrodes disposed in a first region of the semiconductor device to form a first stacked structure and a second stacked structure, wherein the second stacked structure is disposed on the first stacked structure in a first direction perpendicular to an upper surface of the semiconductor layer, wherein the plurality of gate electrodes are spaced apart from each other and stacked in the first direction, and wherein the plurality of gate electrodes include a plurality of first gate electrodes in the first stacked structure and a plurality of second gate electrodes in the second stacked structure; a channel structure penetrating the first and second stacked structures and contacting the semiconductor layer; a first mold structure in the second region, the second region being spaced apart from the first region in a first horizontal direction parallel to the upper surface of the semiconductor layer; an alignment key structure penetrating the first mold structure; and a second mold structure disposed on the first mold structure and the alignment key structure and including a first interlayer insulating layer, a first horizontal sacrificial layer, a second interlayer insulating layer, and a second horizontal sacrificial layer sequentially stacked on the upper surface of the first mold structure. The first mold structure has a recessed region that exposes a portion of a side surface and an upper surface of the alignment key structure. When viewed in plan, the first interlayer insulating layer and the first horizontal sacrificial layer are outside the recessed region. A lower surface of a lowermost second gate electrode among the plurality of second gate electrodes in the second stacked structure is disposed at the same height as a lower surface of the first horizontal sacrificial layer.

[0008] According to one aspect of the present disclosure, a data storage system includes: a semiconductor memory device including a semiconductor layer, a circuit element on one side of the semiconductor layer, and an input / output pad electrically connected to the circuit element, and having a first region and a second region; and a controller electrically connected to the semiconductor memory device via the input / output pad and configured to control the semiconductor memory device. The semiconductor memory device includes: a plurality of gate electrodes disposed in the first region to form a first stacked structure and a second stacked structure, wherein the second stacked structure is disposed on the first stacked structure in a first direction perpendicular to an upper surface of the semiconductor layer, wherein the plurality of gate electrodes are spaced apart from each other in the first direction and stacked, and wherein the plurality of gate electrodes include a plurality of first gate electrodes in the first stacked structure and a plurality of second gate electrodes in the second stacked structure; a channel structure penetrating the first and second stacked structures and contacting the semiconductor layer; a first mold structure in the second region; an alignment key structure penetrating the first mold structure; and a second mold structure disposed on the first mold structure and the alignment key structure and including a first interlayer insulating layer, a first horizontal sacrificial layer, and a second interlayer insulating layer sequentially stacked on an upper surface of the first mold structure. The first interlayer insulating layer and the first horizontal sacrificial layer are spaced apart from the alignment key structure in a horizontal direction parallel to the upper surface of the semiconductor layer. The lowermost second gate electrode of the plurality of second gate electrodes in the second stacked structure is disposed at the same height as the first horizontal sacrificial layer.

[0009] By optimizing the manufacturing process of the alignment key structure, the first interlayer insulating layer and the first horizontal sacrificial layer of the second mold structure are arranged not to vertically overlap the alignment key structure, thereby providing a semiconductor device with improved reliability and a data storage system including the same.

[0010] The advantages and effects of the present application are not limited to the foregoing, and may be variously expanded without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a schematic plan view of a semiconductor device according to example embodiments.

[0013] Figure 2 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

[0014] Figure 3A and Figure 3B is a partially enlarged view illustrating a partial region of a semiconductor device according to example embodiments.

[0015] Figure 4A and Figure 4B is a partially enlarged view of a semiconductor device according to example embodiments.

[0016] Figure 5 、 Figure 6 、 Figure 7 and Figure 8 is a cross-sectional view of a semiconductor device according to example embodiments.

[0017] Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G 、 Figure 9H 、 Figure 9I 、 Figure 9J and Figure 9K is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0018] Figure 10 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.

[0019] Figure 11 is a perspective view schematically illustrating a data storage system including a semiconductor device according to example embodiments.

[0020] Figure 12 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0022] Figure 1 is a schematic plan view of a semiconductor device according to example embodiments.

[0023] Figure 2 is a schematic cross-sectional view of a semiconductor device according to example embodiments. Figure 2 It is along Figure 1 Cross-sectional views taken along line II' and line II-II'.

[0024] Figure 3A and Figure 3B is a partially enlarged view showing a partial region of a semiconductor device according to example embodiments. Figure 3A In the Figure 2 A magnified view of area 'A', and Figure 3B In the Figure 2 Magnified view of area 'B'.

[0025] Reference Figure 1 、 Figure 2 、 Figure 3A and Figure 3B The semiconductor device 100 may include a peripheral circuit region PERI and a memory cell region CELL. The peripheral circuit region PERI is a first semiconductor structure including a substrate 201, and the memory cell region CELL is a second semiconductor structure including a semiconductor layer 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. In example embodiments, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

[0026] The peripheral circuit region PERI may include a substrate 201 , an impurity region 205 and an element isolation layer 210 inside the substrate 201 , circuit elements 220 disposed on the substrate 201 , a peripheral region insulating layer 290 , circuit contact plugs 270 , and circuit interconnections 280 .

[0027] The substrate 201 may have an upper surface extending in the X and Y directions. An active region may be defined on the substrate 201 by an element isolation layer 210. The X and Y directions may be parallel to the upper surface of the substrate 201. An impurity region 205 including impurities may be provided in a portion of the active region. The substrate 201 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0028] Circuit elements 220 may include planar transistors. Each of circuit elements 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Impurity regions 205 may be provided in substrate 201 on opposite sides of circuit gate electrode 225 as source / drain regions.

[0029] The peripheral region insulating layer 290 may be disposed on the substrate 201 and cover the circuit element 220. The peripheral region insulating layer 290 may include a plurality of insulating layers formed in different process operations. The peripheral region insulating layer 290 may be formed of an insulating material.

[0030] Circuit contact plug 270 and circuit interconnect 280 may be included in a circuit interconnect structure electrically connected to circuit element 220 and impurity region 205. Circuit contact plug 270 may have a cylindrical shape, and circuit interconnect 280 may have a linear shape. Electrical signals may be applied to circuit element 220 through circuit contact plug 270 and circuit interconnect 280. In an area not shown, circuit contact plug 270 may also be connected to circuit gate electrode 225. Circuit interconnect 280 may be connected to circuit contact plug 270 and may be arranged in multiple layers. Circuit contact plug 270 and circuit interconnect 280 may include a conductive material, such as tungsten (W), copper (Cu), and / or aluminum (Al). Each of circuit contact plug 270 and circuit interconnect 280 may also include a diffusion barrier. In example embodiments, the number of layers of circuit contact plug 270 and circuit interconnect 280 may vary.

[0031] The semiconductor device 100 may have a first region R1 and a second region R2. In the first region R1, the memory cell region CELL may include a first horizontal conductive layer 102 and a second horizontal conductive layer 104 on the semiconductor layer 101, a first stacked structure GS1 and a second stacked structure GS2, each including a gate electrode 130 and an interlayer insulating layer 120, a channel structure CH penetrating the first and second stacked structures GS1 and GS2 and including a channel layer 140, an upper separation region US penetrating a portion of the second stacked structure GS2, a separation region WC penetrating the first and second stacked structures GS1 and GS2, a stud 170 on the channel structure CH, a cell interconnect 180 on the stud 170, and a second cell region insulating layer 194 covering the channel structure CH.

[0032] In the second region R2, the memory cell region CELL may include at least one alignment key AK. In the second region R2, the memory cell region CELL may include a horizontal insulating layer 110, a second horizontal conductive layer 104, a first mold structure MS1 including a first cell region insulating layer 192, a second mold structure MS2 including a horizontal sacrificial layer 118 and an interlayer insulating layer 120, an alignment key structure KS penetrating the first mold structure MS1, and a second cell region insulating layer 194 covering the second mold structure MS2.

[0033] In the semiconductor device 100, the first region R1 and the second region R2 may be spaced apart from each other. The first region R1 may be a memory cell region where memory cell strings are arranged based on the channel structure CH (for example, the first stacked structure GS1 and the second stacked structure GS2 form memory cells), and the second region R2 is disposed outside the first region R1 and may be a region where no memory cells are disposed. For example, the second region R2 may be a dummy region. In some example embodiments, the second region R2 may be a scribe lane region. Depending on the interpretation method, the first region R1 and the second region R2 may be referred to as regions of the substrate 201 or the semiconductor layer 101, rather than regions of the semiconductor device 100.

[0034] The semiconductor layer 101 may have an upper surface extending in the X and Y directions. The semiconductor layer 101 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The semiconductor layer 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. The semiconductor layer 101 may include impurities.

[0035] In example embodiments, the semiconductor layer 101 may be provided in both the first region R1 and the second region R2. However, in some example embodiments, the semiconductor layer 101 may be provided only in the first region R1. In this case, the horizontal insulating layer 110 and the second horizontal conductive layer 104 may not be provided in the second region R2, and at least one insulating layer may be provided in a position corresponding to the semiconductor layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104.

[0036] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked and arranged on the upper surface of the semiconductor layer 101 in the first region R1. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be included in a source structure SS together with the semiconductor layer 101. The source structure SS may serve as a common source line of the semiconductor device 100. Figure 3B As shown in FIG, the first horizontal conductive layer 102 may be directly connected to the channel layer 140 around the channel layer 140.

[0037] First horizontal conductive layer 102 and second horizontal conductive layer 104 may include a semiconductor material (e.g., polysilicon). In this case, at least first horizontal conductive layer 102 may be a layer doped with impurities of the same conductivity type as semiconductor layer 101. Second horizontal conductive layer 104 may be a doped layer or a layer including impurities diffused from first horizontal conductive layer 102. In some example embodiments, a relatively thin insulating layer may be interposed between first horizontal conductive layer 102 and second horizontal conductive layer 104.

[0038] The first stacked structure GS1 and the second stacked structure GS2 may be sequentially stacked along the Z direction from the semiconductor layer 101 in the first region R1. The Z direction may be a direction perpendicular to the upper surface of the substrate 201 or the upper surface of the semiconductor layer 101. Each of the first stacked structure GS1 and the second stacked structure GS2 may include a gate electrode 130 and an interlayer insulating layer 120 alternately disposed with the gate electrode 130. Each of the first stacked structure GS1 and the second stacked structure GS2 may further include an upper interlayer insulating layer 125 disposed in an uppermost portion and having a relatively thick thickness.

[0039] The gate electrodes 130 may be vertically spaced apart from each other and stacked on the semiconductor layer 101 to form a first stacked structure GS1 and a second stacked structure GS2. The gate electrodes 130 may include a lower gate electrode for a ground select transistor, memory gate electrodes for a plurality of memory cells, and an upper gate electrode for a string select transistor. The number of memory gate electrodes may be determined based on the capacity of the semiconductor device 100. According to example embodiments, the number of upper and lower gate electrodes may each be one to four or more, and the upper and lower gate electrodes may have structures that are identical to or different from those of the memory gate electrodes. In example embodiments, the gate electrodes 130 may also include a gate electrode disposed above the upper gate electrode and / or below the lower gate electrode and configured to form a gate electrode of an erase transistor used in an erase operation utilizing a gate-induced drain leakage (GIDL) phenomenon. At least one of the gate electrodes 130 (e.g., a memory gate electrode adjacent to the upper or lower gate electrode) may be a dummy gate electrode. For example, the gate electrode 130 may include at least one dummy gate electrode between the upper gate electrode and the memory gate electrode or between the lower gate electrode and the memory gate electrode.

[0040] like Figure 1 As shown in FIG, the gate electrodes 130 may be separated from each other in the Y direction by the separation region WC. The gate electrodes 130 between a pair of separation regions WC may be included in one memory block, but the scope of the memory block is not limited thereto.

[0041] The gate electrode 130 may include a metal material (e.g., tungsten (W)). According to example embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In example embodiments, the gate electrode 130 may further include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0042] The interlayer insulating layer 120 may be disposed between the gate electrodes 130 in the first region R1 and between the horizontal sacrificial layers 118 in the second mold structure MS2 in the second region R2. Similar to the gate electrodes 130 and the horizontal sacrificial layers 118, the interlayer insulating layers 120 may also be spaced apart from each other in the Z direction and may extend in the X direction. A relatively thick upper interlayer insulating layer 125 may be disposed on the uppermost portions of the first stacked structure GS1, the second stacked structure GS2, and the second mold structure MS2. However, the relative thicknesses and arrangement positions of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may vary in example embodiments. The interlayer insulating layer 120 and the upper interlayer insulating layer 125 may include insulating materials such as silicon oxide and silicon nitride.

[0043] Each of the channel structures CH forms a memory cell string and may be spaced apart from each other in rows and columns in the first region R1. The channel structures CH may be arranged in an XY plane to form a grid pattern, or may be arranged in a zigzag shape in one direction. The channel structures CH have a pillar shape and may have inclined side surfaces that narrow as they approach the semiconductor layer 101 according to an aspect ratio (or "height-to-width ratio" or "depth-to-width ratio").

[0044] The channel structure CH may include a first channel structure CH1 and a second channel structure CH2 stacked vertically. The first channel structure CH1 may penetrate the first stacked structure GS1 and may contact the semiconductor layer 101, and the second channel structure CH2 may penetrate the second stacked structure GS2 and may connect to the first channel structure CH1. Due to the difference in width in the region where the first and second channel structures CH1 and CH2 are connected, the channel structure CH may have a curved portion. For example, at the boundary between the first and second channel structures CH1 and CH2, the first width of the upper end (i.e., the top surface) of the first channel structure CH1 in the Y direction may be different from the second width of the lower end (i.e., the bottom surface) of the second channel structure CH2 in the Y direction. The top surface of the first channel structure CH1 may contact the bottom surface of the second channel structure CH2. In embodiments, the first width of the upper end of the first channel structure CH1 may be greater than the second width of the lower end of the second channel structure CH2. However, according to example embodiments, the number of channel structures stacked in the Z direction may vary. The term "contacting" as used herein means directly connected (ie, physically touching) unless the context indicates otherwise.

[0045] Each of the channel structures CH may include a gate dielectric layer 145, a channel layer 140, a channel filling insulating layer 147, and a channel pad 149 sequentially disposed inside the channel hole. The channel layer 140, the gate dielectric layer 145, and the channel filling insulating layer 147 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. Figure 3B , the channel layer 140 may be formed in a ring shape surrounding the channel filling insulating layer 147, and the channel filling insulating layer 147 may be disposed within a space defined by the channel layer 140. According to example embodiments, the channel layer 140 may have a columnar shape (such as a cylinder and a prism) without the channel filling insulating layer 147. The channel layer 140 may be connected to the first horizontal conductive layer 102 at the bottom. The channel layer 140 may include a semiconductor material (such as polycrystalline silicon and single crystal silicon).

[0046] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer stacked sequentially from the channel layer 140. The tunneling layer can tunnel charges into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-κ dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 145 may extend in horizontal directions (such as the X and Y directions) along the gate electrode 130.

[0047] The channel pad 149 may be disposed only on the upper end of the second channel structure CH2. The channel pad 149 may include, for example, doped polysilicon.

[0048] The separation region WC may extend in the X direction by penetrating the first stacked structure GS1, the second stacked structure GS2, the first horizontal conductive layer 102, and the second horizontal conductive layer 104 in the first region R1, and may be connected to the semiconductor layer 101. Figure 1 As shown in , the separation regions WC may be arranged parallel to each other. The separation regions WC may separate the gate electrodes 130 from each other in the Y direction. The separation regions WC may have a shape whose width decreases toward the semiconductor layer 101 due to a high aspect ratio. The separation regions WC may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0049] like Figure 1 As shown in FIG, the upper separation region US may extend in the X direction between the separation regions WC adjacent to each other in the Y direction in the first region R1. The upper separation region US may penetrate at least one gate electrode 130 including the uppermost gate electrode among the gate electrodes 130. Figure 2 As shown in FIG, the upper separation region US may separate, for example, a total of three gate electrodes 130 from each other in the Y direction. However, the number of gate electrodes 130 separated by the upper separation region US may be variously changed in example embodiments. The upper separation region US may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0050] The second cell region insulating layer 194 may be provided to cover the second stacked structure GS2 and the second mold structure MS2. According to example embodiments, the second cell region insulating layer 194 may include a plurality of insulating layers. The second cell region insulating layer 194 may be formed of an insulating material and may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0051] Pillars 170 and cell interconnects 180 may be disposed on the channel structures CH in the first region R1 and may be included in a cell interconnect structure electrically connected to the memory cells. Pillars 170 may penetrate the second cell region insulating layer 194 and may be connected to the channel structures CH. Pillars 170 may electrically connect the channel structures CH to cell interconnects 180 corresponding to, for example, bit lines. Pillars 170 may have a cylindrical shape and may have inclined side surfaces such that their width decreases toward the semiconductor layer 101 according to the aspect ratio of the hole forming pillars 170. Cell interconnects 180 may have a linear shape. In example embodiments, the number of plugs and interconnects included in the cell interconnect structure may vary. Pillars 170 and cell interconnects 180 may not be disposed in the second region R2. Pillars 170 and cell interconnects 180 may be formed of a conductive material and may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).

[0052] The first mold structure MS1 and the second mold structure MS2 may be sequentially stacked along the Z direction from the semiconductor layer 101 in the second region R2. The upper surface of the first mold structure MS1 may be disposed at substantially the same height as the upper surface of the first stacked structure GS1 and the upper surface or upper end of the first channel structure CH1. The second mold structure MS2 may be disposed at substantially the same height as the second stacked structure GS2. The upper surface of the second mold structure MS2 may be disposed at substantially the same height as the upper surface of the second channel structure CH2. As used herein, terms such as "same," "equal," "planar," or "coplanar" encompass approximate equivalence, including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize such meaning.

[0053] The first mold structure MS1 may include a first cell region insulating layer 192 disposed on the second horizontal conductive layer 104. Unlike the second mold structure MS2, the first mold structure MS1 may be formed of or composed of a single material. The first cell region insulating layer 192 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The first cell region insulating layer 192 may include multiple insulating layers stacked in the Z direction, and even in this case, the multiple insulating layers may include the same material.

[0054] The second mold structure MS2 may be disposed on the first mold structure MS1 and the alignment key structure KS. The second mold structure MS2 may include horizontal sacrificial layers 118 and interlayer insulating layers 120 alternately disposed with the horizontal sacrificial layers 118. The second mold structure MS2 may also include an upper interlayer insulating layer 125 disposed in the uppermost portion and having a relatively thick thickness compared to the thicknesses of the horizontal sacrificial layers 118 and the interlayer insulating layers 120. In the second mold structure MS2, the horizontal sacrificial layers 118 may each extend horizontally at substantially the same height as the gate electrodes 130 of the second stacked structure GS2. In the second mold structure MS2, the interlayer insulating layers 120 may each extend horizontally at substantially the same height as the interlayer insulating layers 120 of the second stacked structure GS2.

[0055] The second mold structure MS2 may be provided in a shape or region in which the first mold structure MS1 (e.g., the first cell region insulating layer 192) is recessed by a predetermined thickness around the alignment key structure KS. Therefore, the horizontal sacrificial layer 118 and the interlayer insulating layer 120 included in the second mold structure MS2 may have a key pattern portion KP extending toward the semiconductor layer 101.

[0056] The horizontal insulating layer 110 may be disposed in the second region R2 at the same height as the first horizontal conductive layer 102 in the first region R1. The horizontal insulating layer 110 may include a plurality of insulating layers (e.g., three insulating layers) alternately stacked on the semiconductor layer 101. The horizontal insulating layer 110 may be a layer that remains after a portion of the horizontal insulating layer 110 is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100. The horizontal insulating layer 110 may include at least one of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0057] The horizontal sacrificial layers 118 may be vertically spaced apart from each other and stacked on the second region R2 of the semiconductor layer 101 to form a second mold structure MS2. The horizontal sacrificial layers 118 may be disposed at the same height as the gate electrode 130 with substantially the same thickness. The horizontal sacrificial layers 118 may be formed of an insulating material different from that of the interlayer insulating layer 120. The horizontal sacrificial layers 118 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0058] like Figure 1 As shown in FIG, the alignment key structure KS may be provided in the second region R2 and may be arranged in a specific pattern inside the alignment key AK. The alignment key AK may be a key for aligning an upper pattern with a lower pattern during a photolithography process in the manufacturing process of the semiconductor device 100. For example, the alignment key structure KS may be used in a process of aligning the second channel structure CH2 with the first channel structure CH1. This will be referred to below. Figure 9HIn example embodiments, one or more align keys AK may be provided, and the shape and size of a pattern formed by the align key structure KS within the align key AK may be variously changed.

[0059] The alignment key structure KS may penetrate the first mold structure MS1, the horizontal insulating layer 110, and the second horizontal conductive layer 104 and may contact the semiconductor layer 101. The upper surface of the alignment key structure KS may be disposed at substantially the same height as the upper surface (e.g., the uppermost surface) of the first mold structure MS1. The upper surface of the alignment key structure KS may be disposed at substantially the same height as the upper surface of the first channel structure CH1. The alignment key structure KS may have an internal structure different from that of the first channel structure CH1. The diameter of the alignment key structure KS may be equal to or greater than that of the first channel structure CH1. The alignment key structure KS may have a pillar shape. In some example embodiments, the alignment key structure KS may have a wall shape extending lengthwise in the X-direction rather than a pillar shape.

[0060] The horizontal sacrificial layer 118 and the interlayer insulating layer 120 included in the second mold structure MS2 may horizontally extend on the alignment key structure KS. The alignment key structure KS may overlap the horizontal sacrificial layer 118 in the Z direction.

[0061] The alignment key structure KS may include a vertical sacrificial layer 119. The vertical sacrificial layer 119 may include a carbon (C) material or a carbon-based material. For example, the vertical sacrificial layer 119 may be composed of a single material layer including a carbon (C) material. The vertical sacrificial layer 119 may include a different material than the interlayer insulating layer 120 and the horizontal sacrificial layer 118. The vertical sacrificial layer 119 may include, for example, or may be composed of, for example, an amorphous carbon layer (ACL), but the present disclosure is not limited thereto. The alignment key structure KS may include an air gap AG therein, but the present disclosure is not limited thereto. As discussed herein, the term "air" may refer to atmospheric air or other gases that may be present during the manufacturing process.

[0062] Reference Figure 3A The first mold structure MS1 (e.g., the first cell region insulating layer 192) may have a recessed region RC surrounding the alignment key structure KS. The alignment key structure KS may protrude into the recessed region RC. The upper surface of the alignment key structure KS and a portion of the side surface extending from the upper surface may be exposed through the recessed region RC. For example, the depth D1 of the recessed region RC may be equal to or less than the thickness of the upper interlayer insulating layer 125 of the first stacked structure GS1. In example embodiments, the length L1 of the recessed region RC from the alignment key structure KS (e.g., a side of the alignment key structure KS) (e.g., the distance from the sidewall of the recessed region RC to the side surface of the alignment key structure KS) may vary.

[0063] The second mold structure MS2 may include a first interlayer insulating layer 120_1, a first horizontal sacrificial layer 118_1, a second interlayer insulating layer 120_2, and a second horizontal sacrificial layer 118_2, sequentially stacked from the upper surface of the first mold structure MS1. The first interlayer insulating layer 120_1 and the second interlayer insulating layer 120_2 may be disposed at substantially the same height as the lowermost interlayer insulating layer and the interlayer insulating layer disposed on the lowermost interlayer insulating layer among the interlayer insulating layers 120 in the second stacked structure GS2, respectively. The first horizontal sacrificial layer 118_1 and the second horizontal sacrificial layer 118_2 may be disposed at substantially the same height as the lowermost gate electrode and the gate electrode disposed on the lowermost gate electrode among the gate electrodes 130 in the second stacked structure GS2, respectively. For example, the lower surface of the first horizontal sacrificial layer 118_1 may be disposed at substantially the same height as the lower surface of the lowermost gate electrode among the gate electrodes 130 in the second stacked structure GS2.

[0064] The first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1 may be spaced apart from the alignment key structure KS in the horizontal direction (e.g., in the X and Y directions). For example, when viewed in a plan view, the first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1 may be spaced apart from the alignment key structure KS in the horizontal direction. The first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1 may be disposed outside the alignment key structure KS and may not extend onto the alignment key structure KS. Furthermore, they may not overlap with the alignment key structure KS in the Z direction. For example, when viewed in a plan view, the first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1 may be disposed outside the alignment key structure KS. Side surfaces of the first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1 may be substantially coplanar with each other and may also be coplanar with sidewalls of the recessed region RC. The first thickness T1 of the first interlayer insulating layer 120_1 may be equal to or less than the second thickness T2 of the first horizontal sacrificial layer 118_1, but the present disclosure is not limited thereto. The second thickness T2 may be substantially the same as the thickness of the lowermost gate electrode 130 disposed at the same height in the second stacked structure GS2. For example, the second thickness T2 may have a value within a range of approximately 230 Å to approximately 270 Å. Terms such as "approximately" or "approximately" may reflect an amount, size, orientation, or layout that varies only in a small relative manner and / or in a manner that does not significantly alter the operation, function, or structure of a particular element. For example, a range of "approximately 0.1 to approximately 1" may encompass ranges such as deviations of 0% to 5% around 0.1 and deviations of 0% to 5% around 1, particularly where such deviations maintain the same effect as the recited ranges. In some example embodiments, the first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1 may be disposed outside the recessed region RC when viewed in plan view.

[0065] The second interlayer insulating layer 120_2 may be disposed on the first horizontal sacrificial layer 118_1 and may extend vertically while covering the side surfaces of the first interlayer insulating layer 120_1 and the side surfaces of the first horizontal sacrificial layer 118_1. It may also conformally extend along the sidewalls and bottom surface of the recessed region RC. The second interlayer insulating layer 120_2 may cover a portion of the side surfaces and the top surface of the alignment key structure KS exposed by the recessed region RC. The lower surface of the second interlayer insulating layer 120_2 may be disposed at a first height above the alignment key structure KS, at a second height lower than the first height above the first mold structure MS1 surrounding the alignment key structure KS, and at a third height higher than the first height above the first horizontal sacrificial layer 118_1. In one embodiment, the second interlayer insulating layer 120_2 may include a first horizontal portion on the top surface of the alignment key structure KS, a second horizontal portion on the recessed top surface of the first mold structure MS1 surrounding the alignment key structure KS, and a third horizontal portion on the top surface of the first horizontal sacrificial layer 118_1. The first horizontal portion may be higher than the second horizontal portion and lower than the third horizontal portion. In some example embodiments, the second interlayer insulating layer 120_2 may include a vertical portion extending in the Z direction and covering the side surfaces of the first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1, and the vertical portion may be around the portion of the side surface of the alignment key structure KS.

[0066] The second horizontal sacrificial layer 118_2 may be disposed on the second interlayer insulating layer 120_2 and may include a region vertically extending toward the recessed region RC. In this example embodiment, the second horizontal sacrificial layer 118_2 may completely fill the recessed region RC together with the second interlayer insulating layer 120_2.

[0067] The second interlayer insulating layer 120_2, the second horizontal sacrificial layer 118_2, and the other interlayer insulating layers 120 and other horizontal sacrificial layers 118 formed thereon may each have a key pattern portion KP having a concave shape corresponding to the center of the alignment key structure KS. However, the key pattern portion KP may have a shape that gradually becomes flatter as it moves upward. For example, the higher the position of the key pattern portion KP, the smaller the shape of the key pattern portion KP becomes. The key pattern portion KP may be located at the upper surface of the interlayer insulating layer 120 and the upper surface of the horizontal sacrificial layer 118. As described above, the key pattern portion KP may serve as an alignment key for alignment between the upper pattern and the lower pattern during the manufacturing process of the semiconductor device 100.

[0068] Figure 4A and Figure 4B is a partially enlarged view of a semiconductor device according to example embodiments. Figure 4A and Figure 4B Shown with Figure 3A Corresponding area.

[0069] Reference Figure 4A In the semiconductor device 100a, in a region adjacent to the alignment key structure KS, the side surface of the first interlayer insulating layer 120_1 may be disposed outside the side surface of the first horizontal sacrificial layer 118_1. A portion of the lower surface of the first horizontal sacrificial layer 118_1 may be exposed through the first interlayer insulating layer 120_1. An undercut region UC may be formed between the first interlayer insulating layer 120_1 and the first horizontal sacrificial layer 118_1. Consequently, the profile of at least some of the horizontal sacrificial layers 118 and the interlayer insulating layer 120 disposed on the first horizontal sacrificial layer 118_1 and the first interlayer insulating layer 120_1 may be changed. For example, the second interlayer insulating layer 120_2 may be conformally formed on the upper surface of the combined structure of the first horizontal sacrificial layer 118_1, the first interlayer insulating layer 120_1, and the vertical sacrificial layer 119 disposed in the recessed region RC, and the second horizontal sacrificial layer 118_2 may be conformally formed on the upper surface of the second interlayer insulating layer 120_2. The shape of the upper surface of the combined structure can be transferred to the shape of the upper surface of the second interlayer insulating layer 120_2, and the shape of the upper surface of the second interlayer insulating layer 120_2 can be transferred to the shape of the upper surface of the second horizontal sacrificial layer 118_2. In this way, the shape of the upper surface of the combined structure having the recessed area RC can be transferred to the shape of the upper surface of the uppermost horizontal sacrificial layer in the shape of the key pattern portion KP, and therefore, the shape of the upper surface of the combined structure can affect the shape and position of the key pattern portion KP. When the vertical sacrificial layer 119 is asymmetric due to damage thereon, the position of the key pattern portion KP when viewed in a plan view may be offset from the center of the vertical sacrificial layer 119 in an undamaged state.

[0070] Reference Figure 4B In the semiconductor device 100b, the size of the recess region RC exposing the align key structure KS may be relatively small, and therefore, the layer filling the recess region RC may be different from the size of the recess region RC. Figure 3A In example embodiments, the length L2 of the recessed region RC from one side of the alignment key structure KS (eg, the distance from the sidewall of the recessed region RC to the side surface of the alignment key structure KS) may be shorter than Figure 3A Thus, the second interlayer insulating layer 120_2 may fill the recessed region RC. In this manner, in example embodiments, the size of the recessed region RC may be variously changed, and the specific shape of the second mold structure MS2 layer on the align key structure KS may also be changed accordingly.

[0071] Figure 5 、 Figure 6 、 Figure 7 and Figure 8is a cross-sectional view of a semiconductor device according to example embodiments. Figures 5 to 8 Shown with Figure 2 Corresponding area.

[0072] Reference Figure 5 In the semiconductor device 100c, the structure of the first mold structure MS1 may be different from Figure 2 1 . The structure of the first molded structure MS1 in the exemplary embodiment of FIG.

[0073] Similar to the second mold structure MS2, the first mold structure MS1 may include interlayer insulating layers 120 and horizontal sacrificial layers 118 alternately stacked, and may further include an upper interlayer insulating layer 125 disposed on the uppermost portion of the first mold structure MS1. In the first mold structure MS1, the interlayer insulating layers 120 may be disposed at substantially the same height as the interlayer insulating layers 120 of the first stacked structure GS1. In the first mold structure MS1, the horizontal sacrificial layers 118 may be disposed at substantially the same height as the gate electrodes 130 of the first stacked structure GS1.

[0074] The upper interlayer insulating layer 125 of the first mold structure MS1 may be partially removed to have a recessed area. For example, the upper interlayer insulating layer 125 may be removed in the area surrounding the alignment key structure KS to a depth equivalent to the thickness of the upper interlayer insulating layer 125. However, in example embodiments, the depth of the recess of the upper interlayer insulating layer 125 may vary. The alignment key structure KS may be connected to the semiconductor layer 101 by penetrating the interlayer insulating layer 120, the horizontal sacrificial layer 118, the horizontal insulating layer 110, and the second horizontal conductive layer 104.

[0075] Reference Figure 6 The semiconductor device 100d may further include a third stacked structure GS3, a third mold structure MS3, and a third cell region insulating layer 196. The channel structure CH may further include a third channel structure CH3. The first mold structure MS1 may include a first cell region insulating layer 192, the second mold structure MS2 may include a second cell region insulating layer 194, and the third mold structure MS3 may include alternately stacked interlayer insulating layers 120 and horizontal sacrificial layers 118.

[0076] The third stacked structure GS3 may include interlayer insulating layers 120 and gate electrodes 130 alternately stacked, and may further include an upper interlayer insulating layer 125 in an uppermost portion of the third stacked structure GS3. The third channel structure CH3 may be connected to the second channel structure CH2 by penetrating the third stacked structure GS3, and may include a channel pad 149 disposed on an upper end of the third channel structure CH3.

[0077] The alignment key structure KS may penetrate the second mold structure MS2. The interlayer insulating layer 120 and the horizontal sacrificial layer 118 included in the third mold structure MS3 may have a key pattern portion KP. Figure 3A The explanation described above is equally applicable to the alignment key structure KS and the structure of the third mold structure MS3 layer on the alignment key structure KS. During the manufacture of the semiconductor device 100d, the alignment key structure KS may be used so that the channel hole of the third channel structure CH3 is formed to be aligned with the channel hole of the second channel structure CH2.

[0078] In this manner, in example embodiments, the number of stack structures and mold structures stacked in the Z direction may be variously changed, and thus, the height at which the align key structure KS is arranged may also be changed.

[0079] Figure 7 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

[0080] Reference Figure 7 , the memory cell region CELL of the semiconductor device 100e may further include a horizontal insulating layer 150 and a string channel structure SCH connected to the channel structure CH.

[0081] Among the gate electrodes 130, the upper gate electrode 130U in the uppermost portion may be provided to be relatively thick compared with the other gate electrodes 130. The string channel structure SCH may penetrate the upper gate electrode 130U, and the channel structure CH may penetrate the gate electrodes 130 other than the upper gate electrode 130U. The upper gate electrodes 130U may be separated by the upper separation region US.

[0082] The string channel structures SCH may be connected to the channel structures CH, respectively. The string channel structures SCH may be disposed on the channel structures CH, respectively, and may be disposed offset from the channel structures CH in a horizontal direction (e.g., a Y direction), but the present disclosure is not limited thereto. Each of the string channel structures SCH may include a string channel layer disposed in a string channel hole and may have a structure identical or similar to that of the channel structures CH. The string channel layer may include a channel layer 140 connected to a lower end of a connection pad 151 and electrically connected to the channel structure CH via the connection pad 151. The connection pad 151 may include a conductive material (e.g., polysilicon).

[0083] The horizontal insulating layer 150 may be disposed between the channel structure CH and the string channel structure SCH and may extend horizontally. The horizontal insulating layer 150 may be disposed between the upper gate electrode 130U and the other gate electrodes 130. The horizontal insulating layer 150 may serve as an etch stop layer when forming the string channel structure SCH and may also be a layer used when forming the connection pad 151. The horizontal insulating layer 150 may also be disposed in the second region R2, but in some example embodiments, the horizontal insulating layer 150 may not be disposed in the second region R2. The horizontal insulating layer 150 may include an insulating material and may include a material different from the interlayer insulating layer 120 and the second cell region insulating layer 194. In the first region R1, the second cell region insulating layer 194 may be disposed above and below the upper gate electrode 130U.

[0084] Reference Figure 8 , the semiconductor device 100 f may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded using a wafer bonding method.

[0085] Refer to above Figure 2 The description of the peripheral circuit region (PERI) can be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may further include a first bonding via 295, a first bonding metal layer 298, and a first bonding insulating layer 299 as bonding structures. The first bonding via 295 may be provided on the uppermost portion of the circuit interconnect 280 and may be connected to the circuit interconnect 280. At least a portion of the first bonding metal layer 298 may be connected to the first bonding via 295. The first bonding metal layer 298 may be connected to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 and the second bonding metal layer 198 may provide an electrical connection path between the first semiconductor structure S1 and the second semiconductor structure S2. At least one of the first bonding metal layers 298 may be provided solely for bonding and not connected to the circuit interconnect 280. The first bonding via 295 and the first bonding metal layer 298 may include a conductive material (e.g., copper (Cu)). The first bonding insulating layer 299 may be provided around the first bonding metal layer 298. The first bonding insulating layer 299 may also serve as a diffusion barrier for the first bonding metal layer 298 , and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0086] Unless otherwise stated, the above references Figure 1 、 Figure 2 、 Figure 3A and Figure 3BThe description of the memory cell region CELL described above can be applied to the second semiconductor structure S2. The second semiconductor structure S2 may further include a lower contact plug 182 and a lower cell interconnect 184 as interconnect structures, and may further include a second bonding via 195, a second bonding metal layer 198, and a second bonding insulating layer 199 as bonding structures. The second semiconductor structure S2 may further include a passivation layer 106 covering the upper surface of the semiconductor layer 101.

[0087] The lower cell interconnection 184 may be electrically connected to the cell interconnection 180 through the lower contact plug 182. However, in example embodiments, the number of layers and arrangement of the contact plugs and interconnections included in the interconnection structure may be variously changed. The lower contact plug 182 and the lower cell interconnection 184 may be formed of a conductive material and may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).

[0088] A second bonding via 195 and a second bonding metal layer 198 may be provided below the lower cell interconnect 184. The second bonding via 195 may connect the lower cell interconnect 184 to the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. A second bonding insulating layer 199 may be bonded and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 195 and the second bonding metal layer 198 may include a conductive material (e.g., copper (Cu)). The second bonding insulating layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0089] The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded by bonding the first bonding metal layer 298 and the second bonding metal layer 198, and bonding the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding of the first bonding metal layer 298 and the second bonding metal layer 198 can be, for example, a copper (Cu)-to-copper (Cu) bond, and the bonding of the first bonding insulating layer 299 and the second bonding insulating layer 199 can be, for example, a dielectric-to-dielectric bond (such as a SiCN-to-SiCN bond). The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded by a hybrid bonding including a copper (Cu)-to-copper (Cu) bond and a dielectric-to-dielectric bond.

[0090] In example embodiments, the second semiconductor structure S2 may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see FIG. Figure 2 ). The channel structure CH may be directly connected to the semiconductor layer 101 using the channel layer 140 exposed through its upper end. However, the electrical connection form of the channel structure CH and the common source line may be variously changed in example embodiments, and the channel structure CH and the source structure SS may have the same Figure 2 The same structure as the exemplary embodiment.

[0091] The passivation layer 106 may be disposed on the upper surface of the semiconductor layer 101 and may protect the semiconductor device 100f. The passivation layer 106 may include at least one of an insulating material such as silicon oxide, silicon nitride, and silicon carbide.

[0092] Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G 、 Figure 9H 、 Figure 9I 、 Figure 9J and Figure 9K is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G 、 Figure 9H 、 Figure 9I 、 Figure 9J and Figure 9K Shown with Figure 2 Corresponding cross section.

[0093] Reference Figure 9A The first preliminary mold structure MS1p may be formed by forming a peripheral circuit region PERI, then forming a horizontal insulating layer 110 and a second horizontal conductive layer 104 on the semiconductor layer 101, and alternately stacking horizontal sacrificial layers 118 and interlayer insulating layers 120.

[0094] First, an element isolation layer 210 may be formed in a substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The element isolation layer 210 may be formed using, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of a polysilicon layer and a metal silicide layer, but the present disclosure is not limited thereto. Next, a spacer layer 224 and an impurity region 205 may be formed on opposing sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. According to example embodiments, the spacer layer 224 may be formed of multiple layers. The impurity region 205 may be formed by performing an ion implantation process.

[0095] The circuit contact plugs 270 between the circuit interconnections 280 may be formed by forming a portion of the peripheral region insulating layer 290, then etching and removing a portion of the portion of the peripheral region insulating layer 290, and filling the removed portion with a conductive material. The circuit interconnections 280 may be formed, for example, by depositing a conductive material and then patterning the conductive material.

[0096] The peripheral region insulating layer 290 may be formed of a plurality of insulating layers. The peripheral region insulating layer 290 may include a plurality of insulating layers formed by various steps of forming a circuit interconnection structure. Thus, a peripheral circuit region PERI may be formed.

[0097] The semiconductor layer 101 may be formed on the peripheral region insulating layer 290. The semiconductor layer 101 may be formed of, for example, polysilicon and may be formed by a CVD process. The polysilicon included in the semiconductor layer 101 may include impurities.

[0098] The horizontal insulating layer 110 may include a plurality of layers including different materials. The horizontal insulating layer 110 may be formed by a subsequent process by the first horizontal conductive layer 102 (see FIG. Figure 2 ) is replaced by a layer. For example, the horizontal insulating layer 110 may include a first layer and a third layer formed of the same material as the interlayer insulating layer 120, and may further include a second layer formed of the same material as the horizontal sacrificial layer 118 and disposed between the first layer and the third layer. The second horizontal conductive layer 104 may be formed on the horizontal insulating layer 110.

[0099] In the first preliminary mold structure MS1p, the horizontal sacrificial layer 118 may be formed by the gate electrode 130 (see FIG. Figure 2 ) is replaced by a layer. The horizontal sacrificial layer 118 may be formed of a material different from the interlayer insulating layer 120, and may be formed of a material that can be etched with an etch selectivity relative to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the horizontal sacrificial layer 118 may be formed of a material different from the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, the thickness of the interlayer insulating layer 120 may not be uniform. A relatively thick upper interlayer insulating layer 125 may be formed in the uppermost portion of the first preliminary mold structure MS1p. In example embodiments, the thickness of the interlayer insulating layer 120 and the horizontal sacrificial layer 118, as well as the number of films included, may vary from those shown.

[0100] Reference Figure 9B , the first preliminary mold structure MS1p may be removed from the second region R2.

[0101] The first preliminary mold structure MS1p may be removed by an etching process. The horizontal insulating layer 110 and the second horizontal conductive layer 104 may remain without being removed. However, in some example embodiments, the horizontal insulating layer 110 and the second horizontal conductive layer 104 may also be removed together with the first preliminary mold structure MS1p. In some example embodiments, the semiconductor layer 101 may also be removed together with the first preliminary mold structure MS1p. Figure 5 In the case of the example embodiment, the semiconductor device can be manufactured by omitting this process step.

[0102] Reference Figure 9C , a first cell region insulating layer 192 may be formed in the second region R2, and a vertical sacrificial layer 119 may be formed in the first and second regions R1 and R2.

[0103] The first cell region insulating layer 192 may be formed to have an upper surface coplanar with the first preliminary mold structure MS1p (eg, an upper surface of the first preliminary mold structure MS1p) through a planarization process. The first cell region insulating layer 192 may form the first mold structure MS1 of the second region R2.

[0104] Available in Figure 2 A vertical sacrificial layer 119 is formed in regions corresponding to the first channel structure CH1 and the alignment key structure KS. The vertical sacrificial layer 119 may be formed by forming a lower channel hole penetrating the first preliminary mold structure MS1p and the first mold structure MS1, then depositing a material included in the vertical sacrificial layer 119 in the lower channel hole and performing a planarization process on the material. The vertical sacrificial layer 119 may include carbon or a carbon-based material.

[0105] Reference Figure 9D , a first interlayer insulating layer 120_1 and a first horizontal sacrificial layer 118_1 may be formed on the first preliminary mold structure MS1p and the first mold structure MS1.

[0106] The first interlayer insulating layer 120_1 may be formed to cover the upper surface of the vertical sacrificial layer 119, and the first horizontal sacrificial layer 118_1 may be formed on the first interlayer insulating layer 120_1. The first interlayer insulating layer 120_1 may include a material different from that of the vertical sacrificial layer 119 and the first horizontal sacrificial layer 118_1. For example, the vertical sacrificial layer 119 includes carbon, the first interlayer insulating layer 120_1 includes oxide, and the first horizontal sacrificial layer 118_1 may include nitride. In this process step, Figure 2 The first horizontal sacrificial layer 118_1 may be formed to be relatively thin compared to the final structure.

[0107] Reference Figure 9E, a mask layer ML exposing a portion of the first horizontal sacrificial layer 118_1 may be formed in the second region R2, and the exposed first horizontal sacrificial layer 118_1 may be removed.

[0108] The mask layer ML may be, for example, a photoresist layer. The mask layer ML may be patterned and formed to have a first opening OP1 that partially exposes a portion of the first horizontal sacrificial layer 118_1 in the second region R2. Specifically, the first opening OP1 of the mask layer ML may expose a portion of the first horizontal sacrificial layer 118_1 on the vertical sacrificial layer 119 in the second region R2.

[0109] The first horizontal sacrificial layer 118_1 exposed through the first opening OP1 may be removed using, for example, a dry etching process. During the etching process, only the first horizontal sacrificial layer 118_1 may be selectively removed such that the first interlayer insulating layer 120_1 remains.

[0110] Reference Figure 9F , the mask layer ML may be removed, and the first interlayer insulating layer 120_1 and the first mold structure MS1 may be partially removed using the first horizontal sacrificial layer 118_1 as an etch mask so that the vertical sacrificial layer 119 is exposed in the second region R2.

[0111] The mask layer ML can be removed through an ashing and stripping process. During this process, the mask layer ML can be removed without exposing the vertical sacrificial layer 119. Therefore, even if the vertical sacrificial layer 119 is formed of a carbon material, the vertical sacrificial layer 119 can be covered by the first interlayer insulating layer 120_1 and thus protected from damage. Therefore, the vertical sacrificial layer 119 can be composed of a single material containing carbon, and there is no need to adopt a double-layer structure in which the upper portion of the vertical sacrificial layer 119 is filled with a material other than carbon.

[0112] The first interlayer insulating layer 120_1 exposed from the first horizontal sacrificial layer 118_1 in the second region R2 may be removed, and the first cell region insulating layer 192 included in the first mold structure MS1 may be partially removed. Consequently, a recessed region RC may be formed, exposing the upper end of the vertical sacrificial layer 119. This process step may be performed using the opening of the first horizontal sacrificial layer 118_1 as an etching mask without forming a separate mask layer, and may be performed using a dry etching process or a wet etching process. During the etching process, the first horizontal sacrificial layer 118_1 may also be partially removed, so that the thickness of the first horizontal sacrificial layer 118_1 may be reduced.

[0113] The recessed region RC of the first mold structure MS1 may be a region surrounding the vertical sacrificial layer 119 in the second region R2. In example embodiments, the width and depth of the first mold structure MS1 recessed along the periphery of the vertical sacrificial layer 119 may be variously changed. Figure 4A In an example embodiment, in this process step, the semiconductor device may be manufactured by forming the recessed region RC using a wet etching process. For example, during the wet etching process using the first horizontal sacrificial layer 118_1 as an etching mask, a portion of the first interlayer insulating layer 120_1 and the first cell region insulating layer 192 included in the first mold structure MS1 below the first horizontal sacrificial layer 118_1 may be partially removed, thereby forming an undercut region UC below the first horizontal sacrificial layer 118_1.

[0114] Reference Figure 9G , on the first horizontal sacrificial layer 118_1, a second mold structure MS2 may be formed by alternately stacking horizontal sacrificial layers 118 and interlayer insulating layers 120. When the vertical sacrificial layer 119 is damaged, the horizontal sacrificial layer 118 and the interlayer insulating layer 120 may be formed on the damaged vertical sacrificial layer 119. Since the horizontal sacrificial layer 118 and the interlayer insulating layer 120 are conformally formed on the damaged vertical sacrificial layer 119, when viewed in a plan view, the key pattern portion KP formed at the upper surface of the horizontal sacrificial layer 118 and the interlayer insulating layer 120 may be offset from the center of the vertical sacrificial layer 119 in an undamaged state. Such an offset of the key pattern portion KP may cause the key pattern portion KP to be positioned at a position which will be referred to below. Figure 9H The damage to the vertical sacrificial layer 119 may include removing at least one corner of the upper end of the vertical sacrificial layer 119 .

[0115] Similar to the first preliminary mold structure MS1p, the second mold structure MS2 can be formed by alternately stacking horizontal sacrificial layers 118 and interlayer insulating layers 120, and stacking an upper interlayer insulating layer 125 on the uppermost of the horizontal sacrificial layers 118. In the second region R2, a depression may be formed in the horizontal sacrificial layers 118 and interlayer insulating layers 120 above the recessed region RC of the first mold structure MS1. The shape of the depression may gradually become flatter toward its upper portion, which may form a notch shape in some layers. For example, the higher the horizontal sacrificial layers 118 and interlayer insulating layers 120 are positioned, the smaller the depression becomes. The depression may form a key pattern portion KP. The key pattern portion KP may be formed in a region corresponding to the center of the vertical sacrificial layer 119. For example, when viewed in plan, the center of the vertical sacrificial layer 119 and the key pattern portion KP may overlap.

[0116] Reference Figure 9H, an upper vertical sacrificial layer 119 ′ penetrating the second mold structure MS2 may be formed in the first region R1 .

[0117] The upper vertical sacrificial layer 119' may be formed on the Figure 2 The upper vertical sacrificial layer 119' can be formed by forming an upper channel hole that penetrates the second mold structure MS2 to connect to the vertical sacrificial layer 119, depositing the material included in the upper vertical sacrificial layer 119' in the upper channel hole, and performing a planarization process on the material. The upper vertical sacrificial layer 119' may include carbon or a carbon-based material. In this process step, during the photolithography process for forming the upper channel hole, the key pattern portion KP may be used as an alignment key to align the photomask.

[0118] The upper vertical sacrificial layer 119 ′ may be formed only in the first region R1 and not in the second region R2 . However, in some example embodiments, the upper vertical sacrificial layer 119 ′ may also be formed on the align key structure KS in the second region R2 .

[0119] Reference Figure 9I , a channel structure CH may be formed in the first region R1.

[0120] The channel structure CH may be formed by removing the vertical sacrificial layer 119 and the upper vertical sacrificial layer 119′ in the first region R1 to form a hole-shaped channel hole, and then sequentially depositing at least a portion of the gate dielectric layer 145, the channel layer 140, the channel filling insulating layer 147, and the channel pad 149 in the channel hole (see also FIG. Figure 3B ).

[0121] The gate dielectric layer 145 may be formed to a uniform thickness using an ALD process or a CVD process. In this process step, the gate dielectric layer 145 may be formed in whole or in part, and a portion extending vertically along the channel structure CH and the semiconductor layer 101 may be formed. A channel layer 140 may be formed on the gate dielectric layer 145 in the channel hole. A channel filling insulating layer 147 may be formed to fill the channel hole, and the channel filling insulating layer 147 may be formed of an insulating material. A channel pad 149 may be formed by partially removing the channel filling insulating layer 147 from the upper end of the channel hole and then filling the removed portion with a conductive material, and the channel pad 149 may be formed of, for example, polysilicon.

[0122] Reference Figure 9J A second opening OP2 penetrating the first preliminary mold structure MS1p and the second mold structure MS2 and exposing the semiconductor layer 101 may be formed in the first region R1, and the first horizontal conductive layer 102 may be formed, and then the horizontal sacrificial layer 118 may be removed.

[0123] First, a second cell region insulating layer 194 may be formed on the upper interlayer insulating layer 125, and a second cell region insulating layer 194 may be formed in the first region R1 in a region adjacent to the separation region WC (see FIG. Figure 2 ) is formed in a position corresponding to the second opening OP2. Next, an etch-back process may be performed while forming a separate sacrificial spacer layer in the second opening OP2, so that in the first region R1, the horizontal insulating layer 110 may be exposed, and the horizontal insulating layer 110 may be removed from the exposed area. The horizontal insulating layer 110 may be removed by, for example, a wet etching process. During the removal process of the horizontal insulating layer 110, portions of the gate dielectric layer 145 exposed in the area where the horizontal insulating layer 110 has been removed may also be removed. In the first region R1, after forming the first horizontal conductive layer 102 by depositing a conductive material in the area where the horizontal insulating layer 110 has been removed, the sacrificial spacer layer may be removed from the second opening OP2. Through this process step, the first horizontal conductive layer 102 may be formed in the first region R1, and a source structure SS including the semiconductor layer 101, the first horizontal conductive layer 102, and the second horizontal conductive layer 104 may be formed.

[0124] Next, the horizontal sacrificial layer 118 may be removed selectively with respect to the interlayer insulating layer 120, the upper interlayer insulating layer 125, and the second horizontal conductive layer 104 using, for example, wet etching, thereby forming a tunnel portion TL between two adjacent interlayer insulating layers in the interlayer insulating layer 120. In this process step, since the second opening OP2 is not formed in the second region R2, the horizontal insulating layer 110 and the horizontal sacrificial layer 118 may remain.

[0125] Reference Figure 9K , in the first region R1, the gate electrode 130 may be formed in the tunnel portion TL, and the separation region WC may be formed.

[0126] In the first region R1, the gate electrode 130 may be formed by filling the tunnel portion TL from which the horizontal sacrificial layer 118 has been removed with a conductive material. Thus, a first stacked structure GS1 and a second stacked structure GS2 including the gate electrode 130 may be formed in the first region R1. When a portion of the gate dielectric layer 145 extends horizontally along the gate electrode 130, in this process step, the portion of the gate dielectric layer 145 may be formed before forming the gate electrode 130. The gate electrode 130 may include a conductive material (e.g., a metal, polysilicon, or a metal silicide material).

[0127] After forming the gate electrode 130 , the separation region WC may be formed by filling the second opening OP2 with an insulating material.

[0128] Next, refer to Figure 2, the semiconductor device 100 may be manufactured by forming the pillars 170 connected to the channel structures CH and the cell interconnections 180 in the first region R1.

[0129] Figure 10 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.

[0130] Reference Figure 10 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0131] The semiconductor device 1100 may be a nonvolatile memory device (eg, as described above with reference to Figures 1 to 8 The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1, a second gate upper line UL2, a first gate lower line LL1, a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0132] In the second structure 1100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously modified according to example embodiments.

[0133] In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. Gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. Word line WL may be a gate electrode of the memory cell transistor MCT, and gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0134] In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for deleting data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0135] The common source line CSL, the first gate lower line LL1, the second gate lower line LL2, the word line WL, the first gate upper line UL1, and the second gate upper line UL2 may be electrically connected to the decoder circuit 1110 through a first connection interconnection 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnection 1125 extending from the first structure 1100F to the second structure 1100S.

[0136] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through the input / output connection interconnect 1135 extending from the first structure 1100F to the second structure 1100S.

[0137] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . According to example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0138] Processor 1210 can control the overall operation of data storage system 1000 (including controller 1200). Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include a controller interface 1221 configured to handle communications with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be recorded in memory cell transistors MCT of semiconductor device 1100, and data to be read from memory cell transistors MCT of semiconductor device 1100 can be transmitted via controller interface 1221. Host interface 1230 can provide communication functionality between data storage system 1000 and an external host. Upon receiving a control command from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0139] Figure 11 is a perspective view schematically illustrating a data storage system including a semiconductor device according to example embodiments.

[0140] Reference Figure 11 , the data storage system 2000 may include a mainboard 2001, a controller 2002 mounted on the mainboard 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnection pattern 2005 formed on the mainboard 2001.

[0141] Mainboard 2001 may include a connector 2006 including a plurality of pins for coupling to an external host. The number and arrangement of the plurality of pins in connector 2006 may vary depending on the communication interface between data storage system 2000 and the external host. In an example embodiment, data storage system 2000 may communicate with the external host using any of the interfaces of Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an example embodiment, data storage system 2000 may operate using power supplied from the external host via connector 2006. Data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to controller 2002 and semiconductor package 2003.

[0142] The controller 2002 may record data to or read data from the semiconductor package 2003 , and may increase the operating speed of the data storage system 2000 .

[0143] DRAM 2004 may be a buffer memory for alleviating the speed difference between semiconductor package 2003, which serves as a data storage space, and an external host. DRAM 2004 included in data storage system 2000 may also operate as a cache memory and provide a space for temporarily storing data during control operations for semiconductor package 2003. When data storage system 2000 includes DRAM 2004, controller 2002 may further include a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0144] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0145] The package substrate 2100 may be a printed circuit board including an upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 10 Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include the gate stack structure 3210 and the channel structure 3220. Figures 1 to 8 A semiconductor device is described.

[0146] In example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 and the upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and may be electrically connected to the upper pad 2130 of the package substrate 2100. According to example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a connection structure including a through-silicon via (TSV, or also referred to as a through-silicon via) instead of the connection structure 2400 using a bonding wire method.

[0147] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main board 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via interconnects formed on the interposer substrate.

[0148] Figure 12 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments. Figure 12 Show Figure 11 An example embodiment of a semiconductor package 2003 and conceptually represents Figure 11 The semiconductor package 2003 is cut along the line III-III'.

[0149] Reference Figure 12 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, an upper pad 2130 disposed at the upper surface of the package substrate body 2120, a lower pad 2125 disposed at the lower surface of the package substrate body 2120 or exposed through the lower surface of the package substrate body 2120, and an internal interconnection 2135 electrically connecting the upper pad 2130 to the lower pad 2125 within the package substrate body 2120. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the connection structure 2400 via a conductive connection 2800. Figure 11 2005 of the interconnection pattern 2001 of the main board 2001 of the data storage system 2000 shown in FIG.

[0150] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and a separation region 3230 penetrating the gate stack structure 3210, and a bit line 3240 electrically connected to the channel structure 3220. As described above with reference to Figures 1 to 8 As described, the key pattern portion KP and the alignment key structure KS used for alignment during the manufacturing process may be provided in one region of each of the semiconductor chips 2200 .

[0151] Each of the semiconductor chips 2200 may include a through-interconnect 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through-interconnect 3245 may be disposed outside the gate stack structure 3210 and may also be disposed to penetrate the gate stack structure 3210. Each of the semiconductor chips 2200 may also include an input / output connection interconnect 3265 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connection interconnect 3265.

[0152] The present disclosure is not limited to the above-described embodiments and drawings, but is defined by the appended claims. Therefore, those skilled in the art may make various substitutions, modifications, changes, or combinations of the embodiments without departing from the scope of the present disclosure as defined by the appended claims, and such substitutions, modifications, changes, or combinations of the embodiments should be construed as being included within the scope of the present disclosure.

Claims

1. A semiconductor device comprising: semiconductor layer; a plurality of first gate electrodes disposed in a first region of the semiconductor device, wherein the plurality of first gate electrodes are spaced apart from each other in a first direction perpendicular to an upper surface of the semiconductor layer and stacked to form a first stacked structure; a plurality of second gate electrodes stacked in the first direction to form a second stacked structure, wherein the second stacked structure is disposed on the first stacked structure; a channel structure comprising a first channel structure and a second channel structure respectively penetrating the first stacked structure and the second stacked structure, wherein the first channel structure comprises an upper end contacting a lower end of the second channel structure and a lower end contacting the semiconductor layer; a first molding structure in a second region of the semiconductor device, wherein the second region is spaced apart from the first region in a first horizontal direction parallel to an upper surface of the semiconductor layer; an alignment key structure penetrating the first molding structure and contacting the semiconductor layer; and a second molding structure disposed on the first molding structure and the alignment key structure, and comprising a plurality of interlayer insulating layers and a plurality of horizontal sacrificial layers alternately stacked in a first direction, wherein the second molding structure comprises a first interlayer insulating layer among the plurality of interlayer insulating layers, a first horizontal sacrificial layer among the plurality of horizontal sacrificial layers, a second interlayer insulating layer among the plurality of interlayer insulating layers, and a second horizontal sacrificial layer among the plurality of horizontal sacrificial layers sequentially stacked in the first direction on an upper surface of the first molding structure, wherein, when viewed in a plan view, the first interlayer insulating layer and the first horizontal sacrificial layer are spaced apart from the alignment key structure in a horizontal direction, and The second interlayer insulating layer covers a portion of the side surface and the upper surface of the alignment key structure.

2. The semiconductor device according to claim 1, wherein The second interlayer insulating layer includes a vertical portion extending in the first direction and covering a side surface of the first interlayer insulating layer and a side surface of the first horizontal sacrificial layer, and The vertical portion of the second interlayer insulating layer is around the portion of the side surface of the alignment key structure.

3. The semiconductor device according to claim 1, wherein The second interlayer insulating layer includes: a first horizontal portion on the upper surface of the alignment key structure; a second horizontal portion on the recessed upper surface of the first mold structure around the alignment key structure; and a third horizontal portion on the upper surface of the first horizontal sacrificial layer, and The first horizontal portion is higher than the second horizontal portion and lower than the third horizontal portion.

4. The semiconductor device according to claim 1, wherein An upper end of the first channel structure in the first stack structure has a width greater than a width of a lower end of the second channel structure in the second stack structure, and Wherein, in the second stacked structure, the lowermost second gate electrode among the plurality of second gate electrodes is disposed at the same height as the first horizontal sacrificial layer.

5. The semiconductor device according to claim 1, wherein The first molding structure includes an insulating layer in contact with the first interlayer insulating layer, and The insulating layer has a recessed area exposing the portion of the side surface and the upper surface of the alignment key structure. The semiconductor device according to claim 5 , wherein: The second interlayer insulating layer and the second horizontal sacrificial layer fill the recessed area.

7. The semiconductor device according to claim 1, wherein The alignment bond structure comprises carbon, and Wherein, the first interlayer insulating layer includes oxide.

8. The semiconductor device according to claim 1, wherein The first region is a memory cell region in which the first stacked structure and the second stacked structure form a memory cell, and Among them, the second area is a lane area.

9. The semiconductor device according to claim 1, wherein The plurality of horizontal sacrificial layers have a plurality of key pattern portions overlapping the alignment key structure, and The plurality of key pattern portions correspond to the recessed portions of the plurality of horizontal sacrificial layers.

10. The semiconductor device according to claim 1, wherein An upper surface of the alignment key structure is disposed at the same height as an uppermost surface of the first molding structure.

11. The semiconductor device according to claim 1, wherein The first molded structure is formed from a single insulating material.

12. The semiconductor device according to claim 1, wherein An upper surface of the first channel structure is disposed at the same height as an upper surface of the alignment key structure.

13. The semiconductor device according to claim 1, wherein The alignment key structure overlaps horizontal sacrificial layers other than the first horizontal sacrificial layer among the plurality of horizontal sacrificial layers in a first direction.

14. A semiconductor device comprising: semiconductor layer; a plurality of gate electrodes disposed in a first region of the semiconductor device to form a first stacked structure and a second stacked structure, wherein the second stacked structure is disposed on the first stacked structure in a first direction perpendicular to an upper surface of the semiconductor layer, wherein the plurality of gate electrodes are spaced apart from each other in the first direction and stacked, and wherein the plurality of gate electrodes include a plurality of first gate electrodes in the first stacked structure and a plurality of second gate electrodes in the second stacked structure; a channel structure penetrating the first stacked structure and the second stacked structure and contacting the semiconductor layer; a first molding structure in a second region of the semiconductor device, the second region of the semiconductor device being spaced apart from the first region in a first horizontal direction parallel to an upper surface of the semiconductor layer; an alignment key structure penetrating the first mold structure; and a second molding structure disposed on the first molding structure and the alignment key structure and comprising a first interlayer insulating layer, a first horizontal sacrificial layer, a second interlayer insulating layer, and a second horizontal sacrificial layer sequentially stacked on an upper surface of the first molding structure, wherein the first molding structure has a recessed area exposing a portion of the side surface and the upper surface of the alignment key structure, wherein, when viewed in a plan view, the first interlayer insulating layer and the first horizontal sacrificial layer are outside the alignment key structure, and Wherein, a lower surface of a lowermost second gate electrode among the plurality of second gate electrodes in the second stacked structure is disposed at the same height as a lower surface of the first horizontal sacrificial layer.

15. The semiconductor device according to claim 14, wherein When viewed in a plan view, the first interlayer insulating layer and the first horizontal sacrificial layer are outside the recessed region, and Wherein, the second interlayer insulating layer is arranged in the recessed area.

16. The semiconductor device according to claim 14, wherein The thickness of the first horizontal sacrificial layer is equal to or greater than the thickness of the first interlayer insulating layer.

17. The semiconductor device according to claim 14, wherein The thickness of the first horizontal sacrificial layer is equal to the thickness of the lowermost second gate electrode.

18. The semiconductor device according to claim 14, wherein One second gate electrode adjacent to the lowermost second gate electrode among the plurality of second gate electrodes is disposed at the same height as the second horizontal sacrificial layer.

19. A data storage system comprising: A semiconductor device including a semiconductor layer, a circuit element on one side of the semiconductor layer, and an input / output pad electrically connected to the circuit element, and having a first region and a second region; as well as a controller electrically connected to the semiconductor device through an input / output pad and configured to control the semiconductor device, The semiconductor device includes: a plurality of gate electrodes disposed in the first region to form a first stacked structure and a second stacked structure, The second stacked structure is arranged on the first stacked structure in a first direction perpendicular to the upper surface of the semiconductor layer. wherein the plurality of gate electrodes are spaced apart from each other and stacked in a first direction, and wherein the plurality of gate electrodes include a plurality of first gate electrodes in a first stacked structure and a plurality of second gate electrodes in a second stacked structure; a channel structure penetrating the first stacked structure and the second stacked structure and contacting the semiconductor layer; a first molded structure in the second region; an alignment key structure penetrating the first mold structure; and a second molding structure disposed on the first molding structure and the alignment key structure and including a first interlayer insulating layer, a first horizontal sacrificial layer, and a second interlayer insulating layer sequentially stacked on an upper surface of the first molding structure, wherein the first interlayer insulating layer and the first horizontal sacrificial layer are spaced apart from the alignment key structure in a horizontal direction parallel to the upper surface of the semiconductor layer, and The lowermost second gate electrode among the plurality of second gate electrodes in the second stacked structure is disposed at the same height as the first horizontal sacrificial layer.

20. The data storage system according to claim 19, wherein: The second interlayer insulating layer covers a portion of the side surface and the upper surface of the alignment key structure.

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