Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The method for manufacturing the semiconductor structure comprises the following steps: alternately stacking a first dielectric layer and a second dielectric layer to form a laminated structure; forming a through hole extending to the first dielectric layer along a direction opposite to the stacking direction of the laminated structure and a barrier layer extending along the stacking direction on the side wall of the through hole; removing part of the first dielectric layer through the through hole to form a sacrifice gap, wherein the length of the sacrifice gap along the first direction is greater than that of the through hole along the first direction; forming a conductive structure on one side, far away from the laminated structure, of the barrier layer and in the sacrificial gap; forming a first virtual channel hole and a second virtual channel hole which penetrate through the laminated structure and are positioned on two sides of the through hole along the first direction; and expanding the first virtual channel hole and the second virtual channel hole until the first virtual channel hole and the second virtual channel hole separate the conductive structure to form a first conductive structure and a second conductive structure which are adjacently distributed along the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for manufacturing the semiconductor structure, a memory, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the demand for storage density in semiconductor structures, such as three-dimensional semiconductor memory devices, is increasing. However, as the number of stacked layers in a semiconductor structure increases, the space occupied by the contact structures used to connect the conductive layers in different stacks becomes increasingly difficult, which in turn leads to an increasing area of ​​the semiconductor structure and a decrease in overall performance. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The method includes: alternately stacking a first dielectric layer and a second dielectric layer to form a stacked structure; forming a through hole extending to the first dielectric layer in a direction opposite to the stacking direction of the stacked structure, and a barrier layer extending along the stacking direction on the sidewall of the through hole; removing a portion of the first dielectric layer through the through hole to form a sacrificial gap, wherein the length of the sacrificial gap along the first direction is greater than the length of the through hole along the first direction; forming a conductive structure on a side of the barrier layer away from the stacked structure and within the sacrificial gap; forming a first virtual channel hole and a second virtual channel hole penetrating the stacked structure and located on both sides of the through hole along the first direction; and enlarging the first virtual channel hole and the second virtual channel hole to separate the conductive structure to form a first conductive structure and a second conductive structure adjacently distributed along a second direction, wherein the first direction, the second direction, and the stacking direction intersect with each other.

[0005] In one embodiment, enlarging the first virtual channel hole and the second virtual channel hole to the first virtual channel hole and the second virtual channel hole to separate the conductive structure includes: removing the portion of the conductive structure exposed by the sacrificial gap through the through hole; and enlarging the first virtual channel hole and the second virtual channel hole to the first virtual channel hole and the second virtual channel hole to separate the conductive structure.

[0006] In one embodiment, the method also includes: forming a first virtual channel structure and a second virtual channel structure that penetrate the stacked structure and include a first sacrificial material layer; wherein, forming a first virtual channel hole and a second virtual channel hole that penetrate the stacked structure and are located on both sides of the through hole along the first direction includes: removing the first sacrificial material layer of the first virtual channel structure and the second virtual channel structure to form the first virtual channel hole and the second virtual channel hole, respectively.

[0007] In one embodiment, the method further includes: forming a filling dielectric layer in the remaining space of the through hole except for the barrier layer and the remaining conductive structure; wherein, enlarging the first virtual channel hole and the second virtual channel hole to the first virtual channel hole and the second virtual channel hole to separate the conductive structure includes: enlarging the first virtual channel hole and the second virtual channel hole to the first virtual channel hole and the second virtual channel hole to separate the conductive structure and expose the filling dielectric layer; and forming a filling material layer in the enlarged first virtual channel hole and the second virtual channel hole, wherein the filling material layer and the filling dielectric layer are connected along the first direction.

[0008] In one embodiment, the first dielectric layer to which the through hole extends includes a first sub-dielectric layer and a second sub-dielectric layer located at different heights, wherein removing a portion of the first dielectric layer through the through hole to form a sacrificial gap includes: removing a portion of the first sub-dielectric layer and the second sub-dielectric layer through the through hole to form the sacrificial gap, wherein the first conductive structure and the second conductive structure both extend to heights corresponding to the first sub-dielectric layer and the second sub-dielectric layer, and the semiconductor structure further includes a third virtual channel hole that penetrates the stacked structure and is located on a side closer to the first conductive structure relative to the second conductive structure along the second direction, wherein the method further includes: expanding the third virtual channel hole until the third virtual channel hole separates the first conductive structure to form a first contact conductive layer and a second contact conductive layer adjacently distributed along the first direction, wherein the first contact conductive layer extends to a height corresponding to the first sub-dielectric layer, and the second contact conductive layer extends to a height corresponding to the second sub-dielectric layer.

[0009] In one embodiment, the semiconductor structure further includes a fourth virtual channel hole that penetrates the stacked structure and is located on a side close to the second conductive structure relative to the first conductive structure along the second direction, wherein the method further includes: expanding the fourth virtual channel hole to separate the second conductive structure by the fourth virtual channel hole to form a third contact conductive layer and a fourth contact conductive layer adjacently distributed along the first direction, wherein the third contact conductive layer extends to a height corresponding to the first sub-dielectric layer, and the fourth contact conductive layer extends to a height corresponding to the second sub-dielectric layer.

[0010] In one embodiment, the semiconductor structure further includes a fifth virtual channel hole that passes through the stacked structure and is located between a plurality of the third virtual channel holes along the first direction, wherein expanding the third virtual channel hole until the third virtual channel hole separates the first conductive structure includes: expanding the third virtual channel hole and the fifth virtual channel hole until the third virtual channel hole separates the first conductive structure and the third virtual channel hole and the fifth virtual channel hole are connected along the first direction.

[0011] In one embodiment, the method also includes: forming a third virtual channel structure and a fifth virtual channel structure that penetrate the stacked structure and include a second sacrificial material layer; wherein, expanding the third virtual channel hole to the third virtual channel hole to separate the first conductive structure includes: removing the second sacrificial material layer of the third virtual channel structure and the fifth virtual channel structure to form a third virtual channel hole and a fifth virtual channel hole, respectively; and expanding the third virtual channel hole and the fifth virtual channel hole to the third virtual channel hole to separate the first conductive structure and the third virtual channel hole and the fifth virtual channel hole are connected along the first direction.

[0012] In one embodiment, the third virtual channel hole and the fifth virtual channel hole are connected along the first direction to form a gate line gap extending along the first direction; wherein the method further includes: replacing a portion of the first dielectric layer with a conductive layer through the gate line gap; and forming a gate line gap structure in the gate line gap.

[0013] In one embodiment, the method further includes: removing part of the first dielectric layer and the second dielectric layer to form a step structure, wherein the second dielectric layer in the step structure is exposed; forming an initial through hole extending along the stacking direction, wherein the initial through hole moves the step structure to the first sub-dielectric layer, and the exposed second dielectric layer in the step structure includes a third sub-dielectric layer located on the surface of the first sub-dielectric layer and a fourth sub-dielectric layer located on the surface of the second sub-dielectric layer; forming a barrier layer and a first barrier layer on the sidewalls of the initial through hole and the surface of the step structure, respectively; removing the first barrier layer, the third sub-dielectric layer and the fourth sub-dielectric layer in contact with the first barrier layer to form the through hole, wherein the first sub-dielectric layer and the second sub-dielectric layer are exposed by the through hole.

[0014] In one embodiment, the method further includes: forming a second barrier layer on the side wall of the step structure, wherein the portion of the conductive structure exposed by the sacrificial gap covers the second barrier layer, and removing the portion of the conductive structure exposed by the sacrificial gap through the through hole, including: removing the portion of the conductive structure exposed by the sacrificial gap through at least one removal process.

[0015] In one embodiment, the through hole is located in a connection area of ​​the semiconductor structure, and the gate line gap extends from the connection area to an array area of ​​the semiconductor structure adjacent to the connection area, wherein the method further comprises: forming a channel structure penetrating the stacked structure in the array area, the channel structure comprising a blocking layer extending along the stacking direction, a charge capture layer, a tunneling layer, and a channel layer sequentially distributed on a side of the blocking layer away from the stacked structure.

[0016] Another aspect of the present application provides a semiconductor structure. The semiconductor structure includes: a first stacked structure located in a connection region, comprising alternating first and second dielectric layers; a second stacked structure surrounding the first stacked structure and extending from the connection region to an array region adjacent to the connection region along a first direction, comprising alternating conductive layers and first dielectric layers, wherein the conductive layers contact the first dielectric layers and the first dielectric layers contact the second dielectric layers; a plurality of dummy channel structures, including a first dummy channel structure and a second dummy channel structure extending through the first stacked structure and adjacent to each other along the first direction; a first contact structure comprising a first conductive structure extending along the stacking direction of the first stacked structure to the first dielectric layer; a second contact structure adjacent to the first contact structure along a second direction, comprising a second conductive structure extending along the stacking direction to the first dielectric layer; wherein the first and second conductive structures contact the conductive layer along the second direction, with portions of the first and second dummy channel structures located between the first and second conductive structures; and the first direction, the second direction, and the stacking direction intersecting each other.

[0017] In one embodiment, the first contact structure further includes a first filling dielectric layer located on a side of the first conductive structure away from the first stacked structure; the second contact structure further includes a second filling dielectric layer located on a side of the second conductive structure away from the first stacked structure; wherein the first filling dielectric layer and the second filling dielectric layer are in contact, and the first virtual channel structure and the second virtual channel structure are both in contact with the first filling dielectric layer and the second filling dielectric layer.

[0018] In one embodiment, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer located at different heights; the multiple virtual channel structures also include a third virtual channel structure that penetrates the second stacked structure and is located on a side closer to the first conductive structure relative to the second conductive structure along the second direction; wherein the first conductive structure includes: a first contact conductive layer, which is in contact with the conductive layer and extends to the first sub-dielectric layer along the stacking direction; and a second contact conductive layer, which is in contact with the conductive layer, is distributed adjacent to the first contact conductive layer along the first direction and extends to the second sub-dielectric layer along the stacking direction, wherein part of the third virtual channel structure is located between the first contact conductive layer and the second contact conductive layer.

[0019] In one embodiment, the multiple virtual channel structures also include a fourth virtual channel structure that penetrates the second stacked structure and is located on a side close to the second conductive structure relative to the first conductive structure along the second direction; wherein the second conductive structure includes: a third contact conductive layer, which is in contact with the conductive layer and extends to the first sub-dielectric layer along the stacking direction; and a fourth contact conductive layer, which is in contact with the conductive layer, is distributed adjacent to the third contact conductive layer along the first direction and extends to the second sub-dielectric layer along the stacking direction, wherein part of the fourth virtual channel structure is located between the third contact conductive layer and the fourth contact conductive layer.

[0020] In one embodiment, the plurality of dummy channel structures further include a fifth dummy channel structure located between the plurality of third dummy channel structures along the first direction, wherein the third dummy channel structure and the fifth dummy channel structure are connected along the first direction.

[0021] In one embodiment, the plurality of dummy channel structures further include a sixth dummy channel structure located between the plurality of fourth dummy channel structures along the first direction, wherein the fourth dummy channel structure and the sixth dummy channel structure are connected along the first direction.

[0022] In one embodiment, the first contact structure further includes a first barrier layer located between the first conductive structure and the first stacking structure and extending along the stacking direction; and the second contact structure further includes a second barrier layer located between the second conductive structure and the first stacking structure and extending along the stacking direction.

[0023] In one embodiment, the semiconductor structure further includes: a channel structure located in the array region and penetrating the second stacked structure.

[0024] On the other hand, the present application provides a memory, which includes: a memory cell array including the semiconductor structure as described above; and a peripheral circuit coupled to the memory cell array.

[0025] On the other hand, the present application provides a storage system, which includes at least one memory; and a controller coupled to the memory and configured to control the memory to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0027] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0028] Figure 2 1 is a schematic structural diagram after forming a substrate 100 and a stacked structure 1100 according to an exemplary embodiment of the present application;

[0029] Figure 3 and Figure 4 is a structural diagram after forming a first dummy channel structure 1210, a second dummy channel structure 1220 and a step structure S according to an exemplary embodiment of the present application, wherein: Figure 4 yes Figure 3 Schematic diagram of the partial cross-section structure along the AA direction;

[0030] Figure 5 and Figure 6 is a schematic structural diagram after forming the initial through hole 310 according to an exemplary embodiment of the present application, wherein: Figure 6 yes Figure 5 Schematic diagram of the partial cross-section structure along the AA direction;

[0031] Figure 7 and Figure 8 is a schematic structural diagram after forming a barrier layer 410, a first barrier layer 420, and a second barrier layer 430 according to an exemplary embodiment of the present application, wherein: Figure 8 yes Figure 7 Schematic diagram of the partial cross-section structure along the AA direction;

[0032] Figure 9 and Figure 10 is a schematic structural diagram after forming a through hole 300 according to an exemplary embodiment of the present application, wherein: Figure 10 yes Figure 9 Schematic diagram of the partial cross-section structure along the AA direction;

[0033] Figure 11 and Figure 12 is a schematic structural diagram after forming a sacrificial gap 500 according to an exemplary embodiment of the present application, wherein: Figure 12 yes Figure 11 Schematic diagram of the partial cross-section structure along the AA direction;

[0034] Figure 13 and Figure 14 is a schematic structural diagram after forming a conductive structure 1300 according to an exemplary embodiment of the present application, wherein: Figure 14 yes Figure 13 Schematic diagram of the partial cross-section structure along the AA direction;

[0035] Figure 15 and Figure 16is a schematic structural diagram after removing the portion of the conductive structure 1300 exposed by the sacrificial gap 500 according to an exemplary embodiment of the present application, wherein: Figure 16 yes Figure 15 Schematic diagram of the partial cross-section structure along the AA direction;

[0036] Figures 17 to 19 is a schematic structural diagram after forming a filling dielectric layer 600 according to an exemplary embodiment of the present application, wherein: Figure 18 yes Figure 17 Schematic diagram of the partial cross-section structure along the AA direction, Figure 19 yes Figure 18 Schematic diagram of the partial cross-section structure along the BB direction;

[0037] Figure 20 and Figure 21 is a structural diagram after forming a first virtual channel hole 1211 and a second virtual channel hole 1221 according to an exemplary embodiment of the present application, wherein: Figure 21 yes Figure 20 Schematic diagram of the partial cross-section structure along the AA direction;

[0038] Figures 22 to 24 is a structural diagram after the first virtual channel hole 1211 and the second virtual channel hole 1221 are enlarged according to an exemplary embodiment of the present application, wherein: Figure 23 yes Figure 22 Schematic diagram of the partial cross-section structure along the AA direction, Figure 24 yes Figure 22 Schematic diagram of the partial cross-section structure along the CC direction;

[0039] Figures 25 to 27 is a schematic structural diagram after forming a filling material layer 700 according to an exemplary embodiment of the present application, wherein: Figure 26 yes Figure 25 Schematic diagram of the partial cross-section structure along the AA direction, Figure 27 yes Figure 25 Schematic diagram of the partial cross-section structure along the CC direction;

[0040] Figure 28 12 is a schematic structural diagram after forming a third dummy channel hole 1231 , a fourth dummy channel hole 1241 , a fifth dummy channel hole 1251 , and a sixth dummy channel hole 1261 according to an exemplary embodiment of the present application;

[0041] Figure 29 12 is a schematic structural diagram of the enlarged third virtual channel hole 1231 , the fourth virtual channel hole 1241 , the fifth virtual channel hole 1251 and the sixth virtual channel hole 1261 according to an exemplary embodiment of the present application;

[0042] Figure 30 yes Figure 29 Schematic diagram of the partial cross-section structure along the CC direction;

[0043] Figure 31 yes Figure 29 Schematic diagram of the partial cross-section structure along the DD direction;

[0044] Figures 32 to 34 1 is a schematic structural diagram after forming a conductive layer 1130, a gate line gap structure 1400, and a channel structure 1500 according to an exemplary embodiment of the present application, wherein: Figure 33 yes Figure 32 Schematic diagram of the partial cross-section structure along the DD direction, Figure 34 yes Figure 32 Schematic diagram of the partial cross-section structure along the EE direction;

[0045] Figure 35 is a schematic block diagram of a memory 2000 according to an exemplary embodiment of the present application;

[0046] Figure 36 is an exemplary block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application; and

[0047] Figure 37A and Figure 37B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way.

[0049] It should be noted that in this specification, the terms "first," "second," "third," etc., are used solely to distinguish one feature from another and do not limit the features, and in particular do not indicate any order of precedence. Therefore, without departing from the teachings of this application, the first dielectric layer discussed in this application may also be referred to as the second dielectric layer, the first direction may also be referred to as the second direction, the first virtual channel hole may also be referred to as the second virtual channel hole, the first conductive structure may also be referred to as the second conductive structure, and vice versa.

[0050] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0051] In addition, in this document, when describing that one part is located "on" another part, the meaning of "on...", "above..." and "over..." should be interpreted in the broadest manner, so that "on..." means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above..." or "over..." does not absolutely mean being above based on the direction of gravity, nor does it mean not only "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0052] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplarily" is intended to refer to an example or illustration.

[0053] This document describes exemplary embodiments with reference to schematic diagrams. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather encompass various equivalent structures capable of performing the same functions, as well as deviations in shape and size resulting, for example, from manufacturing. The positions shown in the figures are schematic in nature and are not intended to limit the positions of components.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0055] As used herein, the term "layer" refers to a portion of a material comprising an area having a height. A layer can be an area of ​​a uniform or non-uniform continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers.

[0056] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0057] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0058] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0059] like Figure 1 As shown, a method 1000 for manufacturing a semiconductor structure may include: S1100, alternately stacking a first dielectric layer and a second dielectric layer to form a stacked structure; S1200, forming a through hole extending to the first dielectric layer in a direction opposite to the stacking direction of the stacked structure, and a barrier layer extending along the stacking direction on the sidewall of the through hole; S1300, removing a portion of the first dielectric layer through the through hole to form a sacrificial gap, wherein the length of the sacrificial gap along the first direction is greater than the length of the through hole along the first direction; S1400, forming a conductive structure on a side of the barrier layer away from the stacked structure and within the sacrificial gap; S1500, forming a first dummy channel hole and a second dummy channel hole penetrating the stacked structure and located on either side of the through hole along the first direction; and S1600, enlarging the first dummy channel hole and the second dummy channel hole to separate the conductive structures, thereby forming a first conductive structure and a second conductive structure adjacent to each other along the second direction. Steps S1100 to S1600 will be described in detail below.

[0060] In the exemplary embodiment of the present application, Figure 2 As shown, first dielectric layers 1110 and second dielectric layers 1120 may be alternately stacked to form a stacked structure 1100 .

[0061] For example, a first dielectric layer 1110 and a second dielectric layer 1120 may be alternately stacked on a substrate 100 to form a stacked structure 1100. For example, the first dielectric layer 1110 and the second dielectric layer 1120 may be stacked in sequence by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the stacked structure 1100.

[0062] It should be understood that a first dielectric layer 1110 and a second dielectric layer 1120 may form a stack, and the stack structure 1100 may include multiple stacks. The number and thickness of the first dielectric layer 1110 and the second dielectric layer 1120 are not limited to Figure 2 , without departing from the concept of the present application, those skilled in the art may set any number and thickness of the first dielectric layer 1110 and the second dielectric layer 1120 as needed. In addition, the thickness of the first dielectric layer 1110 may be greater than the thickness of the second dielectric layer 1120. The materials of the first dielectric layer 1110 and the second dielectric layer 1120 may be selected from suitable materials known in the art. For example, the material of the first dielectric layer 1110 may include a nitride such as silicon nitride, and the material of the second dielectric layer 1120 may include an oxide such as silicon oxide.

[0063] The substrate 100 may be, for example, a polycrystalline silicon substrate, a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 100 may also be a multilayer structure, such as Si / SiGe. In other embodiments, the substrate 100 may also be other epitaxial structures, such as silicon germanium on insulator (SGOI).

[0064] Figure 9 and Figure 10 3 is a partial structural diagram of forming a through hole 300 and a barrier layer 410 according to an exemplary embodiment of the present application, wherein: Figure 10 yes Figure 9 Schematic diagram of the partial cross-section structure along the AA direction.

[0065] For example, Figure 10 As shown, the first direction X, the second direction Y and the stacking direction Z of the stacked structure 1100 may intersect each other. The third direction D may be opposite to the stacking direction Z. For example, a through hole 300 extending along the third direction D to the first dielectric layer 1110 and a barrier layer 410 extending along the stacking direction Z on the sidewall of the through hole 300 may be formed. For example, as Figure 9 As shown, a plurality of through holes 300 may be formed and distributed at intervals along the first direction X. The plurality of through holes 300 may extend to the first dielectric layer 1110 at different heights, respectively.

[0066] like Figure 10As shown, in an exemplary embodiment of the present application, a through hole 300 can extend to the first dielectric layer 1110 in multiple stacks, such as two adjacent stacks. In other words, the bottom surface of the through hole 300 can have a stepped structure, i.e., a height difference. Of course, in another exemplary embodiment of the present application, a through hole 300 can extend to the first dielectric layer 1110 in a stack (including a first dielectric layer 1110 and a second dielectric layer 1120). In other words, the bottom surface of the through hole 300 can be a substantially flat surface, i.e., without a height difference.

[0067] For example, the plurality of through holes 300 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. For example, the barrier layer 410 may be formed by a combination of a thin film deposition process and a removal process, such as an etching process.

[0068] like Figures 3 to 10 , a process diagram for forming a through hole 300 extending into the first dielectric layer 1110 of two adjacent stacked layers, provided in an exemplary embodiment of the present application. It should be understood that the process for forming through hole 300 provided herein is merely an example and is not intended to be limiting. In actual practice, the process for forming through hole 300 may be appropriately configured based on actual needs.

[0069] For example, Figure 10 As shown, the first dielectric layer 1110 to which the through hole 300 extends may include a first sub-dielectric layer 1111 and a second sub-dielectric layer 1112 located at different heights. In other words, the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 may be located in different stacks. For example, the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 may be located in two adjacent stacks.

[0070] like Figures 3 to 10 As shown, forming the through hole 300 may include: removing a portion of the first dielectric layer 1110 and the second dielectric layer 1120 to form a step structure S, wherein the second dielectric layer 1120 in the step structure S is exposed ( Figure 4 ); forming an initial through hole 310 extending along the stacking direction Z, wherein the initial through hole 310 moves the step structure S to the first sub-dielectric layer 1111, and the exposed second dielectric layer 1120 in the step structure S includes a third sub-dielectric layer 1121 located on the surface of the first sub-dielectric layer 1111 and a fourth sub-dielectric layer 1122 located on the surface of the second sub-dielectric layer 1112 ( Figure 5 and Figure 6 ); forming a barrier layer 410 and a first barrier layer 420 (on the sidewalls of the initial through hole 310 and the surface of the step structure S, respectively; Figure 7 and Figure 8); removing the first barrier layer 420, the third sub-dielectric layer 1121 and the fourth sub-dielectric layer 1122 in contact with the first barrier layer 420, to form a through hole 300, wherein the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 are exposed by the through hole 300 ( Figure 9 and Figure 10 ).

[0071] Figure 3 and Figure 4 is a structural diagram after forming a first dummy channel structure 1210, a second dummy channel structure 1220 and a step structure S according to an exemplary embodiment of the present application, wherein: Figure 4 yes Figure 3 Schematic diagram of the partial cross-section structure along the AA direction.

[0072] In the exemplary embodiment of the present application, Figure 3 and Figure 4 As shown, a first dummy channel structure 1210 and a second dummy channel structure 1220 may be formed that penetrate the stacked structure 1100 and include the first sacrificial material layer 210. For example, the first dummy channel structure 1210 and the second dummy channel structure 1220 may penetrate the stacked structure 1100 along the third direction D and extend into the substrate 100. The first dummy channel structure 1210 and the second dummy channel structure 1220 may be spaced apart along the first direction X.

[0073] For example, Figure 3 and Figure 4 As shown, forming the first dummy channel structure 1210 and the second dummy channel structure 1220 may include: forming a plurality of dummy channel structures 1200 penetrating the stacked structure 1100 and including the sacrificial material layer 200 , wherein the plurality of dummy channel structures 1200 may include the first dummy channel structure 1210 and the second dummy channel structure 1220 .

[0074] Exemplarily, forming a plurality of virtual channel structures 1200 may include: forming a plurality of initial virtual channel holes (not shown) that penetrate the stacked structure 1100 along a third direction D and extend into the substrate 100; and forming a sacrificial material layer 200 (including a first sacrificial material layer 210, a second sacrificial material layer 220 and a third sacrificial material layer 230) within the initial virtual channel holes to form a plurality of virtual channel structures 1200.

[0075] For example, the initial virtual channel hole can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed. The initial virtual channel hole can have a cylindrical or columnar shape extending along the stacking direction Z in the stacked structure 1100 and the substrate 100. For example, a sacrificial material layer 200 can be formed in the initial virtual channel hole by a thin film deposition process to form a plurality of virtual channel structures 1200. The material of the sacrificial material layer 200 can include, but is not limited to, any one or a combination of carbon (such as amorphous carbon, graphite, etc.), carbon-containing organic matter, polymers, photoresist, etc., and its density is relatively low to facilitate subsequent removal.

[0076] For example, Figure 3 As shown, the plurality of dummy channel structures 1200 may further include a third dummy channel structure 1230, a fourth dummy channel structure 1240, a fifth dummy channel structure 1250, and a sixth dummy channel structure 1260. The plurality of third dummy channel structures 1230 and the fifth dummy channel structure 1250 may include a second sacrificial material layer 220. The plurality of fourth dummy channel structures 1240 and the sixth dummy channel structure 1260 may include a third sacrificial material layer 230. The plurality of third dummy channel structures 1230 may be spaced apart along the first direction X. The fifth dummy channel structure 1250 may be located between the plurality of third dummy channel structures 1230 along the first direction X. The plurality of fourth dummy channel structures 1240 may be spaced apart along the first direction X. The sixth dummy channel structure 1260 may be located between the plurality of fourth dummy channel structures 1240 along the first direction X. The third dummy channel structure 1230 and the fourth dummy channel structure 1240 may be located along the second direction Y at both sides of the first dummy channel structure 1210 and the second dummy channel structure 1220 .

[0077] For example, Figure 3 and Figure 4 As shown, a portion of the first dielectric layer 1110 and the second dielectric layer 1120 may be removed along a third direction D between the first dummy channel structure 1210 and the second dummy channel structure 1220 to form a groove G, wherein the second dielectric layer 1120 may be exposed through the groove G. A certain height difference may exist between the exposed second dielectric layer 1120 and the removed portion of the second dielectric layer 1120, so as to form a step structure S.

[0078] For example, the groove G can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed to form the step structure S.

[0079] Figure 5 and Figure 6is a schematic structural diagram after forming the initial through hole 310 according to an exemplary embodiment of the present application, wherein: Figure 6 yes Figure 5 Schematic diagram of the partial cross-section structure along the AA direction.

[0080] For example, Figure 6 As shown, an initial through hole 310 extending along the stacking direction Z may be formed, wherein the initial through hole 310 may move the step structure S to the first sub-dielectric layer 1111. The exposed second dielectric layer 1120 in the step structure S may include a third sub-dielectric layer 1121 located on a surface of the first sub-dielectric layer 1111 and a fourth sub-dielectric layer 1122 located on a surface of the second sub-dielectric layer 1112.

[0081] For example, the opening size of the initial through hole 310 along the first direction X can be larger than the opening size of the groove G along the first direction X, so that a step structure S can be formed on one side of the initial through hole 310, and the step structure S can be moved to one side of the initial through hole 310, such as to the first sub-dielectric layer 1111. For example, the initial through hole 310 can be formed by removing portions of the first dielectric layer 1110 and the second dielectric layer 1120 along the third direction D through at least one etching process.

[0082] Figure 7 and Figure 8 is a schematic structural diagram after forming a barrier layer 410, a first barrier layer 420, and a second barrier layer 430 according to an exemplary embodiment of the present application, wherein: Figure 8 yes Figure 7 Schematic diagram of the partial cross-section structure along the AA direction.

[0083] For example, Figure 8 As shown, a barrier layer 410 and a first barrier layer 420 may be formed on the sidewalls of the initial through hole 310 and the surface of the step structure S, respectively. It should be understood that during the process of forming the barrier layer 410 and the first barrier layer 420, a second barrier layer 430 may inevitably be formed on the sidewalls of the step structure S.

[0084] For example, the barrier layer 410, the first barrier layer 420, and the second barrier layer 430 may be an integral structure. The barrier layer 410, the first barrier layer 420, and the second barrier layer 430 may be made of the same material as the second dielectric layer 1120, such as oxides such as silicon oxide.

[0085] For example, a material such as silicon oxide may be deposited on the sidewalls of the initial through hole 310 and the surface and sidewalls of the step structure S by a thin film deposition process to form an integrated barrier layer 410 , a first barrier layer 420 , and a second barrier layer 430 .

[0086] Figure 9 and Figure 10 is a schematic structural diagram after forming a through hole 300 according to an exemplary embodiment of the present application, wherein: Figure 10 yes Figure 9 Schematic diagram of the partial cross-section structure along the AA direction.

[0087] For example, Figure 9 and Figure 10 As shown, the first barrier layer 420 , the third sub-dielectric layer 1121 and the fourth sub-dielectric layer 1122 contacting the first barrier layer 420 may be removed to form a through hole 300 , wherein the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 are exposed by the through hole 300 .

[0088] For example, the first barrier layer 420 , the third sub-dielectric layer 1121 and the fourth sub-dielectric layer 1122 contacting the first barrier layer 420 may be removed along the third direction D by, for example, a dry etching process to expose the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 .

[0089] Figure 11 and Figure 12 is a schematic structural diagram after forming a sacrificial gap 500 according to an exemplary embodiment of the present application, wherein: Figure 12 yes Figure 11 Schematic diagram of the partial cross-section structure along the AA direction.

[0090] For example, Figure 12 As shown, a portion of the first dielectric layer 1110 may be removed through the through hole 300 to form the sacrificial gap 500 , wherein the length of the sacrificial gap 500 along the first direction X is greater than the length of the through hole 300 along the first direction X. For example, a portion of the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 may be removed through the through hole 300 to form the sacrificial gap 500 .

[0091] For example, the sacrificial gap 500 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed.

[0092] Figure 13 and Figure 14 is a schematic structural diagram after forming a conductive structure 1300 according to an exemplary embodiment of the present application, wherein: Figure 14 yes Figure 13 Schematic diagram of the partial cross-section structure along the AA direction.

[0093] For example, Figure 14As shown, the conductive structure 1300 may be formed on the side of the barrier layer 410 away from the stacked structure 1100 and within the sacrificial gap 500 . It should be understood that in actual processes, the portion of the conductive structure 1300 exposed by the sacrificial gap 500 may cover the second barrier layer 430 .

[0094] For example, the conductive structure 1300 may be formed by a thin film deposition process through the through hole 300 and the sacrificial gap 500. The material of the conductive structure 1300 may include at least one of conductive materials such as polycrystalline silicon (p-Si, poly-Si), titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (ITO, In-Ti-O), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), etc.

[0095] For example, Figure 15 and Figure 16 As shown, the portion of the conductive structure 1300 exposed by the sacrificial gap 500 can be removed through the through hole 300, so as to facilitate the subsequent segmentation of the conductive structure 1300 into a first conductive structure 1310 and a second conductive structure 1320 adjacently distributed along the second direction Y ( Figure 22 ).

[0096] For example, the portion of the conductive structure 1300 exposed by the sacrificial gap 500 can be removed through at least one removal process. For example, when the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 have a large height difference, the sidewall of the step structure S is longer along the stacking direction Z. Consequently, the second barrier layer 430 formed on the sidewall of the step structure S is longer along the stacking direction Z, which in turn may result in a longer portion of the conductive structure 1300 covering the second barrier layer 430 along the stacking direction Z. In this case, the portion of the conductive structure 1300 covering the second barrier layer 430 may not be completely removed through a single removal process. Therefore, multiple removal processes may be used to remove the portion of the conductive structure 1300 covering the second barrier layer 430.

[0097] For example, the portion of the conductive structure 1300 exposed by the sacrificial gap 500 may be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed to form Figure 15 and Figure 16 The structure shown.

[0098] Figures 17 to 19 is a schematic structural diagram after forming a filling dielectric layer 600 according to an exemplary embodiment of the present application, wherein: Figure 18 yes Figure 17 Schematic diagram of the partial cross-section structure along the AA direction, Figure 19 yes Figure 18 Schematic diagram of the partial cross-section structure along the BB direction.

[0099] For example, Figures 17 to 19 As shown, a filling dielectric layer 600 may be formed in the remaining space of the through hole 300 except for the barrier layer 410 and the remaining conductive structure 1300. For example, the filling dielectric layer 600 may be formed by a thin film deposition process. The material of the filling dielectric layer 600 may include oxides such as silicon oxide.

[0100] Figure 20 and Figure 21 is a structural diagram after forming a first virtual channel hole 1211 and a second virtual channel hole 1221 according to an exemplary embodiment of the present application, wherein: Figure 21 yes Figure 20 Schematic diagram of the partial cross-section structure along the AA direction.

[0101] For example, Figure 20 and Figure 21 As shown, a first dummy channel hole 1211 and a second dummy channel hole 1221 penetrating the stacked structure 1100 and located on both sides of the through hole 300 , ie, the filling dielectric layer 600 along the first direction X, may be formed.

[0102] For example, the first dummy channel hole 1211 and the second dummy channel hole 1221 can be formed respectively by removing the first sacrificial material layer 210 of the first dummy channel structure 1210 and the second dummy channel structure 1220. For example, removing the first sacrificial material layer 210 may include: forming a patterned mask (not shown) on the surface of the stacked structure 1100, and removing the plurality of first sacrificial material layers 210 by one or more dry etching and / or wet etching processes using the patterned mask as a mask.

[0103] Figures 22 to 24 is a structural diagram after the first virtual channel hole 1211 and the second virtual channel hole 1221 are enlarged according to an exemplary embodiment of the present application, wherein: Figure 23 yes Figure 22 Schematic diagram of the partial cross-section structure along the AA direction, Figure 24 yes Figure 22 Schematic diagram of the partial cross-section structure along the CC direction.

[0104] For example, Figure 22 As shown, the first dummy channel hole 1211 and the second dummy channel hole 1221 can be expanded to separate the conductive structure 1300 to form the first conductive structure 1310 and the second conductive structure 1320 adjacently distributed along the second direction Y.

[0105] For example, Figure 22 and Figure 23 As shown, expanding the first virtual channel hole 1211 and the second virtual channel hole 1221 to the first virtual channel hole 1211 and the second virtual channel hole 1221 to separate the conductive structure 1300 may include: expanding the first virtual channel hole 1211 and the second virtual channel hole 1221 to the first virtual channel hole 1211 and the second virtual channel hole 1221 to separate the conductive structure 1300 and expose the filling dielectric layer 600.

[0106] like Figure 24 As shown, the first conductive structure 1310 can extend to a height corresponding to the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112. It should be understood that the second conductive structure 1320 and the first conductive structure 1310 can be substantially symmetrical along the first direction X, and the second conductive structure 1320 can also extend to a height corresponding to the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112.

[0107] Figures 25 to 27 is a schematic structural diagram after forming a filling material layer 700 according to an exemplary embodiment of the present application, wherein: Figure 26 yes Figure 25 Schematic diagram of the partial cross-section structure along the AA direction, Figure 27 yes Figure 25 Schematic diagram of the partial cross-section structure along the CC direction.

[0108] like Figure 25 As shown, a filling material layer 700 is formed in the enlarged first dummy channel hole 1211 and the second dummy channel hole 1221 , wherein the filling material layer 700 and the filling dielectric layer 600 may be connected along the first direction X. The filling material layer 700 and the filling dielectric layer 600 connected along the first direction X may divide the stacked structure 1100 into a plurality of memory blocks.

[0109] In the present application, the first conductive structure 1310 and the second conductive structure 1320 can be used to establish electrical connections with conductive layers in different stacks (formed by replacing the first dielectric layer 1110), thereby extracting current. By separating the conductive structure 1300 and forming the first conductive structure 1310 and the second conductive structure 1320 adjacently distributed along the second direction Y, the area occupied by the first conductive structure 1310 or the second conductive structure 1320 in each memory block can be significantly smaller than the area of ​​the conductive structure 1300, for example, approximately half the area of ​​the conductive structure 1300. This helps ensure that the space occupied by the first conductive structure 1310 and / or the second conductive structure 1320 for extracting the conductive layers from different stacks is reduced without increasing the difficulty of forming the conductive structure 1300 (i.e., without reducing the area of ​​the conductive structure 1300). This further helps reduce the area of ​​the semiconductor structure, increase the operating speed of the semiconductor structure, improve the packaging efficiency of the semiconductor structure, and ultimately improve the overall performance of the semiconductor structure.

[0110] Figure 28 12 is a schematic structural diagram after forming a third dummy channel hole 1231 , a fourth dummy channel hole 1241 , a fifth dummy channel hole 1251 and a sixth dummy channel hole 1261 according to an exemplary embodiment of the present application.

[0111] For example, Figure 28 As shown, a third dummy channel hole 1231 may be formed penetrating the stacked structure 1100 and located on a side closer to the first conductive structure 1310 relative to the second conductive structure 1320 along the second direction Y. By way of example, a fourth dummy channel hole 1241 may also be formed penetrating the stacked structure 1100 and located on a side closer to the second conductive structure 1320 relative to the first conductive structure 1310 along the second direction Y. By way of example, a fifth dummy channel hole 1251 may also be formed penetrating the stacked structure 1100 and located between the plurality of third dummy channel holes 1231 along the first direction X. By way of example, a sixth dummy channel hole 1261 may also be formed penetrating the stacked structure 1100 and located between the plurality of fourth dummy channel holes 1241 along the first direction X.

[0112] By way of example, the third dummy channel hole 1231 and the fifth dummy channel hole 1251 may be formed by removing the second sacrificial material layer 220 of the third dummy channel structure 1230 and the fifth dummy channel structure 1250, respectively. By way of example, the fourth dummy channel hole 1241 and the sixth dummy channel hole 1261 may be formed by removing the third sacrificial material layer 230 of the fourth dummy channel structure 1240 and the sixth dummy channel structure 1260, respectively. By way of example, the third dummy channel hole 1231, the fifth dummy channel hole 1251, the fourth dummy channel hole 1241, and the sixth dummy channel hole 1261 may be formed in the same process.

[0113] For example, the process of removing the second sacrificial material layer 220 and the third sacrificial material layer 230 is similar to the process of removing the first sacrificial material layer 210. Therefore, to avoid redundancy, the process of removing the second sacrificial material layer 220 and the third sacrificial material layer 230 will not be described in detail herein.

[0114] Figure 29 1 is a structural diagram of the enlarged third dummy channel hole 1231 , the fourth dummy channel hole 1241 , the fifth dummy channel hole 1251 and the sixth dummy channel hole 1261 according to an exemplary embodiment of the present application. Figure 30 yes Figure 29 Schematic diagram of the partial cross-section structure along the CC direction. Figure 31 yes Figure 29 Schematic diagram of the partial cross-section structure along the DD direction.

[0115] For example, Figure 29 As shown, the third dummy channel hole 1231 can be expanded to separate the first conductive structure 1310 to form a first contact conductive layer 1311 and a second contact conductive layer 1312 adjacently distributed along the first direction X. For example, as Figure 30 As shown, the first contact conductive layer 1311 can extend to a height corresponding to the first sub-dielectric layer 1111. The second contact conductive layer 1312 can extend to a height corresponding to the second sub-dielectric layer 1112. The first contact conductive layer 1311 and the second contact conductive layer 1312 can be used to achieve electrical connection with conductive layers in different stacks (formed by replacing the first dielectric layer 1110), thereby leading out current.

[0116] For example, Figure 29 As shown, enlarging the third dummy channel hole 1231 until the third dummy channel hole 1231 separates the first conductive structure 1310 may include: enlarging the third dummy channel hole 1231 and the fifth dummy channel hole 1251 until the third dummy channel hole 1231 separates the first conductive structure 1310 and the third dummy channel hole 1231 and the fifth dummy channel hole 1251 are connected along the first direction X. For example, as Figure 29 and Figure 31 As shown, the third dummy channel hole 1231 and the fifth dummy channel hole 1251 are connected along the first direction X to form a gate line gap 800 extending along the first direction X. The gate line gap 800 can divide the stacked structure 1100 into a plurality of memory blocks.

[0117] For example, Figure 29As shown, the fourth dummy channel hole 1241 can be expanded to separate the second conductive structure 1320, forming a third contact conductive layer 1321 and a fourth contact conductive layer 1322 adjacent to each other along the first direction X. It should be understood that the third contact conductive layer 1321 and the first contact conductive layer 1311 can have a substantially symmetrical structure along the first direction X, and the third contact conductive layer 1321 can extend to a height corresponding to the first sub-dielectric layer 1111. The fourth contact conductive layer 1322 and the second contact conductive layer 1312 can have a substantially symmetrical structure along the first direction X, and the fourth contact conductive layer 1322 can extend to a height corresponding to the second sub-dielectric layer 1112. The third contact conductive layer 1321 and the fourth contact conductive layer 1322 can be used to establish electrical connections with conductive layers in different stacks (formed by replacing the first dielectric layer 1110), thereby conducting current.

[0118] For example, Figure 29 As shown, enlarging the fourth virtual channel hole 1241 to the fourth virtual channel hole 1241 to separate the second conductive structure 1320 may include: enlarging the fourth virtual channel hole 1241 and the sixth virtual channel hole 1261 to the fourth virtual channel hole 1241 to separate the second conductive structure 1320 and the fourth virtual channel hole 1241 and the sixth virtual channel hole 1261 are connected along the first direction X. For example, as Figure 29 and Figure 31 As shown, the fourth dummy channel hole 1241 and the sixth dummy channel hole 1261 are connected along the first direction X to form another gate line gap 800 extending along the first direction X.

[0119] In the present application, the gate line gap 800 and the filling material layer 700 and the filling dielectric layer 600 connected along the first direction X can be used to divide the stacked structure 1100 into multiple memory blocks. Figure 29 As shown, at least one memory block is formed between the filling material layer 700 and the filling dielectric layer 600 that are connected to the adjacent gate line gap 800 along the first direction X. That is, the first contact conductive layer 1311 and the second contact conductive layer 1312 that extend to heights corresponding to the first dielectric layer 1110 at different heights can be located in the same memory block, and the third contact conductive layer 1321 and the fourth contact conductive layer 1322 that extend to heights corresponding to the first dielectric layer 1110 at different heights can be located in the same memory block.

[0120] In a memory block where the first and second contact conductive layers 1311 and 1312 are located, the first and second contact conductive layers 1311 and 1312 can be used to establish electrical connections with conductive layers in different stacks (formed by replacing the first dielectric layer 1110), thereby drawing current. By separating the first conductive structure 1310 and forming the first and second contact conductive layers 1311 and 1312 adjacently distributed along the first direction X, the area occupied by the first and second contact conductive layers 1311 and 1312 in the memory block can be significantly smaller than the area of ​​the first conductive structure 1310, for example, approximately half the area of ​​the first conductive structure 1310, and further significantly smaller than the area of ​​the conductive structure 1300, for example, approximately one-quarter the area of ​​the conductive structure 1300. This helps to ensure that the space occupied by the first contact conductive layer 1311 and / or the second contact conductive layer 1312 that lead out the conductive layers in different stacks is reduced without increasing the difficulty of the formation process of the conductive structure 1300 (i.e., without reducing the area of ​​the conductive structure 1300), which is conducive to further reducing the area of ​​the semiconductor structure, increasing the operating speed of the semiconductor structure, improving the packaging effect of the semiconductor structure, and thus improving the overall performance of the semiconductor structure.

[0121] For example, the gate line gap 800 can also serve as a path for providing an etchant. For example, the gate line gap 800 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate line gap 800 can penetrate the stacked structure 1100 along the third direction D and can extend along the first direction X. As an option, Figure 31 As shown, the gate line slit 800 may penetrate the stacked structure 1100 along the third direction D and extend to the substrate 100 .

[0122] Figures 32 to 34 1 is a schematic structural diagram after forming a conductive layer 1130, a gate line gap structure 1400, and a channel structure 1500 according to an exemplary embodiment of the present application, wherein: Figure 33 yes Figure 32 Schematic diagram of partial cross-section structure along DD direction, Figure 34 yes Figure 32 Schematic diagram of the partial cross-section structure along the EE direction.

[0123] For example, Figure 32 As shown, the through hole 300 (i.e., the space where the first contact conductive layer 1311, the second contact conductive layer 1312, the third contact conductive layer 1321, and the fourth contact conductive layer 1322 are located) can be located in the connection region A of the semiconductor structure. The gate line gap 800 (i.e., the space where the gate line gap structure 1400 is located) can extend from the connection region A to the array region B of the semiconductor structure, which is adjacent to the connection region A. For example, the connection region A can be adjacent to the array region B along the first direction X.

[0124] For example, Figure 32 and Figure 33 As shown, a portion of the first dielectric layer 1110 may be replaced with a conductive layer 1130 via the gate line gap 800 ; and a gate line gap structure 1400 may be formed in the gate line gap 800 .

[0125] For example, Figure 32 and Figure 33 As shown, the first dielectric layer 1110 near the gate line slit 800 in the connection region A can be replaced with a conductive layer 1130 via the gate line slit 800. Portions of the first dielectric layer 1110, which are penetrated by the first contact conductive layer 1311, the second contact conductive layer 1312, the third contact conductive layer 1321, and the fourth contact conductive layer 1322 and are away from the gate line slit 800, may not be replaced with the conductive layer 1130. The first dielectric layer 1110 and the second dielectric layer 1120 that are not replaced with the conductive layer 1130 may form a first stacked structure 1100-1. That is, the first stacked structure 1100-1 may be located in the connection region A and may include the first dielectric layers 1110 and the second dielectric layers 1120 that are alternately stacked.

[0126] For example, Figure 32 and Figure 34 As shown, the first dielectric layer 1110 in array region B can be replaced with a conductive layer 1130 via the gate line gap 800. That is, both the first dielectric layer 1110 near the gate line gap 800 in connection region A and the first dielectric layer 1110 in array region B can be replaced with the conductive layer 1130. The second dielectric layer 1120 in array region B can be referred to as the first dielectric layer 1140. The first dielectric layer 1140 and the conductive layer 1130 can be formed into a second stacked structure 1100-2. That is, the second stacked structure 1100-2 can surround the first stacked structure 1100-1 and extend from the connection region A to the array region B, including alternating conductive layers 1130 and first dielectric layers 1140. The conductive layer 1130 can contact the first dielectric layer 1110, and the first dielectric layer 1140 can contact the second dielectric layer 1120.

[0127] For example, the first conductive contact layer 1311 and the second conductive contact layer 1312 may extend to the conductive layer 1130 at different heights, thereby drawing current out of the conductive layer 1130. The third conductive contact layer 1321 and the fourth conductive contact layer 1322 may extend to the conductive layer 1130 at different heights, thereby drawing current out of the conductive layer 1130.

[0128] For example, a portion of the first dielectric layer 1110 can be removed through the gate line gap 800 by using a process such as wet etching; then, a conductive layer 1130 can be formed in the removed space by using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0129] For example, the material of conductive layer 1130 may include at least one of polycrystalline silicon (p-Si, poly-Si), titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (ITO, In-Ti-O), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), and the like. Conductive layer 1130 may serve as the control gate of each layer of memory cells, improving the control gate's control capability.

[0130] For example, the gate line gap 800 can be filled with an insulating material 1410 and a dielectric material 1420 in sequence from the outside to the inside to form a gate line gap structure 1400. By filling the inner wall of the gate line gap 800 with the insulating material 1410, the present application can disconnect adjacent conductive layers 1130, thereby avoiding the subsequent phenomenon of electrically connecting different stacked conductive layers 1130.

[0131] For example, after filling the insulating material 1410, the remaining area of ​​the gate line gap 800 may be filled with a dielectric material 1420 to form a gate line gap structure 1400. The gate line gap structure 1400 may be used to divide the storage area into multiple storage blocks. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to fill the remaining area of ​​the gate line gap 800 with the dielectric material 1420 to form the gate line gap structure 1400. The dielectric material 1420 may be an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or a semiconductor material such as polysilicon, which is not limited in this application.

[0132] For example, Figure 32 and Figure 34 As shown, a channel structure 1500 penetrating the second stacked structure 1100-2 may be formed in the array region B. For example, the first contact conductive layer 1311, the second contact conductive layer 1312, the third contact conductive layer 1321, and the fourth contact conductive layer 1322 may be connected to the channel structure 1500 via the conductive layer 1130, respectively, to transmit electrical signals between the outside world and the channel structure 1500.

[0133] The channel structure 1500 may include a blocking layer (not shown) extending along the stacking direction Z, a charge trapping layer (not shown) sequentially distributed on a side of the blocking layer away from the second stacked structure 1100 - 2 , a tunneling layer (not shown), and a channel layer (not shown).

[0134] For example, the channel structure 1500 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Specifically, a blocking layer, a charge trapping layer, a tunneling layer, and a channel layer can be sequentially formed from the outside to the inside within the channel hole (not shown); a channel filling dielectric layer (not shown) and a channel plug (not shown) can also be formed. It should be understood that the channel structure 1500 can extend along the stacking direction Z to the substrate 100.

[0135] A blocking layer may be located on the inner wall of the channel hole to block charge outflow. A charge trapping layer may be located on the surface of the blocking layer to store charge during operation of the semiconductor structure. A tunneling layer may be located on the surface of the charge trapping layer. The blocking layer may include one or more layers, each of which may include one or more materials. Materials for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. The charge trapping layer may include one or more layers, each of which may include one or more materials. Materials for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide-bandgap material, etc. The tunneling layer may include one or more layers, each of which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. By way of example, the blocking layer, charge trapping layer, and tunneling layer may be formed as functional layers. The functional layer may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that the functional layer may also have a structure other than an ONO configuration. For example, the functional layer may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0136] The channel layer may include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon. The material of the channel layer includes but is not limited to P-type doped polycrystalline silicon. Specifically, a filling semiconductor material may be used to fill the channel hole to form a channel layer. The filling medium may include an oxidizing medium layer, such as silicon oxide. Exemplarily, during the filling process, a plurality of insulating gaps may be formed in the filling medium layer by controlling the channel filling process to reduce structural stress. The channel layer can be used to transport the required charges (electrons or holes). Exemplarily, a channel layer may be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0137] In addition, the channel structure also includes a channel plug formed at one end of the channel layer away from the substrate 100 (which can be understood as the top of the channel structure 1500). Specifically, the channel plug can be formed in the portion of the channel filling dielectric layer located at the top of the channel hole. The channel plug can be made of the same material as the channel layer, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer.

[0138] Figures 32 to 34 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0139] The semiconductor structure may include a first stacked structure 1100 - 1 , a second stacked structure 1100 - 2 , a plurality of dummy channel structures 1200 , a first contact structure (including a first conductive structure 1310 ), and a second contact structure (including a first conductive structure 1320 ).

[0140] like Figure 32 and Figure 33 As shown, the first stacked structure 1100-1 may be located in the connection region A and may include first dielectric layers 1110 and second dielectric layers 1120 that are alternately stacked. Figure 32 and Figure 34 As shown, the second stacked structure 1100-2 may surround the first stacked structure 1100-1 and may extend from the connection area A to the array area B adjacent to the connection area A along the first direction X. The second stacked structure 1100-2 may include conductive layers 1130 and first dielectric layers 1140 stacked alternately. The conductive layer 1130 may contact the first dielectric layer 1110, and the first dielectric layer 1140 may contact the second dielectric layer 1120. For example, as shown in FIG. Figure 33 and Figure 34 As shown, a first stacked structure 1100 - 1 and a second stacked structure 1100 - 2 may be located on a substrate 100 .

[0141] It should be understood that a first dielectric layer 1110 and a second dielectric layer 1120 may form a stack, and the first stack structure 1100-1 may include multiple stacks. The number and thickness of the first dielectric layer 1110 and the second dielectric layer 1120 are not limited to Figure 33 , without departing from the concept of the present application, those skilled in the art may set any number and thickness of the first dielectric layer 1110 and the second dielectric layer 1120 as needed. In addition, the thickness of the first dielectric layer 1110 may be greater than the thickness of the second dielectric layer 1120. The materials of the first dielectric layer 1110 and the second dielectric layer 1120 may be selected from suitable materials known in the art. For example, the material of the first dielectric layer 1110 may include a nitride such as silicon nitride, and the material of the second dielectric layer 1120 may include an oxide such as silicon oxide.

[0142] A conductive layer 1130 and a first dielectric layer 1140 can form a stack, and the second stack structure 1100-2 can include multiple stacks. The number and thickness of the conductive layer 1130 and the first dielectric layer 1110 can correspond one-to-one, and the number and thickness of the first dielectric layer 1140 and the second dielectric layer 1120 can correspond one-to-one. Furthermore, the materials for the conductive layer 1130 and the first dielectric layer 1140 can be selected from suitable materials known in the art. For example, the material of the conductive layer 1130 can include a conductive material such as tungsten, and the material of the first dielectric layer 1140 can be the same as that of the second dielectric layer 1120, such as an oxide such as silicon oxide. The conductive layer 1130 can serve as the control gate of each layer of memory cells, improving the control capability of the control gate.

[0143] The substrate 100 may be, for example, a polycrystalline silicon substrate, a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 100 may also be a multilayer structure, such as Si / SiGe. In other embodiments, the substrate 100 may also be other epitaxial structures, such as silicon germanium on insulator (SGOI).

[0144] For example, the plurality of dummy channel structures 1200 may include a first dummy channel structure 1210 and a second dummy channel structure 1220 penetrating the first stacked structure 1100 - 1 and adjacently distributed along the first direction X. The first dummy channel structure 1210 and the second dummy channel structure 1220 may include a filling material layer 700 .

[0145] The first contact structure may include a first conductive structure 1310 extending along the stacking direction Z of the first stacked structure 1100-1 to the first dielectric layer 1110. The second contact structure may be adjacent to the first contact structure along the second direction Y and include a second conductive structure 1320 extending along the stacking direction Z to the first dielectric layer 1110. For example, the first conductive structure 1310 and the second conductive structure 1320 may be substantially symmetrical along the first direction X.

[0146] For example, Figure 32As shown, the first direction X, the second direction Y, and the stacking direction Z may intersect in pairs. The first conductive structure 1310 and the second conductive structure 1320 may contact the conductive layer 1130 along the second direction Y. Part of the first dummy channel structure 1210 and part of the second dummy channel structure 1220 may be located between the first conductive structure 1310 and the second conductive structure 1320. The filling material layer 700 in the first and second dummy channel structures 1210 and 1220 may be connected to the filling dielectric layer 600 between the first and second conductive structures 1310 and 1320 along the first direction X. The filling material layer 700 and the filling dielectric layer 600 connected along the first direction X may divide the first stacked structure 1100-1 and the second stacked structure 1100-2 into multiple memory blocks.

[0147] In an exemplary embodiment of the present application, a first conductive structure 1310 may extend to the first dielectric layer 1110 in multiple stacks, such as two adjacent stacks. In other words, the bottom surface of the first conductive structure 1310 may have a stepped structure, i.e., a height difference. Of course, in another exemplary embodiment of the present application, a first conductive structure 1310 may extend to the first dielectric layer 1110 in a stack (including a first dielectric layer 1110 and a second dielectric layer 1120). In other words, the bottom surface of the first conductive structure 1310 may be a substantially flat surface, i.e., without a height difference. It should be understood that the structure of the second conductive structure 1320 may be the same as that of the first conductive structure 1310. To avoid redundancy, the structure of the second conductive structure 1320 will not be described in detail herein.

[0148] Exemplarily, the materials of the first conductive structure 1310 and the second conductive structure 1320 may include at least one of conductive materials such as polycrystalline silicon (p-Si, poly-Si), titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (ITO, In-Ti-O), aluminum (Al), copper (Cu), ruthenium (Ru), and silver (Ag).

[0149] The following describes in detail the first conductive structure 1310 extending to the first dielectric layer 1110 in two adjacent stacked layers as an example.

[0150] For example, the first contact structure further includes a first filling dielectric layer located on a side of the first conductive structure 1310 away from the first stacked structure 1100-1. The second contact structure further includes a second filling dielectric layer located on a side of the second conductive structure 1320 away from the first stacked structure 1100-1. Figure 32As shown, the first filling dielectric layer and the second filling dielectric layer are in contact with each other and can form a filling dielectric layer 600 of an integral structure. The material of the filling dielectric layer 600 may include an oxide such as silicon oxide. For example, the filling material layer 700 in the first dummy channel structure 1210 and the second dummy channel structure 1220 can both be in contact with the filling dielectric layer 600.

[0151] In the present application, the first conductive structure 1310 and the second conductive structure 1320 can be used to establish electrical connections with the conductive layers 1130 in different stacks, thereby drawing current out. By providing the first conductive structure 1310 and the second conductive structure 1320, the area occupied by the first conductive structure 1310 or the second conductive structure 1320 in each memory block can be significantly smaller than the area of ​​the conductive structure 1300, for example, approximately half the area of ​​the conductive structure 1300. This helps reduce the space occupied by the first conductive structure 1310 and / or the second conductive structure 1320, which draws the conductive layers 1130 in different stacks out, thereby reducing the area of ​​the semiconductor structure, increasing the operating speed of the semiconductor structure, improving the packaging efficiency of the semiconductor structure, and ultimately improving the overall performance of the semiconductor structure.

[0152] For example, reference may be made to Figure 27 The first dielectric layer 1110 to which the first conductive structure 1310 extends may include a first sub-dielectric layer 1111 and a second sub-dielectric layer 1112 located at different heights. In other words, the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 may be located in different stacks. For example, the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112 may be located in two adjacent stacks. For example, the second conductive structure 1320 may also extend to a height corresponding to the first sub-dielectric layer 1111 and the second sub-dielectric layer 1112.

[0153] like Figure 32As shown, the multiple dummy channel structures 1200 may further include a third dummy channel structure 1230, a fourth dummy channel structure 1340, a fifth dummy channel structure 1250, and a sixth dummy channel structure 1260 that penetrate the second stacked structure 1100-2. The third dummy channel structure 1230 may be located on a side of the second conductive structure 1320 closer to the first conductive structure 1310 along the second direction Y. The fourth dummy channel structure 1340 may be located on a side of the first conductive structure 1310 closer to the second conductive structure 1320 along the second direction Y. The fifth dummy channel structure 1250 may be located between the multiple third dummy channel structures 1230 along the first direction X. The sixth dummy channel structure 1260 may be located between the multiple fourth dummy channel structures 1240 along the first direction X. For example, the third dummy channel structure 1230 and the fifth dummy channel structure 1250 may be connected along the first direction X to form the gate line gap structure 1400. The fourth dummy channel structure 1240 and the sixth dummy channel structure 1260 may be connected along the first direction X to form another gate line gap structure 1400 .

[0154] For example, Figure 32 As shown, the gate line gap structure 1400 may include, from the outside inward, a filling insulating material 1410 and a dielectric material 1420. Gate line gap structure 1400 may be used to divide the storage area into multiple storage blocks. Dielectric material 1420 may be an insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, or a semiconductor material such as polysilicon, although this application does not limit this.

[0155] For example, Figure 32 As shown, the first conductive structure 1310 may include a first contact conductive layer 1311 and a second contact conductive layer 1312 . A portion of the third dummy channel structure 1230 is located between the first contact conductive layer 1311 and the second contact conductive layer 1312 .

[0156] The first contact conductive layer 1311 may contact the conductive layer 1130 and may extend to the first sub-dielectric layer 1111 along the stacking direction Z. The second contact conductive layer 1312 may contact the conductive layer 1130, be adjacent to the first contact conductive layer 1311 along the first direction X, and extend to the second sub-dielectric layer 1112 along the stacking direction Z. The first contact conductive layer 1311 and the second contact conductive layer 1312 may be used to establish electrical connections with the conductive layers 1130 in different stacks, thereby conducting current.

[0157] For example, Figure 32 As shown, the second conductive structure 1320 may include a third contact conductive layer 1321 and a fourth contact conductive layer 1322 . A portion of the fourth dummy channel structure 1240 may be located between the third contact conductive layer 1321 and the fourth contact conductive layer 1322 .

[0158] It should be understood that the third conductive contact layer 1321 and the first conductive contact layer 1311 may have a substantially symmetrical structure along the first direction X. The fourth conductive contact layer 1322 and the second conductive contact layer 1312 may have a substantially symmetrical structure along the first direction X. The third conductive contact layer 1321 may contact the conductive layer 1130 and extend along the stacking direction Z to the first sub-dielectric layer 1111. The fourth conductive contact layer 1322 may contact the conductive layer 1130 and be adjacent to the third conductive contact layer 1321 along the first direction X, and extend along the stacking direction Z to the second sub-dielectric layer 1112. The third conductive contact layer 1321 and the fourth conductive contact layer 1322 may be used to establish electrical connections with the conductive layers 1130 in different stacks, thereby extracting current.

[0159] For example, Figure 32 and Figure 33 As shown, the first contact structure may further include a first barrier layer located between the first conductive structure 1310 and the first stacked structure 1100-1 and extending along the stacking direction Z, wherein the first barrier layer may be a portion of the barrier layer 410. The second contact structure may further include a second barrier layer located between the second conductive structure 1320 and the first stacked structure 1100-1 and extending along the stacking direction Z, wherein the second barrier layer may be another portion of the barrier layer 410. The first barrier layer and the second barrier layer may be made of the same material and may be the same material as the second dielectric layer 1120, such as an oxide such as silicon oxide.

[0160] In the present application, the gate line gap structure 1400 and the filling material layer 700 and the filling dielectric layer 600 connected along the first direction X can be used to divide the first stacked structure 1100-1 and the second stacked structure 1100-2 into multiple memory blocks. Figure 32 As shown, at least one memory block is formed between the filling material layer 700 and the filling dielectric layer 600 that are connected to the adjacent gate line gap structure 1400 along the first direction X. That is, the first contact conductive layer 1311 and the second contact conductive layer 1312 that extend to heights corresponding to the first dielectric layer 1110 at different heights can be located in the same memory block, and the third contact conductive layer 1321 and the fourth contact conductive layer 1322 that extend to heights corresponding to the first dielectric layer 1110 at different heights can be located in the same memory block.

[0161] In a memory block where the first and second contact conductive layers 1311 and 1312 are located, the first and second contact conductive layers 1311 and 1312 can be used to establish electrical connections with the conductive layer 1130 in a different stack, thereby drawing current out. By providing the first and second contact conductive layers 1311 and 1312, the area occupied by the first and second contact conductive layers 1311 and 1312 in the memory block can be significantly smaller than the area of ​​the first conductive structure 1310, for example, approximately half the area of ​​the first conductive structure 1310, and further significantly smaller than the area of ​​the conductive structure 1300, for example, approximately one-quarter the area of ​​the conductive structure 1300. This helps to ensure that the space occupied by the first contact conductive layer 1311 and / or the second contact conductive layer 1312 that lead out the conductive layers in different stacks is reduced without increasing the difficulty of the formation process of the conductive structure 1300 (i.e., without reducing the area of ​​the conductive structure 1300), which is conducive to further reducing the area of ​​the semiconductor structure, increasing the operating speed of the semiconductor structure, improving the packaging effect of the semiconductor structure, and thus improving the overall performance of the semiconductor structure.

[0162] For example, Figure 34 As shown, the semiconductor structure may further include a channel structure 1500 located in the array region B and extending through the second stacked structure 1100-2. For example, the first contact conductive layer 1311, the second contact conductive layer 1312, the third contact conductive layer 1321, and the fourth contact conductive layer 1322 may be connected to the channel structure 1500 via the conductive layer 1130, respectively, to transmit electrical signals between the outside world and the channel structure 1500.

[0163] The channel structure 1500 may include a blocking layer (not shown) extending along the stacking direction Z, a charge trapping layer (not shown) sequentially distributed on a side of the blocking layer away from the second stacked structure 1100 - 2 , a tunneling layer (not shown), and a channel layer (not shown).

[0164] A blocking layer may be located on the inner wall of the channel hole to block charge outflow. A charge trapping layer may be located on the surface of the blocking layer to store charge during operation of the semiconductor structure. A tunneling layer may be located on the surface of the charge trapping layer. The blocking layer may include one or more layers, each of which may include one or more materials. Materials for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. The charge trapping layer may include one or more layers, each of which may include one or more materials. Materials for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide-bandgap material, etc. The tunneling layer may include one or more layers, each of which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. By way of example, the blocking layer, charge trapping layer, and tunneling layer may be formed as functional layers. The functional layer may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that the functional layer may also have a structure other than an ONO configuration. For example, the functional layer may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0165] The channel layer may include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon. The material of the channel layer includes but is not limited to P-type doped polycrystalline silicon. Specifically, a filling semiconductor material may be used to fill the channel hole to form a channel layer. The filling medium may include an oxidizing medium layer, such as silicon oxide. Exemplarily, during the filling process, a plurality of insulating gaps may be formed in the filling medium layer by controlling the channel filling process to reduce structural stress. The channel layer can be used to transport the required charges (electrons or holes). Exemplarily, a channel layer may be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0166] In addition, the channel structure also includes a channel plug formed at one end of the channel layer away from the substrate 100 (which can be understood as the top of the channel structure 1500). Specifically, the channel plug can be formed in the portion of the channel filling dielectric layer located at the top of the channel hole. The channel plug can be made of the same material as the channel layer, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer.

[0167] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, related or similar contents will not be described in detail herein.

[0168] Although the exemplary structure and fabrication method of the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced, or added to the fabrication method of the semiconductor structure. In addition, the illustrated layers and their materials are merely exemplary.

[0169] Figure 35 2 is a schematic block diagram of a memory according to an exemplary embodiment of the present application. The memory 2000 may include a memory cell array 2100 and a peripheral circuit 2200 .

[0170] The memory cell array 2100 and the peripheral circuit 2200 may be separately formed on different substrates and then bonded to form the memory 2000 .

[0171] The peripheral circuit 2200 may be coupled to the memory cell array 2100. The peripheral circuit 2200 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array 2100. For example, the peripheral circuit 2200 may include one or more of a page buffer, decoders (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., a transistor, a diode, a resistor, or a capacitor).

[0172] The memory cell array 2100 may include a semiconductor structure as described in any embodiment of the present application. For example, the memory cell array 2100 may include a plurality of memory cells, such as NAND memory cells. NAND memory cells are capable of maintaining a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the memory cell region. Each memory cell may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0173] Figure 36 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0174] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having the storage system 12 located therein. Figure 36As shown, system 10 may include a host 18 and a storage system 12 having one or more memories, such as a three-dimensional memory 14, and a controller 17. Host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0175] The three-dimensional memory 14 may include a semiconductor structure as described in any of the embodiments herein. According to some embodiments, a controller 17 is coupled to the three-dimensional memory 14 and a host 18 and is configured to control the three-dimensional memory 14. The controller 17 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 17 is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the controller 17 is designed to operate in a high-duty-cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The controller 17 may be configured to control operations of the three-dimensional memory 14, such as read, erase, and program operations. The controller 17 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the controller 17 is further configured to process error correction code (ECC) associated with data read from or written to the three-dimensional memory 14. The controller 17 may also perform any other appropriate functions, such as formatting the three-dimensional memory 14. The controller 17 may communicate with an external device (e.g., a host computer 18) according to a specific communication protocol. For example, the controller 17 may communicate with the external device via at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-Express, PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, and the like.

[0176] The controller 17 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of final electronic products. Figure 37AIn one example shown in FIG, the controller 17 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Figure 36 The host 18 in the memory card connector 24 is coupled. Figure 37B In another example shown in FIG, the controller 17 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 36 In some embodiments, the SSD 26 has a storage capacity and / or an operating speed that is higher than that of the memory card 22.

[0177] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Alternately stacking first dielectric layers and second dielectric layers to form a laminated structure; forming a through hole extending to the first dielectric layer in a direction opposite to the stacking direction of the stacked structure and a barrier layer extending along the stacking direction on a sidewall of the through hole; removing a portion of the first dielectric layer through the through hole to form a sacrificial gap, wherein a length of the sacrificial gap along the first direction is greater than a length of the through hole along the first direction; forming a conductive structure on a side of the barrier layer away from the stacked structure and in the sacrificial gap; forming a first dummy channel hole and a second dummy channel hole penetrating the stacked structure and located on both sides of the through hole along the first direction; as well as The first virtual channel hole and the second virtual channel hole are enlarged to separate the conductive structure to form a first conductive structure and a second conductive structure adjacent to each other along the second direction. The first direction, the second direction and the stacking direction intersect with each other.

2. The method according to claim 1, wherein Enlarging the first virtual channel hole and the second virtual channel hole to separate the conductive structure from the first virtual channel hole and the second virtual channel hole includes: removing the portion of the conductive structure exposed by the sacrificial gap through the through hole; and The first dummy channel hole and the second dummy channel hole are enlarged to the first dummy channel hole and the second dummy channel hole to separate the conductive structure.

3. The method according to claim 1 or 2, wherein: The method further comprises: forming a first dummy channel structure and a second dummy channel structure penetrating the stacked structure and including a first sacrificial material layer; The method of forming a first virtual channel hole and a second virtual channel hole penetrating the stacked structure and located on both sides of the through hole along the first direction includes: The first sacrificial material layer of the first dummy channel structure and the second dummy channel structure is removed to form the first dummy channel hole and the second dummy channel hole, respectively.

4. The method according to claim 3, wherein: The method further comprises: A filling dielectric layer is formed in the remaining space of the through hole except the barrier layer and the remaining conductive structure; The step of enlarging the first virtual channel hole and the second virtual channel hole to separate the conductive structure into the first virtual channel hole and the second virtual channel hole comprises: Enlarging the first dummy channel hole and the second dummy channel hole to separate the conductive structure and expose the filling dielectric layer; and A filling material layer is formed in the enlarged first dummy channel hole and the second dummy channel hole, wherein the filling material layer and the filling dielectric layer are connected along the first direction.

5. The method according to claim 2, wherein: The first dielectric layer to which the through hole extends includes a first sub-dielectric layer and a second sub-dielectric layer located at different heights. Wherein, removing a portion of the first dielectric layer through the through hole to form a sacrificial gap includes: A portion of the first sub-dielectric layer and the second sub-dielectric layer is removed through the through hole to form a sacrificial gap, wherein the first conductive structure and the second conductive structure are extended to a height corresponding to the first sub-dielectric layer and the second sub-dielectric layer, The semiconductor structure further includes a third dummy channel hole penetrating the stacked structure and located on a side of the second conductive structure closer to the first conductive structure along the second direction. The method further comprises: The first conductive structure is separated by enlarging the third virtual channel hole to the third virtual channel hole to form a first contact conductive layer and a second contact conductive layer adjacently distributed along the first direction, wherein the first contact conductive layer extends to a height corresponding to the first sub-dielectric layer, and the second contact conductive layer extends to a height corresponding to the second sub-dielectric layer.

6. The method according to claim 5, wherein: The semiconductor structure further includes a fourth dummy channel hole penetrating the stacked structure and located on a side of the first conductive structure closer to the second conductive structure along the second direction. The method further comprises: The fourth virtual channel hole is enlarged to the fourth virtual channel hole to separate the second conductive structure, forming a third contact conductive layer and a fourth contact conductive layer adjacently distributed along the first direction, wherein the third contact conductive layer extends to a height corresponding to the first sub-dielectric layer, and the fourth contact conductive layer extends to a height corresponding to the second sub-dielectric layer.

7. The method according to claim 5 or 6, wherein: The semiconductor structure further includes a fifth dummy channel hole penetrating the stacked structure and located between the plurality of third dummy channel holes along the first direction. The step of enlarging the third dummy channel hole to separate the first conductive structure includes: The third dummy channel hole and the fifth dummy channel hole are enlarged until the third dummy channel hole separates the first conductive structure and the third dummy channel hole and the fifth dummy channel hole are connected along the first direction.

8. The method according to claim 7, wherein: The method further comprises: forming a third dummy channel structure and a fifth dummy channel structure penetrating the stacked structure and including a second sacrificial material layer; The step of enlarging the third dummy channel hole to separate the first conductive structure includes: removing the second sacrificial material layer of the third dummy channel structure and the fifth dummy channel structure to form a third dummy channel hole and a fifth dummy channel hole, respectively; and The third dummy channel hole and the fifth dummy channel hole are enlarged until the third dummy channel hole separates the first conductive structure and the third dummy channel hole and the fifth dummy channel hole are connected along the first direction.

9. The method according to claim 8, wherein The third dummy channel hole and the fifth dummy channel hole are connected along the first direction to form a gate line gap extending along the first direction; The method further comprises: replacing a portion of the first dielectric layer with a conductive layer via the gate line gaps; and A gate line gap structure is formed in the gate line gap.

10. The method according to claim 5, wherein The method further comprises: removing a portion of the first dielectric layer and the second dielectric layer to form a step structure, wherein the second dielectric layer in the step structure is exposed; forming an initial through hole extending along the stacking direction, wherein the initial through hole moves the step structure to the first sub-dielectric layer, and the exposed second dielectric layer in the step structure includes a third sub-dielectric layer located on a surface of the first sub-dielectric layer and a fourth sub-dielectric layer located on a surface of the second sub-dielectric layer; forming a barrier layer and a first barrier layer on the sidewall of the initial through hole and the surface of the step structure respectively; The first barrier layer, the third sub-dielectric layer and the fourth sub-dielectric layer contacting the first barrier layer are removed to form the through hole, wherein the first sub-dielectric layer and the second sub-dielectric layer are exposed by the through hole.

11. The method according to claim 10, wherein: The method further comprises: A second barrier layer is formed on the sidewall of the step structure, wherein a portion of the conductive structure exposed by the sacrificial gap covers the second barrier layer. Removing the portion of the conductive structure exposed by the sacrificial gap through the through hole includes: The portion of the conductive structure exposed by the sacrificial gap is removed through at least one removal process.

12. The method according to claim 9, wherein The through hole is located in the connection area of ​​the semiconductor structure, and the gate line gap extends from the connection area to the array area of ​​the semiconductor structure adjacent to the connection area. The method further comprises: A channel structure penetrating the stacked structure is formed in the array region, and the channel structure includes a blocking layer extending along the stacking direction, a charge trapping layer, a tunneling layer, and a channel layer sequentially distributed on a side of the blocking layer away from the stacked structure.

13. A semiconductor structure, wherein: include: The first stacked structure is located in the connection area and includes first dielectric layers and second dielectric layers stacked alternately. a second stacked structure surrounding the first stacked structure and extending from the connection area to an array area adjacent to the connection area along a first direction, comprising alternatingly stacked conductive layers and first dielectric layers, wherein the conductive layers are in contact with the first dielectric layers, and the first dielectric layers are in contact with the second dielectric layers; a plurality of dummy channel structures, including a first dummy channel structure and a second dummy channel structure penetrating the first stacked structure and adjacently distributed along the first direction; A first contact structure includes a first conductive structure extending to the first dielectric layer along a stacking direction of the first stacked structure; a second contact structure, distributed adjacent to the first contact structure along a second direction, comprising a second conductive structure along the stacking direction and extending to the first dielectric layer; The first conductive structure and the second conductive structure are in contact with the conductive layer along the second direction, and part of the first dummy channel structure and part of the second dummy channel structure are both located between the first conductive structure and the second conductive structure; The first direction, the second direction and the stacking direction intersect with each other.

14. The semiconductor structure according to claim 13, wherein: The first contact structure further includes a first filling dielectric layer located on a side of the first conductive structure away from the first stacked structure; The second contact structure further includes a second filling dielectric layer located on a side of the second conductive structure away from the first stacked structure; Wherein, the first filling dielectric layer and the second filling dielectric layer are in contact with each other. The first dummy channel structure and the second dummy channel structure are both in contact with the first filling dielectric layer and the second filling dielectric layer.

15. The semiconductor structure according to claim 13, wherein The first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer located at different heights; The plurality of dummy channel structures further include a third dummy channel structure penetrating the second stacked structure and located on a side of the second conductive structure closer to the first conductive structure along the second direction; Wherein, the first conductive structure includes: a first contact conductive layer, contacting the conductive layer and extending along the stacking direction to the first sub-dielectric layer; and a second contact conductive layer, contacting the conductive layer, adjacent to the first contact conductive layer along the first direction and extending to the second sub-dielectric layer along the stacking direction, wherein: A portion of the third dummy channel structure is located between the first contact conductive layer and the second contact conductive layer.

16. The semiconductor structure according to claim 15, wherein The plurality of dummy channel structures further include a fourth dummy channel structure penetrating the second stacked structure and located on a side of the first conductive structure close to the second conductive structure along the second direction; Wherein, the second conductive structure includes: a third contact conductive layer, contacting the conductive layer and extending along the stacking direction to the first sub-dielectric layer; and a fourth contact conductive layer, contacting the conductive layer, adjacent to the third contact conductive layer along the first direction and extending to the second sub-dielectric layer along the stacking direction, wherein: A portion of the fourth dummy channel structure is located between the third contact conductive layer and the fourth contact conductive layer.

17. The semiconductor structure according to claim 15, wherein The plurality of dummy channel structures further include a fifth dummy channel structure located between the plurality of third dummy channel structures along the first direction, The third dummy channel structure and the fifth dummy channel structure are connected along the first direction.

18. The semiconductor structure according to claim 16, wherein The plurality of dummy channel structures further include a sixth dummy channel structure located between the plurality of fourth dummy channel structures along the first direction, The fourth dummy channel structure and the sixth dummy channel structure are connected along the first direction.

19. The semiconductor structure according to any one of claims 13 to 18, wherein: The first contact structure further includes a first barrier layer located between the first conductive structure and the first stacked structure and extending along the stacking direction; as well as The second contact structure further includes a second barrier layer located between the second conductive structure and the first stacked structure and extending along the stacking direction.

20. The semiconductor structure according to any one of claims 13 to 18, wherein The semiconductor structure further comprises: A channel structure is located in the array region and penetrates the second stacked structure.

21. A memory, wherein: include: A memory cell array comprising the semiconductor structure according to any one of claims 13 to 20; as well as The peripheral circuit is coupled to the memory cell array.

22. A storage system, wherein: include: The memory according to claim 20; as well as The controller is coupled to the memory and is used to control the memory to store data.

Images