Semiconductor structure and preparation method thereof, memory and memory system

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation method thereof, a memory and a memory system. The semiconductor structure comprises a semiconductor layer, a stacking structure and a channel structure. The stacked structure is arranged on one side of the semiconductor layer and comprises insulating layers and gate layers which are alternately stacked. The channel structure at least partially penetrates through the stacking structure in the stacking direction of the stacking structure, and comprises a channel layer and a functional lamination layer located on the side, close to the stacking structure, of the channel layer; the functional stack includes an amorphous first dielectric layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to semiconductor technology, and relate to but are not limited to a semiconductor structure and a manufacturing method thereof, a memory, and a memory system. Background Art

[0002] Memory is a device used to store information. With the increasing demand for memory storage capacity and density, vertically stacking multiple semiconductor layers is being used to increase storage capacity per unit area. As the number of stacked layers in a memory increases, the spacing between adjacent layers decreases to reduce the overall thickness of the memory. This increases the accuracy required to distinguish signals transmitted by adjacent layers, placing higher demands on the reliability of electrical transmission within the channel structure within the stacked layers. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a memory, and a memory system.

[0004] In a first aspect, embodiments of the present application provide a semiconductor structure. The semiconductor structure comprises: a semiconductor layer, a stacked structure, and a channel structure. The stacked structure is disposed on one side of the semiconductor layer and comprises alternating insulating layers and gate layers. The channel structure at least partially penetrates the stacked structure along its stacking direction and comprises a channel layer and a functional stack located on a side of the channel layer proximal to the stacked structure; the functional stack comprises an amorphous first dielectric layer.

[0005] In some examples, the functional stack includes a capture layer; the capture layer includes the first dielectric layer and a second dielectric layer; and the dielectric constant of the first dielectric layer is greater than the dielectric constant of the second dielectric layer.

[0006] In some examples, the capture layer includes three stacked layers of the second dielectric layer, the first dielectric layer, and the second dielectric layer.

[0007] In some examples, the capture layer includes a plurality of alternating first dielectric layers and a plurality of alternating second dielectric layers, wherein the number of the first dielectric layers is greater than or equal to the number of the second dielectric layers.

[0008] In some examples, the dielectric constant of the first dielectric layer is greater than 20.

[0009] In some examples, the material of the first dielectric layer includes a nanocrystalline material in which doped particles are combined with a high dielectric constant material.

[0010] In some examples, the concentration of the dopant particles is 6% to 20%.

[0011] In some examples, the high dielectric constant material of the first dielectric layer includes one or more of aluminum oxide, hafnium oxide, and zirconium oxide.

[0012] In some examples, the doping particles include one or more of aluminum oxide, hafnium oxide, and silicon oxide; and the high dielectric constant material of the first dielectric layer is different from the doping particles.

[0013] In some examples, the thickness of the first dielectric layer ranges from 1.2 nm to 3 nm.

[0014] In some examples, the thickness of the first dielectric layer ranges from 1.2 nm to 1.5 nm.

[0015] In some examples, the material of the second dielectric layer includes an amorphous material; and the second dielectric layer is configured to provide a growth interface for the first dielectric layer.

[0016] In some examples, the functional stack further includes a barrier layer and a tunnel layer. The barrier layer is disposed on a side of the capture layer close to the stack structure. The tunnel layer is disposed between the capture layer and the channel layer.

[0017] In some examples, the material of the barrier layer includes an amorphous material; the amorphous material of the barrier layer is located on a side away from the stacked structure and in contact with the capture layer, and is configured to provide a growth interface for the first dielectric layer.

[0018] The functional stack in the above-mentioned semiconductor structure is used to realize signal transmission between the stack structure and the channel layer. By setting the functional stack to include an amorphous first dielectric layer and the amorphous material properties of the first dielectric layer, the electron capture density of the first dielectric layer can be increased, the leakage probability can be reduced, and the signal transmission efficiency can be improved, and the speed and data retention effect of the semiconductor structure applied to data reading and writing can be improved.

[0019] In a second aspect, embodiments of the present application further provide a method for fabricating a semiconductor structure. The fabrication method comprises: providing a substrate; forming a stacked structure located on one side of the substrate, comprising alternating insulating layers and sacrificial layers; and forming a channel structure that at least partially penetrates the stacked structure, the channel structure extending along the stacking direction of the stacked structure. The channel structure comprises a channel layer and a functional stack located on a side of the channel layer proximal to the stacked structure; the functional stack comprises an amorphous first dielectric layer.

[0020] In some examples, forming a channel structure that at least partially penetrates the stacked structure includes etching the stacked structure to form a channel hole that at least partially penetrates the stacked structure. Forming a barrier layer on sidewalls of the channel hole. Forming the first dielectric layer on a side of the barrier layer away from the stacked structure. The dielectric constant of the barrier layer is less than that of the first dielectric layer; and / or the material of the barrier layer in contact with the first dielectric layer comprises an amorphous material.

[0021] In some examples, forming a channel structure that at least partially penetrates the stacked structure includes etching the stacked structure to form a channel hole that at least partially penetrates the stacked structure. Sequentially forming a barrier layer and a second dielectric layer on sidewalls of the channel hole. Forming the first dielectric layer on a side of the second dielectric layer away from the stacked structure. The dielectric constant of the second dielectric layer is less than that of the first dielectric layer; and / or the material of the second dielectric layer in contact with the first dielectric layer comprises an amorphous material.

[0022] In some examples, after forming the first dielectric layer, the method further includes: forming the second dielectric layer on a side of the first dielectric layer away from the stacked structure; or alternately forming a plurality of stacked first dielectric layers and a plurality of second dielectric layers.

[0023] In some examples, forming the first dielectric layer includes: growing a doped particle material layer on one side of the initial material of the first dielectric layer to form an amorphous first dielectric layer under conditions in a first temperature range; different doped particle material layers have different process temperatures for forming the amorphous first dielectric layer.

[0024] In some examples, forming a channel structure that at least partially penetrates the stack structure includes: forming a tunneling layer located on a side of the first dielectric layer close to the channel layer; the dielectric constant of the tunneling layer is smaller than the dielectric constant of the first dielectric layer.

[0025] The above-mentioned method for fabricating a semiconductor structure enables electrical signal transmission by providing a first dielectric layer within the functional stack, located between the channel layer and the stack structure. Compared to the crystalline state, the amorphous properties of the first dielectric layer improve the electrical signal transmission performance between the stack structure and the channel layer, such as electron migration speed and electron capture density, thereby enhancing the accuracy and rate of electrical signal transmission.

[0026] In a third aspect, embodiments of the present application further provide a memory. The memory comprises: one or more semiconductor structures as provided in the above examples, and peripheral circuitry. The semiconductor structures are configured to store data. The peripheral circuitry is coupled to the one or more semiconductor structures and configured to write, read, or erase data within the semiconductor structures in response to received instructions.

[0027] The beneficial effects of the memory provided in this application are the same as the beneficial effects of the semiconductor structure provided in any of the above examples, and will not be repeated here.

[0028] In a fourth aspect, embodiments of the present application further provide a memory system. The memory system includes: one or more memories as provided in the above examples; and a memory controller. The memories are configured to store data. The memory controller is coupled to the one or more memories and configured to control the memories to perform programming operations.

[0029] The beneficial effects of the memory system provided in this application are the same as the beneficial effects of the memory provided in any of the above examples, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0031] Figure 1 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application;

[0032] Figure 2 A schematic structural diagram of a memory card provided in one embodiment of the present application;

[0033] Figure 3 A schematic diagram of the structure of a solid-state drive (SSD) provided in one embodiment of the present application;

[0034] Figure 4 A schematic diagram of the structure of a memory system provided in one embodiment of the present application;

[0035] Figure 5 and Figure 6 A schematic structural diagram of a memory including a memory cell array and peripheral circuits provided in one embodiment of the present application;

[0036] Figure 7 A schematic structural diagram of a memory including a page buffer group provided in one embodiment of the present application;

[0037] Figure 8A schematic structural diagram of a memory system including a semiconductor structure provided in an embodiment of the present disclosure;

[0038] Figure 9 for Figure 8 An enlarged schematic diagram of a local G1 of the semiconductor structure shown;

[0039] Figure 10 for Figure 9 Enlarged view of local G2 Figure 1 ;

[0040] Figure 11 for Figure 9 Enlarged view of local G2 Figure 2 ;

[0041] Figure 12 for Figure 9 Enlarged view of local G2 Figure 3 ;

[0042] Figure 13 for Figure 9 Enlarged view of local G2 Figure 4 ;

[0043] Figure 14 for Figure 9 Enlarged view of local G2 Figure 5 ;

[0044] Figure 15 for Figure 9 Enlarged view of local G2 Figure 6 ;

[0045] Figure 16 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0046] Figure 17 (a)~ Figure 17 (i) is a schematic diagram of a process flow for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figure 18 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0048] Figure 19 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0049] Figure 20 A schematic diagram of another method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0050] Figure 21 A schematic diagram of another method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0051] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0053] The terms "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding the term include the elements or objects listed after the term and their equivalents, without excluding other elements or objects. Terms such as "connect" or "connected" or "coupled" are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

[0054] It should be understood that “some embodiments” or “some examples” mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, “in some embodiments” or “in some examples” appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0055] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0056] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0057] like Figure 1 As shown, the embodiment of the present application shows an electronic device 10. By way of example, the electronic device 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device 32 therein.

[0058] Please continue reading Figure 1 , the electronic device 10 may include a host 20 and a memory system 30 .

[0059] The host 20 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP))) of an electronic device. The host 20 may be configured to send data to or receive data from the memory system 30.

[0060] The memory system 30 includes a memory controller 31, one or more memory devices 32, and other integrated circuit structures for signal transmission. The memory controller 31 and one or more memory devices 32 can be integrated and packaged into the same storage device. This facilitates the application of the memory system 30 in various types of terminal electronic products.

[0061] For example, the types of storage devices integrating the memory controller 31 and the one or more memory devices 32 include Universal Flash Storage (UFS) or Embedded MultiMedia Card (eMMC) or other types of storage devices.

[0062] There are many forms of integrated circuits for the storage device, for example, a memory card 40 (eg, a memory card 40) formed by integrating a single memory device 32 and a memory controller 31. Figure 2 ), or a plurality of memory devices 32 and a memory controller 31 may be integrated to form an SSD 50 (as shown in FIG. Figure 3 shown).

[0063] For example, the memory card 40 may include one or more types of storage devices including a Personal Computer Memory Card International Association (PC) card, a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMC micro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), and UFS.

[0064] Please continue to see Figure 2 , the memory card 40 further includes a memory card connector 41. The memory card connector 41 is configured to connect the memory card 40 to a host (eg, Figure 1 For example, the memory card connector 41 includes gold fingers.

[0065] Alternatively, please continue to Figure 3 , SSD 50 further includes an SSD connector 51. The SSD connector 51 is configured to connect the SSD 50 to a host (e.g., Figure 1 For example, the SSD connector 51 includes gold fingers.

[0066] It will be appreciated that the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40 .

[0067] The memory controller 31 integrated in the same storage device is coupled to the memory device 32 (and the host 20 ). The memory controller 31 is configured to control the memory device 32 .

[0068] Exemplarily, the memory controller 31 may be designed to operate in a low duty cycle environment. For example, it may be designed to operate in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or in other dielectrics used in electronic devices such as personal computers, digital cameras, and mobile phones. As another example, the memory controller 31 may be designed to operate in a high duty cycle environment, for example, in an SSD or an embedded Multi-Media Card (eMMC). SSDs or eMMCs may be used as data storage for mobile devices such as smartphones, tablet computers, and laptop computers, as well as enterprise storage arrays.

[0069] Furthermore, the memory controller 31 can manage data in the memory device 32 and communicate with the host 20. The memory controller 31 can be configured to control operations such as reading, erasing, and programming of the memory device 32; can also be configured to manage various functions related to data stored or to be stored in the memory device 32, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.; and can also be configured to process error correction codes (ECC) on data read from or written to the memory device 32.

[0070] In addition, the memory controller 31 may also perform any other suitable functions, such as formatting the memory device 32, or communicating with an external device (eg, Figure 1For example, the memory controller 31 can communicate with the host 20 through at least one of various interface protocols. The interface protocols include one or more of the following protocols: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc.

[0071] The above-mentioned memory device 32 may include but is not limited to one or more memories selected from NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0072] Based on the above description, this application uses the memory device 32 as a semiconductor memory, such as a solid-state electronic device (e.g., NAND memory) that stores data information, manufactured using semiconductor integrated circuit technology, as an example to describe the subsequent embodiments. The subsequent examples of this application do not limit the specific internal structure of the memory device 32.

[0073] It is understood that, in order to facilitate the distinction between the adaptive adjustments made by the memory device 32 in different scenarios, for example, based on the various structures of the memory device 32 exemplified in the foregoing content, the memory device (e.g., NAND memory) provided in the subsequent examples of this application is described as a memory 60, and a memory system 70 including the memory 60 (see Figure 4 and Figure 5 ).

[0074] Memory is a device used to store information. With the increasing demand for memory storage capacity and density, vertically stacking multiple semiconductor layers is being used to increase storage capacity per unit area. As the number of stacked layers in a memory increases, the spacing between adjacent layers decreases to reduce the overall thickness of the memory. This increases the accuracy required to distinguish signals transmitted by adjacent layers, placing higher demands on the reliability of electrical transmission within the channel structure within the stacked layers.

[0075] Therefore, the memory 60 and memory system 70 provided in this application can achieve better electrical signal transmission performance, which is specifically embodied in the semiconductor structure 80 provided in the subsequent embodiments.

[0076] In some embodiments, as Figure 4 As shown, an embodiment of the present application provides a memory system 70. The memory system 70 includes one or more memories 60 and a memory controller 71.

[0077] The memory 60 is configured to store data. The memory controller 71 is coupled to one or more memories 60 and is configured to control the memory 60 to perform a programming operation.

[0078] For example, Figure 5 As shown, the memory 60 may include a memory cell array 601 and a peripheral circuit 602 coupled to the memory cell array 601 .

[0079] The memory cell array 601 is coupled to a plurality of bit lines BL. For example, the memory cell array 601 may be a NAND flash memory cell array. For example, the memory cell array 601 is a circuit structure arranged in the form of an array of NAND memory strings 6011. Each NAND memory string 6011 extends vertically on the substrate. For example, each NAND memory string 6011 may include a plurality of memory cells coupled in series and stacked vertically. Each memory cell transmits a signal in a state of maintaining a continuous analog value (e.g., voltage or charge), and the analog value of the memory cell depends on the number of electrons captured in the memory cell area.

[0080] For example, each memory cell in the memory cell array 601 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor, which is not limited in the present application.

[0081] Please continue reading Figure 5 The peripheral circuit 602 may be coupled to the memory cell array 601 via a bit line (BL), a word line (WL), a source line, a source select gate (SSG), and a drain select gate (DSG). The peripheral circuit 602 is configured to implement logic operations (e.g., programming, reading, or writing operations) of the memory cell array 601 by applying a voltage signal and / or a current signal to each target memory cell via the bit line BL, the word line WL, the source SL, the source select gate SSG, or the drain select gate DSG, and sensing the voltage signal and / or the current signal from each target memory cell.

[0082] It should be understood that although Figure 5 , one source select gate line SSG and one drain select gate line DSG are shown, but the number of source select gate lines SSG and the number of drain select gate lines DSG (and the number of source select transistors and drain select transistors coupled to the source select gate line SSG and the drain select gate line DSG, respectively) may vary in other examples.

[0083] For example, the peripheral circuit 602 includes various types of circuit structures formed using metal-oxide-semiconductor (MOS) transistors. Figure 6 As shown, the peripheral circuit 602 may include a row decoder / word line driver 6020, a page buffer (PB) / sense amplifier 6021, a column decoder / bit line driver 6023, a voltage generator 6024, a control logic unit 6025, a latch circuit 6026, an interface 6027 and a data bus 6028 and other circuit structures.

[0084] Further, such as Figure 7 As shown, the peripheral circuit 602 may include a page buffer group consisting of a plurality of page buffers 6021. The page buffer group may be coupled to the memory cell array 601 via a plurality of bit lines (BL1 to BLk). One page buffer 6021 is coupled to the memory cell array 601 via one bit line. For example, Figure 7 As shown, a plurality of page buffers 6021 may be coupled to the memory cell array 601 via corresponding bit lines BL1 to BLk, respectively.

[0085] In some embodiments, as Figure 8 As shown, the embodiment of the present application further provides a memory 60. The memory 60 includes one or more semiconductor structures 80 and a peripheral circuit 61.

[0086] Semiconductor structure 80 is configured to store data. It is understood that semiconductor structure 80 (from the perspective of the layer structure of the physical product) and the memory cell array 601 mentioned above (from the perspective of the circuit principle of the connection between the various components) are the same product structure described from different perspectives. To highlight the improvements to the technical problems to be solved by this application, the subsequent embodiments are exemplified based on semiconductor structure 80.

[0087] Peripheral circuit 61 is coupled to one or more semiconductor structures 80 and is configured to write, read, or erase data within semiconductor structure 80 in response to received instructions. It is understood that peripheral circuit 61 and peripheral circuit 602 mentioned above are described separately based on their respective coupled structures and are identical in structure. This application example does not specifically limit the distinction between peripheral circuit 61 and peripheral circuit 602 mentioned above.

[0088] In some embodiments, as Figures 8 to 15 As shown, the embodiment of the present application provides a semiconductor structure 80. Figure 9 As shown, the semiconductor structure 80 includes a semiconductor layer 81 , a stacked structure 82 and a channel structure 83 .

[0089] The semiconductor layer 81 may be used as a common source of the array and electrically connected to a plug (not shown) in the stack structure 82 .

[0090] The stacked structure 82 is disposed on one side of the semiconductor layer 81. Figure 9 As shown, the stack structure 82 includes alternately stacked insulating layers 821 and gate layers 822. The number of pairs of insulating layers 821 and gate layers 822 can determine the number of memory cell arrays 601 (see FIG. Figure 5 ) in the memory cell.

[0091] The gate layer 822 may extend laterally at the top of the stacked structure 82 as a drain select gate line DSG, extend laterally at the bottom of the stacked structure 82 as a source select gate line SSG, or extend laterally between the drain select gate line DSG and the source select gate line SSG as a word line WL, and be coupled to the peripheral circuit 61 via the word line WL. The embodiment of the present application does not show the connection method between the gate layer 822 and the peripheral circuit 61, and can be set according to actual needs.

[0092] For example, the material of gate layer 822 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. For example, gate layer 822 includes a metal layer, such as a tungsten layer. For another example, gate layer 822 includes a doped polysilicon layer.

[0093] The channel structure 83 at least partially penetrates the stack structure 82 along the stacking direction of the stack structure 82. For example, the channel structure 83 may have a pillar shape (eg, a cylindrical shape).

[0094] In some examples, such as Figure 9 As shown, the channel structure 83 includes a channel layer 831 and a functional stack 832 located on a side of the channel layer 831 close to the stack structure 82. The functional stack 832 includes an amorphous first dielectric layer 8321.

[0095] Due to the increase in the number of stacked layers of the stacked structure 82, in order to reduce the overall thickness of the semiconductor structure 80, the spacing between adjacent gate layers 822 is shortened. In order to reduce the probability of errors in the signals transmitted by adjacent gate layers 822, and the probability of leakage due to coupling caused by the close distance between adjacent gate layers 822. The present application provides a functional stack 832 in the semiconductor structure 80, including an amorphous first dielectric layer 8321, and a technical means based on the amorphous material properties of the first dielectric layer 8321. This can increase the electron capture density of the first dielectric layer 8321, reduce the leakage probability, and improve the signal transmission efficiency, and improve the speed and data retention effect of the semiconductor structure 80 used for data reading and writing.

[0096] It should be understood that the electron capturing ability of crystalline dielectric materials is relatively poor. In order to reduce the crystallinity of dielectric materials, examples of how to obtain amorphous dielectric materials are provided in the subsequent methods.

[0097] In some examples, such as Figure 9 As shown, the functional stack 832 includes a capture layer 8320. The capture layer 8320 includes an amorphous first dielectric layer 8321. Figure 9 The functional stack 832 further includes a barrier layer 8323 and a tunneling layer 8324 .

[0098] The barrier layer 8323 is disposed on a side of the capture layer 8320 that is close to the stacked structure 82. For example, the barrier layer 8323 is made of an amorphous material. The amorphous material of the barrier layer 8323 is located on a side away from the stacked structure 82 and in contact with the capture layer 8320, and is configured to provide a growth interface for the first dielectric layer 8321.

[0099] The tunneling layer 8324 is disposed between the capture layer 8320 and the channel layer 831 .

[0100] For example, along a direction X perpendicular to the extension direction of the channel structure 83 and in a direction away from the channel layer 831, the functional stack 832 includes a tunneling layer 8324, a capture layer 8320, and a barrier layer 8323. The capture layer 8320 includes a first dielectric layer 8321, or at least one first dielectric layer 8321 and at least one second dielectric layer 8322.

[0101] For example, Figure 9 As shown, the channel structure 83 includes a channel layer 831 , a tunneling layer 8324 , a first dielectric layer 8321 (ie, a capture layer 8320 ), and a barrier layer 8323 .

[0102] It is understood that the dielectric constant of the barrier layer 8323 is smaller than that of the capture layer 8320. The dielectric constant of the tunneling layer 8324 is smaller than that of the capture layer 8320. The capture layer 8320 (or first dielectric layer 8321) is disposed between the tunneling layer 8324 and the barrier layer 8323 to further enhance the electron capture capability of the capture layer 8320.

[0103] The dielectric constant of the first dielectric layer 8321 is greater than 20.

[0104] For example, the material of the blocking layer 8323 includes silicon nitride. The material of the first dielectric layer 8321 includes a nanocrystalline material formed of silicon nitride doped with hafnium oxide particles. The dielectric constant of the blocking layer 8323 is smaller than the dielectric constant of the capture layer 8320.

[0105] Thus, the capture layer 8320 includes only a first dielectric layer 8321. Because the barrier layer 8323 provides a growth interface for the first dielectric layer 8321, the first dielectric layer 8321 (i.e., the capture layer 8320) is not in direct contact with the stacked structure 82. This prevents the amorphous nature of the first dielectric layer 8321 from causing leakage current when transmitting electrical signals to the gate layers 821 in the stacked structure 82, thereby preventing the adjacent gate layers 821 from being electrically interconnected. Furthermore, because the surface energy of silicon oxide can cause heterogeneous hafnium oxide to crystallize, this helps to increase the processing temperature range of the amorphous first dielectric layer 8321, expanding its application scenarios.

[0106] In some examples, the material of the first dielectric layer 8321 includes a nanocrystalline material in which doped particles are combined with a high dielectric constant material.

[0107] It is understood that high dielectric constant materials refer to materials with a dielectric constant greater than 3.9 (ie, the dielectric constant of silicon oxide). Doped particles refer to nanoparticles that are doped into the ion exchange membrane and can change the performance of the membrane.

[0108] Illustratively, the high dielectric constant material of the first dielectric layer 8321 includes one or more of aluminum oxide, hafnium oxide, and zirconium oxide.

[0109] For example, the doping particles include one or more of aluminum oxide, hafnium oxide, and silicon oxide. The high dielectric constant material of the first dielectric layer 8321 is different from the doping particles.

[0110] For example, the high dielectric constant material of the first dielectric layer 8321 includes aluminum oxide, and the doping particles include hafnium oxide. Alternatively, the high dielectric constant material of the first dielectric layer 8321 includes hafnium oxide, and the doping particles include aluminum oxide.

[0111] For another example, the high dielectric constant material of the first dielectric layer 8321 includes hafnium oxide, and the doped particles include aluminum oxide. Alternatively, the high dielectric constant material of the first dielectric layer 8321 includes aluminum oxide, and the doped particles include hafnium oxide.

[0112] In some examples, the concentration of the doping particles is 6% to 20%, for example, the concentration of the doping particles is 6%, 8%, 10%, 15%, or 20%.

[0113] For example, the high dielectric constant material of the first dielectric layer 8321 includes hafnium oxide, the doping particles include aluminum oxide, and the concentration of the doping particles aluminum oxide is 6% to 20%.

[0114] For example, the process temperature for forming the first dielectric layer 8321 may exceed 1050° C. without causing crystallization.

[0115] It should be understood that the process temperature for preparing the first dielectric layer 8321 varies depending on the dopant concentration. For example, the high-k dielectric material of the first dielectric layer 8321 includes hafnium oxide, the dopant concentration includes 20% aluminum oxide, and the process temperature for forming the amorphous first dielectric layer 8321 is 1000° C. to 1100° C. For another example, the high-k dielectric material of the first dielectric layer 8321 includes hafnium oxide, the dopant concentration includes 10% silicon oxide, and the process temperature for forming the amorphous first dielectric layer 8321 is 650° C. to 1050° C.

[0116] It can be understood that the degree of crystallization of the first dielectric layer 8321 is not only related to its process temperature, but also related to the thickness of the first dielectric layer 8321.

[0117] In some examples, the thickness of the first dielectric layer 8321 ranges from 1.2 nm to 3 nm. For example, the thickness of the first dielectric layer 8321 includes 1.2 nm, 1.53 nm, 1.77 nm, 1.82 nm, or 3 nm.

[0118] For example, when the process temperature does not exceed 650° C., the thickness of the first dielectric layer 8321 reaches 3 nm, and the high dielectric material within the thickness of the first dielectric layer 8321 will not be crystallized.

[0119] For example, the high dielectric material of the first dielectric layer 8321 includes hafnium oxide, the doped particles include silicon oxide, and the preparation process temperature is 650° C. The thickness of the amorphous first dielectric layer 8321 that can be prepared is 3 nm.

[0120] In some other examples, the thickness of the first dielectric layer 8321 ranges from 1.2 nm to 1.5 nm. For example, the thickness of the first dielectric layer 8321 includes 1.2 nm, 1.3 nm, 1.4 nm, or 1.5 nm.

[0121] For example, when the process temperature exceeds 1050° C., the thickness of the first dielectric layer 8321 is further reduced to reduce the probability of crystallization of the high dielectric material of the first dielectric layer 8321 due to the high process temperature.

[0122] For example, the high dielectric material of the first dielectric layer 8321 includes hafnium oxide, the doped particles include silicon oxide, and the preparation process temperature is 1100° C. The thickness of the amorphous first dielectric layer 8321 that can be prepared is 1.5 nm.

[0123] Furthermore, when the thickness of the first dielectric layer 8321 is less than 1.2 nm, an amorphous first dielectric layer 8321 can be obtained by using a process temperature exceeding 1050°C. Considering that the first dielectric layer 8321 is used to form the channel structure 83 for electrical connection with the gate layer 822, a first dielectric layer 8321 with a thickness less than 1.2 nm has relatively weak electrical properties. In other application scenarios, the embodiments provided herein do not limit the thickness of the first dielectric layer 8321.

[0124] Based on the structure of the functional stack 832 in the above-mentioned channel structure 83 and the material of the first dielectric layer 8321 in the functional layer 832, the following examples illustrate functional stacks 832 with different layer structures through the specific number and arrangement positions of the first dielectric layer 8321 and the second dielectric layer 8322.

[0125] In some examples, such as Figures 10 to 15 As shown, the capture layer 8320 includes an amorphous first dielectric layer 8321 and a second dielectric layer 8322. The dielectric constant of the first dielectric layer 8321 is greater than the dielectric constant of the second dielectric layer 8322.

[0126] For example, the material of the second dielectric layer 8322 includes an amorphous material. The second dielectric layer 8322 is configured to provide a growth interface for the first dielectric layer 8321. In this way, the first dielectric layer 8321 is grown on the amorphous second dielectric layer 8322, and the first dielectric layer 8321 obtained under high temperature process conditions is not easily crystallized.

[0127] For example, Figure 10 As shown, the capture layer 8320 includes a first dielectric layer 8321 and a second dielectric layer 8322 , and the first dielectric layer 8321 is located on a side of the second dielectric layer 8322 away from the stack structure 82 .

[0128] In some examples, such as Figure 11 and Figure 12 As shown, the capture layer 8320 includes three layers of a second dielectric layer 8322, a first dielectric layer 8321 and a second dielectric layer 8322 stacked together.

[0129] For example, Figure 11 As shown, the capture layer 8320 includes a first dielectric layer 8321 and two second dielectric layers 8322 , and the first dielectric layer 8321 is located between the two second dielectric layers 8322 .

[0130] Or, as Figure 12 As shown, the capture layer 8320 includes two first dielectric layers 8321 and a second dielectric layer 8322, wherein the second dielectric layer 8322 is located between the two first dielectric layers 8321. The first dielectric layer 8321 located on the side of the second dielectric layer 8322 close to the barrier layer 8323 is grown on the barrier layer 8323; the first dielectric layer 8321 located on the side of the second dielectric layer 8322 away from the barrier layer 8323 is grown on the second dielectric layer 8322.

[0131] The first dielectric layer 8321 and the second dielectric layer 8322 enhance the electron capture capability (characterized by data retention performance) and electrical signal transmission rate of the functional stack 832. Due to the different growth interfaces of the first dielectric layer 8321, parameters such as the fabrication process temperature and dopant concentration can be adjusted to enhance the electron capture capability of the capture layer 8320.

[0132] In other examples, such as Figures 13 to 15 As shown, the capture layer 8320 includes a plurality of alternating first dielectric layers 8321 and a plurality of second dielectric layers 8322. Figure 15 As shown, the number of the first dielectric layers 8321 is greater than or equal to the number of the second dielectric layers 8322 .

[0133] For example, Figure 13As shown, the capture layer 8320 includes two first dielectric layers 8321 and two second dielectric layers 8322 alternately. Alternatively, as shown Figure 14 As shown, the capture layer 8320 includes three alternating first dielectric layers 8321 and two second dielectric layers 8322. Alternatively, as Figure 15 As shown, the capture layer 8320 includes four first dielectric layers 8321 and two second dielectric layers 8322 alternatingly.

[0134] By increasing the number of first dielectric layers 8321, the thickness of each first dielectric layer 8321 can be reduced, thereby reducing the probability of crystallization of the high-dielectric material in the first dielectric layer 8321 under high-temperature process conditions and improving the electron capture capability of the capture layer 8320. This improves the data retention capability and transmission speed of the semiconductor structure 100 when used for data storage.

[0135] In some embodiments, the present application also provides a method for preparing the semiconductor structure 100. Figures 16 to 21 As shown, the preparation method includes: S100 to S300.

[0136] S100: Figure 16 and Figure 17 As shown in (a) in FIG. 8 , a substrate 801 is provided.

[0137] For example, the material of the substrate 801 may include silicon (eg, single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0138] It is understandable that the substrate 801 is used to provide support for the stacking structure 82 , and the substrate 801 can be removed from the memory 60 formed subsequently.

[0139] S200: Figure 16 and Figure 17 As shown in (b) of FIG. 8 , a stacked structure 82 is formed on one side of the substrate 801 . The stacked structure 82 includes insulating layers 821 and sacrificial layers 822 ′ that are alternately stacked.

[0140] For example, a deposition process is used to alternately form a stacked insulating layer 821 and a sacrificial layer 822'. The sacrificial layer 822' will be replaced by a gate material after the channel hole 830 is subsequently formed to form a gate layer 822 (see Figure 17 (c) in the figure.

[0141] S300: Figure 16 and Figure 17As shown in (h), a channel structure 83 is formed that at least partially penetrates the stack structure 82 and extends along the stacking direction of the stack structure 82. The channel structure 83 includes a channel layer 831 and a functional stack 832 located on a side of the channel layer 831 close to the stack structure 82.

[0142] Furthermore, the functional stack 832 includes an amorphous first dielectric layer 8321. That is, the capture layer 8320 includes at least the amorphous first dielectric layer 8321. For example, the capture layer 8320 may include one or more layers of the amorphous first dielectric layer 8321, or may include one or more layers of the amorphous first dielectric layer 8321 and other material layers as required.

[0143] Based on this, the following is a process of fabricating the first dielectric layer 8321 using the surface of the barrier layer 8323 as the growth interface (see Figure 18 and Figure 19 ), or the surface of the second dielectric layer 8322 is used as the growth interface (see Figure 20 and Figure 21 ) as an example to illustrate the layer structure of the capture layer 8320.

[0144] In some examples, such as Figure 17 (c)~ Figure 17 (h) Figure 18 and Figure 19 As shown, S300 includes: S311 to S313.

[0145] S311: If Figure 17 (c) Figure 18 and Figure 19 As shown, the stack structure 82 is etched to form a channel hole 830 that at least partially penetrates the stack structure 82 .

[0146] It should be noted that the stacking structure 82 mentioned in this example includes a structural form in which the channel hole 830 is not etched, and also includes a structural form in which the sacrificial layer is replaced with material through the channel hole 830 after etching the channel hole 830 to form a gate layer 822. The example of this application does not distinguish between the forms of the stacking structure 82 in different steps, nor does it limit the changes in the specific film layer materials and structures of the stacking structure 82.

[0147] For example, a photolithography process can be used to form the channel hole 830. It is understood that the channel hole 830 is a region for forming the channel structure 83. The present example does not illustrate a structure of an empty hole without a channel structure 83. The specific size and shape of the channel hole 830 can be designed and manufactured according to the actual requirements of the channel structure 83, and the present embodiment does not impose any restrictions on this.

[0148] S312: If Figure 17 (d) Figure 18 and Figure 19 As shown, a barrier layer 8323 is formed on the sidewalls of the channel hole 830 .

[0149] For example, a deposition or sputtering process is used to form a barrier layer 8323 on the sidewalls of the trench hole 830. The thickness of the barrier layer 8323 is related to the duration of the deposition or sputtering process.

[0150] S313: If Figure 17 (e) and Figure 19 As shown, a capture layer 8320 is formed on a side of the barrier layer 8323 away from the stack structure 82. Illustratively, the capture layer 8320 includes a first dielectric layer 8321.

[0151] The dielectric constant of the barrier layer 8323 is smaller than the dielectric constant of the first dielectric layer 8321 ; and / or the material of the barrier layer 8323 in contact with the first dielectric layer 8321 includes an amorphous material.

[0152] For example, the barrier layer 8323 includes a single layer or a multilayer structure. For example, the barrier layer 8323 is a single layer structure, and the material of the barrier layer 8323 is silicon nitride. In this way, the dielectric constant of the barrier layer 8323 is smaller than the dielectric constant of the first dielectric layer 8321, which helps to reduce the probability of leakage of the first dielectric layer 8321.

[0153] For another example, the barrier layer 8323 includes a multi-layer structure. The material layer of the barrier layer 8323 in contact with the first dielectric layer 8321 includes an amorphous material, which is conducive to the growth of the first dielectric layer 8321 and reduces the crystallinity of the first dielectric layer 8321 formed by the high-temperature process, thereby improving the electron capture capability of the first dielectric layer 8321.

[0154] For another example, the barrier layer 8323 includes a multi-layer structure. The material layer of the barrier layer 8323 in contact with the first dielectric layer 8321 includes an amorphous material, and the dielectric constant of the barrier layer 8323 is smaller than the dielectric constant of the first dielectric layer 8321. The first dielectric layer 8321 formed in this way can further reduce the probability of leakage.

[0155] In some examples, such as Figure 18 As shown, S313 includes S3131: growing a doped particle material layer on one side of the initial material of the first dielectric layer 8321, under conditions in a first temperature range, to form an amorphous first dielectric layer 8321. Different doped particle material layers have different process temperatures for forming the amorphous first dielectric layer 8321.

[0156] For example, the high dielectric constant material of the first dielectric layer 8321 includes hafnium oxide, and the doped particles include aluminum oxide. The process temperature for forming the first dielectric layer 8321 includes 1000° C. to 1100° C.

[0157] As another example, the high-k dielectric constant material of the first dielectric layer 8321 includes hafnium oxide, and the doped particles include silicon oxide. The process temperature for forming the first dielectric layer 8321 ranges from 650°C to 1050°C.

[0158] The concentration of the above-mentioned doped particles can be adjusted according to the film thickness of the high dielectric constant material and the process temperature. For example, at 1100°C, as the thickness of the high dielectric constant material increases, the concentration of the doped particles is increased, the probability of crystallization of the first dielectric layer 8321 is reduced, and the electron capture density of the first dielectric layer 8321 is increased.

[0159] In other examples, such as Figure 20 and Figure 21 As shown, S300 includes: S321 to S323.

[0160] S321: If Figure 17 As shown in (c) , the stack structure 82 is etched to form a channel hole 830 that at least partially penetrates the stack structure 82 .

[0161] It should be noted that the stacking structure 82 mentioned in this example includes a structural form in which the channel hole 830 is not etched, and also includes a structural form in which the sacrificial layer 822′ is replaced with material through the channel hole 830 to form a gate layer 822 after the channel hole 830 is etched. The example of this application does not distinguish between the forms of the stacking structure 82 in different steps, nor does it limit the changes in the specific film layer materials and structures of the stacking structure 82.

[0162] For example, a photolithography process can be used to form the channel hole 830. It is understood that the channel hole 830 is a region for forming the channel structure 83. The specific size and shape of the channel hole 830 can be designed and manufactured according to the actual requirements of the channel structure 83, and the embodiment of the present application does not limit this.

[0163] S322: If Figure 17 (d) Figure 10 、 Figure 11 、 Figure 13 and Figure 14 As shown, a blocking layer 8323 and a second dielectric layer 8322 are sequentially formed on the sidewalls of the channel hole 830 .

[0164] For example, a deposition or sputtering process can be used to form a barrier layer 8323 on the sidewalls of the trench hole 830. The thickness of the barrier layer 8323 is related to the duration of the deposition or sputtering process. Then, a second dielectric layer 8322 can be formed on the barrier layer 8323 using a deposition or sputtering process.

[0165] S323: If Figure 10 As shown, a first dielectric layer 8321 is formed on a side of the second dielectric layer 8322 away from the stack structure 82 .

[0166] The dielectric constant of the second dielectric layer 8322 is smaller than that of the first dielectric layer 8321 , which is beneficial to reducing the probability of leakage of the first dielectric layer 8321 .

[0167] And / or, the material of the second dielectric layer 8322 in contact with the first dielectric layer 8321 includes an amorphous material, which is conducive to the growth of the first dielectric layer 8321 and reduces the crystallization rate of the first dielectric layer 8321 formed by the high temperature process, thereby improving the electron capture ability of the first dielectric layer 8321.

[0168] For example, the material of the second dielectric layer 8322 is silicon nitride, and the material of the first dielectric layer 8311 is a nanocrystalline material formed by hafnium oxide doped with aluminum oxide particles.

[0169] In some examples, such as Figure 18 As shown, S323 includes S3131: growing a doped particle material layer on one side of the initial material of the first dielectric layer 8321, under conditions in a first temperature range, to form an amorphous first dielectric layer 8321. Different doped particle material layers have different process temperatures for forming the amorphous first dielectric layer 8321.

[0170] For example, the initial material of the first dielectric layer 8321 includes hafnium oxide, and the doped particle material layer includes aluminum oxide. The first temperature range includes 1000°C to 1100°C.

[0171] As another example, the high-k dielectric material of the first dielectric layer 8321 includes hafnium oxide, and the doped particles include silicon oxide. The process temperature for forming the first dielectric layer 8321 is 600°C to 1050°C.

[0172] In some examples, such as Figure 11 、 Figure 13 、 Figure 14 Figure 19 and Figure 21 As shown, S300 further includes S330: forming a second dielectric layer 8322 on a side of the first dielectric layer 8321 away from the stack structure 82; or, alternately forming a plurality of stacked first dielectric layers 8321 and a plurality of second dielectric layers 8322.

[0173] For example, Figure 11 As shown, the capture layer 8320 includes a first dielectric layer 8321 and two second dielectric layers 8322 , and the first dielectric layer 8321 is located between the two second dielectric layers 8322 .

[0174] Or, as Figure 12 As shown, the capture layer 8320 includes two first dielectric layers 8321 and a second dielectric layer 8322, wherein the second dielectric layer 8322 is located between the two first dielectric layers 8321. The first dielectric layer 8321 located on the side of the second dielectric layer 8322 close to the barrier layer 8323 is grown on the barrier layer 8323; the first dielectric layer 8321 located on the side of the second dielectric layer 8322 away from the barrier layer 8323 is grown on the second dielectric layer 8322.

[0175] Another example, such as Figure 13 As shown, the capture layer 8320 includes two first dielectric layers 8321 and two second dielectric layers 8322 alternately. Alternatively, as shown Figure 14 As shown, the capture layer 8320 includes three alternating first dielectric layers 8321 and two second dielectric layers 8322. Alternatively, as Figure 15 As shown, the capture layer 8320 includes four first dielectric layers 8321 and two second dielectric layers 8322 alternatingly.

[0176] The electron capture capability (characterized by data retention performance) and electrical signal transmission rate of the functional stack 832 are improved by the first dielectric layer 8321 and the second dielectric layer 8322. Among them, due to the different growth interfaces of the first dielectric layer 8321, the parameters such as the temperature and doping particle concentration of the preparation process can be adjusted to improve the electron capture capability of the capture layer 8320. Among them, since the surface energy of silicon oxide will cause heterogeneous hafnium oxide to crystallize, it is beneficial to increase the process temperature range of the amorphous first dielectric layer 8321 and expand the application scenario. In addition, by increasing the number of layers of the first dielectric layer 8321, the thickness of each first dielectric layer 8321 can be reduced, the probability of crystallization of the high dielectric material of the first dielectric layer 8321 under high temperature process conditions can be reduced, and the electron capture capability of the capture layer 8320 can be improved. Thereby, the data retention capability and transmission speed of the semiconductor structure 100 applied to data storage are improved.

[0177] It should be noted that if Figure 17As shown in (f), after forming the capture layer 8320 and before forming the tunneling layer 8324, the channel hole 830 can be etched again so that the gap in the channel hole 830 penetrates the capture layer 8320 into the substrate 801, thereby facilitating coupling when multiple semiconductor structures 80 are subsequently integrated. The specific process and the position at which the gap in the channel hole 830 penetrates the capture layer 8320 into the substrate 801 can be set according to the actual structure of the substrate 801 and are not limited by the examples of this application.

[0178] like Figure 17 (g) in Figure 17 (h) Figure 19 and Figure 21 As shown, after S330, S340 is further included: forming a tunneling layer 8324 located on the side of the first dielectric layer 8321 close to the channel layer 831. It can be understood that, as Figure 17 (g) in Figure 17 As shown in FIG. 8( h ), after the tunnel layer 8324 is formed, the channel layer 831 is formed to fill the region surrounded by the tunnel layer 8324 .

[0179] The dielectric constant of the tunneling layer 8324 is smaller than that of the first dielectric layer 8321 , which can further improve the electron capture capability of the first dielectric layer 8321 and reduce the probability of electrons migrating to the tunneling layer 8324 .

[0180] As well as Figure 17 As shown in (i), after the channel structure 83 is formed, the substrate 801 is removed to expose the bottom of the channel structure 83; then, a semiconductor layer 81 is formed to cover the bottom of the channel structure 83. The semiconductor layer 81 can be used as an array common source and electrically connected to the plug (not shown in the figure) in the stack structure 82.

[0181] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0182] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0183] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: semiconductor layer; A stacked structure, disposed on one side of the semiconductor layer, comprising alternately stacked insulating layers and gate layers; A channel structure at least partially penetrates the stack structure along the stacking direction of the stack structure, comprising a channel layer and a functional stack located on a side of the channel layer close to the stack structure; the functional stack comprises an amorphous first dielectric layer.

2. The semiconductor structure according to claim 1, wherein: The functional stack includes a capture layer; the capture layer includes the first dielectric layer and the second dielectric layer; the dielectric constant of the first dielectric layer is greater than the dielectric constant of the second dielectric layer.

3. The semiconductor structure according to claim 2, wherein: The capture layer includes three stacked layers of the second dielectric layer, the first dielectric layer, and the second dielectric layer.

4. The semiconductor structure according to claim 2, wherein: The capture layer includes a plurality of alternating first dielectric layers and a plurality of alternating second dielectric layers; The number of the first dielectric layers is greater than or equal to the number of the second dielectric layers.

5. The semiconductor structure according to claim 1, wherein: The dielectric constant of the first dielectric layer is greater than 20. The semiconductor structure according to claim 1 , wherein: The material of the first dielectric layer includes a nanocrystalline material in which doped particles are combined with a high dielectric constant material.

7. The semiconductor structure according to claim 6, wherein: Therefore, the concentration of doped particles is 6% to 20%.

8. The semiconductor structure according to claim 6, wherein: The high dielectric constant material of the first dielectric layer includes one or more of aluminum oxide, hafnium oxide and zirconium oxide.

9. The semiconductor structure according to claim 6, wherein: The doping particles include one or more of aluminum oxide, hafnium oxide and silicon oxide; the high dielectric constant material of the first dielectric layer is different from the doping particles.

10. The semiconductor structure according to claim 1, wherein: The thickness of the first dielectric layer ranges from 1.2 nm to 3 nm.

11. The semiconductor structure according to claim 1, wherein: The thickness of the first dielectric layer is in the range of 1.2 nm to 1.5 nm.

12. The semiconductor structure according to claim 2, wherein: The material of the second dielectric layer includes an amorphous material; the second dielectric layer is configured to provide a growth interface for the first dielectric layer.

13. The semiconductor structure according to claim 2, wherein: The functional stack further comprises: a barrier layer, disposed on a side of the capture layer close to the stacking structure; The tunneling layer is disposed between the capture layer and the channel layer.

14. The semiconductor structure according to claim 13, wherein: The material of the barrier layer includes an amorphous material; the amorphous material of the barrier layer is located on a side away from the stacked structure and in contact with the capture layer, and is configured to provide a growth interface for the first dielectric layer.

15. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure located on one side of the substrate, comprising alternately stacked insulating layers and sacrificial layers; forming a channel structure at least partially penetrating the stack structure, wherein the channel structure extends along a stacking direction of the stack structure; The channel structure includes a channel layer and a functional stack located on a side of the channel layer close to the stack structure; the functional stack includes an amorphous first dielectric layer.

16. The preparation method according to claim 15, characterized in that The forming of the channel structure at least partially penetrating the stack structure includes: Etching the stack structure to form a channel hole that at least partially penetrates the stack structure; forming a barrier layer on the sidewalls of the channel hole; forming the first dielectric layer on a side of the barrier layer away from the stacked structure; The dielectric constant of the barrier layer is smaller than the dielectric constant of the first dielectric layer; and / or the material of the barrier layer in contact with the first dielectric layer includes an amorphous material.

17. The preparation method according to claim 15, characterized in that The forming of the channel structure at least partially penetrating the stack structure includes: Etching the stack structure to form a channel hole that at least partially penetrates the stack structure; forming a barrier layer and a second dielectric layer in sequence on the sidewalls of the trench hole; forming the first dielectric layer on a side of the second dielectric layer away from the stacked structure; The dielectric constant of the second dielectric layer is smaller than the dielectric constant of the first dielectric layer; and / or the material of the second dielectric layer in contact with the first dielectric layer includes an amorphous material.

18. The preparation method according to claim 16 or 17, characterized in that: After forming the first dielectric layer, the method further includes: forming the second dielectric layer on a side of the first dielectric layer away from the stacked structure; or, A plurality of the first dielectric layers and a plurality of the second dielectric layers are alternately stacked.

19. The preparation method according to claim 16 or 17, characterized in that: Forming the first dielectric layer includes: A doped particle material layer is grown on one side of the initial material of the first dielectric layer to form the amorphous first dielectric layer under a first temperature range; different doped particle material layers have different process temperatures for forming the amorphous first dielectric layer.

20. The preparation method according to claim 15, characterized in that The forming of the channel structure at least partially penetrating the stack structure includes: forming a tunneling layer located on a side of the first dielectric layer close to the channel layer; The dielectric constant of the tunneling layer is smaller than the dielectric constant of the first dielectric layer.

21. A memory, characterized in that: include: One or more semiconductor structures according to any one of claims 1 to 14, configured to store data; The peripheral circuit is coupled to the one or more semiconductor structures and is configured to write, read, or erase data in the semiconductor structures in response to a received instruction.

22. A memory system, characterized in that: The memory system comprises: One or more memories as claimed in claim 21, configured to store data; A memory controller is coupled to the one or more memories and configured to control the memories to perform a programming operation.

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