Power semiconductor device and preparation method thereof

Abstract

The invention provides a power semiconductor device and a preparation method thereof, and the preparation method comprises the steps: providing a first conductive type substrate with a first conductive type epitaxial layer, and forming a plurality of gate groove structures, a plurality of source groove structures and a plurality of connecting groove structures in the epitaxial layer, a second conductive type body region is formed on the upper surface layer of the epitaxial layer except the gate groove structure, the source groove structure and the connecting groove structure, the second conductive type is opposite to the first conductive type, a first conductive type source region is formed on the upper surface layer of the body region, an electrode structure is formed, and the electrode structure comprises a first conductive column and a second conductive column; the first conductive column is electrically connected with the source trench structure, and the second conductive column penetrates through the source region and is electrically connected with the body region. According to the power semiconductor device, the breakdown voltage is improved through the gate groove structure and the source groove structure which are separated from each other, and meanwhile the on-resistance is further reduced through the connecting groove structure filled with the gate polycrystalline silicon layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing and relates to a power semiconductor device and a preparation method thereof. Background Art

[0002] The shielded gate trench (SGT) structure achieves low on-resistance, low switching losses, and good avalanche performance through deep trench design and shielded gate technology. However, in the existing SGT structure, the gate and source are located in the same trench and separated from the active area by an oxide layer dielectric. This leads to limited trench depletion capability, which in turn limits the device's ability to increase breakdown voltage (BV) and output capacitance (Coss), making it impossible to further increase the epitaxial concentration and thus effectively reduce the on-resistance (RdSon). At the same time, the gate is too close to the bottom source, which also increases the gate-source capacitance (Cgs).

[0003] Therefore, how to provide a power semiconductor device and a preparation method thereof to reduce on-resistance, reduce switching loss, and meet customer needs has become an important issue that needs to be urgently solved by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power semiconductor device and a preparation method thereof, so as to solve the problem of limited improvement in on-resistance and breakdown voltage capability of power semiconductor devices in the prior art.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a power semiconductor device, comprising the following steps:

[0007] Providing a first conductive type substrate, and forming a first conductive type epitaxial layer on one side of the substrate;

[0008] forming a plurality of gate trench structures, a plurality of source trench structures, and a plurality of connection trench structures in the epitaxial layer, wherein the plurality of gate trench structures are spaced apart along a first direction, the plurality of source trench structures are located between two adjacent gate trench structures and spaced apart along a second direction, the second direction being perpendicular to the first direction, and each connection trench structure connecting two adjacent source trench structures;

[0009] forming a second conductivity type body region on an upper surface layer of the epitaxial layer outside the gate trench structure, the source trench structure, and the connection trench structure, wherein the second conductivity type is opposite to the first conductivity type;

[0010] forming a first conductive type source region on an upper surface layer of the body region;

[0011] An electrode structure is formed, wherein the electrode structure includes a first conductive column and a second conductive column, wherein the first conductive column is electrically connected to the source trench structure, and the second conductive column penetrates the source region and is electrically connected to the body region.

[0012] Optionally, forming a gate trench structure, a source trench structure, and a connection trench structure in the epitaxial layer includes the following steps:

[0013] Etching the epitaxial layer to form a plurality of gate trenches and a plurality of source trenches in the epitaxial layer, wherein the plurality of gate trenches are spaced apart along the first direction, and the plurality of source trenches are located between two adjacent gate trenches and spaced apart along the second direction;

[0014] forming a field oxide layer and a source polysilicon layer in sequence in the source trench;

[0015] Etching the epitaxial layer and the field oxide layer to form a plurality of connection trenches, wherein the connection trenches include surrounding trenches and bridge trenches, wherein the surrounding trenches are located in the field oxide layer and surround the source polysilicon layer, and the bridge trenches are located in the epitaxial layer and connect two adjacent surrounding trenches;

[0016] A gate oxide layer and a gate polysilicon layer are sequentially formed in the gate trench and the connecting trench.

[0017] Optionally, the depths of the gate trench and the connection trench are smaller than the depth of the source trench.

[0018] Optionally, the cross-sectional shape of the source trench is any one of a hexagon, a circle, a triangle and a rectangle.

[0019] Optionally, the cross-sectional shape of the surrounding groove is any one of a hexagonal ring, a circular ring, a triangular ring and a rectangular ring.

[0020] The present invention also provides a power semiconductor device, comprising:

[0021] A first conductive type substrate, wherein a first conductive type epitaxial layer is provided on one side of the substrate;

[0022] A plurality of gate trench structures are arranged in the epitaxial layer at intervals along a first direction;

[0023] a plurality of source trench structures, spaced apart in the epitaxial layer along a second direction and located between two adjacent gate trench structures, wherein the second direction is perpendicular to the first direction;

[0024] A plurality of connection trench structures are disposed in the epitaxial layer, and each of the connection trench structures connects two adjacent source trench structures.

[0025] Optionally, it also includes:

[0026] A second conductive type body region is provided on an upper surface layer of the epitaxial layer outside the gate trench structure, the source trench structure and the connection trench structure, wherein the second conductive type is opposite to the first conductive type;

[0027] A first conductive type source region is provided on the upper surface layer of the body region;

[0028] The electrode structure includes a first conductive column and a second conductive column, wherein the first conductive column is electrically connected to the source trench structure, and the second conductive column passes through the source region and is electrically connected to the body region.

[0029] Optionally, the source trench structures are distributed in columns along the second direction, and the source trench structures in adjacent columns are staggered, the source trench structures have a hexagonal outline on a cross-section parallel to the upper surface of the epitaxial layer, and two opposite corners of the hexagonal outline are distributed along the second direction, and in the second direction, the connecting trench structure connects the corners of the hexagonal outlines of two adjacent source trench structures; and the gate trench structure is in a broken line shape along the second direction, and adjacent gate trench structures enclose a region with a maximum width and a minimum width in the first direction, wherein the source trench structure is located in the region with the maximum width, and the connecting trench structure is located in the region with the minimum width.

[0030] Optionally, the gate trench structure includes a gate trench, a gate oxide layer and a gate polysilicon layer, the gate trench is arranged in the epitaxial layer, the gate oxide layer is arranged on the sidewall and bottom of the gate trench, and the gate polysilicon layer is filled in the gate trench.

[0031] Optionally, the gate trench is any one of a zigzag trench, a straight trench and a curved trench.

[0032] Optionally, the source trench structure includes a source trench, a field oxide layer and a source polysilicon layer, the source trench is arranged in the epitaxial layer, the field oxide layer is arranged on the sidewall and bottom of the source trench, and the source polysilicon layer is filled in the source trench.

[0033] Optionally, the cross-sectional shape of the source trench is any one of a hexagon, a circle, a triangle and a rectangle.

[0034] Optionally, the connection groove structure includes a connection groove, a gate oxide layer and a gate polysilicon layer, the connection groove includes a surrounding groove and a bridge groove, the surrounding groove is located in the field oxide layer and surrounds the source polysilicon layer, the bridge groove is located in the epitaxial layer and connects two adjacent surrounding grooves, the gate oxide layer is arranged on the side wall and bottom of the connection groove, and the gate polysilicon layer is filled in the connection groove.

[0035] Optionally, the cross-sectional shape of the surrounding groove is any one of a hexagonal ring, a circular ring, a triangular ring and a rectangular ring.

[0036] As described above, the method for preparing a power semiconductor device of the present invention includes the steps of providing a first conductivity type substrate having a first conductivity type epitaxial layer, forming a plurality of gate trench structures, a plurality of source trench structures, and a plurality of connection trench structures in the epitaxial layer, forming a second conductivity type body region on the upper surface layer of the epitaxial layer outside the gate trench structures, the source trench structures, and the connection trench structures, the second conductivity type being opposite to the first conductivity type, forming a first conductivity type source region on the upper surface layer of the body region, and forming an electrode structure, the electrode structure including a first conductive pillar and a second conductive pillar, the first conductive pillar being electrically connected to the source trench structure, and the second conductive pillar extending through the source region and electrically connected to the body region. The power semiconductor device of the present invention improves the breakdown voltage by separating the gate trench structure and the source trench structure, while further reducing the on-resistance by filling the connection trench structure of the gate polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Shown is a process flow chart of the method for preparing a power semiconductor device of the present invention.

[0038] Figure 2 It is a schematic diagram showing a substrate provided in the method for manufacturing a power semiconductor device of the present invention.

[0039] Figure 3 It shows a top view of the structure obtained after forming the gate trench structure, the source trench structure and the connection trench structure in the method for manufacturing the power semiconductor device of the present invention.

[0040] Figure 4 It is a schematic diagram showing the structure obtained after forming gate trenches and source trenches in the method for manufacturing a power semiconductor device of the present invention.

[0041] Figure 5 It is a schematic diagram showing the structure obtained after forming a field oxide layer and a source polysilicon layer in the method for manufacturing a power semiconductor device of the present invention.

[0042] Figure 6 It is a schematic diagram showing the structure obtained after forming the connection groove in the method for manufacturing the power semiconductor device of the present invention.

[0043] Figure 7 It is a schematic diagram showing the structure obtained after forming a gate oxide layer and a gate polysilicon layer in the method for preparing a power semiconductor device of the present invention.

[0044] Figure 8 It is a schematic diagram showing the structure obtained after forming the body region in the method for manufacturing a power semiconductor device of the present invention.

[0045] Figure 9 It is a schematic diagram showing the structure obtained after forming the source region in the method for manufacturing a power semiconductor device of the present invention.

[0046] Figure 10 It is a schematic diagram showing the structure obtained after forming the electrode structure in the method for preparing the power semiconductor device of the present invention.

[0047] Figure 11 A top view showing a structure of a power semiconductor device according to the present invention is shown.

[0048] Figure 12 A top view showing another structure of a power semiconductor device according to the present invention is shown.

[0049] Figure 13 A top view showing another structure of a power semiconductor device according to the present invention is shown.

[0050] Description of Reference Numerals

[0051] 1 substrate

[0052] 2 Epitaxial layer

[0053] 3 Gate trench structure

[0054] 301 gate trench

[0055] 302 gate oxide layer

[0056] 303 gate polysilicon layer

[0057] 4 Source trench structure

[0058] 401 Source Trench

[0059] 402 Field Oxide Layer

[0060] 403 Source polysilicon layer

[0061] 5. Connection slot structure

[0062] 501 Surrounding groove

[0063] 502 bridge slot

[0064] 6 body zones

[0065] 7 Source area

[0066] 8 Electrode structure

[0067] 801 first conductive column

[0068] 802 second conductive column

[0069] Steps S1 to S5 DETAILED DESCRIPTION

[0070] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0071] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0072] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0073] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0074] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0075] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0076] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0077] See also Figure 1 , which is a process flow chart of a method for preparing a power semiconductor device of the present invention, comprising the following steps:

[0078] S1: providing a first conductive type substrate, and forming a first conductive type epitaxial layer on one side of the substrate;

[0079] S2: forming a plurality of gate trench structures, a plurality of source trench structures, and a plurality of connecting trench structures in the epitaxial layer, wherein the plurality of gate trench structures are spaced apart along a first direction, the plurality of source trench structures are located between two adjacent gate trench structures and spaced apart along a second direction, the second direction being perpendicular to the first direction, and each connecting trench structure connecting two adjacent source trench structures;

[0080] S3: forming a second conductivity type body region on the upper surface layer of the epitaxial layer outside the gate trench structure, the source trench structure, and the connection trench structure, wherein the second conductivity type is opposite to the first conductivity type;

[0081] S4: forming a first conductivity type source region on the upper surface of the body region;

[0082] S5: forming an electrode structure, wherein the electrode structure includes a first conductive pillar and a second conductive pillar, wherein the first conductive pillar is electrically connected to the source trench structure, and the second conductive pillar penetrates the source region and is electrically connected to the body region.

[0083] The following will be combined Figures 2 to 10 , detailing each step of the method for preparing a power semiconductor device of the present invention.

[0084] First see Figure 2 , performing step S1: providing a first conductive type substrate 1, and forming a first conductive type epitaxial layer 2 on one side of the substrate 1.

[0085] See also Figure 3, execute step S2: form a plurality of gate trench structures 3, a plurality of source trench structures 4 and a plurality of connection trench structures 5 in the epitaxial layer 2, the plurality of gate trench structures 3 are arranged at intervals along a first direction, the plurality of source trench structures 4 are located between two adjacent gate trench structures 3 and are arranged at intervals along a second direction, the second direction is perpendicular to the first direction, and each connection trench structure 5 connects two adjacent source trench structures 4.

[0086] It should be noted that Figure 3 A schematic diagram of the layout. Figure 2 The left side corresponds to Figure 3 Schematic diagram of the cross section along the AA' section, the right side is the corresponding Figure 3 In this application, in order to facilitate the description of the manufacturing process of the power semiconductor device, Figures 4 to 10 The schematic method and Figure 2 Same, that is, the left side corresponds to Figure 3 Schematic diagram of the cross section along the AA' section, the right side is the corresponding Figure 3 Cross-sectional view along the BB' section.

[0087] As an example, forming the gate trench structure 3, the source trench structure 4 and the connection trench structure 5 in the epitaxial layer 2 includes the following steps:

[0088] (1) Please refer to Figure 4 , etching the epitaxial layer 2 to form a plurality of gate trenches 301 and a plurality of source trenches 401 in the epitaxial layer 2, wherein the plurality of gate trenches 301 are spaced apart along the first direction, and the plurality of source trenches 401 are located between two adjacent gate trenches 301 and spaced apart along the second direction;

[0089] (2) Please refer to Figure 5 , forming a field oxide layer 402 and a source polysilicon layer 403 in sequence in the source trench 401;

[0090] (3) Please refer to Figure 6 , etching the epitaxial layer 2 and the field oxide layer 402 to form a plurality of connection grooves, wherein the connection grooves include a surrounding groove 501 and a bridge groove 502, wherein the surrounding groove 501 is located in the field oxide layer 402 and surrounds the source polysilicon layer 403, and the bridge groove 502 is located in the epitaxial layer 2 and connects two adjacent surrounding grooves 501;

[0091] (4) Please refer to Figure 7 , sequentially forming a gate oxide layer 302 and a gate polysilicon layer 303 in the gate trench 301 and the connecting trench, wherein the connecting trench includes the surrounding trench 501 and the bridge trench 502, and the surrounding trench 501 is located in the field oxide layer 402, Figure 7The gate oxide layer 302 deposited in the surrounding groove 501 is not marked. In other embodiments, the surrounding groove 501 can be filled with only the gate polysilicon layer 303, and the field oxide layer 402 can also isolate the gate polysilicon layer 303 in the surrounding groove 501 from the epitaxial layer 2 and the source polysilicon layer 403.

[0092] Specifically, the source trench structure 4 and the gate trench structure 3 are separated from each other, which can not only reduce the electric field peak in the epitaxial layer 2 (i.e., the drift region), thereby increasing the breakdown voltage of the device, but also optimize the electric field distribution in the epitaxial layer 2, thereby reducing the resistance of the epitaxial layer 2 and reducing the on-resistance. In addition, the connecting groove connects the two adjacent source trenches 401 through the surrounding groove 501 and the bridge groove 502, and the gate polysilicon layer 303 is filled in the connecting groove. This design increases the gate branch, increases the channel density, and provides more carrier transmission paths, thereby improving the current carrying capacity of the device, further reducing the on-resistance, reducing the conduction loss, reducing the on-resistance, reducing the power loss, and improving the efficiency of the device. At the same time, this structure also enhances the gate control capability, further improving the amplification capability and response speed of the device.

[0093] As an example, the depths of the gate trench 301 and the connection trench are smaller than the depth of the source trench 401 .

[0094] Specifically, when etching the epitaxial layer 2 to form multiple gate trenches 301 and multiple source trenches 401, multiple gate trenches 301 and multiple source trenches 401 with the same depth can be etched first, and then the source trenches 401 are etched a second time to obtain the source trenches 401 of the expected depth. That is to say, the source trenches 401 can be etched in two steps.

[0095] As an example, the cross-sectional shape of the source trench 401 is any one of a hexagon, a circle, a triangle and a rectangle.

[0096] As an example, the cross-sectional shape of the surrounding groove 501 is any one of a hexagonal ring, a circular ring, a triangular ring and a rectangular ring.

[0097] As an example, the thickness of the field oxide layer 402 is greater than the thickness of the gate oxide layer 302 .

[0098] See also Figure 8 , perform step S3: form a second conductivity type body region 6 on the upper surface layer of the epitaxial layer 2 outside the gate trench structure 3, the source trench structure 4 and the connection trench structure 5, where the second conductivity type is opposite to the first conductivity type.

[0099] See also Figure 9 , executing step S4: forming a first conductive type source region 7 on the upper surface layer of the body region 6.

[0100] See also Figure 10 Execute step S5: form an electrode structure 8, the electrode structure 8 includes a first conductive column 801 and a second conductive column 802, the first conductive column 801 is electrically connected to the source trench structure 4, and the second conductive column 802 passes through the source region 7 and is electrically connected to the body region 6.

[0101] It should be noted that, in this embodiment, the electrical connection between the first conductive pillar 801 and the source trench structure 4 refers to the electrical connection between the first conductive pillar 801 and the source polysilicon layer 403 in the source trench structure 4 .

[0102] In this embodiment, the motor structure 8 is formed by etching carbon nanotubes, and a metal layer is deposited on the upper surface of the carbon nanotubes to increase the conductivity of the carbon nanotubes.

[0103] Through steps S1 to S5, the power semiconductor device fabrication method of the present invention can increase channel density and reduce device on-resistance without sacrificing MOS area and avalanche capability. This method does not require special processes and is fully compatible with existing processes. Furthermore, the optimized gate structure design helps reduce gate resistance, thereby reducing device switching losses.

[0104] As an example, the method further includes forming a leakage metal layer, wherein the leakage metal layer is provided on the back side of the substrate 1 .

[0105] So far, a power semiconductor device has been manufactured. Figure 10 The power semiconductor device includes a first conductive type substrate 1, a plurality of gate trench structures 3, a plurality of source trench structures 4, and a plurality of connection trench structures 5, wherein a first conductive type epitaxial layer 2 is provided on one side of the substrate 1.

[0106] For details, please refer to Figure 11 , multiple gate trench structures 3 are arranged in the epitaxial layer 2 at intervals along a first direction, multiple source trench structures 4 are arranged in the epitaxial layer 2 at intervals along a second direction and are located between two adjacent gate trench structures 3, the second direction is perpendicular to the first direction, multiple connecting trench structures 5 are arranged in the epitaxial layer 2, and each connecting trench structure 5 connects two adjacent source trench structures 4.

[0107] As an example, see Figure 10The power semiconductor device also includes a second conductive type body region 6, a first conductive type source region 7 and an electrode structure 8, wherein the second conductive type is opposite to the first conductive type, the body region 6 is arranged on the upper surface of the epitaxial layer 2 outside the gate trench structure 3, the source trench structure 4 and the connection trench structure 5, the source region 7 is arranged on the upper surface of the body region 6, and the electrode structure 8 includes a first conductive column 801 and a second conductive column 802, the first conductive column 801 is electrically connected to the source trench structure 4, and the second conductive column 802 passes through the source region 7 and is electrically connected to the body region 6.

[0108] As an example, see Figure 11 The source trench structures 4 are distributed in columns along the second direction, and the source trench structures 4 in adjacent columns are staggered. The source trench structures 4 have a hexagonal outline on a cross section parallel to the upper surface of the epitaxial layer 2, and two opposite corners of the hexagonal outline are distributed along the second direction. In the second direction, the connecting groove structure 5 connects the corners of the hexagonal outlines of two adjacent source trench structures 4; and the gate trench structure 3 is in a broken line shape along the second direction, and adjacent gate trench structures 3 enclose a region with a maximum width and a minimum width in the first direction, wherein the source trench structure 4 is located in the region with the maximum width, and the connecting groove structure 5 is located in the region with the minimum width.

[0109] As an example, the gate trench structure 3 includes a gate trench 301, a gate oxide layer 302 and a gate polysilicon layer 303, the gate trench 301 is arranged in the epitaxial layer 2, the gate oxide layer 302 is arranged on the sidewall and bottom of the gate trench 301, and the gate polysilicon layer 303 is filled in the gate trench 301.

[0110] As an example, the gate trench 301 is any one of a zigzag trench, a straight line trench and a curved trench. In this embodiment, please refer to Figure 11 The gate trench 301 is a folded line trench, which is formed by continuously splicing a plurality of trapezoidal structural units connected end to end. Each of the trapezoidal structural units includes a first oblique line portion, a transition straight line portion and a second oblique line portion connected in sequence.

[0111] As an example, the source trench structure 4 includes a source trench 401, a field oxide layer 402 and a source polysilicon layer 403, the source trench 401 is arranged in the epitaxial layer 2, the field oxide layer 402 is arranged on the sidewall and bottom of the source trench 401, and the source polysilicon layer 403 is filled in the source trench 401, wherein the source polysilicon layer 403 is electrically connected to the first conductive column 801.

[0112] As an example, the cross-sectional shape of the source trench 401 is any one of a hexagon, a circle, a triangle and a rectangle.

[0113] As an example, the connection groove structure 5 includes a connection groove, a gate oxide layer 302 and a gate polysilicon layer 303, the connection groove includes a surrounding groove 501 and a bridge groove 502, the surrounding groove 501 is located in the field oxide layer 402 and surrounds the source polysilicon layer 403, the bridge groove 502 is located in the epitaxial layer 2 and connects two adjacent surrounding grooves 501, the gate oxide layer 302 is arranged on the side wall and bottom of the connection groove, and the gate polysilicon layer 303 is filled in the connection groove.

[0114] As an example, the cross-sectional shape of the surrounding groove 501 is any one of a hexagonal ring, a circular ring, a triangular ring and a rectangular ring.

[0115] As an example, see Figures 11 to 13 The cross-sectional areas of the gate trench structure 3, the source trench structure 4 and the connection trench 5 can be of different shapes and can be adjusted according to specific needs. No excessive restrictions are made here. Figure 11 It is a top view showing a structure of a power semiconductor device of the present invention, Figure 12 A top view showing another structure of the power semiconductor device of the present invention is shown. Figure 13 A top view showing another structure of a power semiconductor device according to the present invention is shown.

[0116] In summary, the method for preparing a power semiconductor device of the present invention includes the following steps: providing a first conductivity type substrate having a first conductivity type epitaxial layer, forming a plurality of gate trench structures, a plurality of source trench structures, and a plurality of connection trench structures in the epitaxial layer, forming a second conductivity type body region on the upper surface layer of the epitaxial layer outside the gate trench structures, the source trench structures, and the connection trench structures, wherein the second conductivity type is opposite to the first conductivity type, forming a first conductivity type source region on the upper surface layer of the body region, and forming an electrode structure, wherein the electrode structure includes a first conductive pillar and a second conductive pillar, wherein the first conductive pillar is electrically connected to the source trench structure, and the second conductive pillar extends through the source region and is electrically connected to the body region. The power semiconductor device of the present invention improves the breakdown voltage by separating the gate trench structure and the source trench structure, while further reducing the on-resistance by filling the connection trench structure of the gate polysilicon layer. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0117] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a power semiconductor device, characterized in that: The following steps are involved: Providing a first conductive type substrate, and forming a first conductive type epitaxial layer on one side of the substrate; forming a plurality of gate trench structures, a plurality of source trench structures, and a plurality of connection trench structures in the epitaxial layer, wherein the plurality of gate trench structures are spaced apart along a first direction, the plurality of source trench structures are located between two adjacent gate trench structures and spaced apart along a second direction, the second direction being perpendicular to the first direction, and each connection trench structure connecting two adjacent source trench structures; forming a second conductivity type body region on an upper surface layer of the epitaxial layer outside the gate trench structure, the source trench structure, and the connection trench structure, wherein the second conductivity type is opposite to the first conductivity type; forming a first conductive type source region on an upper surface layer of the body region; An electrode structure is formed, wherein the electrode structure includes a first conductive column and a second conductive column, wherein the first conductive column is electrically connected to the source trench structure, and the second conductive column penetrates the source region and is electrically connected to the body region.

2. The method for preparing a power semiconductor device according to claim 1, wherein: Forming a gate trench structure, a source trench structure, and a connection trench structure in the epitaxial layer includes the following steps: Etching the epitaxial layer to form a plurality of gate trenches and a plurality of source trenches in the epitaxial layer, wherein the plurality of gate trenches are spaced apart along the first direction, and the plurality of source trenches are located between two adjacent gate trenches and spaced apart along the second direction; forming a field oxide layer and a source polysilicon layer in sequence in the source trench; Etching the epitaxial layer and the field oxide layer to form a plurality of connection trenches, wherein the connection trenches include surrounding trenches and bridge trenches, wherein the surrounding trenches are located in the field oxide layer and surround the source polysilicon layer, and the bridge trenches are located in the epitaxial layer and connect two adjacent surrounding trenches; A gate oxide layer and a gate polysilicon layer are sequentially formed in the gate trench and the connecting trench.

3. The method for preparing a power semiconductor device according to claim 2, wherein: The depths of the gate trench and the connection trench are smaller than the depth of the source trench.

4. The method for preparing a power semiconductor device according to claim 2, wherein: The cross-sectional shape of the source trench is any one of a hexagon, a circle, a triangle and a rectangle.

5. The method for preparing a power semiconductor device according to claim 2, wherein: The cross-sectional shape of the surrounding groove is any one of a hexagonal ring, a circular ring, a triangular ring and a rectangular ring.

6. A power semiconductor device, characterized in that: include: A first conductive type substrate, wherein a first conductive type epitaxial layer is provided on one side of the substrate; A plurality of gate trench structures are arranged in the epitaxial layer at intervals along a first direction; a plurality of source trench structures, spaced apart in the epitaxial layer along a second direction and located between two adjacent gate trench structures, wherein the second direction is perpendicular to the first direction; A plurality of connection trench structures are disposed in the epitaxial layer, and each of the connection trench structures connects two adjacent source trench structures.

7. The power semiconductor device according to claim 6, characterized in that Also includes: A second conductive type body region is provided on an upper surface layer of the epitaxial layer outside the gate trench structure, the source trench structure and the connection trench structure, wherein the second conductive type is opposite to the first conductive type; A first conductive type source region is provided on the upper surface layer of the body region; The electrode structure includes a first conductive column and a second conductive column, wherein the first conductive column is electrically connected to the source trench structure, and the second conductive column passes through the source region and is electrically connected to the body region.

8. The power semiconductor device according to claim 6, wherein: The source trench structures are distributed in columns along the second direction, and the source trench structures in adjacent columns are staggered; The source trench structure has a hexagonal outer profile in a cross section parallel to the upper surface of the epitaxial layer, two opposite corners of the hexagonal outer profile are distributed along the second direction, and in the second direction, the connecting groove structure connects the corners of the hexagonal outer profiles of two adjacent source trench structures; as well as The gate trench structure is in a zigzag shape along the second direction, and adjacent gate trench structures enclose a region with maximum and minimum widths in the first direction, wherein the source trench structure is located in the region with maximum width, and the connection trench structure is located in the region with minimum width.

9. The power semiconductor device according to claim 6, wherein: The gate trench structure includes a gate trench, a gate oxide layer and a gate polysilicon layer. The gate trench is arranged in the epitaxial layer, the gate oxide layer is arranged on the sidewall and bottom of the gate trench, and the gate polysilicon layer is filled in the gate trench.

10. The power semiconductor device according to claim 9, wherein: The gate trench is any one of a zigzag trench, a straight trench and a curved trench.

11. The power semiconductor device according to claim 6, wherein: The source trench structure includes a source trench, a field oxide layer and a source polysilicon layer. The source trench is arranged in the epitaxial layer, the field oxide layer is arranged on the sidewall and bottom of the source trench, and the source polysilicon layer is filled in the source trench.

12. The power semiconductor device according to claim 11, wherein: The cross-sectional shape of the source trench is any one of a hexagon, a circle, a triangle and a rectangle.

13. The power semiconductor device according to claim 11, wherein: The connection groove structure includes a connection groove, a gate oxide layer and a gate polysilicon layer. The connection groove includes a surrounding groove and a bridge groove. The surrounding groove is located in the field oxide layer and surrounds the source polysilicon layer. The bridge groove is located in the epitaxial layer and connects two adjacent surrounding grooves. The gate oxide layer is arranged on the sidewall and bottom of the connection groove, and the gate polysilicon layer is filled in the connection groove.

14. The power semiconductor device according to claim 13, wherein: The cross-sectional shape of the surrounding groove is any one of a hexagonal ring, a circular ring, a triangular ring and a rectangular ring.

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