Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, wherein the semiconductor body further comprises a well region and a first region; the first surface is further provided with a groove, the groove comprises a voltage-withstanding layer filling groove and a grid electrode groove which are communicated, the grid electrode groove extends into the semiconductor body from the first surface, and the voltage-withstanding layer filling groove is located between the grid electrode groove and the second surface; the pressure-resistant filling layer is located in the pressure-resistant layer filling groove; the two-dimensional material layer is arranged to be of the first conduction type and is located on the side wall of the gate trench; the carrier mobility of the two-dimensional material layer is greater than that of silicon carbide; the trench gate is positioned on one side, far away from the semiconductor body, of the first insulating layer in the gate trench; the source electrode is located on the first surface. According to the technical scheme of the embodiment of the invention, the on resistance of the semiconductor device is reduced, and the voltage resistance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] In the prior art, a positive voltage is applied to the gate of a SiC or GaN metal-oxide-semiconductor field-effect transistor (MOSFET). When the threshold voltage is reached, an inversion layer is formed in the well region. The direction of electron movement is from the first region formed by ion implantation of the metal conductive layer to the inversion layer in the well region, and then through the semiconductor body to reach the drain.

[0004] However, in the prior art, ion implantation to form the first region causes lattice damage to the semiconductor body, leading to an increase in interface states, reduced electron mobility in the channel region, and excessively high on-resistance in SiC or GaN MOSFETs. Furthermore, in the prior art, when the gate structure is a trench gate structure, the withstand voltage performance of the semiconductor device is poor. Summary of the Invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of the semiconductor device and improve the withstand voltage performance of the semiconductor device.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0007] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a trench being further provided on the first surface, the trench comprising a connected voltage-resistant layer-filled trench and a gate trench, the gate trench extending from the first surface into the semiconductor body, the voltage-resistant layer-filled trench being located between the gate trench and the second surface; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on a sidewall of the gate trench;

[0008] a pressure-resistant filling layer, located in the pressure-resistant layer filling groove;

[0009] a two-dimensional material layer, the two-dimensional material layer being of a first conductivity type and being located on a sidewall of the gate trench; the two-dimensional material layer being located between the first region and the first insulating layer, and the two-dimensional material layer being located between the well region and the first insulating layer; and the carrier mobility of the two-dimensional material layer being greater than that of silicon carbide;

[0010] a trench gate, the trench gate being located in the gate trench on a side of the first insulating layer away from the semiconductor body;

[0011] a source electrode, located on the first surface;

[0012] The drain is located on the second surface.

[0013] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0014] Providing a first semiconductor body, wherein the first semiconductor body includes a third surface and a second surface arranged opposite to each other;

[0015] forming a voltage-resistant layer-filled trench on the third surface, wherein the voltage-resistant layer-filled trench extends from the third surface into the first semiconductor body;

[0016] forming a pressure-resistant filling layer in the pressure-resistant layer filling groove;

[0017] forming a second semiconductor body on the third surface, the second semiconductor body including a first surface and a fourth surface opposite to each other, the fourth surface being in contact with the third surface, the first semiconductor body and the second semiconductor body constituting a semiconductor body, the semiconductor body including the first surface and the second surface opposite to each other;

[0018] A well region, a first region, and a gate trench are formed in the second semiconductor body, wherein the first region is configured to be of a first conductivity type and is located on the first surface, and the well region is configured to be of a second conductivity type and is located on a side of the first region away from the first surface; the gate trench is located on the first surface and is connected to the voltage-resistant layer-filled trench, forming a trench provided on the first surface;

[0019] forming a two-dimensional material layer on a sidewall of the gate trench, wherein the two-dimensional material layer is set to a first conductivity type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide;

[0020] forming a first insulating layer on a sidewall of the gate trench, wherein the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer;

[0021] forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench;

[0022] forming a source electrode on the first surface;

[0023] A drain electrode is formed on the second surface.

[0024] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0025] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0026] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0027] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0028] In the semiconductor device and manufacturing method, power module, power conversion circuit and vehicle of the embodiments of the present invention, the trench gate extends from the first surface into the semiconductor body, and there is no need to set a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. The voltage-resistant filling layer is located in the voltage-resistant layer filling trench and between the gate structure and the second surface, which can effectively reduce the peak electric field under the first insulating layer of the trench-type gate structure close to the second surface, thereby improving the voltage resistance performance of the semiconductor device. A two-dimensional material layer with a carrier mobility greater than that of silicon carbide is located on the sidewall of the gate trench. The two-dimensional material layer serves as the channel of the semiconductor device, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. The well region forms a PN junction contact with the two-dimensional material layer, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device. Because the carrier mobility of the two-dimensional material layer is greater than that of silicon carbide, it can effectively improve the carrier mobility of the semiconductor device channel, and the effects of lattice damage to the semiconductor body, increased interface states, and reduced carrier mobility in the channel region caused by the ion doping process when forming the first region can be ignored. Furthermore, there is no need to limit the thickness of the first insulating layer to reduce on-resistance, thereby increasing the threshold voltage of the semiconductor device and improving the control performance of the semiconductor device.

[0029] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0032] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0033] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0034] Figure 4 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0035] Figure 5-Figure 15 yes Figure 4 Schematic diagram of the structure corresponding to each step;

[0036] Figure 16 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0037] Figures 17-26 yes Figure 16 Schematic diagram of the structure corresponding to each step;

[0038] Figure 27 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0039] Figures 28-37 yes Figure 27 Schematic diagram of the structure corresponding to each step in . DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] In order to reduce the on-resistance of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0043] like Figure 1 As shown, Figure 11 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 100, comprising a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 100 further comprising a well region 103 and a first region 104, the first region 104 being configured as a first conductive type and being located on the first surface 101, the well region 103 being configured as a second conductive type and being located on a side of the first region 104 away from the first surface 101; the first surface 101 further comprising a trench T0, the trench T0 comprising a connected voltage-resistant layer-filled trench T1 and a gate trench T2, the gate trench T2 extending from the first surface 101 into the semiconductor body 100, the voltage-resistant layer-filled trench T1 and the gate trench T2 extending from the first surface 101 into the semiconductor body 100, The groove T1 is located between the gate trench T2 and the second surface 102; the semiconductor body 100 also includes a first insulating layer 401, which is located on the side wall of the gate trench T2; a voltage-resistant filling layer 200, which is located in the voltage-resistant layer filling trench T1; a two-dimensional material layer 300, which is set to a first conductive type and is located on the side wall of the gate trench T2; the carrier mobility of the two-dimensional material layer 300 is greater than the carrier mobility of silicon carbide; a trench gate 402, which is located on the side of the first insulating layer 401 in the gate trench T2 away from the semiconductor body 100; a source 503, which is located on the first surface 101; and a drain 600, which is located on the second surface 102.

[0044] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0045] For example, for an N-type MOSFET, first region 104 is an N+ doped region, where the N-type dopant ions may be phosphorus (P) or nitrogen (N). Well region 103 is a P-well region, where the P-type dopant ions may be aluminum (Al) or boron (B). Two-dimensional material layer 300 is an N-type channel layer, and the carrier mobility of two-dimensional material layer 300 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0046] like Figure 1As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by an epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0047] Optionally, an interlayer insulating layer 403 is used to insulate the gate and source.

[0048] In an embodiment of the present invention, the two-dimensional material layer 300 includes a semiconductor layer and may also include a non-semiconductor layer. In crystallography, the two-dimensional material layer 300 refers to a material with a thickness of only a single atomic layer or two atomic layers, and its thickness is on the order of a few nanometers. The two-dimensional material layer 300 has a high carrier mobility. The carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. In addition, the well region 103 and the two-dimensional material layer 300 have different conductivity types, and can form a PN junction contact, generate a depletion region at the channel, and reduce the off-state leakage current of the semiconductor device.

[0049] In the semiconductor device of the embodiment of the present invention, the trench gate 402 extends from the first surface 101 into the semiconductor body 100, eliminating the need for a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. The voltage-resistant filling layer 200 is located within the voltage-resistant layer-filled trench T1 and between the trench gate and the second surface 102. This effectively reduces the peak electric field below the first insulating layer 401 of the trench-type gate close to the second surface 102, thereby improving the voltage resistance of the semiconductor device. A two-dimensional material layer 300 having a carrier mobility greater than that of silicon carbide is located on the sidewall of the gate trench T2. The two-dimensional material layer 300 serves as the channel of the semiconductor device, effectively improving the carrier mobility of the semiconductor device channel and reducing the on-resistance. The well region 103 forms a PN junction contact with the two-dimensional material layer 300, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device. Among them, because the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide, it can effectively improve the carrier mobility of the semiconductor device channel, and the effects of lattice damage to the semiconductor body 100, increase in interface states, and reduction in carrier mobility in the channel region caused by the ion doping process to form the first region 104 can be ignored. In addition, there is no need to limit the thickness of the first insulating layer 401 to reduce the on-resistance, thereby increasing the threshold voltage of the semiconductor device and improving the control performance of the semiconductor device. Among them, the ion doping process includes ion implantation, ion diffusion, or vapor deposition.

[0050] In other optional embodiments of the present invention, refer to Figure 1 , the carrier mobility of the two-dimensional material layer 300 in different directions is the same.

[0051] Optionally, based on the above technical solution, Figure 1 As shown, the two-dimensional material layer 300 includes a two-dimensional material semiconductor layer.

[0052] Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material that is only a single atomic layer or two atomic layers thick, with a thickness on the order of a few nanometers. Two-dimensional material semiconductor layers have high carrier mobility, and common two-dimensional material semiconductor layers include graphene and graphene derivatives. The carrier mobility of a two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the two-dimensional material layer 300, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0053] Optionally, based on the above technical solution, the voltage-resistant layer filling trench T1 includes a V-shaped trench or a U-shaped trench, or the gate trench T2 includes a V-shaped trench or a U-shaped trench; or, the voltage-resistant layer filling trench T1 includes a V-shaped trench or a U-shaped trench, and the gate trench T2 includes a V-shaped trench or a U-shaped trench.

[0054] like Figure 1 As shown, the voltage-resistant layer-filled trench T1 is a V-shaped trench. In other optional embodiments of the present invention, the voltage-resistant layer-filled trench T1 may also be a U-shaped trench. The voltage-resistant layer-filled trench T1 is configured as a V-shaped trench, which reduces the area occupied by the semiconductor body 100, thereby reducing the on-resistance. The voltage-resistant layer-filled trench T1 is configured as a U-shaped trench, which reduces the manufacturing difficulty of the voltage-resistant layer-filled trench T1, thereby reducing the manufacturing cost of the semiconductor device.

[0055] like Figure 1 As shown, the gate trench T2 is a V-shaped groove. In other optional embodiments of the present invention, the gate trench T2 can also be a U-shaped groove. The first surface 101 is provided with a gate trench T2 including a V-shaped groove or a U-shaped groove, so that the trench gate 402 extends from the first surface 101 into the semiconductor body 100, and there is no need to set a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. The gate trench T2 with a V-shaped groove reduces the area occupied by the semiconductor body 100, thereby reducing the on-resistance. The gate trench T2 with a U-shaped groove reduces the manufacturing difficulty of the gate trench T2, thereby reducing the preparation cost of the semiconductor device.

[0056] Optionally, based on the above technical solution, Figure 2 As shown, Figure 2 This is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. A plurality of gate trenches T2 are provided on the first surface 101. The plurality of gate trenches T2 are located on the first surface 101 and are spaced apart. A voltage-resistant layer fills the trenches T1 and the gate trenches T2 in a one-to-one correspondence. The voltage-resistant layer fills the trenches T1 and the gate trenches T2 in a one-to-one correspondence. A voltage-resistant filling layer 200 is provided in each of the voltage-resistant layer fills. As the number of voltage-resistant layer fills the trenches T1 and the gate trenches T2 increases, the area of ​​the semiconductor body 100 is further reduced, thereby further reducing the on-resistance of the semiconductor device.

[0057] Optionally, based on the above technical solution, Figure 3 As shown, Figure 3This is a structural schematic diagram of another semiconductor device provided by an embodiment of the present invention, in which a source trench T3 is further provided in the semiconductor body 100; the semiconductor body 100 also includes a second region 105, which is set to a second conductive type and surrounds the bottom surface and side walls of the source trench T3; the ion concentration of the second region 105 is greater than the ion concentration of the well region 103; the vertical distance d1 between the second region 105 and the second surface 102 is less than the vertical distance d2 between the voltage-resistant layer filling trench T1 and the second surface 102; the semiconductor device also includes a source trench structure 500, 500 includes a filling layer 502 and a second insulating layer 501; the second insulating layer 501 is located at the bottom surface and side walls of the source trench T3; the filling layer 502 is located on the side of the second insulating layer 501 in the source trench T3 away from the semiconductor body 100. The source semiconductor body 100 further includes a third region 106 . The third region 106 is configured to be of the second conductivity type. The third region 106 is located on the first surface 101 and covers the second region 105 , the second insulating layer 501 and the source filling layer 502 .

[0058] Specifically, the provision of the source trench structure 500 can effectively reduce the peak electric field below the first insulating layer 401 near the second surface 102 of the trench gate 402, thereby improving the withstand voltage performance of the semiconductor device. In addition, a third region 106 is provided on the first surface 101, and the third region 106 is in direct contact with the source 503. The third region 106 can form a good ohmic contact with the source 503. In addition, the third region 106 is located between the source 503 and the second region 105, the second insulating layer 501 and the source filling layer 502, further increasing the depth of the source trench T3, helping to further reduce the peak electric field below the first insulating layer 401 near the second surface 102 of the trench gate 402, and improving the withstand voltage performance of the semiconductor device. Among them, the semiconductor body 100 may also include a second region 105, the conductivity type of the second region 105 is the second conductivity type, and the ion concentration of the second region 105 is greater than the ion concentration of the well region 103, so as to form a good ohmic contact with the source 503.

[0059] Optionally, based on the above technical solution, the source trench T3 comprises a V-shaped trench or a U-shaped trench. Compared to a U-shaped trench, a V-shaped trench reduces the area occupied by the semiconductor body 100, thereby reducing the on-resistance of the semiconductor device. The U-shaped source trench T3 reduces the manufacturing difficulty of the source trench T3, thereby reducing the manufacturing cost of the semiconductor device.

[0060] In other optional embodiments, when the semiconductor device includes a source trench structure 500, at least two spaced trenches T0 may also be provided on one side of the source trench structure 500, a two-dimensional material layer 300 is provided in a one-to-one correspondence in the sidewalls of the gate trench T2, and a trench gate 402 is provided in a one-to-one correspondence in the gate trench T2; the voltage-resistant layer filling trench T1 and the gate trench T2 are connected in a one-to-one correspondence, and a voltage-resistant filling layer 200 is provided in a one-to-one correspondence in the voltage-resistant layer filling trench T1, further reducing the area of ​​the semiconductor body 100, thereby further reducing the on-resistance of the semiconductor device.

[0061] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0062] The semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device, the semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0063] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0064] It should be noted that in the semiconductor device provided in an embodiment of the present invention, a two-dimensional material layer 300 having a carrier mobility greater than that of silicon carbide is located on the sidewalls of the gate trench T2. The two-dimensional material layer 300, serving as the channel of the semiconductor device, can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. When the gate trench T2 extends to the drift layer, the two-dimensional material layer 300 can be disposed only on the sidewalls of the gate trench T2 that contact the first region 104 and the well region 103, thereby achieving the effect of improving the carrier mobility within the channel and reducing the on-resistance of the semiconductor device.

[0065] Optionally, based on the above technical solution, the voltage-resistant filling layer 200 includes one or more voltage-resistant filling sublayers; the voltage-resistant filling sublayers include any one of silicon oxide, silicon nitride and polysilicon, and the material of the voltage-resistant filling layer 200 can be flexibly selected.

[0066] For example, Figure 1-Figure 3As shown, the voltage-resistant filling layer 200 includes two voltage-resistant filling sublayers, namely a first voltage-resistant filling sublayer 201 and a second voltage-resistant filling sublayer 202. The first voltage-resistant filling sublayer 201 is silicon oxide, and the second voltage-resistant filling sublayer 202 is polysilicon. In other optional embodiments, the first voltage-resistant filling sublayer 201 can be made of silicon nitride or polysilicon, and the second voltage-resistant filling sublayer 202 can be made of silicon oxide or silicon nitride.

[0067] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 4 As shown, Figure 4 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, the manufacturing method comprising the following steps:

[0068] S110 , providing a first semiconductor body, wherein the first semiconductor body includes a third surface and a second surface opposite to each other.

[0069] like Figure 5 As shown, a first semiconductor body 100a in a semiconductor body 100 is provided, and the first semiconductor body 100a includes a third surface 110 and a second surface 102 arranged opposite to each other. Exemplarily, the first semiconductor body 100a includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first semiconductor body 100a may also include only the epitaxial layer 20. In other embodiments of the present invention, the first semiconductor body 100a may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 by an epitaxial process, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0070] S120 , forming a voltage-resistant layer-filled trench on the third surface, wherein the voltage-resistant layer-filled trench extends from the third surface into the first semiconductor body.

[0071] like Figure 6 As shown, a voltage-withstanding layer-filled trench T1 is formed on the third surface 110 through a trench etching process, a sacrificial oxide layer preparation process, and an oxide layer removal process. The voltage-withstanding layer-filled trench T1 extends from the third surface 110 into the first semiconductor body 100 a .

[0072] S130 , forming a voltage-resistant filling layer in the voltage-resistant layer filling groove.

[0073] The process of forming the voltage-resistant filling layer 200 in the voltage-resistant layer filling trench T1 is as follows:

[0074] like Figure 7 As shown, a first voltage-resistant filling sub-layer 201 in the voltage-resistant filling layer 200 is formed in the voltage-resistant filling trench T1 by deposition or thermal oxidation process. Figure 8 As shown, a second voltage-resistant filling sublayer 202 is formed by a deposition process on the side of the first voltage-resistant filling sublayer 201 in the voltage-resistant layer filling trench T1 away from the first semiconductor body 100a. Exemplarily, the first voltage-resistant filling sublayer 201 is silicon oxide, and the second voltage-resistant filling sublayer 202 is polysilicon.

[0075] S140. Form a second semiconductor body on the third surface, the second semiconductor body including a first surface and a fourth surface opposite to each other, the fourth surface and the third surface contacting each other, the first semiconductor body and the second semiconductor body constituting a semiconductor body, the semiconductor body including a first surface and a second surface opposite to each other.

[0076] like Figure 9 As shown, a second semiconductor body 100b is formed on the third surface 110 through an epitaxial process. The second semiconductor body 100b is an epitaxial layer. The second semiconductor body 100b includes a first surface 101 and a fourth surface disposed opposite each other. The fourth surface is in contact with the third surface 110. The first semiconductor body 100a and the second semiconductor body 100b constitute a semiconductor body 100. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite each other.

[0077] S150: Form a well region, a first region, and a gate trench within the second semiconductor body. The first region is configured to be of the first conductivity type and located on the first surface. The well region is configured to be of the second conductivity type and located on a side of the first region away from the first surface. The gate trench is located on the first surface and communicates with the voltage-resistant layer-filled trench, forming a trench disposed on the first surface.

[0078] like Figure 10 As shown, a well region 103 and a first region 104 are formed in the second semiconductor body 100 b through an ion doping process and a high-temperature retreat process. The first region 104 is set to the first conductivity type and is located on the first surface 101. The well region 103 is set to the second conductivity type and is located on a side of the first region 104 away from the first surface 101. The ion doping process includes ion implantation, ion diffusion, or vapor deposition.

[0079] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0080] Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0081] Optionally, based on the above technical solution, Figure 10 As shown, a second region 105 may be formed in the semiconductor body 100 . The conductivity type of the second region 105 is the second conductivity type, and the ion concentration of the second region 105 is greater than the ion concentration of the well region 103 , so as to form a good ohmic contact with the subsequently formed source.

[0082] like Figure 11 As shown, a gate trench T2 is formed on the first surface 101 by trench etching, sacrificial oxide layer preparation, and oxide layer removal. The gate trench T2 is connected to the voltage-resistant layer filled trench T1 and constitutes a trench T0 disposed on the first surface 101 .

[0083] In other optional embodiments, a gate trench T2 may be first formed on the first surface 101, and then the well region 103 and the first region 104 may be formed in the second semiconductor body 100. S160: Form a two-dimensional material layer on the sidewalls of the gate trench. The two-dimensional material layer is configured to be of the first conductivity type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide.

[0084] like Figure 12 As shown, a two-dimensional material layer 300 is formed on the sidewalls of gate trench T2 through a deposition process. The two-dimensional material layer 300 is configured as a first conductivity type, and the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide. For example, for an N-type MOSFET, the two-dimensional material layer 300 is an N-type channel layer, and the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0085] S170 , forming a first insulating layer on the sidewall of the gate trench, the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer.

[0086] like Figure 13 As shown, a first insulating layer 401 is formed on the sidewalls and bottom surface of the gate trench T2 by deposition or thermal oxidation. The first insulating layer 401 covers the two-dimensional material layer 300. The first insulating layer 301 may include a high-k dielectric layer such as silicon dioxide, HfO, or ZrO2. When the semiconductor body 100 includes silicon carbide and the first insulating layer 301 is silicon dioxide, a thermal oxidation process may be used to form the first insulating layer 401.

[0087] S180 , forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench.

[0088] The trench gate 302 can be made of polysilicon. Figure 14 As shown, a trench gate 402 is formed by a deposition process on a side of the first insulating layer 401 in the gate trench T2 away from the semiconductor body 100. The trench gate 402 can be made of polysilicon.

[0089] S190 , forming a source on the first surface.

[0090] like Figure 15 As shown, before forming the source 503, an interlayer insulating layer 403 for insulating the trench gate 402 and the source 503 is formed on the first surface 101. The interlayer insulating layer 403 is provided with a contact hole for placing the source 503.

[0091] like Figure 1 As shown, a source 503 is formed on the first surface 101 .

[0092] S200 , forming a drain on the second surface.

[0093] like Figure 1 As shown, a drain electrode 600 is formed on the second surface 102 by a back metal conductive layer deposition process. The drain electrode 600 may include a metal stack material composed of Ti, Ni, and Ag. Optionally, before forming the drain electrode 600, the second surface 102 may be thinned to reduce the on-resistance of the semiconductor device.

[0094] In an embodiment of the present invention, the two-dimensional material layer 300 includes a semiconductor layer and may also include a non-semiconductor layer. In crystallography, the two-dimensional material layer 300 refers to a material with a thickness of only a single atomic layer or two atomic layers, and its thickness is on the order of a few nanometers. The two-dimensional material layer 300 has a high carrier mobility. The carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. In addition, the well region 103 and the two-dimensional material layer 300 have different conductivity types, and can form a PN junction contact, generate a depletion region at the channel, and reduce the off-state leakage current of the semiconductor device.

[0095] In a semiconductor device prepared by the manufacturing method provided in an embodiment of the present invention, the trench gate 402 extends from the first surface 101 into the semiconductor body 100, eliminating the need for a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. The voltage-resistant filling layer 200 is located within the voltage-resistant layer-filled trench T1 and between the trench gate and the second surface 102. This effectively reduces the peak electric field below the first insulating layer 401 of the trench-type gate close to the second surface 102, thereby improving the voltage resistance of the semiconductor device. A two-dimensional material layer 300 having a carrier mobility greater than that of silicon carbide is located on the sidewalls of the gate trench T2. The two-dimensional material layer 300 serves as the channel of the semiconductor device, effectively improving the carrier mobility of the semiconductor device channel and reducing the on-resistance. The well region 103 forms a PN junction contact with the two-dimensional material layer 300, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device. Among them, because the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide, it can effectively improve the carrier mobility of the semiconductor device channel, and the effects of lattice damage to the semiconductor body 100, increase in interface states, and reduction in carrier mobility in the channel region caused by the ion doping process to form the first region 104 can be ignored. In addition, there is no need to limit the thickness of the first insulating layer 401 to reduce the on-resistance, thereby increasing the threshold voltage of the semiconductor device and improving the control performance of the semiconductor device. Among them, the ion doping process includes ion implantation, ion diffusion, or vapor deposition.

[0096] In other optional embodiments of the present invention, refer to Figure 1 , the carrier mobility of the two-dimensional material layer 300 in different directions is the same.

[0097] Optionally, based on the above technical solution, S160 forming a two-dimensional material layer on the sidewall of the gate trench includes:

[0098] A two-dimensional material layer including a two-dimensional material semiconductor layer is formed on the sidewall of the gate trench.

[0099] like Figure 12 As shown, a two-dimensional material layer 300 including a two-dimensional material semiconductor layer is formed on the sidewall of the gate trench T2.

[0100] Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material that is only a single atomic layer or two atomic layers thick, with a thickness on the order of a few nanometers. Two-dimensional material semiconductor layers have high carrier mobility, and common two-dimensional material semiconductor layers include graphene and graphene derivatives. The carrier mobility of a two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the two-dimensional material layer 300, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0101] Optionally, based on the above technical solution, S120 of forming a voltage-resistant layer on the third surface to fill the groove includes:

[0102] A voltage-resistant layer including a V-shaped groove or a U-shaped groove is formed on the third surface to fill the groove.

[0103] Alternatively, forming a gate trench on the first surface includes:

[0104] A gate trench including a V-shaped trench or a U-shaped trench is formed on the first surface.

[0105] Alternatively, S120 forming a voltage-resistant layer on the third surface to fill the trench includes:

[0106] A voltage-resistant layer including a V-shaped groove or a U-shaped groove is formed on the third surface to fill the groove.

[0107] Forming a gate trench on the first surface includes:

[0108] A gate trench including a V-shaped trench or a U-shaped trench is formed on the first surface.

[0109] Among them, such as Figure 6 As shown, a voltage-resistant layer including a V-shaped groove or a U-shaped groove is formed on the third surface 110 to fill the groove T1. Figure 11 As shown, a gate trench T2 including a V-shaped trench or a U-shaped trench is formed on the first surface 101 .

[0110] like Figure 6 As shown, the voltage-resistant layer-filled trench T1 is a V-shaped trench. In other optional embodiments of the present invention, the voltage-resistant layer-filled trench T1 may also be a U-shaped trench. The voltage-resistant layer-filled trench T1 is configured as a V-shaped trench, which reduces the area occupied by the semiconductor body 100, thereby reducing the on-resistance. The voltage-resistant layer-filled trench T1 is configured as a U-shaped trench, which reduces the manufacturing difficulty of the voltage-resistant layer-filled trench T1, thereby reducing the manufacturing cost of the semiconductor device.

[0111] like Figure 11As shown, the gate trench T2 is a V-shaped groove. In other optional embodiments of the present invention, the gate trench T2 can also be a U-shaped groove. The first surface 101 is provided with a gate trench T2 including a V-shaped groove or a U-shaped groove, so that the trench gate 402 extends from the first surface 101 into the semiconductor body 100, and there is no need to set a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. The gate trench T2 with a V-shaped groove reduces the area occupied by the semiconductor body 100, thereby reducing the on-resistance. The gate trench T2 with a U-shaped groove reduces the manufacturing difficulty of the gate trench T2, thereby reducing the preparation cost of the semiconductor device.

[0112] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0113] The semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device, the semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0114] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0115] Optionally, based on the above technical solution, S130 forming a voltage-resistant filling layer in the voltage-resistant layer filling groove includes:

[0116] A voltage-resistant filling layer including one or more voltage-resistant filling sublayers is formed in the voltage-resistant layer filling trench, and the voltage-resistant filling sublayers include any one of silicon oxide, silicon nitride and polysilicon.

[0117] like Figure 7 As shown, a first voltage-resistant filling sub-layer 201 in the voltage-resistant filling layer 200 is formed in the voltage-resistant filling trench T1 by deposition or thermal oxidation process. Figure 8 As shown, a second voltage-resistant filling sub-layer 202 is formed on a side of the first voltage-resistant filling sub-layer 201 in the voltage-resistant layer filling trench T1 away from the first semiconductor body 100 a through a deposition process.

[0118] For example, Figure 8As shown, the voltage-resistant filling layer 200 includes two voltage-resistant filling sublayers, namely a first voltage-resistant filling sublayer 201 and a second voltage-resistant filling sublayer 202. The first voltage-resistant filling sublayer 201 is silicon oxide, and the second voltage-resistant filling sublayer 202 is polycrystalline silicon. In other optional embodiments, the first voltage-resistant filling sublayer 201 can be silicon nitride or polycrystalline silicon, and the second voltage-resistant filling sublayer 202 can be silicon oxide or silicon nitride. The voltage-resistant filling sublayer includes any one of silicon oxide, silicon nitride, and polycrystalline silicon, allowing for flexible selection of the material of the voltage-resistant filling layer 200.

[0119] The embodiment of the present invention also provides another method for manufacturing a semiconductor device. Figure 16 As shown, Figure 16 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, the method comprising the following steps:

[0120] S210 , providing a first semiconductor body, where the first semiconductor body includes a third surface and a second surface that are opposite to each other.

[0121] like Figure 5 As shown, a first semiconductor body 100a in a semiconductor body 100 is provided, and the first semiconductor body 100a includes a third surface 110 and a second surface 102 arranged opposite to each other. Exemplarily, the first semiconductor body 100a includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first semiconductor body 100a may also include only the epitaxial layer 20. In other embodiments of the present invention, the first semiconductor body 100a may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 by an epitaxial process, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0122] S220 , forming at least two interval-spaced voltage-resistant layer-filled trenches on the third surface, wherein the voltage-resistant layer-filled trenches extend from the third surface into the first semiconductor body.

[0123] like Figure 17 As shown, at least two interval-spaced voltage-resistant layer-filled trenches T1 are formed on the third surface 110 through a trench etching process, a sacrificial oxide layer preparation process, and an oxide layer removal process. The voltage-resistant layer-filled trenches T1 extend from the third surface 110 into the first semiconductor body 100a. For example, Figure 17 Three interval-spaced voltage-resistant layer-filled trenches T1 are formed on the third surface 110 .

[0124] S230 , forming a pressure-resistant filling layer in the pressure-resistant layer filling groove, wherein the pressure-resistant filling layer is provided in the pressure-resistant layer filling groove in a one-to-one correspondence.

[0125] The process of forming the voltage-resistant filling layer 200 in the voltage-resistant layer filling trench T1 is as follows:

[0126] like Figure 18 As shown, a first voltage-resistant filling sub-layer 201 in the voltage-resistant filling layer 200 is formed in the voltage-resistant filling trench T1 by deposition or thermal oxidation process. Figure 19 As shown, a second voltage-resistant filling sublayer 202 is formed by a deposition process on the side of the first voltage-resistant filling sublayer 201 in the voltage-resistant layer filling trench T1 away from the first semiconductor body 100a. Exemplarily, the first voltage-resistant filling sublayer 201 is silicon oxide, and the second voltage-resistant filling sublayer 202 is polysilicon.

[0127] S240. Form a second semiconductor body on the third surface, the second semiconductor body including a first surface and a fourth surface opposite to each other, the fourth surface and the third surface are in contact, the first semiconductor body and the second semiconductor body constitute a semiconductor body, and the semiconductor body includes a first surface and a second surface opposite to each other.

[0128] like Figure 20 As shown, a second semiconductor body 100b is formed on the third surface 110 through an epitaxial process. The second semiconductor body 100b is an epitaxial layer. The second semiconductor body 100b includes a first surface 101 and a fourth surface disposed opposite each other. The fourth surface is in contact with the third surface 110. The first semiconductor body 100a and the second semiconductor body 100b constitute a semiconductor body 100. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite each other.

[0129] S250: Forming a well region, a first region, and at least two gate trenches spaced apart from each other on the first surface within the second semiconductor body. The first region is configured as a first conductivity type and is located on the first surface, and the well region is configured as a second conductivity type and is located on a side of the first region away from the first surface. The gate trenches and the voltage-resistant layer-filled trenches are connected and arranged in a one-to-one correspondence, forming a trench disposed on the first surface.

[0130] like Figure 21 As shown, a well region 103 and a first region 104 are formed in the second semiconductor body 100b by ion implantation and high-temperature retreat processes. The first region 104 is set to the first conductivity type and is located on the first surface 101. The well region 103 is set to the second conductivity type and is located on the side of the first region 104 away from the first surface 101.

[0131] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0132] Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0133] Optionally, based on the above technical solution, Figure 21 As shown, a second region 105 may be formed in the semiconductor body 100 . The conductivity type of the second region 105 is the second conductivity type, and the ion concentration of the second region 105 is greater than the ion concentration of the well region 103 , so as to form a good ohmic contact with the subsequently formed source.

[0134] like Figure 22 As shown, at least two spaced-apart gate trenches T2 are formed on the first surface 101 by trench etching, sacrificial oxide layer preparation, and oxide layer removal processes. The gate trenches T2 are connected to the voltage-resistant layer filling trenches T1 in a one-to-one correspondence, and constitute trenches T0 disposed on the first surface 101.

[0135] In other optional embodiments, the gate trench T2 may be first formed on the first surface 101; and then the well region 103 and the first region 104 may be formed in the second semiconductor body 100. S260: Form a two-dimensional material layer on the sidewall of the gate trench. The two-dimensional material layer is configured to be of the first conductivity type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide. The two-dimensional material layer is disposed in a one-to-one correspondence within the sidewall of the gate trench.

[0136] like Figure 23 As shown, a two-dimensional material layer 300 is formed on the sidewalls of the gate trench T2 through a deposition process. The two-dimensional material layer 300 is configured as a first conductivity type, and the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide. The two-dimensional material layer 300 is disposed one-to-one within the sidewalls of the gate trench T2. For example, for an N-type MOSFET, the two-dimensional material layer 300 is an N-type channel layer, and the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0137] S270 , forming a first insulating layer on the sidewall of the gate trench, the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer.

[0138] like Figure 24 As shown, a first insulating layer 401 is formed on the sidewalls and bottom surface of the gate trench T2 by deposition or thermal oxidation. The first insulating layer 401 covers the two-dimensional material layer 300. Gates are disposed in a one-to-one correspondence within the gate trenches T2. The first insulating layer 301 can include a high-k dielectric layer such as silicon dioxide, HfO, or ZrO2. When the semiconductor body 100 includes silicon carbide and the first insulating layer 301 is silicon dioxide, a thermal oxidation process can be used to form the first insulating layer 401.

[0139] S280 , forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench.

[0140] The trench gate 302 can be made of polysilicon. Figure 25 As shown, a trench gate 402 is formed by a deposition process on a side of the first insulating layer 401 in the gate trench T2 away from the semiconductor body 100. The trench gate 402 can be made of polysilicon.

[0141] S290 , forming a source on the first surface.

[0142] like Figure 26 As shown, before forming the source 503, an interlayer insulating layer 403 for insulating the trench gate 402 and the source 503 is formed on the first surface 101. The interlayer insulating layer 403 is provided with a contact hole for placing the source 503.

[0143] S300 , forming a drain on the second surface.

[0144] like Figure 2 As shown, a drain electrode 600 is formed on the second surface 102 by a back metal conductive layer deposition process. The drain electrode 600 may include a metal stack material composed of Ti, Ni, and Ag. Optionally, before forming the drain electrode 600, the second surface 102 may be thinned to reduce the on-resistance of the semiconductor device.

[0145] Optionally, based on the above technical solution, the voltage-resistant layer filling trench T1 and the gate trench T2 are connected and arranged in a one-to-one correspondence, and a voltage-resistant filling layer 200 is arranged in a one-to-one correspondence in the voltage-resistant layer filling trench T1. As the number of voltage-resistant layer filling trenches T1 and gate trenches T2 increases, the area of ​​the semiconductor body 100 is further reduced, thereby further reducing the on-resistance of the semiconductor device.

[0146] The embodiment of the present invention also provides another method for manufacturing a semiconductor device. Figure 27As shown, Figure 27 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, the method comprising the following steps:

[0147] S310 , providing a first semiconductor body, wherein the first semiconductor body includes a third surface and a second surface that are opposite to each other.

[0148] like Figure 5 As shown, a first semiconductor body 100a in a semiconductor body 100 is provided, and the first semiconductor body 100a includes a third surface 110 and a second surface 102 arranged opposite to each other. Exemplarily, the first semiconductor body 100a includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first semiconductor body 100a may also include only the epitaxial layer 20. In other embodiments of the present invention, the first semiconductor body 100a may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 by an epitaxial process, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0149] S320 , forming a voltage-resistant layer-filled trench and a source trench on the third surface, wherein the voltage-resistant layer-filled trench extends from the third surface into the first semiconductor body, and the source trench extends from the third surface into the first semiconductor body.

[0150] like Figure 28 As shown, a voltage-resistant layer-filled trench T1 and a source trench T3 are formed on the third surface 110 through a trench etching process, a sacrificial oxide layer preparation process, and an oxide layer removal process. The voltage-resistant layer-filled trench T1 extends from the third surface 110 to the first semiconductor body 100a, and the source trench T3 extends from the third surface 110 to the first semiconductor body 100a.

[0151] S330. A second region is formed on the bottom surface and side wall of the source trench, the second region is set to a second conductive type and surrounds the bottom surface and side wall of the source trench; the ion concentration of the second region is greater than the ion concentration of the well region; the vertical distance between the second region and the second surface is less than the vertical distance between the voltage-resistant layer-filled trench and the second surface.

[0152] like Figure 28 As shown, a second region 105 is formed on the bottom surface and side wall of the source trench T3 by an ion implantation process. The second region 105 is set to the second conductive type and surrounds the bottom surface and side wall of the source trench T3. The ion concentration of the second region 105 is greater than the ion concentration of the well region 103. The vertical distance d1 between the second region 105 and the second surface 102 is less than the vertical distance d2 between the voltage-resistant layer-filled trench T1 and the second surface 102.

[0153] S340 , forming a second insulating layer on the bottom surface and sidewalls of the source trench.

[0154] like Figure 29 As shown, a second insulating layer 501 is formed on the bottom surface and sidewalls of the source trench T3 by a deposition process or a thermal oxidation process.

[0155] S350 , forming a source filling layer on a side of the second insulating layer in the source trench away from the first semiconductor body.

[0156] like Figure 30 As shown, a source filling layer 502 is formed on a side of the second insulating layer 501 in the source trench T3 away from the first semiconductor body 100 a through a deposition process.

[0157] S360 , forming a voltage-resistant filling layer in the voltage-resistant layer filling groove.

[0158] The process of forming the voltage-resistant filling layer 200 in the voltage-resistant layer filling trench T1 is as follows:

[0159] like Figure 29 As shown, a second insulating layer 501 is formed on the bottom surface and sidewall of the source trench T3 by a deposition process or a thermal oxidation process, and a first voltage-resistant filling sublayer 201 in the voltage-resistant filling layer 200 is formed in the voltage-resistant layer filling trench T1 by a deposition process or a thermal oxidation process.

[0160] like Figure 30 As shown, a source filling layer 502 is formed by a deposition process on the side of the second insulating layer 501 in the source trench T3 away from the first semiconductor body 100a. At the same time, a second voltage-sustaining filling sublayer 202 is formed by a deposition process on the side of the first voltage-sustaining filling sublayer 201 in the voltage-sustaining layer filling trench T1 away from the first semiconductor body 100a. Exemplarily, the first voltage-sustaining filling sublayer 201 is silicon oxide, and the second voltage-sustaining filling sublayer 202 is polysilicon. The second insulating layer 501 is silicon oxide, and the source filling layer 502 is silicon oxide.

[0161] S370. Form a second semiconductor body on the third surface. The second semiconductor body includes a first surface and a fourth surface that are oppositely disposed. The fourth surface is in contact with the third surface. The first semiconductor body and the second semiconductor body constitute a semiconductor body. The semiconductor body includes a first surface and a second surface that are oppositely disposed.

[0162] like Figure 31As shown, a second semiconductor body 100b is formed on the third surface 110 through an epitaxial process. The second semiconductor body 100b is an epitaxial layer. The second semiconductor body 100b includes a first surface 101 and a fourth surface disposed opposite each other. The fourth surface is in contact with the third surface 110. The first semiconductor body 100a and the second semiconductor body 100b constitute a semiconductor body 100. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite each other.

[0163] S380: Form a well region, a first region, a third region, and a gate trench within the second semiconductor body. The first region is configured as a first conductivity type and is located on the first surface. The well region is configured as a second conductivity type and is located on a side of the first region away from the first surface. The third region is configured as a second conductivity type and is located on the first surface, covering the second region, the second insulating layer, and the source filling layer. The gate trench is located on the first surface and communicates with the voltage-resistant layer filling trench, forming a trench disposed on the first surface.

[0164] like Figure 32 As shown, a well region 103, a first region 104, and a third region 106 are formed in the second semiconductor body 100b through an ion doping process and a high-temperature retreat process. The first region 104 is configured as a first conductivity type and is located on the first surface 101. The well region 103 is configured as a second conductivity type and is located on a side of the first region 104 away from the first surface 101. The third region 106 is configured as a second conductivity type, is located on the first surface 101, and covers the second region 105, the second insulating layer 501, and the source filling layer 502.

[0165] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0166] For example, for an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, where the P-type dopant ions may be aluminum (Al) ions or boron (B) ions. The second region 105 and the third region 106 are P+ doped regions, where the P-type dopant ions may be aluminum (Al) ions or boron (B) ions.

[0167] like Figure 33As shown, a gate trench T2 is formed on the first surface 101 by trench etching, sacrificial oxide layer preparation, and oxide layer removal. The gate trench T2 is connected to the voltage-resistant layer filled trench T1 and constitutes a trench T0 disposed on the first surface 101 .

[0168] In other optional embodiments, the gate trench T2 may be formed on the first surface 101 first; and then the well region 103 and the first region 104 may be formed in the second semiconductor body 100 .

[0169] S390. Form a two-dimensional material layer on the sidewall of the gate trench, wherein the two-dimensional material layer is set to a first conductive type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide.

[0170] like Figure 34 As shown, a two-dimensional material layer 300 is formed on the sidewalls of gate trench T2 through a deposition process. The two-dimensional material layer 300 is configured as a first conductivity type, and the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide. For example, for an N-type MOSFET, the two-dimensional material layer 300 is an N-type channel layer, and the carrier mobility of the two-dimensional material layer 300 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0171] S400 , forming a first insulating layer on the sidewall of the gate trench, the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer.

[0172] like Figure 35 As shown, a first insulating layer 401 is formed on the sidewalls and bottom surface of the gate trench T2 by deposition or thermal oxidation. The first insulating layer 401 covers the two-dimensional material layer 300. The first insulating layer 301 may include a high-k dielectric layer such as silicon dioxide, HfO, or ZrO2. When the semiconductor body 100 includes silicon carbide and the first insulating layer 301 is silicon dioxide, a thermal oxidation process may be used to form the first insulating layer 401.

[0173] S410 , forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench.

[0174] The trench gate 302 can be made of polysilicon. Figure 36 As shown, a trench gate 402 is formed by a deposition process on a side of the first insulating layer 401 in the gate trench T2 away from the semiconductor body 100. The trench gate 402 can be made of polysilicon.

[0175] S420 , forming a source electrode on the first surface.

[0176] like Figure 37As shown, before forming the source trench T3 of the source, an interlayer insulating layer 403 for insulating the gate and the source is formed on the first surface 101. The interlayer insulating layer 403 is provided with a contact hole.

[0177] like Figure 3 As shown, before forming the source 503, an interlayer insulating layer 403 for insulating the trench gate 402 and the source 503 is formed on the first surface 101. The interlayer insulating layer 403 is provided with a contact hole for placing the source 503.

[0178] S4200 , forming a drain on the second surface.

[0179] like Figure 3 As shown, a drain 600 is formed on the second surface 102 by a backside metal deposition process.

[0180] Based on the above technical solution, the provision of the source trench structure 500 can effectively reduce the peak electric field below the first insulating layer 401 where the trench gate 402 is close to the second surface 102, thereby improving the withstand voltage performance of the semiconductor device. Furthermore, a third region 106 is provided on the first surface 101, and the third region 106 is in direct contact with the source 503. The third region 106 can form a good ohmic contact with the source 503. Furthermore, the third region 106 is located between the source 503 and the second region 105, the second insulating layer 501, and the source filling layer 502, further increasing the depth of the source trench T3, helping to further reduce the peak electric field below the first insulating layer 401 where the trench gate 402 is close to the second surface 102, and improving the withstand voltage performance of the semiconductor device. Furthermore, the semiconductor body 100 may further include a second region 105, the conductivity type of the second region 105 being the second conductivity type, and the ion concentration being greater than the ion concentration of the well region 103, so as to form a good ohmic contact with the source 503.

[0181] In other optional embodiments, when the semiconductor device includes a source trench structure 500, at least two spaced trenches T0 may also be provided on one side of the source trench structure 500, a two-dimensional material layer 300 is provided in a one-to-one correspondence in the sidewalls of the gate trench T2, and a trench gate 402 is provided in a one-to-one correspondence in the gate trench T2; the voltage-resistant layer filling trench T1 and the gate trench T2 are connected in a one-to-one correspondence, and a voltage-resistant filling layer 200 is provided in a one-to-one correspondence in the voltage-resistant layer filling trench T1, further reducing the area of ​​the semiconductor body 100, thereby further reducing the on-resistance of the semiconductor device.

[0182] Optionally, based on the above technical solution, S520 forming a source trench on the third surface includes:

[0183] A source trench including a V-shaped trench or a U-shaped trench is formed on the third surface.

[0184] like Figure 28 As shown, a source trench T3 including a V-shaped trench or a U-shaped trench is formed on the third surface 110 through a trench etching process, a sacrificial oxide layer preparation process, and an oxide layer removal process.

[0185] Compared to a U-shaped trench, a V-shaped trench reduces the area occupied by the semiconductor body 100 and reduces the on-resistance of the semiconductor device. The source trench T3 includes a U-shaped trench, which reduces the manufacturing difficulty of the source trench T3 and thus reduces the manufacturing cost of the semiconductor device.

[0186] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0187] An embodiment of the present invention provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, the semiconductor device being electrically connected to the circuit board. Therefore, the beneficial effects of the power conversion circuit including any of the semiconductor devices described in any of the embodiments of the present invention are not further elaborated here.

[0188] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0189] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0190] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0191] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a trench being further provided on the first surface, the trench comprising a connected voltage-resistant layer-filled trench and a gate trench, the gate trench extending from the first surface into the semiconductor body, the voltage-resistant layer-filled trench being located between the gate trench and the second surface; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on a sidewall of the gate trench; a pressure-resistant filling layer, located in the pressure-resistant layer filling groove; a two-dimensional material layer, the two-dimensional material layer being of a first conductivity type and being located on a sidewall of the gate trench; the two-dimensional material layer being located between the first region and the first insulating layer, and the two-dimensional material layer being located between the well region and the first insulating layer; The carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide; a trench gate, the trench gate being located in the gate trench on a side of the first insulating layer away from the semiconductor body; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The two-dimensional material layer has the same carrier mobility in different directions.

3. The semiconductor device according to claim 1, wherein The voltage-resistant layer filling groove includes a V-shaped groove or a U-shaped groove, or the gate groove includes a V-shaped groove or a U-shaped groove; or the voltage-resistant layer filling groove includes a V-shaped groove or a U-shaped groove, and the gate groove includes a V-shaped groove or a U-shaped groove.

4. The semiconductor device according to claim 1, wherein The first surface is provided with a plurality of gate trenches, and the plurality of gate trenches are located on the first surface and are arranged at intervals; The voltage-resistant layer filling trenches and the gate trenches are arranged in a one-to-one correspondence.

5. The semiconductor device according to claim 1, wherein A source trench is also provided in the semiconductor body; The semiconductor body further includes a second region, the second region being of a second conductivity type and surrounding a bottom surface and sidewalls of the source trench; the ion concentration of the second region is greater than the ion concentration of the well region; and the vertical distance between the second region and the second surface is less than the vertical distance between the trench filled with the voltage-resistant layer and the second surface; The semiconductor device further includes a source trench structure, the source trench structure including a filling layer and a second insulating layer; the second insulating layer is located on the bottom surface and sidewalls of the source trench; the filling layer is located in the source trench on a side of the second insulating layer away from the semiconductor body; The semiconductor body further includes a third region, which is configured to be of the second conductivity type. The third region is located on the first surface and covers the second region, the second insulating layer, and the filling layer.

6. The semiconductor device according to claim 5, wherein The source trench includes a V-shaped trench or a U-shaped trench.

7. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

8. The semiconductor device according to claim 1, wherein The pressure-resistant filling layer includes one or more pressure-resistant filling sublayers; The voltage-resistant filling sublayer includes any one of silicon oxide, silicon nitride and polysilicon.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a first semiconductor body, wherein the first semiconductor body includes a third surface and a second surface arranged opposite to each other; forming a voltage-resistant layer-filled trench on the third surface, wherein the voltage-resistant layer-filled trench extends from the third surface into the first semiconductor body; forming a pressure-resistant filling layer in the pressure-resistant layer filling groove; forming a second semiconductor body on the third surface, the second semiconductor body including a first surface and a fourth surface opposite to each other, the fourth surface being in contact with the third surface, the first semiconductor body and the second semiconductor body constituting a semiconductor body, the semiconductor body including the first surface and the second surface opposite to each other; A well region, a first region, and a gate trench are formed in the second semiconductor body, wherein the first region is configured to be of a first conductivity type and is located on the first surface, and the well region is configured to be of a second conductivity type and is located on a side of the first region away from the first surface; the gate trench is located on the first surface and is connected to the voltage-resistant layer-filled trench, forming a trench provided on the first surface; forming a two-dimensional material layer on a sidewall of the gate trench, wherein the two-dimensional material layer is set to a first conductivity type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide; forming a first insulating layer on a sidewall of the gate trench, wherein the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer; forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a two-dimensional material layer on the sidewall of the gate trench includes: A two-dimensional material layer having the same carrier mobility in different directions is formed on the sidewall of the gate trench.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a voltage-resistant layer filling the groove on the third surface includes: forming a voltage-resistant layer-filled groove including a V-shaped groove or a U-shaped groove on the third surface; Alternatively, forming a gate trench on the first surface includes: forming a gate trench including a V-shaped trench or a U-shaped trench on the first surface; Alternatively, forming a voltage-resistant layer on the third surface to fill the groove includes: forming a voltage-resistant layer-filled groove including a V-shaped groove or a U-shaped groove on the third surface; Forming a gate trench on the first surface includes: A gate trench including a V-shaped trench or a U-shaped trench is formed on the first surface.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a voltage-resistant layer filling the groove on the third surface includes: forming at least two interval-spaced voltage-resistant layer-filled grooves on the third surface; Forming a gate trench on the first surface includes: At least two gate trenches are formed on the first surface, and the voltage-resistant layer-filled trenches are arranged in a one-to-one correspondence with the gate trenches.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: Before forming a source electrode on the first surface, the method includes: When forming the voltage-resistant layer filling trench on the third surface, the method further includes: forming a source trench on the third surface, wherein the source trench extends from the third surface into the first semiconductor body; A second region is formed on the bottom surface and sidewalls of the source trench, the second region being of a second conductivity type and surrounding the bottom surface and sidewalls of the source trench; the ion concentration of the second region is greater than the ion concentration of the well region; and the vertical distance between the second region and the second surface is less than the vertical distance between the voltage-resistant layer-filled trench and the second surface; forming a second insulating layer on the bottom surface and sidewalls of the source trench; forming a source filling layer on a side of the second insulating layer in the source trench away from the first semiconductor body; When forming a well region and a first region in the second semiconductor body, it also includes: forming a third region in the second semiconductor body, the third region is set to the second conductivity type, the third region is located on the first surface, and covers the second region, the second insulating layer and the source filling layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: Forming a source trench on the third surface includes: A source trench including a V-shaped trench or a U-shaped trench is formed on the third surface.

15. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of forming a well region, a first region, and a gate trench in the second semiconductor body includes: forming a well region and a first region in the second semiconductor body; forming a gate trench on the first surface; or; forming a gate trench on the first surface; A well region and a first region are formed in the second semiconductor body.

16. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

17. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a voltage-resistant filling layer in the voltage-resistant layer filling groove includes: A voltage-resistant filling layer including one or more voltage-resistant filling sublayers is formed in the voltage-resistant layer-filled trench. The voltage-resistant filling sublayers include any one of silicon oxide, silicon nitride and polysilicon.

18. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 8, wherein the substrate is used to support the semiconductor device.

19. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

20. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 19, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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