Semiconductor device

Abstract

A semiconductor device may include: a substrate including an active region extending in a first direction; a device isolation layer defining an active region; a first gate electrode and a second gate electrode extending in the second direction and spaced apart from each other; first channel layers separated from each other and surrounded by the first gate electrode; second channel layers separated from each other and surrounded by the second gate electrode; an insulating isolation pattern between the first gate electrode and the second gate electrode and between the first channel layer and the second channel layer; a gate dielectric layer between the first channel layer and the first gate electrode and between the second channel layer and the second gate electrode; and epitaxial layers on opposite side surfaces of the first channel layer and the second channel layer. Portions of the epitaxial layer may overlap the insulating isolation pattern, the gate dielectric layer, the first gate electrode, and the second gate electrode in the third direction.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0033687 filed on March 11, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to semiconductor devices. Background Art

[0003] As demands for high performance, high speed, and / or multifunctionality of semiconductor devices have increased, the integration density of semiconductor devices has increased. To overcome limitations in operational properties caused by the reduction in size of planar MOSFETs (metal oxide semiconductor field effect transistors (FETs)), efforts have been made to develop semiconductor devices including fin field effect transistors (FinFETs) including fin-shaped channels and gate-all-around field effect transistors including nanosheets surrounded by gates. Summary of the Invention

[0004] Example embodiments of the present disclosure will provide a semiconductor device having improved electrical properties and reliability.

[0005] According to example embodiments, a semiconductor device may include: a substrate including a first region and a second region, the substrate including an active region extending in a first direction; a device isolation layer defining the active region, the device isolation layer being on the substrate; a first gate electrode and a second gate electrode extending in a second direction, the second direction intersecting the active region, the first gate electrode and the second gate electrode being spaced apart from each other; a plurality of first channel layers spaced apart from each other in a third direction, the third direction being perpendicular to an upper surface of the substrate, the plurality of first channel layers being surrounded by the first gate electrode on the first region; a plurality of second channel layers spaced apart from each other in the third direction, the plurality of second channel layers being surrounded by the second gate electrode on the second region; an insulating isolation pattern extending in the first direction between the first gate electrode and the second gate electrode and between the plurality of first channel layers and the plurality of second channel layers, the insulating isolation pattern being on the substrate; a gate dielectric layer between the plurality of first channel layers and the first gate electrode, and a gate dielectric layer between the plurality of second channel layers and the second gate electrode; and an epitaxial layer on side surfaces of the plurality of first channel layers and the plurality of second channel layers respectively facing each other. A portion of each of the epitaxial layers may overlap the insulating isolation pattern, the gate dielectric layer, the first gate electrode, and the second gate electrode in the third direction.

[0006] According to example embodiments, a semiconductor device may include: a substrate including an active region extending in a first direction; a first gate electrode and a second gate electrode extending in a second direction, the second direction intersecting the active region, the first gate electrode and the second gate electrode being spaced apart from each other; a plurality of first channel layers spaced apart from each other in a third direction, the third direction being perpendicular to an upper surface of the substrate, and the plurality of first channel layers being surrounded by the first gate electrode; a plurality of second channel layers spaced apart from each other in the third direction, the plurality of second channel layers being surrounded by the second gate electrode; an insulating isolation pattern between the plurality of first channel layers and the plurality of second channel layers, the insulating isolation pattern extending to a height lower than a height of an upper surface of the active region; a first epitaxial layer on opposite side surfaces of the plurality of first channel layers and the plurality of second channel layers, the first epitaxial layer being in contact with the insulating isolation pattern in the active region; and a second epitaxial layer in the active region of the substrate and having an upper surface in contact with the insulating isolation pattern.

[0007] According to example embodiments, a semiconductor device may include: a substrate including a first region and a second region, the substrate including an active region extending in a first direction; a first gate electrode and a second gate electrode extending in a second direction, the second direction intersecting the active region, the first gate electrode including a first conductive layer, the second gate electrode including a second conductive layer, the first gate electrode and the second gate electrode each including a third conductive layer, the first conductive layer and the third conductive layer of the first gate electrode being stacked in sequence, and the second conductive layer and the third conductive layer of the second gate electrode being stacked in sequence; a plurality of channel layers stacked in a third direction on the active region, the third direction being perpendicular to an upper surface of the substrate, and the plurality of channel layers overlapping with the third conductive layer of the first gate electrode in the third direction; a gate dielectric layer covering a portion of each of the plurality of channel layers; an insulating isolation pattern between the first gate electrode and the second gate electrode; and a semiconductor material layer disposed on a side surface of at least one of the plurality of channel layers, wherein the first conductive layer and the second conductive layer may include different metal materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects, features, and advantages of example embodiments and other aspects, features, and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a plan view illustrating a semiconductor device according to an example embodiment of the present disclosure.

[0010] Figure 2A is a cross-sectional view illustrating a semiconductor device taken along line II′ according to an example embodiment of the present disclosure.

[0011] Figure 2Bis a cross-sectional view illustrating a semiconductor device taken along line II-II′ according to an example embodiment of the present disclosure.

[0012] Figure 2C is a cross-sectional view illustrating a semiconductor device taken along line III-III′ according to an example embodiment of the present disclosure.

[0013] Figure 3 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure.

[0014] Figure 4 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure.

[0015] Figure 5 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure.

[0016] Figure 6 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure.

[0017] Figure 7 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure.

[0018] Figures 8A to 8I are diagrams illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments among exemplary embodiments will be described with reference to the accompanying drawings as follows.

[0020] Figure 1 is a plan view illustrating a semiconductor device 100 according to example embodiments.

[0021] Figures 2A to 2C is a cross-sectional view illustrating a semiconductor device 100 according to example embodiments. Figure 2A is a cross-sectional view illustrating a semiconductor device 100 taken along line II' according to example embodiments; Figure 2B is a cross-sectional view illustrating the semiconductor device 100 taken along line II-II′ according to example embodiments; Figure 2C is a cross-sectional view illustrating the semiconductor device 100 taken along line III-III′ according to example embodiments.

[0022] Reference Figures 1 to 2CThe semiconductor device 100 may include a substrate 101, an active area 105, a channel structure 140, a first gate electrode 170A, a second gate electrode 170B, an insulating isolation pattern 130, a semiconductor material layer EP, a source / drain region 150 and a contact plug 180. The substrate 101 has a first region R1 and a second region R2. The active area 105 is on the substrate 101. The channel structure 140 includes a plurality of channel layers 141, 142 and 143 vertically arranged on the active area 105 and spaced apart from each other. The first gate electrode 170A and the second gate electrode 170B extend by intersecting the active area 105. The insulating isolation pattern 130 isolates the first gate electrode 170A from the second gate electrode 170B. The source / drain region 150 contacts the channel structure 140. The contact plug 180 is connected to the source / drain region 150. The semiconductor device 100 may further include a device isolation layer 110 , a gate dielectric layer 162 , a gate spacer layer 163 , a gate capping layer 166 , a first interlayer insulating layer IL1 , and a second interlayer insulating layer IL2 .

[0023] In the semiconductor device 100, the active region 105 may have a fin structure, the first gate electrode 170A and the second gate electrode 170B may be disposed between the active region 105 and the channel structure 140, between the plurality of channel layers 141, 142, and 143 in the channel structure 140, and on the channel structure 140, and the insulating isolation pattern 130 may be disposed between the plurality of first channel layers and the plurality of second channel layers, the plurality of first channel layers and the plurality of second channel layers being spaced apart from each other in a horizontal direction (e.g., a Y-axis direction). Therefore, the semiconductor device 100 may include a multi-bridge channel FET (MBCFET) as a gate-all-around field effect transistor. TM ) structure, or a transistor with a forksheet structure containing insulating pillars between multiple nanosheets.

[0024] The substrate 101 may have an upper surface extending in a first direction (e.g., the X-axis direction) and a second direction (e.g., the Y-axis direction). The substrate 101 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0025] The substrate 101 may include a first region R1 and a second region R2, and the first region R1 and the second region R2 may be adjacent to each other. A portion of the active region 105, the source / drain region 150 (e.g., the first source / drain region 150A), and the first gate electrode 170A may be disposed in the first region R1, and another portion of the active region 105, the source / drain region 150 (e.g., the second source / drain region 150B), and the second gate electrode 170B may be disposed in the second region R2. For example, an nFET (n-type field-effect transistor) may be disposed in the first region R1, and a pFET (p-type field-effect transistor) may be disposed in the second region R2. In some example embodiments, transistors having the same conductivity type but different electrical properties may be disposed in the first region R1 and the second region R2.

[0026] The active region 105 may be defined by the device isolation layer 110 and may be arranged to extend in a first direction (e.g., the X-axis direction). According to the description, the active region 105 may be described as a portion of the substrate 101. The active region 105 may partially protrude into the device isolation layer 110 (e.g., partially protrude above the device isolation layer 110), so that the upper surface of the active region 105 may be arranged at a height higher than the level of the upper surface of the device isolation layer 110. The active region 105 may include a portion of the substrate 101, or may include an epitaxial layer grown from the substrate 101. However, the active region 105 may be partially recessed to form recessed regions on both sides of the first gate electrode 170A and the second gate electrode 170B, and source / drain regions 150 having different conductivity types may be arranged in the recessed regions.

[0027] In example embodiments, a region of the active region 105 that overlaps the first region R1 may be referred to as a first active region, and a region of the active region 105 that overlaps the second region R2 may be referred to as a second active region. Each of the first and second active regions may include a well region, the well region including impurities. For example, in the first active region of the first region R1 where an nFET is provided, the well region may include a P-type impurity such as boron (B), gallium (Ga), or aluminum (Al). In the second active region of the second region R2 where a pFET is provided, the well region may include an N-type impurity such as phosphorus (P), arsenic (As), or antimony (Sb). For example, the well region may be provided at a predetermined depth from the upper surface of each of the first and second active regions.

[0028] The device isolation layer 110 may define the active region 105 in the substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. The device isolation layer 110 may expose the upper surface of the active region 105 and may partially expose the upper portion of the active region 105. In some example embodiments, the device isolation layer 110 may have a curved upper surface, increasing in height toward the active region 105. The device isolation layer 110 may be formed of an insulating material. For example, the device isolation layer 110 may include oxide, nitride, or a combination thereof.

[0029] The channel structure 140 may include a plurality of first channel layers 140A spaced apart from one another in a third direction (or referred to as a vertical direction; for example, the Z-axis direction) perpendicular to the upper surface of the substrate 101 in the first region R1, and a plurality of second channel layers 140B spaced apart from one another in a third direction (for example, the Z-axis direction) perpendicular to the upper surface of the substrate 101 in the second region R2. The plurality of first channel layers 140A and the plurality of second channel layers 140B may be spaced apart from one another in a second direction (for example, the Y-axis direction). The channel structure 140 may be connected to the source / drain regions 150 (for example, the first source / drain regions 150A and the second source / drain regions 150B) and may be spaced apart from the upper surface of the active region 105.

[0030] The plurality of channel layers 141, 142, and 143 may be formed of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the plurality of channel layers 141, 142, and 143 may be formed of the same material as the substrate 101. In example embodiments, the plurality of channel layers 141, 142, and 143 may include an impurity region disposed in a region adjacent to the source / drain region 150. In example embodiments, the number and shape of the channel layers 141, 142, and 143 of each of the channel structures 140 may vary.

[0031] The first source / drain region 150A and the second source / drain region 150B may be respectively disposed on the first active region and the second active region on both sides of the first gate electrode 170A, the second gate electrode 170B, and the channel structure 140. The first source / drain region 150A may be disposed on the first active region on both sides of the first gate electrode 170A, and the second source / drain region 150B may be disposed on the second active region on both sides of the second gate electrode 170B.

[0032] The first source / drain region 150A and the second source / drain region 150B may be disposed in a recessed region partially recessed into the upper portions of the first active region and the second active region. The first source / drain region 150A and the second source / drain region 150B may be in contact with the first to third channel layers 141, 142, and 143 of the channel structure 140 and may be disposed to cover the side surfaces of each of the plurality of channel layers 141, 142, and 143. The upper surfaces of the first source / drain region 150A and the second source / drain region 150B may be disposed at a height that is the same as or similar to the height of the lower surface of the uppermost regions of the first gate electrode 170A and the second gate electrode 170B, and this height may vary in example embodiments. In example embodiments, the first source / drain region 150A and the second source / drain region 150B may be connected or merged to each other on two or more first active regions and second active regions adjacent to each other along the Y-axis direction, and may form the first source / drain region 150A and the second source / drain region 150B, respectively.

[0033] The first source / drain region 150A and the second source / drain region 150B may include impurities of different conductivity types. For example, the first source / drain region 150A may include N-type impurities, and the second source / drain region 150B may include P-type impurities, but example embodiments are not limited thereto.

[0034] The gate structure may include a first gate electrode 170A, a second gate electrode 170B, a gate dielectric layer 162 , a gate spacer layer 163 , and a gate capping layer 166 .

[0035] The first gate electrode 170A and the second gate electrode 170B may intersect the active region 105 and the channel structure 140 and may extend in a second direction (e.g., the Y-axis direction) over the active region 105 and the channel structure 140. A physical channel region of the transistor may be formed in the active region 105 and / or the channel structure 140 intersecting the first gate electrode 170A and the second gate electrode 170B. The first gate electrode 170A and the second gate electrode 170B may fill the regions between the plurality of first channel layers 140A and the plurality of second channel layers 140B, respectively, over the active region 105 and may extend onto the channel structure 140. The first gate electrode 170A and the second gate electrode 170B may be separated from the first to third channel layers 141, 142, and 143 by the gate dielectric layer 162.

[0036] The first gate electrode 170A and the second gate electrode 170B may be arranged linearly in a second direction (e.g., the Y-axis direction). The first gate electrode 170A and the second gate electrode 170B may be disposed on the first region R1 and the second region R2, respectively, with the insulating isolation pattern 130 between the first gate electrode 170A and the second gate electrode 170B. The first gate electrode 170A may include a first conductive layer 171 and a third conductive layer 173 stacked in sequence, and the second gate electrode 170B may include a second conductive layer 172 and a third conductive layer 173 stacked in sequence. The first gate electrode 170A and the second gate electrode 170B may be included in an nFET and a pFET, respectively. Alternatively, the first gate electrode 170A and the second gate electrode 170B may be included in an nFET having different operating voltages, or in a pFET having different operating voltages.

[0037] The first conductive layer 171 may be disposed on the gate dielectric layer 162 on the first region R1. The first conductive layer 171 may extend on the gate dielectric layer 162 conformally extending along the region between the plurality of first channel layers 140A, and may extend along the upper surface of the device isolation layer 110 and the side surface of the insulating isolation pattern 130. The first conductive layer 171 may conformally extend along the upper surface, side surface, and lower surface of each of the plurality of first channel layers 140A. The third conductive layer 173 may be disposed on the first conductive layer 171 and may fill the space in the first conductive layer 171 in the cross-sectional surface. The first conductive layer 171 may have substantially the same thickness in regions other than the plurality of first channel layers 140A.

[0038] The concept of “substantially the same” of elements may indicate that the elements may be completely the same, and may also indicate that the elements may be determined to be the same in consideration of errors or deviations occurring during processes.

[0039] The second conductive layer 172 may be disposed on the gate dielectric layer 162 on the second region R2. The second conductive layer 172 may extend on the gate dielectric layer 162 conformally extending along the region between the plurality of second channel layers 140B, and may extend along the upper surface of the device isolation layer 110 and the side surface of the insulating isolation pattern 130. The second conductive layer 172 may conformally extend along the upper surface, side surface, and lower surface of each of the plurality of second channel layers 140B. The third conductive layer 173 may be disposed on the second conductive layer 172 and may fill the space in the second conductive layer 172 on the cross-sectional surface. The second conductive layer 172 may have substantially the same thickness in the region other than the plurality of second channel layers 140B.

[0040] The first and second gate electrodes 170A and 170B may be electrically isolated from each other by the insulating isolation pattern 130. The first and second gate electrodes 170A and 170B may have an internal stack structure symmetrical to each other with respect to the insulating isolation pattern 130, but example embodiments thereof are not limited thereto.

[0041] The first gate electrode 170A and the second gate electrode 170B may include a conductive material (e.g., a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN))) and / or may include a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)) or a semiconductor material (such as doped polysilicon). The first conductive layer 171 may include a material different from that of the second conductive layer 172 and the third conductive layer 173, and the second conductive layer 172 and the third conductive layer 173 may include the same material or different materials. Even when the second conductive layer 172 and the third conductive layer 173 include the same material, the second conductive layer 172 and the third conductive layer 173 may be formed in different processes, and the interface surface therebetween may be distinct.

[0042] For example, the first to third conductive layers 171, 172, and 173 may be metal-containing layers. In example embodiments, the second conductive layer 172 may have a work function equal to or less than that of the first conductive layer 171. For example, the first and second conductive layers 171 and 172 may be configured as metal-containing layers for controlling the work function, and the first conductive layer 171 may include a P-type metal and the second conductive layer 172 may include an N-type metal. For example, the first conductive layer 171 may include at least one of TiAlN and TiN, and the second conductive layer 172 may include at least one of TiAlC and TiN, but example embodiments are not limited thereto.

[0043] The gate dielectric layer 162 may be disposed between the active region 105 and the first and second gate electrodes 170A and 170B, between the plurality of first channel layers 140A and the first gate electrode 170A, and between the plurality of second channel layers 140B and the second gate electrode 170B. The gate dielectric layer 162 may be disposed to cover at least a portion of the surfaces of the first and second gate electrodes 170A and 170B. For example, the gate dielectric layer 162 may be disposed to surround the entire surfaces of the first and second gate electrodes 170A and 170B, except for the upper surfaces. The gate dielectric layer 162 may extend to the region between the first and second gate electrodes 170A and 170B and the gate spacer layer 163, but example embodiments are not limited thereto.

[0044] The gate dielectric layer 162 may include oxide, nitride, or high-κ material. High-κ material may refer to a dielectric material having a higher dielectric constant than that of silicon oxide (SiO2). High-κ materials may include, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), Hafnium Oxide (HfO2), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and at least one of praseodymium oxide (Pr 2 O 3 ). In example embodiments, the gate dielectric layer 162 may include a plurality of films.

[0045] The gate spacer layer 163 may be disposed on both side surfaces of the first gate electrode 170A and the second gate electrode 170B, respectively. The gate spacer layer 163 may insulate the first source / drain region 150A and the second source / drain region 150B from the first gate electrode 170A and the second gate electrode 170B. The gate spacer layer 163 may be stacked and may form a multilayer structure. However, in some example embodiments, the gate spacer layer may include a single layer. The gate spacer layer 163 may include at least one of an oxide, a nitride, and an oxynitride, and may include, for example, a low dielectric constant film.

[0046] The gate capping layer 166 may be disposed on upper surfaces of the first and second gate electrodes 170A and 170B and an upper surface of the insulating isolation pattern 130. The gate capping layer 166 may include at least one of oxide, nitride, and oxynitride.

[0047] The insulating isolation pattern 130 may be disposed between the first gate electrode 170A and the second gate electrode 170B to isolate the first gate electrode 170A and the second gate electrode 170B from each other. The upper surface of the insulating isolation pattern 130 may be coplanar with the upper surfaces of the first gate electrode 170A and the second gate electrode 170B. The upper surface of the insulating isolation pattern 130 may be exposed from the gate dielectric layer 162, the first conductive layer 171, and the second conductive layer 172, and may be covered by the gate capping layer 166. In some example embodiments, the upper surface of the insulating isolation pattern 130 may be covered with another layer formed of an insulating material (such as an interlayer insulating layer). The side surfaces of the insulating isolation pattern 130 may be perpendicular to the upper surface of the substrate 101 or may be inclined. In example embodiments, the insulating isolation pattern 130 may have a tapered shape toward the substrate 101.

[0048] At least a portion of a side surface 130CS of the insulating isolation pattern 130 in the second direction (e.g., the Y-axis direction) may have an inwardly concave shape at a height between the channel layers 141, 142, and 143 spaced apart in the vertical direction. At least a portion of the side surface of the insulating isolation pattern 130 in the second direction may contact the first epitaxial layer 145. The first epitaxial layer 145 may have a convex shape toward the insulating isolation pattern 130, and the side surface of the insulating isolation pattern 130 in the second direction may have a convex or concave shape depending on the shape of the adjacent first epitaxial layer 145. The side surface of the insulating isolation pattern 130 in the second direction may have a zigzag shape with convex and concave shapes repeated. The gate dielectric layer 162, the first conductive layer 171 (or the second conductive layer 172), and the third conductive layer 173 may be sequentially stacked on the concave side surface of the insulating isolation pattern 130.

[0049] The shape of the lower surface of the insulating isolation pattern 130 may vary depending on the shape of the adjacent second epitaxial layer 146. The lower surface of the insulating isolation pattern 130 may have a shape that is inclined toward the substrate 101 in a direction away from the first gate electrode 170A and the second gate electrode 170B. Among the lower surfaces of the insulating isolation pattern 130, the lower surface of the central portion adjacent to the boundary between the first region R1 and the second region R2 may have a convex shape toward the substrate 101. The lower surface of the central portion of the insulating isolation pattern 130 may have a shape surrounded by the second epitaxial layer 146. The lowermost end of the insulating isolation pattern 130 may be disposed at a height lower than that of the lowermost ends of the first gate electrode 170A and the second gate electrode 170B, and may be disposed at a height higher than that of the uppermost end of the substrate 101.

[0050] The width of the insulating isolation pattern 130 in the second direction (e.g., the Y-axis direction) between the opposing ends 145e of the first epitaxial layer 145 may be referred to as a first width W1. The width of the portion of the insulating isolation pattern 130 surrounded by the second epitaxial layer 146 in the second direction may be referred to as a second width W2. The portion of the insulating isolation pattern 130 surrounded by the second epitaxial layer 146 may refer to a protruding portion of the insulating isolation pattern 130 facing the substrate 101. The first width W1 and the second width W2 may be substantially the same size. Here, the concept of the same size may include process errors and may indicate that the widths may not be intentionally designed to be different.

[0051] The width of the insulating isolation pattern 130 between the side surfaces 130CS facing each other at a height between the channel layers 141, 142, and 143 spaced apart from each other in the vertical direction (e.g., the width in the second direction (e.g., the Y-axis direction)) may be referred to as a third width W3. The width of the insulating isolation pattern 130 at a height higher than the height of the uppermost channel layer 143 among the plurality of channel layers 141, 142, and 143 (e.g., the width in the second direction (e.g., the Y-axis direction)) may be referred to as a fourth width W4. The size of the third width W3 may be substantially the same as the size of the first width W1. The size of the fourth width W4 may be the same as or greater than the size of the first width W1. As the height of the insulating isolation pattern 130 in the third direction (e.g., the Z-axis direction) changes, the change in the size of the width may be repeated.

[0052] The insulating isolation pattern 130 may include an insulating material. The insulating isolation pattern 130 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and combinations thereof.

[0053] The semiconductor material layer EP may include a first epitaxial layer 145 disposed on side surfaces of the plurality of first channel layers 140A and the plurality of second channel layers 140B respectively facing each other, and a second epitaxial layer 146 disposed in the active region 105 .

[0054] The first epitaxial layer 145 may be disposed on the side surfaces 140S on which the plurality of channel layers 141, 142, and 143 face each other. Among the first epitaxial layers 145, the first epitaxial layer 145 disposed on the side surfaces of the first channel layer 140A and the first epitaxial layer 145 disposed on the side surfaces of the second channel layer 140B at the same height are separated from each other by the insulating isolation pattern 130. The width of each of the first epitaxial layers 145 in the third direction (e.g., the Z-axis direction) may decrease toward the insulating isolation pattern 130. In an example embodiment, the cross-sectional surface of each of the first epitaxial layers 145 may have a triangular shape whose width in the third direction may decrease toward the insulating isolation pattern 130, but example embodiments are not limited thereto. In an example embodiment, the cross-sectional surface of the first epitaxial layers 145 may have opposing triangular shapes, with opposing vertices of the opposing triangular shapes (e.g., vertices facing the insulating isolation pattern 130) corresponding to opposing end portions 145e of the first epitaxial layer 145.

[0055] A second epitaxial layer 146 may be disposed on the substrate 101. The width of the second epitaxial layer 146 in the second direction (e.g., the Y-axis direction) may be substantially the same as the width (e.g., the distance) from the interface surface between the first channel layer 140A and the first epitaxial layer 145 to the interface surface between the second channel layer 140B and the first epitaxial layer 145. The concept of "same size" here may include process variations and may indicate that the widths are not intentionally designed differently. The upper surface of the second epitaxial layer 146 may have a partially inclined shape. Within the upper surface of the second epitaxial layer 146, the upper surface of a central portion adjacent to the boundary between the first region R1 and the second region R2 may have a concave shape toward the substrate 101. The upper surface of the central portion of the second epitaxial layer 146 may have a shape surrounding the insulating isolation pattern 130. The upper surface of the second epitaxial layer 146 may be in contact with the insulating isolation pattern 130.

[0056] The first epitaxial layer 145 and the second epitaxial layer 146 may include the same material, and in example embodiments, may include selectively epitaxially grown silicon (Si). In example embodiments, the first epitaxial layer 145 may include the same material as the plurality of channel layers 141, 142, and 143, and the boundary between the surface where the first epitaxial layer 145 meets the channel layers 141, 142, and 143 may not be clear. In example embodiments, the first epitaxial layer 145 may correspond to a protrusion formed on the plurality of channel layers.

[0057] At least a portion of each of the first epitaxial layers 145 may overlap the insulating isolation pattern 130, the gate dielectric layer 162, the first gate electrode 170A, and the second gate electrode 170B in a third direction (e.g., the Z-axis direction). A third conductive layer 173 may overlap at least a portion of the first epitaxial layer 145 in the third direction between the plurality of first channel layers 140A and / or between the plurality of second channel layers 140B. In the semiconductor device of the exemplary embodiment, by forming the first epitaxial layer 145 extending from the side surfaces of the plurality of channel layers 141, 142, and 143 and including the first gate electrode 170A and the second gate electrode 170B extending into the insulating isolation pattern 130, the effective area and length of the channel layers 141, 142, and 143 may be increased, allowing for smooth electrical signal transmission, thereby improving the electrical properties and reliability of the semiconductor device 100.

[0058] The first interlayer insulating layer IL1 may cover the source / drain regions 150. The first interlayer insulating layer IL1 may include at least one of oxide, nitride, and oxynitride, and may include, for example, a low dielectric constant material. In example embodiments, the first interlayer insulating layer IL1 may include a plurality of insulating layers.

[0059] The contact plug 180 may penetrate the first interlayer insulating layer IL1, may be connected to the source / drain region 150, and may apply an electrical signal to the source / drain region 150. The contact plug 180 may have an inclined side surface, where the width of the lower portion may be further reduced compared to the width of the upper portion according to the aspect ratio (also known as the height-to-width ratio or depth-to-width ratio), but example embodiments are not limited thereto. The contact plug 180 may extend downward, for example, to a region below the lower surface of the channel layer 143, which is the uppermost channel layer of the plurality of first channel layers 140A or the plurality of second channel layers 140B, but example embodiments are not limited thereto. In some example embodiments, the contact plug 180 may not recess the source / drain region 150 and may contact the upper surface of the source / drain region 150.

[0060] Each of the contact plugs 180 may include a metal-semiconductor compound layer (e.g., a metal silicide layer) disposed on a lower end including the lower surface, and may further include a barrier layer that forms a side surface of the contact plug 180 and extends to the upper surface of the metal-semiconductor compound layer. For example, the barrier layer may include a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)). The contact plugs 180 may include a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)). In example embodiments, the number of conductive layers included in the contact plugs 180 and their arrangement may vary.

[0061] An interconnection structure such as a contact plug may be further disposed on the first gate electrode 170A and the second gate electrode 170B, and an interconnection structure such as an interconnection line M1 connected to the contact plug 180 may be further disposed on the contact plug 180. In some example embodiments, an upper insulating layer 191 may be disposed between the interconnection structures such as the contact plug and / or the interconnection line M1.

[0062] In the description of the following exemplary embodiments, the above referenced Figures 1 to 2C Descriptions of descriptions that overlap.

[0063] Figure 3 is a cross-sectional view showing a semiconductor device according to example embodiments, and Figure 2B The corresponding area.

[0064] Reference Figure 3 , except that the cross-sectional surface of the first epitaxial layer 145 has a configuration of a trapezoidal shape, the semiconductor device 100A in the example embodiment may be configured similarly to the reference Figures 1 to 2C The semiconductor device 100A may include a first epitaxial layer 145 having a trapezoidal cross-sectional surface. The width of the first epitaxial layer 145 of the semiconductor device 100A in the second direction (eg, the Y-axis direction) may be smaller than that of the semiconductor device 100 (see FIG. Figure 2B ) in the second direction. In the semiconductor device 100A in the example embodiment, the end portion 145e of the first epitaxial layer 145 may be substantially parallel to the side surface 140S on which the channel layers 141, 142, and 143 are opposite to each other. The first epitaxial layer 145 may have a shape in which its width in the third direction (e.g., the Z-axis direction) may decrease toward the insulating isolation pattern 130. The width of the second epitaxial layer 146 of the semiconductor device 100A in the second direction (e.g., the Y-axis direction) and the third direction (e.g., the Z-axis direction) from the interface surface with the active region 105 may be smaller than that of the semiconductor device (100, see Figure 2B ) of the second epitaxial layer 146 in the second and third directions from the interface surface with the active region 105. In example embodiments, the cross-sectional surface of each of the first epitaxial layers 145 may have a quadrangular shape. In example embodiments, the first epitaxial layer 145 may have a rectangular cross-sectional surface shape whose width may be constantly maintained in the third direction.

[0065] and Figure 2B Refer to it together Figure 3, the side surface of the insulating isolation pattern 130 may have a zigzag shape in which convex and concave shapes are repeated along the shapes of the first epitaxial layer 145, the first gate electrode 170A, and the second gate electrode 170B that are in contact with or adjacent to the insulating isolation pattern 130. The first width W1 of the portion of the insulating isolation pattern 130 between the end portions 145e of the first epitaxial layer 145 opposite to each other may be substantially equal to the second width W2 of the portion of the insulating isolation pattern 130 surrounded by the second epitaxial layer 146. Here, the configuration of the same size may include process errors and may indicate that the widths are not intentionally designed differently. The first width W1 and the second width W2 of the insulating isolation pattern 130 in the semiconductor device 100A may be larger than those in the semiconductor device (100, see Figure 2B ). The first width W1 and the second width W2 of the insulating isolation pattern 130 in the semiconductor device 100A may be greater than the fourth width W4. At a height between the channel layers 141, 142, and 143 spaced apart from each other in the vertical direction, a third width W3 between the side surfaces 130CS of the insulating isolation pattern 130 facing each other may be smaller than the first width W1.

[0066] Figure 4 is a cross-sectional view showing a semiconductor device according to example embodiments, and Figure 2B The corresponding area.

[0067] Reference Figure 4 , except that one end portion 145e of the first epitaxial layer 145 has a rounded configuration, the semiconductor device 100B in the example embodiment may be configured similarly to the reference Figures 1 to 3 The semiconductor device 100B may include a first epitaxial layer 145, and the width of the first epitaxial layer 145 in a third direction (e.g., the Z-axis direction) may decrease toward the insulating isolation pattern 130. In the semiconductor device 100B in the example embodiment, an end portion 145e of the first epitaxial layer 145 may have a circular shape or an arc shape.

[0068] The first width W1 of the portion of the insulating isolation pattern 130 between the opposite ends 145 e of the first epitaxial layer 145 may be the same as or greater than the second width W2 of the portion of the insulating isolation pattern 130 surrounded by the second epitaxial layer 146. The fourth width W4 of the insulating isolation pattern 130 in the semiconductor device 100B may be substantially the same as or greater than the first width W1. The first width W1 and the second width W2 of the insulating isolation pattern 130 in the semiconductor device 100B may be greater than those of the semiconductor device 100 (see FIG. 1 ). Figure 2B). At a height between the channel layers 141, 142, and 143 spaced apart from each other in the vertical direction, a third width W3 between the side surfaces 130CS of the insulating isolation pattern 130 facing each other may be smaller than the first width W1.

[0069] Figure 5 is a cross-sectional view showing a semiconductor device according to example embodiments, and Figure 2B The corresponding area.

[0070] Reference Figure 5 , except for the configuration in which at least a portion 130LS of the side surface of the insulating isolation pattern 130 linearly extends along the end portion 145e of the first epitaxial layer 145 in the second direction, the semiconductor device 100C in the example embodiment may be configured similarly to the reference Figures 1 to 4 The examples described are the same or similar. In the semiconductor device 100C, at least a portion 130LS of the side surface of the insulating isolation pattern 130 may be configured to extend in a third direction (e.g., the Z-axis direction) along an end 145e of the first epitaxial layer 145 in the second direction (e.g., the Y-axis direction). At least a portion 130LS of the side surface of the insulating isolation pattern 130 may be substantially parallel to side surfaces 140S of the plurality of channel layers 141, 142, and 143 that are opposite to each other (e.g., toward the insulating isolation pattern 130).

[0071] A first width W1 of a portion of the insulating isolation pattern 130 between opposing ends 145e of the first epitaxial layer 145 may be substantially the same as a second width W2 of a portion of the insulating isolation pattern 130 surrounded by the second epitaxial layer 146. A third width W3 between opposing side surfaces of the insulating isolation pattern 130 at a height between the vertically spaced channel layers 141, 142, and 143 may be substantially the same as the first width W1. A fourth width W4 of the insulating isolation pattern 130 in the semiconductor device 100C may be greater than the first width W1, the second width W2, and the third width W3. As another example, the fourth width W4 of the insulating isolation pattern 130 in the semiconductor device 100C may be substantially the same as the first width W1, the second width W2, and the third width W3. Here, a configuration of identical dimensions may include process errors and may indicate that the widths were not intentionally designed differently. The insulating isolation pattern 130 may have a shape in which its width (e.g., width in the second direction (e.g., Y-axis direction)) may be constant in a third direction (e.g., Z-axis direction) in a region from the end 145e of the uppermost first epitaxial layer 145 to the second epitaxial layer 146.

[0072] The gate dielectric layer 162, the first conductive layer 171, and the third conductive layer 173 may be sequentially stacked on at least a portion of the side surface of the insulating isolation pattern 130, and the gate dielectric layer 162 and the first conductive layer 171 may conformally extend along the at least a portion of the side surface of the insulating isolation pattern 130. The second conductive layer 172 may have the same or similar configuration as the first conductive layer 171.

[0073] Figure 6 is a cross-sectional view showing a semiconductor device according to example embodiments, and Figure 2B The corresponding area.

[0074] Reference Figure 6 , except for the configuration in which the ends of the first epitaxial layer 145 opposite to each other do not contact the gate dielectric layer 162, the semiconductor device 100D in the example embodiment may be configured as described with reference to FIG. Figures 1 to 5 (For example, Figure 5 ) is the same as or similar to the example described in . In the semiconductor device 100D, at least a portion 130LS of the side surface of the insulating isolation pattern 130 may extend parallel to the side surfaces 140S on which the plurality of channel layers 141, 142, and 143 are opposite to each other, and the end portions 145e of the first epitaxial layer 145 that are opposite to each other may not directly contact the gate dielectric layer 162 and may be spaced apart from each other. In the semiconductor device 100D, the end portion 145e of the first epitaxial layer 145 may contact the insulating isolation pattern 130. In example embodiments, the relationship between the first width W1, the second width W2, the third width W3, and the fourth width W4 of the insulating isolation pattern 130 in the semiconductor device 100D may be similar to, for example, the semiconductor device 100C (see Figure 5 ) are the same or similar to the relationships among the first width W1, the second width W2, the third width W3 and the fourth width W4 of the insulating isolation pattern 130 in FIG.

[0075] Figure 7 is a cross-sectional view showing a semiconductor device according to example embodiments, and Figure 2B The corresponding area.

[0076] Reference Figure 7 , except that at least a portion of the side surface 130XS of the insulating isolation pattern 130 has a convex shape at a height between the plurality of first channel layers 140A or the plurality of second channel layers 140B, the semiconductor device 100E in the example embodiment may be configured as described with reference to FIG. Figures 1 to 6The examples described are the same or similar. In the semiconductor device 100E, the width of the insulating isolation pattern 130 in the second direction (e.g., the Y-axis direction) may not be uniform. The width of the insulating isolation pattern 130 in the second direction may be widest at a height between the plurality of first channel layers 140A or the plurality of second channel layers 140B and may decrease toward the end 145e of the first epitaxial layer 145. The side surface of the insulating isolation pattern 130 in the second direction may have a concave shape between the plurality of channel layers 141, 142, or 143 arranged at the same height, and may have a convex shape between first epitaxial layers 145 arranged at adjacent heights (e.g., adjacent to each other in the third direction (e.g., the Z-axis direction)) and between the lowest first epitaxial layer 145 and the second epitaxial layer 146 arranged at the lowest height among the first epitaxial layers 145. The side surface of the insulating isolation pattern 130 in the second direction may have a zigzag shape in which the above-described concave and convex shapes are repeated.

[0077] At a height between the channel layers 141 , 142 , and 143 spaced apart from each other in a vertical direction, a third width W3 between opposite side surfaces 130XS of the insulating isolation pattern 130 may be greater than a first width W1 of a portion of the insulating isolation pattern 130 between opposite end portions 145 e of the first epitaxial layer 145 .

[0078] Figures 8A to 8I are diagrams illustrating processes of a method of manufacturing a semiconductor device according to example embodiments. Figures 8A to 8I Shown manufacturing Figures 1 to 2B An example embodiment of a method of a semiconductor device 100 is provided. Figures 8A to 8I Shown along Figure 1 The cross-sectional surface is taken along line II-II'.

[0079] Reference Figure 8A , a sacrificial layer 120 and a plurality of channel layers 141 , 142 , and 143 may be alternately stacked on the substrate 101 .

[0080] like Figure 2A and Figure 2BAs shown in , the sacrificial layer 120 can be replaced with a gate dielectric layer 162 and first and second gate electrodes 170A and 170B through subsequent processes. The sacrificial layer 120 can be formed of a material having an etching selectivity with respect to the first to third channel layers 141, 142, and 143, respectively. The first to third channel layers 141, 142, and 143 can include a material different from that of the sacrificial layer 120. The sacrificial layer 120 and the first to third channel layers 141, 142, and 143 can include, for example, a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), can include different materials, and may or may not include impurities. For example, the sacrificial layer 120 can include silicon germanium (SiGe), and the first to third channel layers 141, 142, and 143 can include silicon (Si).

[0081] The sacrificial layer 120 and the first to third channel layers 141, 142, and 143 may be formed by performing an epitaxial growth process from the substrate 101. The number of channel layers 141, 142, and 143 alternately stacked with the sacrificial layer 120 may vary in example embodiments. The thickness of the sacrificial layer 120U disposed on the uppermost end among the plurality of sacrificial layers 120 may be greater than the thicknesses of the other sacrificial layers 120, but example embodiments are not limited thereto.

[0082] Reference Figure 8B , an active structure may be formed by removing the sacrificial layer 120 , the plurality of channel layers 141 , 142 , and 143 , and a portion of the substrate 101 , and the device isolation layer 110 may be formed.

[0083] The active structure may include a sacrificial layer 120 and a plurality of channel layers 141, 142, and 143 stacked alternately, and may also include an active region 105 protruding from the substrate 101 by removing a portion of the substrate 101. The active structure may be formed in a linear shape extending in a first direction (e.g., the X-axis direction) and may be spaced apart from each other in a second direction (e.g., the Y-axis direction). In example embodiments, when the active region 105 is divided into a first active region and a second active region, the first active region and the second active region may include the same or different impurities, and the impurities may be doped into the substrate 101 before forming the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143.

[0084] In the region where a portion of the substrate 101 has been removed, the device isolation layer 110 may be formed by filling an insulating material and partially removing the insulating material so that the active region 105 may protrude. The upper surface of the device isolation layer 110 may be formed at a height lower than that of the upper surface of the active region 105.

[0085] Reference Figure 8CA first recessed region RC1 may be formed on the active structure, penetrating the sacrificial layer 120 and the channel layers 141, 142, and 143 and extending in a third direction (e.g., the Z-axis direction). The first recessed region RC1 may be formed by patterning the sacrificial layer 120 and the channel layers 141, 142, and 143. The first recessed region RC1 may be configured as a trench region extending in a first direction (e.g., the X-axis direction) along the active structure. The first recessed region RC1 may extend into the substrate 101 and may overlap at least a portion of each of the first and second regions R1 and R2 of the substrate 101 (e.g., the first and second active regions of the active region 105) in a second direction (e.g., the Y-axis direction).

[0086] Reference Figure 8D , a mask layer 135 may be provided on both sides of the active structure, and in the first recessed region RC1, a first epitaxial layer 145 may be formed on the inner side surface 140S of each of the plurality of channel layers 141, 142, and 143, and a second epitaxial layer 146 may be formed on the inner side surface of the active structure (e.g., the inner surface of the active region 105).

[0087] The mask layer 135 may cover both side surfaces of the active structure and at least a portion of the upper surface of the active structure. The mask layer 135 may extend parallel to the active structure in a first direction (e.g., the X-axis direction). The mask layer 135 may not cover the first recessed region RC1 and may cover both side surfaces of the active structure to prevent epitaxial growth of silicon (Si) on these side surfaces in subsequent processes. Side surfaces of the channel layers 141, 142, and 143, including those in the first recessed region RC1, may be exposed from the mask layer 135. The first and second epitaxial layers 145 and 146 may be formed on the surfaces (e.g., side surfaces and / or inner surfaces) of the channel layers 141, 142, and 143 and the active region 105 in the first recessed region RC1 through an epitaxial growth process and may comprise the same material. For example, the first and second epitaxial layers 145 and 146 may comprise silicon (Si). The first epitaxial layer 145 and the second epitaxial layer 146 (eg, a portion of the second epitaxial layer 146 ) may have a cross-sectional surface having a triangular shape as shown, but example embodiments are not limited thereto, and the first epitaxial layer 145 and the second epitaxial layer 146 (eg, a portion of the second epitaxial layer 146 ) may have a cross-sectional surface having a trapezoidal shape (see FIG. 2 ). Figure 3 ). In addition, after forming the first epitaxial layer 145 and the second epitaxial layer 146, etching or other removal processes may be performed. For example, by removing a portion of the end portion 145e of the first epitaxial layer 145, a semiconductor device (100B, see FIG. 10B ) of another exemplary embodiment including the first epitaxial layer 145 having an arc semicircular shape may be formed. Figure 4). The distance between the opposing ends 145e of the first epitaxial layer 145 in the second direction (e.g., the Y-axis direction) may be referred to as a first width W1. At least a portion of the upper surface of the second epitaxial layer 146 may have a concave shape toward the substrate 101 in a central portion adjacent to the boundary between the first region R1 and the second region R2. The width of the concave region of the second epitaxial layer 146 in the second direction may be referred to as a second width W2. The size of the first width W1 may be the same as the size of the second width W2, but example embodiments are not limited thereto. The first width W1 and the second width W2 may be determined according to the extent of formation of the semiconductor material layer EP, and the semiconductor devices of the various example embodiments described above may be formed.

[0088] Reference Figure 8E , a preliminary insulating isolation pattern 130p may be formed by filling the first recessed region RC1 with an insulating material, and the mask layer (135, see Figure 8D ).

[0089] The insulating material may include silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. The preliminary insulating isolation pattern 130p may be formed in the active structure on the active region 105 and may have a shape extending in a first direction (eg, X-axis direction) along the active structure. The first recessed region (RC1, see FIG. 1 ) may be filled with the insulating material. Figure 8D The preliminary insulating isolation pattern 130p formed by the process of (i) may cover the first epitaxial layer 145 and the second epitaxial layer 146. The upper surface of the preliminary insulating isolation pattern 130p may be coplanar with the upper surface of the uppermost sacrificial layer 120U. In subsequent processes, by removing the mask layer 135 covering at least a portion of the two side surfaces and the upper surface of the active structure, the two side surfaces and the upper surface of the active structure may be exposed, and at least a portion of the upper surface of the device isolation layer 110 may be exposed.

[0090] Reference Figure 8F , a sacrificial gate structure 200 and a gate spacer layer 163 may be formed on the active structure (see Figure 2A ).

[0091] The sacrificial gate structure 200 may be constructed such that Figure 2A and Figure 2B The gate dielectric layer 162 and the first and second gate electrodes 170A and 170B shown in FIG are provided in a sacrificial structure formed in a region on the channel structure 140 through subsequent processes. The sacrificial gate structure 200 may have a linear shape that intersects the active structure and extends in one direction. The sacrificial gate structure 200 may extend in the Y-axis direction, for example.

[0092] The sacrificial gate structure 200 may include a first sacrificial gate layer 202, a second sacrificial gate layer 205, and a mask pattern layer 206 stacked in sequence. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be patterned using the mask pattern layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be configured as an insulating layer and a conductive layer, respectively, but example embodiments are not limited thereto, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be configured as an integrated layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon oxide and / or silicon nitride.

[0093] Gate spacer layer (163, see Figure 2A ) may be sequentially formed on both sidewalls of the sacrificial gate structure 200. The gate spacer layers 163 may be formed of a low dielectric constant material, and each of the gate spacer layers 163 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0094] First, a recessed region may be formed by removing a portion of the exposed sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 using the sacrificial gate structure 200 and the gate spacer layer 163 as a mask. Thus, the plurality of channel layers 141, 142, and 143 may form a channel structure 140 having a limited length in a first direction (e.g., the X-axis direction).

[0095] Thereafter, source / drain regions 150 may be formed by growing from the side surfaces of the active region 105 and the channel structure 140, for example, via a selective epitaxial process. Figure 2A and Figure 2C ) may include impurities due to in-situ doping and may include multiple layers with different doping elements and / or doping concentrations.

[0096] Reference Figure 8G , a first interlayer insulating layer IL1 may be formed, and the sacrificial layer 120 and the sacrificial gate structure 200 may be removed.

[0097] The first interlayer insulating layer IL1 may be formed by forming an insulating film covering the sacrificial gate structure 200 and the source / drain regions 150 and performing a planarization process.

[0098] relative to the gate spacer layer 163, the first interlayer insulating layer (IL1, see Figure 2A) and the channel structure 140, the sacrificial layer 120 and the sacrificial gate structure 200 are selectively removed. First, an upper gap region (not shown) can be formed by removing the sacrificial gate structure 200, and a lower gap region (not shown) can be formed by removing the sacrificial layer 120 exposed through the upper gap region. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 120 can be selectively removed by performing a wet etching process. According to the process of removing the sacrificial layer 120, the side surfaces 130ES of the preliminary insulating isolation patterns 130p in contact with the sacrificial layer 120 may be exposed from the plurality of channel layers 141, 142, and 143.

[0099] Reference Figure 8H , the second recess region RC2 and the insulating isolation pattern 130 may be formed by removing a portion of the preliminary insulating isolation pattern 130 p .

[0100] The exposed side surfaces (130ES, see Figure 8G ). When removed by dry etching process, such as Figure 8H As shown in FIG, a portion 130CS of the side surface of the insulating isolation pattern 130 may have a concave shape, but example embodiments thereof are not limited thereto. In example embodiments, when an ALE (atomic layer etching) process is performed, the etching process may be performed in parallel to the exposed side surface 130ES of the preliminary insulating isolation pattern 130p, and the side surface of the insulating isolation pattern 130 may have a linearly extending shape (130LS, see FIG. Figure 5 When the ALE process is performed, the etching speed may not necessarily be constant in the surface direction, and etching may be performed faster in the central portion. In this case, a semiconductor device (100D, see FIG. 100D ) in which the etching process has been less performed on the outer area of ​​the exposed side surface 130ES of the preliminary insulating isolation pattern 130p may be formed. Figure 6 In another example embodiment, the etching process may be performed relatively quickly along the surface on the upper and lower surfaces of the channel layers 141, 142, and 143, and in this case, a semiconductor device (100E, see Figure 7By forming the second recessed region RC2 by removing a portion of the preliminary insulating isolation pattern 130p, a third width W3 between opposing side surfaces 130CS of the insulating isolation pattern 130 may be determined at a height between the channel layers 141, 142, and 143 vertically spaced apart from each other. A fourth width W4 of the insulating isolation pattern 130 at a height higher than the height of the uppermost channel layer 143 among the plurality of channel layers 141, 142, and 143 may be greater than the third width W3, but example embodiments are not limited thereto. By forming the second recessed region RC2, the semiconductor devices of the various example embodiments described above may be formed.

[0101] Reference Figure 8I , a gate dielectric layer 162 may be formed, a first conductive layer 171 and a second conductive layer 172 may be formed, and a preliminary third conductive layer 173p may be formed.

[0102] The gate dielectric layer 162 may be formed to conformally cover the side, lower, and upper surfaces of the plurality of channel layers 141, 142, and 143, as well as the side surfaces of the insulating isolation pattern 130, on the first and second regions R1 and R2. The gate dielectric layer 162 may be formed to cover both the first and second regions R1 and R2 of the substrate 101. A first conductive layer 171 may be formed on the first region R1, and a second conductive layer 172 may be deposited on the second region R2. Using a mask pattern (not shown), the first and second conductive layers 171 and 172 may be formed on the insulating isolation pattern 130 such that one side surface of the first and second conductive layers 171 and 172 are in contact with each other (e.g., contacting on the insulating isolation pattern 130). The first and second conductive layers 171 and 172 may control the work function and may include different metals, but example embodiments are not limited thereto. A preliminary third conductive layer 173p may be formed on the first and second conductive layers 171 and 172. The preliminary third conductive layer 173p may fill the region between the plurality of first channel layers 140A and the plurality of second channel layers 140B and may overlap the first epitaxial layer 145 in a third direction (e.g., the Z-axis direction). The preliminary third conductive layer 173p may extend further than the side surfaces 140S of the plurality of channel layers 141, 142, and 143 facing each other.

[0103] Afterwards, refer to Figures 2A to 2C In subsequent processes, a third conductive layer 173 , a gate capping layer 166 , and a contact plug 180 may be formed, thereby forming the semiconductor device 100 in example embodiments.

[0104] This can be achieved by depositing a preliminary third conductive layer (173p, see Figure 8I) process, a planarization process is further performed to form a third conductive layer 173. The third conductive layer 173 may completely fill the upper gap region (not shown). The planarization process exposes the upper surface of the insulating isolation pattern 130, and the upper surface of the insulating isolation pattern 130 and the upper surface of the third conductive layer 173 may be coplanar with each other. In some example embodiments, the third conductive layer 173 may include multiple conductive layers. As a result, the first gate electrode 170A and the second gate electrode 170B may be formed.

[0105] The gate capping layer 166 may be formed by partially removing the first gate electrode 170A, the second gate electrode 170B, the gate dielectric layer 162, and the gate spacer layer 163, filling the removed regions with an insulating material, and performing a planarization process. In example embodiments, the relative thickness of the gate capping layer 166 and the shape of its lower surface may vary.

[0106] Thereafter, a second interlayer insulating layer IL2 may be further formed, and a contact plug 180 connected to the source / drain region 150 may be formed. Thus, a Figures 1 to 2C The semiconductor device 100 in FIG.

[0107] According to the aforementioned example embodiments, a semiconductor device having improved electrical properties and reliability may be provided by including a channel layer having a portion of its side surface extended and an insulating pillar having a portion of its side surface removed.

[0108] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the example embodiments as defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate comprising a first region and a second region, the substrate comprising an active region extending in a first direction; A device isolation layer defines an active area, and the device isolation layer is on the substrate; a first gate electrode and a second gate electrode extending in a second direction and intersecting the active region, the first gate electrode and the second gate electrode being spaced apart from each other; a plurality of first channel layers spaced apart from each other in a third direction, the third direction being perpendicular to the upper surface of the substrate, and the plurality of first channel layers being surrounded by the first gate electrode on the first region; a plurality of second channel layers spaced apart from each other in a third direction, wherein the plurality of second channel layers are surrounded by a second gate electrode on the second region; an insulating isolation pattern extending in a first direction between the first gate electrode and the second gate electrode and between the plurality of first channel layers and the plurality of second channel layers, the insulating isolation pattern being on the substrate; a gate dielectric layer between the plurality of first channel layers and the first gate electrode, the gate dielectric layer also being between the plurality of second channel layers and the second gate electrode; as well as epitaxial layer on side surfaces of the plurality of first channel layers and the plurality of second channel layers respectively facing each other, A portion of each of the epitaxial layers overlaps the insulating isolation pattern, the gate dielectric layer, the first gate electrode, and the second gate electrode in the third direction.

2. The semiconductor device according to claim 1, in, The first gate electrode includes a first conductive layer conformally extending along an upper surface, a side surface, and a lower surface of each of the plurality of first channel layers, and The second gate electrode includes a second conductive layer, and the second conductive layer conformally extends along the upper surface, the side surface, and the lower surface of each of the plurality of second channel layers.

3. The semiconductor device according to claim 2, wherein The first conductive layer and the second conductive layer include different metal materials.

4. The semiconductor device according to claim 2, wherein The first gate electrode further includes a third conductive layer on the first conductive layer and between the plurality of first channel layers in the third direction.

5. The semiconductor device according to claim 4, wherein The third conductive layer overlaps at least a portion of a corresponding one of the epitaxial layers in the third direction.

6. The semiconductor device according to claim 1, wherein The insulating isolation pattern includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and a combination thereof.

7. The semiconductor device according to claim 1, wherein The insulating isolation pattern extends to a height lower than that of an upper surface of the active region.

8. The semiconductor device according to claim 1, wherein The epitaxial layer includes a first epitaxial layer on a side surface of a corresponding first channel layer among the plurality of first channel layers, and a second epitaxial layer on a side surface of a corresponding second channel layer among the plurality of second channel layers, The first epitaxial layer and the second epitaxial layer are disposed at the same height and are spaced apart from each other, with an insulating isolation pattern between the first epitaxial layer and the second epitaxial layer.

9. The semiconductor device according to claim 1, wherein Each of the epitaxial layers has a width in the third direction that decreases as the epitaxial layer extends toward the insulating isolation pattern.

10. The semiconductor device according to claim 9, wherein A cross-sectional shape of each of the epitaxial layers is one of a triangular shape, a quadrangular shape, and a semicircular shape.

11. The semiconductor device according to claim 1 , further comprising: A gate capping layer is formed on an upper surface of the first gate electrode, an upper surface of the second gate electrode, and an upper surface of the insulating isolation pattern.

12. The semiconductor device according to claim 1, wherein The epitaxial layers each include the same material as a material of an adjacent first channel layer among the plurality of first channel layers or a material of an adjacent second channel layer among the plurality of second channel layers.

13. The semiconductor device according to claim 1, wherein A portion of a side surface of the insulating isolation pattern extends in the third direction along an end portion of the epitaxial layer in the second direction.

14. The semiconductor device according to claim 13, wherein Ends of the epitaxial layer opposite to each other do not contact the gate dielectric layer.

15. The semiconductor device according to claim 1, wherein A portion of a side surface of the insulating isolation pattern has a convex shape toward the outside at a height between the epitaxial layers at different heights.

16. A semiconductor device comprising: a substrate comprising an active region extending in a first direction; a first gate electrode and a second gate electrode extending in a second direction and intersecting the active region, the first gate electrode and the second gate electrode being spaced apart from each other; a plurality of first channel layers spaced apart from each other in a third direction, the third direction being perpendicular to the upper surface of the substrate, and the plurality of first channel layers being surrounded by the first gate electrode; a plurality of second channel layers spaced apart from each other in a third direction, wherein the plurality of second channel layers are surrounded by a second gate electrode; an insulating isolation pattern, between the plurality of first channel layers and the plurality of second channel layers, the insulating isolation pattern extending to a height lower than that of an upper surface of the active region; a first epitaxial layer, on side surfaces of the plurality of first channel layers and the plurality of second channel layers respectively facing each other, the first epitaxial layer being in contact with the insulating isolation pattern on the active region; as well as The second epitaxial layer is in the active region of the substrate and has an upper surface contacting the insulating isolation pattern.

17. The semiconductor device according to claim 16, wherein The first epitaxial layer and the second epitaxial layer include the same material.

18. The semiconductor device according to claim 16, wherein A lower surface of the second epitaxial layer is lower than an upper surface of the active region.

19. A semiconductor device comprising: a substrate comprising a first region and a second region, the substrate comprising an active region extending in a first direction; a first gate electrode and a second gate electrode extending in a second direction and intersecting the active region, the first gate electrode including a first conductive layer, the second gate electrode including a second conductive layer, the first gate electrode and the second gate electrode each further including a third conductive layer, the first conductive layer and the third conductive layer of the first gate electrode being stacked in sequence, and the second conductive layer and the third conductive layer of the second gate electrode being stacked in sequence; a plurality of channel layers stacked in a third direction on the active area, the third direction being perpendicular to the upper surface of the substrate, and the plurality of channel layers overlapping the third conductive layer of the first gate electrode in the third direction; a gate dielectric layer covering a portion of each of the plurality of channel layers; an insulating isolation pattern between the first gate electrode and the second gate electrode; and a semiconductor material layer disposed on a side surface of at least one of the plurality of channel layers, The first conductive layer and the second conductive layer include different metal materials.

20. The semiconductor device according to claim 19, wherein A gate dielectric layer is also between the first gate electrode and the insulating isolation pattern and between the second gate electrode and the insulating isolation pattern.

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