Semiconductor light-emitting device and preparation method thereof

Abstract

A semiconductor light emitting device includes a sapphire substrate, a porous SiO2 pattern layer, and a porous GaN buffer layer. The SiO2 pattern layer is located on one surface of the sapphire substrate and partially covers the sapphire substrate. The GaN buffer layer is located on the side, provided with the SiO2 pattern layer, of the sapphire substrate and completely covers the SiO2 pattern layer. The semiconductor light-emitting device further comprises an N-type GaN layer, a multi-quantum well layer and a P-type GaN layer which are sequentially stacked on the GaN buffer layer. The invention also provides a preparation method of the semiconductor light-emitting device. A porous SiO2 pattern layer structure and a porous GaN buffer layer structure are arranged on a sapphire substrate, so that a low-refractive-index porous composite structure substrate is formed, dislocation density is reduced, internal quantum efficiency is improved, a photon escape angle is increased, light extraction efficiency is improved, and strain and defects of an epitaxial layer caused by In segregation are solved; therefore, the GaN-based light-emitting diode with high luminous efficiency is prepared.

Description

Technical Field

[0001] The present application relates to the field of optics, and in particular to a semiconductor light-emitting device and a method for preparing the semiconductor light-emitting device. Background Art

[0002] A light-emitting diode (LED) is a semiconductor light-emitting device. Currently, GaN-based LEDs are widely used due to their wide bandgap (tunable from 0.7 eV for InN to 3.39 eV for GaN by varying the ratio of In and Ga), excellent mechanical stability, and short hole diffusion length. Sapphire is often used as the substrate for GaN-based LEDs. However, issues such as lattice mismatch, thermal expansion coefficient, and total internal reflection (IR) between GaN and sapphire substrates result in numerous dislocations in the GaN epilayer and a small photon escape angle, reducing the internal quantum efficiency and light extraction efficiency of the LED, thus limiting its lifespan. A conventional solution is to use patterned sapphire substrates. However, the refractive index of single patterned sapphire substrates limits their effectiveness in improving luminous efficiency, making further improvement in LED luminous efficiency a technical challenge. While full-color illumination can be achieved with GaN-based LEDs by adjusting the In content, high In concentrations in the quantum wells can lead to severe In segregation, resulting in stress concentration and reduced LED luminous efficiency. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor light-emitting device, which forms a low-refractive-index porous composite structure substrate by arranging a porous SiO2 pattern layer and a porous GaN buffer layer structure on a sapphire substrate, thereby further reducing the dislocation density, improving the internal quantum efficiency, increasing the photon escape angle, improving the light extraction efficiency, and solving the strain and defects of the epitaxial layer caused by the In segregation problem, thereby preparing a high-efficiency GaN-based light-emitting diode.

[0004] A semiconductor light-emitting device, comprising: Sapphire substrate; a porous SiO2 patterned layer, located on one surface of the sapphire substrate and partially covering the sapphire substrate; a porous GaN buffer layer, located on a side of the sapphire substrate having the SiO2 pattern layer, wherein the GaN buffer layer completely covers the SiO2 pattern layer; An N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially stacked on the GaN buffer layer from bottom to top.

[0005] In some embodiments, a groove is formed in an area of ​​the sapphire substrate not covered by the SiO 2 pattern layer, and the GaN buffer layer fills the groove.

[0006] In some embodiments, the groove has a sidewall, and the sidewall is obliquely connected to the surface of the sapphire substrate where the SiO2 pattern layer is provided.

[0007] In some embodiments, the SiO2 pattern layer includes a top surface facing away from the sapphire substrate, a bottom surface opposite to the top surface, and a side surface connected between the top surface and the bottom surface. The side surface is obliquely connected to the bottom surface, and an area of ​​the top surface is smaller than an area of ​​the bottom surface.

[0008] In some embodiments, the thickness of the SiO2 pattern layer is 25-35 nm; the thickness of the GaN buffer layer is 70-120 nm.

[0009] The present application also provides a method for preparing a semiconductor light-emitting device, which comprises: Providing sapphire substrates; forming a silicon-containing precursor layer on one surface of the sapphire substrate, and sintering the silicon-containing precursor layer to form a porous SiO2 layer; Partially etching the SiO2 layer to transform the SiO2 layer into a SiO2 pattern layer; forming a GaN buffer layer on a side of the sapphire substrate having the SiO2 pattern layer, wherein the GaN buffer layer completely covers the SiO2 pattern layer; Electrochemically etching the GaN buffer layer to form the GaN buffer layer into a porous structure; and An N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially formed on the GaN buffer layer.

[0010] A method for preparing a semiconductor light-emitting device comprises forming a nanometer-scale SiO2 patterned layer structure on a sapphire substrate. The low refractive index and rough surface of the SiO2 patterned layer can improve light extraction efficiency, and the feature of not easily nucleating can reduce dislocation density and improve internal quantum efficiency. A porous GaN buffer layer is formed on the SiO2 patterned layer. The porous GaN buffer layer can release thermal stress generated by dislocations and improve internal quantum efficiency. The porous GaN buffer layer has a relatively low refractive index and can also improve light extraction efficiency. The voids in the porous GaN buffer layer can absorb multi-quantum well In atoms without expanding the crystal structure, thereby preventing strain and defects in the epitaxial layer of the red InGaN light-emitting diode caused by In segregation, thereby realizing an InGaN light-emitting diode with a high In concentration.

[0011] In some embodiments, forming a porous SiO2 layer comprises: providing a sol containing a silicon precursor; applying the sol to a surface of the sapphire substrate to form a wet film; The wet film is dried and sintered in sequence to form a porous SiO2 layer.

[0012] In some embodiments, forming the SiO2 pattern layer includes: forming a photoresist layer on a surface of the SiO2 layer facing away from the sapphire substrate; performing nanoimprint lithography on the photoresist layer to form a patterned photoresist layer; The SiO2 layer is etched using the patterned photoresist layer as a shield to form a SiO2 pattern layer.

[0013] In some embodiments, the SiO2 layer is etched by wet etching, and the etching solution used in the wet etching contains hydrofluoric acid.

[0014] In some embodiments, the preparation method further includes: etching the sapphire substrate to form grooves after forming the SiO2 pattern layer and before forming the GaN buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a flow chart of a method for preparing a semiconductor light-emitting device according to an embodiment of the present application.

[0016] Figure 2 Schematic diagram of steps S1 to S3 of a process for preparing a semiconductor light-emitting device according to an embodiment of the present application.

[0017] Figure 3 Schematic diagram of steps S4 to S6 of the preparation process of the semiconductor light-emitting device according to an embodiment of the present application.

[0018] Figure 4 Schematic cross-sectional view of a semiconductor light-emitting device according to an embodiment of the present application.

[0019] Description of main component symbols: Sapphire substrate 10, wet film 11, SiO2 layer 13, SiO2 pattern layer 20, photoresist layer 15, groove 101, GaN buffer layer 30, N-type GaN layer 40, multi-quantum well layer 50, P-type GaN layer 60, transparent conductive layer 70, A first electrode 80 , a second electrode 90 , and a semiconductor light emitting device 100 . DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Unless otherwise specified, the data range values ​​recorded in this application should include the end values.

[0021] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0022] The semiconductor light-emitting device of the embodiment of the present application forms a low-refractive-index porous composite structure substrate by arranging a porous nano-SiO2 patterned structure and a porous GaN buffer layer structure on a sapphire substrate, thereby further reducing the dislocation density, improving the internal quantum efficiency, increasing the photon escape angle, improving the light extraction efficiency, and solving the strain and defects of the epitaxial layer caused by the In segregation problem, thereby preparing a high-efficiency GaN-based red light LED.

[0023] like Figure 1 As shown, a method for preparing a semiconductor light-emitting device includes steps S1 to S6.

[0024] See also Figure 2 , step S1: providing a sapphire substrate 10.

[0025] In some embodiments, the sapphire substrate 10 may be subjected to conventional cleaning and drying processes to remove impurities and dirt on the surface of the sapphire substrate 10 .

[0026] Sapphire substrate 10 is a key material for semiconductor light-emitting devices. Its chemical composition is single-crystalline α-aluminum oxide with a hexagonal structure. With a Mohs hardness of 9, second only to diamond, sapphire substrate 10 offers exceptional wear resistance. Its melting point is approximately 2050°C, making it highly resistant to high temperatures. It also exhibits high transmittance in the ultraviolet to infrared wavelength range (approximately 150nm to 5500nm) and high resistivity, making it suitable as an insulating substrate.

[0027] Step S2: forming a porous SiO 2 layer on one surface of the sapphire substrate 10 .

[0028] In some embodiments, step S2 further includes steps S21 to S22.

[0029] S21: providing a sol containing a silicon precursor.

[0030] The silicon precursor-containing sol includes a silicon precursor and a liquid solvent.

[0031] In some embodiments, the silicon-containing precursor sol includes a silicon precursor (e.g., tetraethyl orthosilicate), an organic solvent (e.g., ethanol), water (to partially hydrolyze the tetraethyl orthosilicate), and an acid / base catalyst (e.g., hydrochloric acid or aqueous ammonia). The silicon-containing precursor sol is prepared by mixing and stirring tetraethyl orthosilicate, ethanol, an appropriate amount of water, and an acid / base catalyst to obtain a sol. The sol is then allowed to stand for a certain period of time to age and stabilize the sol viscosity. The sol is then applied to the surface of the sapphire substrate 10 to form a film.

[0032] In some embodiments, the molar ratio of ethyl orthosilicate, ethanol, and water is 1:4:4, the amount of catalyst (HCl) added is controlled to have a pH of 2, and the sol is stirred for 1-2 hours; then the sol is aged for 12-24 hours.

[0033] In other embodiments, the silicon-containing precursor sol includes a nano-silica dispersion (e.g., with a particle size of 10-50 nm and a solid content of 5%-20%) and necessary additives, which may include an adhesion promoter and a surfactant. The adhesion promoter (e.g., hexamethyldisilazane (HMDS)) is used to enhance adhesion between the silicon dioxide and the sapphire substrate 10. The surfactant (Triton X-100) is used to improve wettability.

[0034] S22: Figure 1 As shown, a sol containing a silicon precursor is applied on one surface of a sapphire substrate 10 to form a wet film 11 .

[0035] In some embodiments, a wet film 11 of a silicon-containing precursor having a uniform thickness is formed on one surface of a sapphire substrate 10 by spin coating. First, a sol of a silicon-containing precursor is dripped onto the surface of the sapphire substrate 10. The sapphire substrate 10 is rotated, and centrifugal force is used to evenly spread the sol on the surface of the sapphire substrate 10, thereby forming a wet film 11 of uniform thickness. The wet film 11 completely covers one surface of the sapphire substrate 10.

[0036] S22 : Drying and sintering are performed in sequence to form a porous SiO 2 layer 13 on the surface of the sapphire substrate 10 .

[0037] The purpose of drying is to remove the solvent in the wet film 11. The purpose of sintering is to transform the silicon-containing precursor into silicon dioxide, thereby forming a porous SiO2 layer 13, and the SiO2 layer 13 can be firmly bonded to the sapphire substrate 10. Since the organic components in the sol are removed by sintering, pores are formed in the SiO2 layer 13. In some embodiments, the porosity of the porous SiO2 layer 13 is 30%-60%, for example, a porosity of 31%, 35%, 37%, 40%, 43%, 45%, 47%, 50%, 55% or 60%; the pore size of the micropores in the porous SiO2 layer 13 can be several nanometers to more than ten nanometers.

[0038] Step S3 : Partially etching the SiO 2 layer 13 to transform the SiO 2 layer 13 into a SiO 2 pattern layer 20 .

[0039] In some embodiments, step S3 specifically further includes steps S31 to S34.

[0040] S31: providing photoresist.

[0041] The photoresist is a photoresist suitable for nanoimprint lithography that is commonly used in the art. In some embodiments, the photoresist includes a resin matrix, a diluent, a photoinitiator, and an auxiliary agent. The resin matrix can be epoxy acrylate or modified polysilsesquioxane, which can provide the mechanical strength and etching resistance of the photoresist. The diluent can be 2-phenoxyethyl acrylate, which can be used to adjust the viscosity of the photoresist. The photoinitiator can be a triarylsulfonium salt, which is used to initiate polymerization under UV irradiation. The auxiliary agent can be a fluorine / silicon additive, such as modified 2-vinylhexafluoroisopropanol, which is used to reduce surface energy and improve demolding properties.

[0042] S32: forming a photoresist layer 15 on the surface of the SiO2 layer facing away from the sapphire substrate 10.

[0043] In the embodiment of the present application, a photoresist layer 15 of uniform thickness is formed on one surface of the SiO2 layer by spin coating. The photoresist layer 15 completely covers the surface of the SiO2 layer facing away from the sapphire substrate 10. First, photoresist is dripped onto the surface of the sapphire substrate 10. The sapphire substrate 10 is rotated, and the centrifugal force is used to evenly spread the photoresist on the surface of the SiO2 layer, thereby forming a photoresist layer 15 of uniform thickness. It will be understood that the method for forming the photoresist layer 15 on the surface of the SiO2 layer is not limited to spin coating, and various methods conventionally used in the art can also be used.

[0044] S33 : performing nanoimprint lithography on the photoresist layer 15 .

[0045] Nanoimprint lithography (NIL) is a technique that achieves nanoscale pattern transfer through physical imprinting. Compared to traditional optical lithography, it offers advantages such as high resolution, low cost, and low energy consumption. It also surpasses the optical diffraction limit, achieving a resolution of <10 nm. Step S33 is used to form the desired pattern on the photoresist layer, specifically, to form a patterned photoresist layer 15. In this manner, portions of the photoresist layer 15 cover the SiO2 layer, while portions of the SiO2 layer are exposed relative to the photoresist layer 15.

[0046] In some embodiments, a template (e.g., a quartz or silicon-based template) is brought into contact with the photoresist layer 15, and pressure is applied to cause the photoresist layer 15 to surround the template. The photoresist layer 15 is then cured, either by UV curing or heat curing, and the template is then separated from the photoresist layer 15, thereby transferring the pattern of the template to the photoresist layer 15.

[0047] S34: using the photoresist layer 15 as a shield, the SiO 2 layer is etched to form a SiO 2 pattern layer 20 .

[0048] During the etching process, the portion of the SiO2 layer covered / shielded by the photoresist is not etched, while the portion of the SiO2 layer exposed relative to the photoresist is removed by etching. When the etching depth of the SiO2 layer reaches a thickness equal to the SiO2 layer, the etching of the SiO2 layer is complete, and the SiO2 layer forms a SiO2 pattern layer 20, which partially covers the sapphire substrate 10. The pattern of the SiO2 pattern layer 20 can reach the nanometer level.

[0049] In some embodiments, the SiO2 layer is etched by wet etching, wherein the etching solution used contains hydrofluoric acid.

[0050] The SiO2 layer has a porous structure, so the SiO2 pattern layer 20 also has a porous structure. The porous structure can reduce the refractive index of the SiO2 pattern layer 20 and improve the surface roughness of the SiO2 pattern layer 20 to a certain extent.

[0051] After this step S3, a porous nano-SiO2 pattern layer 20 structure with low refractive index, rough surface, and difficulty in GaN nucleation can be formed on the sapphire substrate 10. The low refractive index and rough surface can improve the light extraction efficiency, and the SiO2 pattern layer 20 has the characteristics of difficulty in GaN nucleation, which can reduce the dislocation density and improve the internal quantum efficiency. In the embodiment of the present application, wet etching is adopted. By controlling the etching rate and time, the area where the SiO2 layer is away from the sapphire substrate 10 can be etched to a greater extent. On the contrary, the area where the SiO2 layer is closer to the sapphire substrate 10 is etched to a lesser extent. The SiO2 pattern layer 20 has a top surface facing away from the sapphire substrate 10, a bottom surface opposite to the top surface, and a side surface connected between the top surface and the bottom surface. Therefore, the side surface of the SiO2 pattern layer 20 obtained by the final etching will not be perpendicular to the surface of the sapphire substrate 10, but the side surface of the SiO2 pattern layer 20 is inclined to connect to the surface of the sapphire substrate 10. The side surface of the SiO2 pattern layer 20 intersects with the surface of the sapphire substrate 10 to form an obtuse angle. The area of ​​the top surface is smaller than that of the bottom surface. The inclined side surface of the SiO2 pattern layer 20 is more conducive to reducing dislocation.

[0052] Step S4: Figure 3As shown, the sapphire substrate 10 is etched to form a groove 101 using the SiO2 pattern layer 20 as a shield.

[0053] In some embodiments, during the etching process of the sapphire substrate 10, the photoresist is retained on the SiO2 pattern layer 20 and is not removed. The sapphire substrate 10 is etched downward. The portion of the sapphire substrate 10 that is not covered / shielded by the photoresist and the SiO2 pattern layer 20 will be etched, causing the surface of the sapphire substrate 10 on which the SiO2 pattern layer 20 is set to be recessed downward to form a groove 101 of a certain depth. When the etching depth of the sapphire substrate 10 reaches the required depth, the etching is stopped and the photoresist is removed. Therefore, in the end, except for the area covered by the SiO2 pattern layer 20, the other areas of the surface of the sapphire substrate 10 are all formed into grooves 101. The sidewalls of the groove 101 are not perpendicular to the surface of the sapphire substrate 10 on which the SiO2 pattern layer 20 is set, but are inclined relative to the surface of the sapphire substrate 10 on which the SiO2 pattern layer 20 is set. The structure of the groove 101 can further reduce the dislocation density and improve the internal quantum efficiency.

[0054] Etching step S4 can also be performed using a wet etching method. The etching solution used can be the same as the etching solution used in step S3, containing hydrofluoric acid. That is, etching the SiO2 layer in step S3 and etching the sapphire substrate 10 in step S4 can be performed in the same wet etching process, with the SiO2 layer being etched first and then the sapphire substrate 10. The thickness of the SiO2 pattern layer 20 is 25-35 nm, for example, 25 nm, 27 nm, 30 nm, 32 nm, or 35 nm.

[0055] Step S5: Figure 3 As shown, a GaN buffer layer 30 is formed on the side of the sapphire substrate 10 having the SiO 2 pattern layer 20 .

[0056] In some embodiments, a GaN buffer layer 30 is formed by vapor deposition on the side of the sapphire substrate 10 having the SiO2 patterned layer 20. The thickness of the deposited GaN buffer layer 30 must ensure that it completely fills the groove 101 of the sapphire substrate 10 and completely covers the SiO2 patterned layer 20. In other words, the thickness of the GaN buffer layer 30 is greater than the thickness of the SiO2 patterned layer 20. The thickness of the GaN buffer layer 30 is 70-120 nm, for example, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, or 120 nm.

[0057] Step S6: electrochemically etching the GaN buffer layer 30 to form a porous structure in the GaN buffer layer 30 .

[0058] In some embodiments, the porous GaN buffer layer 30 has a porosity of 20%-40%, for example, 20%, 23%, 25%, 30%, 32%, 35%, 37%, or 40%. The diameter of the micropores in the porous GaN buffer layer 30 can range from a few nanometers to more than ten nanometers. The porous morphology of the GaN buffer layer 30 can effectively reduce the refractive index of the film.

[0059] The porous GaN buffer layer 30 can release the thermal stress generated by dislocations and improve the internal quantum efficiency. Secondly, the pores in the GaN buffer layer 30 can absorb multi-quantum well In atoms without expanding the crystal structure, thereby avoiding strain and defects in the InGaN-based LED epitaxial layer caused by In segregation, and realizing InGaN-based LEDs with a high In concentration.

[0060] In some embodiments, electrochemical etching utilizes a two-electrode system, with the sapphire substrate 10 and the SiO2 patterned layer 20 and GaN buffer layer 30 formed thereon serving as the anode (working electrode). An inert electrode (such as a platinum mesh or graphite) serves as the cathode. A voltage is applied to the anode, and an alkaline solution (such as potassium hydroxide or sodium hydroxide) is used as the electrolyte to dissolve the surface of the GaN buffer layer 30, forming a porous structure. Ethanol or a surfactant may optionally be added to the electrolyte to enhance its permeability, reduce bubble adhesion, and improve the uniformity of the pore structure. The principle of electrochemical etching is that GaN is oxidized and dissolved in the electrolyte to form soluble gallium salts, thereby creating pores. GaN reacts with hydroxide to form soluble gallium salts and release gas.

[0061] Step S7 : sequentially forming an N-type GaN layer 40 , a multi-quantum well layer 50 and a P-type GaN layer 60 on the GaN buffer layer 30 .

[0062] Step S7 includes: forming an N-type GaN layer 40 on the surface of the GaN buffer layer 30 facing away from the sapphire substrate 10 by vapor deposition, forming a multi-quantum well layer 50 on the surface of the N-type GaN layer 40 facing away from the sapphire substrate 10, and forming a P-type GaN layer 60 on the surface of the multi-quantum well layer 50 facing away from the sapphire substrate 10.

[0063] The N-type GaN layer 40 can be a GaN layer doped with silicon (Si) or germanium (Ge), providing electrons (majority carriers) for injection into the multi-quantum well layer 50. The P-type GaN layer 60 can be a GaN layer doped with magnesium (Mg), providing holes for injection into the multi-quantum well layer 50. It also serves as a top contact layer, forming an ohmic contact with the electrodes subsequently formed thereon. The multi-quantum well layer 50 is the region where electrons and holes recombine to emit light (the active light-emitting region). The wavelength of the light emitted is determined by the band gap of the quantum wells. The multi-quantum well layer 50 can be a periodic structure composed of alternating thin layers of GaN and InGaN (or other ternary compounds). The emission wavelength can be controlled by adjusting the indium content in the InGaN. When a forward bias is applied, electrons are injected from the N-type GaN and holes from the P-type GaN into the multi-quantum well layer 50. The electrons and holes recombine in the wells of the multi-quantum well layer 50, releasing photons and thus generating light.

[0064] The method for preparing a semiconductor light-emitting device further includes forming a transparent conductive layer 70, a first electrode 80, and a second electrode 90. The transparent conductive layer 70 is located on the side of the P-type GaN layer 60 facing away from the sapphire substrate 10. The first electrode 80 is located on the side of the transparent conductive layer 70 facing away from the sapphire substrate 10. The second electrode 90 is located on the N-type GaN layer 40 and is not directly opposite the multi-quantum well layer 50 and the P-type GaN layer 60.

[0065] like Figure 4 As shown, an embodiment of the present application further provides a semiconductor light-emitting device 100, comprising a sapphire substrate 10, a porous SiO2 patterned layer, and a porous GaN buffer layer 30. The SiO2 patterned layer 20 is located on the surface of the sapphire substrate 10 and partially covers the sapphire substrate 10. The GaN buffer layer 30 is located on the side of the sapphire substrate 10 having the SiO2 patterned layer 20. The GaN buffer layer 30 completely covers the SiO2 patterned layer.

[0066] The semiconductor light emitting device further includes an N-type GaN layer 40, a multi-quantum well layer 50, and a P-type GaN layer 60 stacked sequentially on the GaN buffer layer 30 from bottom to top. The area of ​​the sapphire substrate 10 not covered by the SiO2 pattern layer is formed into a groove 101, and the GaN buffer layer 30 fills the groove 101.

[0067] The preparation method of the semiconductor light-emitting device 100 of the embodiment of the present application forms a nano-scale SiO2 pattern layer structure on a sapphire substrate 10. The low refractive index and rough surface of the SiO2 pattern layer can improve the light extraction efficiency, and the feature of not easily nucleating can reduce the dislocation density and improve the internal quantum efficiency; a porous GaN buffer layer 30 is formed on the SiO2 pattern layer. The porous GaN buffer layer 30 can release the thermal stress generated by the dislocation and improve the internal quantum efficiency. The refractive index of the porous GaN buffer layer 30 is relatively low, and the light extraction efficiency can also be improved. The voids in the porous GaN buffer layer 30 can absorb multi-quantum well In atoms without expanding the crystal structure, so that the strain and defects of the epitaxial layer of the red InGaN light-emitting diode caused by In segregation will not occur, and an InGaN light-emitting diode with a high In concentration content will be realized.

[0068] It should be noted that the above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application; the embodiments of the present application and the features of the embodiments can be combined with each other unless there is a conflict. Therefore, the scope of protection of the present application shall be based on the scope of protection of the claims.

Claims

1. A semiconductor light emitting device, characterized in that: include: Sapphire substrate; a porous SiO2 patterned layer, located on one surface of the sapphire substrate and partially covering the sapphire substrate; a porous GaN buffer layer, located on a side of the sapphire substrate having the SiO2 pattern layer, wherein the GaN buffer layer completely covers the SiO2 pattern layer; An N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially stacked on the GaN buffer layer from bottom to top.

2. The semiconductor light emitting device according to claim 1, wherein: A groove is formed in an area of ​​the sapphire substrate not covered by the SiO2 pattern layer, and the GaN buffer layer fills the groove.

3. The semiconductor light emitting device according to claim 2, wherein: The groove has a side wall, and the side wall is obliquely connected to the surface of the sapphire substrate where the SiO2 pattern layer is provided.

4. The semiconductor light emitting device according to claim 1, wherein: The SiO2 pattern layer includes a top surface facing away from the sapphire substrate, a bottom surface opposite to the top surface, and a side surface connected between the top surface and the bottom surface. The side surface is obliquely connected to the bottom surface, and an area of ​​the top surface is smaller than an area of ​​the bottom surface.

5. The semiconductor light emitting device according to claim 1, wherein: The thickness of the SiO2 pattern layer is 25-35 nm; The thickness of the GaN buffer layer is 70-120 nm.

6. A method for preparing a semiconductor light-emitting device, characterized in that: include: Providing sapphire substrates; forming a silicon-containing precursor layer on one surface of the sapphire substrate, and sintering the silicon-containing precursor layer to form a porous SiO2 layer; Partially etching the SiO2 layer to transform the SiO2 layer into a SiO2 pattern layer; forming a GaN buffer layer on a side of the sapphire substrate having the SiO2 pattern layer, wherein the GaN buffer layer completely covers the SiO2 pattern layer; Electrochemically etching the GaN buffer layer to form the GaN buffer layer into a porous structure; and An N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially formed on the GaN buffer layer.

7. The method for preparing a semiconductor light-emitting device according to claim 6, wherein: The forming of the porous SiO2 layer comprises: providing a sol containing a silicon precursor; applying the sol to a surface of the sapphire substrate to form a wet film; The wet film is dried and sintered in sequence to form a porous SiO2 layer.

8. The method for preparing a semiconductor light-emitting device according to claim 6, wherein: Forming the SiO2 pattern layer includes: forming a photoresist layer on a surface of the SiO2 layer facing away from the sapphire substrate; performing nanoimprint lithography on the photoresist layer to form a patterned photoresist layer; The SiO2 layer is etched using the patterned photoresist layer as a shield to form a SiO2 pattern layer.

9. The method for preparing a semiconductor light-emitting device according to claim 8, wherein: The SiO2 layer is etched by wet etching, and the etching solution used in the wet etching contains hydrofluoric acid.

10. The method for preparing a semiconductor light emitting device according to claim 6, wherein: The preparation method further includes: etching the sapphire substrate to form grooves after forming the SiO2 pattern layer and before forming the GaN buffer layer.

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