Semiconductor structure and preparation process thereof, and light-emitting array and preparation process thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation process thereof, and a light-emitting array and a preparation process thereof, a mask layer of the semiconductor structure is set as a metal mask layer, and a light-emitting unit can be grown in an opening enclosed by the metal mask layer during selective area epitaxy. The metal mask layer has good light reflection performance and can serve as a reflection layer, so that light emitted by the light-emitting units is reflected out by the metal mask layer, the light-emitting efficiency is improved, and light crosstalk of the light-emitting units in the adjacent openings is prevented. Therefore, no extra reflecting layer needs to be prepared, the preparation process is simplified, and the production efficiency is improved. In addition, the heat dissipation performance of the metal mask layer is good, and the situation that the luminous efficiency is reduced or the service life is shortened due to heat accumulation when the luminous unit emits light can be prevented. Moreover, the light-emitting unit does not need to be etched when the light-emitting unit is formed through the selected area epitaxy technology, and it is guaranteed that the light-emitting efficiency of the light-emitting unit is high.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor optoelectronic devices, and in particular to a semiconductor structure and a preparation process thereof, and a light-emitting array and a preparation process thereof. Background Art

[0002] Micro-LEDs, known as the next generation of display devices, have developed rapidly in recent years due to their advantages such as high responsiveness, high brightness, high contrast, ultra-high resolution, and low power consumption.

[0003] Selective Area Epitaxy (SAE) is a semiconductor manufacturing technique that achieves precise control over material growth by selectively growing thin crystal films in specific areas. The core steps involve depositing a mask layer (such as silicon dioxide or silicon nitride) on a substrate and defining the areas where epitaxial growth is desired through photolithography and etching techniques. Subsequently, under high temperature and a specific gas environment, the epitaxial material grows only in the exposed substrate areas, forming a high-quality crystalline structure.

[0004] However, there are many problems in using selective area epitaxy to prepare micro-sized light-emitting diodes, such as low luminous efficiency, poor heat dissipation performance, and the inability to control the direction and focus of the emitted light. Summary of the Invention

[0005] The present invention provides a semiconductor structure and a light emitting array to solve at least one problem in preparing micro-sized light emitting diodes by selective epitaxy.

[0006] According to one aspect of the present invention, there is provided a semiconductor structure comprising:

[0007] substrate;

[0008] A metal mask layer, wherein the metal mask layer encloses and forms a plurality of openings, wherein the bottoms of the openings expose the upper surface of the substrate; the openings are used to arrange the light-emitting units; and the metal mask layer includes metal sidewalls facing the openings;

[0009] The passivation layer is disposed on the metal sidewall.

[0010] Optionally, the angle between the metal sidewall and the upper surface of the substrate at a set position is less than or equal to 90 degrees; the set position is a position on the upper surface of the substrate corresponding to the bottom surface of the metal mask layer connected to the metal sidewall.

[0011] Optionally, at each height position of the metal mask layer, along the horizontal direction, the thickness of the metal mask layer is greater than the thickness of the passivation layer.

[0012] Optionally, the semiconductor structure includes a central region and an edge region, and the edge region surrounds the central region;

[0013] The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region;

[0014] At the opening in the central area, the first metal sidewall is closer to the edge area than the second metal sidewall; at the opening in the edge area, the first metal sidewall is farther away from the central area than the second metal sidewall;

[0015] The angle between the first metal side wall and the upper surface of the substrate at a set position is a first angle;

[0016] The first angle corresponding to the first metal sidewall at the opening in the central region is greater than the first angle corresponding to the first metal sidewall at the opening in the edge region.

[0017] Optionally, at least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall;

[0018] The first angle corresponding to the first metal sidewall at the opening in the transition region is between the first angle corresponding to the first metal sidewall at the opening in the central region and the first angle corresponding to the first metal sidewall at the opening in the edge region.

[0019] Optionally, from the center line of the central area to the side of the semiconductor structure, the first angle corresponding to the first metal sidewall at each opening gradually decreases.

[0020] Optionally, the semiconductor structure includes a central region and an edge region, and the edge region surrounds the central region;

[0021] The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region;

[0022] At the opening in the central area, the first metal sidewall is closer to the edge area than the second metal sidewall; at the opening in the edge area, the first metal sidewall is farther away from the central area than the second metal sidewall;

[0023] The angle between the second metal side wall and the upper surface of the substrate at a set position is a second angle;

[0024] The second angle corresponding to the second metal sidewall at the opening in the central region is smaller than the second angle corresponding to the second metal sidewall at the opening in the edge region.

[0025] Optionally, at least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall;

[0026] The second angle corresponding to the second metal sidewall at the opening in the transition region is between the second angle corresponding to the second metal sidewall at the opening in the central region and the second angle corresponding to the second metal sidewall at the opening in the edge region.

[0027] Optionally, from the center line of the central area to the side of the semiconductor structure, the second angle corresponding to the second metal sidewall at each opening gradually increases.

[0028] Optionally, at the opening located on the center line of the semiconductor structure, an angle between the metal sidewall and a set position on the upper surface of the substrate is equal to 90 degrees.

[0029] According to another aspect of the present invention, there is provided a light emitting array comprising light emitting units arranged in an array, with an isolation layer provided between the light emitting units;

[0030] The isolation layer includes a metal mask layer and a passivation layer. The metal mask layer encloses a plurality of openings, and the light-emitting unit is located in the opening. The light-emitting unit includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked from the upper surface of the substrate; the metal mask layer includes a metal side wall facing the opening, and the passivation layer is arranged on the metal side wall. The light-emitting unit is in contact with the side wall and the passivation layer.

[0031] Optionally, the light emitting array includes a central area and an edge area, and the edge area surrounds the central area;

[0032] The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region;

[0033] At the opening in the central area, the first metal sidewall is closer to the edge area than the second metal sidewall; at the opening in the edge area, the first metal sidewall is farther away from the central area than the second metal sidewall;

[0034] The included angle between the first metal sidewall and the bottom surface of the metal mask layer is a third included angle;

[0035] The third angle corresponding to the first metal sidewall at the opening in the central region is greater than the third angle corresponding to the first metal sidewall at the opening in the edge region.

[0036] Optionally, at least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall;

[0037] The third angle corresponding to the first metal sidewall at the opening in the transition region is between the third angle corresponding to the first metal sidewall at the opening in the central region and the third angle corresponding to the first metal sidewall at the opening in the edge region.

[0038] Optionally, from the center line of the central area to the side of the light-emitting array, the third angle corresponding to the first metal sidewall at each opening gradually decreases.

[0039] Optionally, the light emitting array includes a central area and an edge area, and the edge area surrounds the central area;

[0040] The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region;

[0041] At the opening in the central area, the first metal sidewall is closer to the edge area than the second metal sidewall; at the opening in the edge area, the first metal sidewall is farther away from the central area than the second metal sidewall;

[0042] The included angle between the second metal sidewall and the bottom surface of the metal mask layer is a fourth included angle;

[0043] The fourth angle corresponding to the second metal sidewall at the opening in the central region is smaller than the fourth angle corresponding to the second metal sidewall at the opening in the edge region.

[0044] Optionally, at least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall;

[0045] The fourth angle corresponding to the second metal sidewall at the opening in the transition region is between the fourth angle corresponding to the second metal sidewall at the opening in the central region and the fourth angle corresponding to the second metal sidewall at the opening in the edge region.

[0046] Optionally, from the center line of the central area to the side of the light-emitting array, the fourth angle corresponding to the second metal sidewall at each opening gradually increases.

[0047] According to another aspect of the present invention, a light-emitting array is provided, comprising a central region and an edge region, wherein the edge region surrounds the central region; the light-emitting array comprises a bottom portion, wherein the bottom portion comprises a first surface facing the light-emitting array and a second surface facing away from the light-emitting array, wherein the first surface and / or the second surface are inclined from the edge region to the central region of the light-emitting array.

[0048] Optionally, the light-emitting array further includes a connection layer, and the light-emitting units are arranged on the connection layer; the connection layer is arranged obliquely from the side of the light-emitting array to the center line of the central area.

[0049] Optionally, the connecting layer includes a reflective layer.

[0050] According to another aspect of the present invention, a process for preparing a semiconductor structure is provided, comprising:

[0051] A substrate is provided; a metal layer is formed on one side of the substrate; the metal layer is patterned to form a plurality of openings and a metal mask layer, wherein the metal mask layer encloses the plurality of openings, and the bottom of the openings exposes the upper surface of the substrate; the metal mask layer includes metal sidewalls facing the openings; and a passivation layer is formed on the metal sidewalls.

[0052] According to another aspect of the present invention, a process for preparing a light-emitting array is provided, comprising:

[0053] A light-emitting unit is formed in the opening of the semiconductor structure. The light-emitting unit includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked on the upper surface of the substrate. The semiconductor structure is any embodiment of the present invention.

[0054] The semiconductor structure and its preparation process, and the light-emitting array and its preparation process of the embodiments of the present invention, by setting the mask layer of the semiconductor structure as a metal mask layer, can grow light-emitting units in the openings enclosed by the metal mask layer during selective epitaxy. The metal mask layer has good light reflection performance and can itself serve as a reflective layer, so that the light emitted by the light-emitting unit is reflected by the metal mask layer, which is beneficial to improving the luminous efficiency and preventing light crosstalk between light-emitting units in adjacent openings. In this way, there is no need to prepare an additional reflective layer, simplifying the preparation process and improving production efficiency. In addition, the metal mask layer has good heat dissipation performance, which can prevent heat accumulation when the light-emitting unit emits light, causing a decrease in luminous efficiency or a shortened service life. Moreover, through the selective epitaxy technology, when forming the light-emitting unit, there is no need to etch the light-emitting unit, ensuring that the light-emitting unit has a high luminous efficiency.

[0055] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 is a top view of a semiconductor structure provided by an embodiment of the present invention;

[0058] Figure 2 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention;

[0059] Figure 3 is a structural schematic diagram of a light emitting array provided by an embodiment of the present invention;

[0060] Figure 4 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0061] Figure 5 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0062] Figure 6 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0063] Figure 7 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0064] Figure 8 is a schematic structural diagram of another light emitting array provided by an embodiment of the present invention;

[0065] Figure 9 is a schematic structural diagram of another light emitting array provided by an embodiment of the present invention;

[0066] Figure 10 is a schematic structural diagram of another light emitting array provided by an embodiment of the present invention;

[0067] Figure 11 This is a flow chart of a process for preparing a semiconductor structure provided by an embodiment of the present invention;

[0068] Figure 12 is a structural diagram of the substrate;

[0069] Figure 13 It is a schematic diagram of the structure after a metal layer is formed on one side of the substrate;

[0070] Figure 14 is a schematic diagram of the structure after the metal mask layer is formed;

[0071] Figure 15 Schematic diagram of the process of forming a passivation layer. DETAILED DESCRIPTION

[0072] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0073] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0074] An embodiment of the present invention provides a semiconductor structure. Figure 1 is a top view of a semiconductor structure provided by an embodiment of the present invention, Figure 2 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present invention, Figure 2 Can correspond Figure 1 Cut along AA', reference Figure 1 and Figure 2 The semiconductor structure includes: a substrate 100; a metal mask layer 200, the metal mask layer 200 encloses a plurality of openings 300, the bottom of the opening 300 exposes the upper surface of the substrate 100; the opening 300 is used to set the light-emitting unit; the metal mask layer 200 includes a metal sidewall 210 facing the opening 300; and a passivation layer 400 is provided on the metal sidewall 210. Figure 1 The metal mask layer 200 and the passivation layer 400 are shown in FIG. Figure 1 The substrate is not shown.

[0075] The substrate 100 includes a substrate 110, the material of which can be at least one of sapphire, silicon, silicon carbide, or gallium arsenide. In some embodiments, the substrate 100 further includes a transition layer 120, which is located on one side of the substrate 110. The transition layer 120 can be at least one of a low-temperature gallium nitride layer, an AlN layer, an AlGaN layer, an undoped gallium nitride layer, or an N-type doped gallium nitride layer. When the substrate 100 includes only the substrate 110, the metal mask layer 200 is disposed on the substrate 110. The upper surface of the substrate 100 refers to the surface of the substrate 110 facing the metal mask layer 200. When the substrate 100 includes both the substrate 110 and the transition layer 120, the metal mask layer 200 is disposed on the transition layer 120. Accordingly, the upper surface of the substrate 100 refers to the surface of the transition layer 120 facing the metal mask layer 200.

[0076] Figure 3 1 is a schematic structural diagram of a light emitting array provided by an embodiment of the present invention. The light emitting array can be obtained by forming light emitting units 500 in openings 300 enclosed by a metal mask layer 200 in a semiconductor structure according to an embodiment of the present invention. Figure 3 The light-emitting array includes a plurality of light-emitting units 500, which are arranged in the opening 300 of the semiconductor structure, and the sidewalls of the light-emitting units 500 are in contact with the passivation layer 400; the light-emitting units 500 include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked on the upper surface of the substrate 100.

[0077] The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer; or the first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer. The P-type semiconductor layer may, for example, include P-type GaN, and the N-type semiconductor layer may, for example, include N-type GaN. In other optional embodiments of the present invention, the P-type semiconductor layer may include other P-type semiconductor materials, and the N-type semiconductor layer may include other N-type semiconductor materials. The light-emitting layer may be a quantum well layer, and may optionally be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.

[0078] The light-emitting unit 500 is selectively epitaxially grown in the opening 300 of the metal mask layer 200 . The bottom of the light-emitting unit 500 can contact the upper surface of the substrate 100 , the sidewall of the light-emitting unit 500 contacts the passivation layer 400 , and the light-emitting unit 500 does not contact the metal mask layer 200 .

[0079] In some related technologies, an epitaxial layer is formed on the substrate 110 by non-selective epitaxy technology, and then the light-emitting unit 500 is formed by an etching process. A passivation layer 400 and a metal layer are sequentially formed on the sidewalls of the light-emitting unit 500. The passivation layer 400 plays an insulating role, and the metal layer plays a reflective role. Forming the light-emitting unit 500 by an etching process will cause damage to the sidewalls, affecting the luminous efficiency of the light-emitting unit 500, and the heat dissipation performance is also difficult to meet the requirements. In other related technologies, the light-emitting unit 500 is formed by selective epitaxy. When performing selective epitaxy, an insulating material such as silicon dioxide or silicon nitride is usually used as a mask layer, and the light-emitting unit 500 is selectively grown in the opening 300 of the mask layer. Materials such as silicon dioxide or silicon nitride have poor reflective properties, so that the light emitted by the light-emitting unit 500 cannot be effectively reflected after entering the mask layer, and the light-emitting efficiency of the light-emitting unit 500 is low. If a metal reflective layer is prepared on the sidewalls of the mask layer, the luminous efficiency can be improved. However, if a metal reflective layer is prepared, an insulating layer must also be prepared to insulate the metal reflective layer from the light-emitting unit 500, making the preparation process complicated. Furthermore, materials such as silicon dioxide and silicon nitride have poor heat dissipation properties and are prone to heat generation during use, affecting the luminous efficiency and service life of the light-emitting unit 500.

[0080] refer to Figure 1-Figure 3 Unlike related art, in the embodiments of the present invention, the mask layer provided for the semiconductor structure is a metal mask layer 200. The metal mask layer 200 is made of a metal, specifically at least one of copper, nickel, gold, silver, chromium, platinum, tin, titanium, iron, or tungsten. The metal mask layer 200 encloses a plurality of openings 300, the bottoms of which expose the upper surface of the substrate 100. During selective area epitaxy, light-emitting units 500 can be grown within the openings 300 enclosed by the metal mask layer 200. The metal mask layer 200 has excellent light reflectivity and can serve as a reflective layer, reflecting light emitted by the light-emitting units 500. This improves luminous efficiency and prevents crosstalk between light-emitting units 500 in adjacent openings 300. This effectively reuses the metal mask layer 200 as a reflective layer, eliminating the need for a separate reflective layer, simplifying the manufacturing process, and improving production efficiency. Furthermore, the excellent heat dissipation properties of metal materials prevent heat accumulation within the light-emitting units 500, which can reduce luminous efficiency or shorten their lifespan. Furthermore, the metal mask layer 200 needs to have a certain thickness in both the horizontal and vertical directions. In this embodiment, the thickness of the metal mask layer 200 in both the horizontal and vertical directions is greater than the thickness of the metal reflective layer in related art. For example, the horizontal thickness is greater than 300 nm, and the vertical thickness is greater than 1000 nm. This further ensures that the metal mask layer 200 can dissipate heat more effectively, so that the heat generated by the light-emitting unit 500 is transferred to the outside through the metal mask layer 200.

[0081] Optionally, the steps of preparing the metal mask layer 200 may include forming an entire metal layer on one side of the substrate 100 , and patterning the entire metal layer, for example, by using an etching process to open a plurality of openings 300 in the metal layer to form the metal mask layer 200 .

[0082] In an embodiment of the present invention, the semiconductor structure further includes a passivation layer 400, which is disposed on the metal sidewall 210. The passivation layer 400 is made of an insulating material. The passivation layer 400 can isolate the light-emitting unit 500 from the metal mask layer 200, ensuring good insulation performance between the light-emitting unit 500 and the metal mask layer 200. In addition, the passivation layer 400 is made of a light-transmitting material to ensure that light emitted by the light-emitting unit 500 can pass through the passivation layer 400 and reach the metal mask layer 200, allowing the metal mask layer 200 to reflect the light emitted by the light-emitting unit 500. Optionally, the passivation layer 400 is a single crystal layer having a wurtzite structure, such as at least one of an aluminum nitride layer, a silicon carbide layer, a silicon oxide layer, or a zinc oxide layer.

[0083] Optionally, the preparation steps of the passivation layer 400 may include, after forming the metal mask layer 200, forming an entire passivation layer 400 on the top surface, side wall and bottom of the opening 300 of the metal mask layer 200, and then removing the passivation layer 400 material on the top surface of the metal mask layer 200 and the bottom of the opening 300 through a graphical process, retaining the passivation layer 400 on the metal side wall 210.

[0084] Among them, the passivation layer 400 is set on the metal side wall 210, and the passivation layer 400 is not set at the bottom of the opening 300 and the top surface of the metal mask layer 200. In this way, on the one hand, the light-emitting unit 500 can grow normally on the surface of the substrate 100, and on the other hand, the light-emitting unit 500 will not be formed on the top surface of the metal mask layer 200, thereby limiting the light-emitting unit 500 to the opening 300 of the metal mask layer 200.

[0085] It should be noted that Figure 1 The top view of the semiconductor structure is rectangular as an example. In other optional embodiments of the present invention, the top view of the semiconductor structure may be circular, elliptical or other shapes to accommodate display devices of different shapes.

[0086] The semiconductor structure of this embodiment, by setting the mask layer of the semiconductor structure as a metal mask layer, can grow light-emitting units in the openings enclosed by the metal mask layer during selective epitaxy. The metal mask layer has good light reflection performance and can itself serve as a reflective layer, so that the light emitted by the light-emitting unit is reflected by the metal mask layer, which is beneficial to improving the luminous efficiency and preventing light crosstalk between light-emitting units in adjacent openings. In this way, there is no need to prepare an additional reflective layer, which simplifies the preparation process and improves production efficiency. In addition, the metal mask layer has good heat dissipation performance, which can prevent heat accumulation when the light-emitting unit emits light, causing a decrease in luminous efficiency or a shortened service life. Moreover, through the selective epitaxy technology, when forming the light-emitting unit, there is no need to etch the light-emitting unit, ensuring that the light-emitting unit has a high luminous efficiency.

[0087] Continue to refer Figure 2 and Figure 3 Optionally, at each height position of the metal mask layer 200 , along the horizontal direction x, the thickness of the metal mask layer 200 is greater than the thickness of the passivation layer 400 .

[0088] The horizontal direction x is perpendicular to the thickness direction y of the semiconductor structure. By setting the thickness of the metal mask layer 200 at each height position along the horizontal direction x to be greater than the thickness of the passivation layer 400, this ensures that the metal mask layer 200 has a greater thickness, ensuring good heat dissipation performance of the metal mask layer 200. Furthermore, by ensuring that the passivation layer 400 has a smaller thickness, the passivation layer 400 has less impact on light propagation between the light-emitting unit and the metal mask layer 200, thereby improving luminous efficiency.

[0089] refer to Figure 2 and Figure 3 Optionally, the angle c between the metal side wall 210 and the upper surface of the substrate 100 at the set position M1 is less than or equal to 90 degrees; the set position M1 is the position on the upper surface of the substrate 100 corresponding to the bottom surface B1 of the metal mask layer 200 connected to the metal side wall 210.

[0090] Among them, the position on the upper surface of the substrate 100 corresponding to the bottom surface B1 of the metal mask layer 200 connected to the metal sidewall 210 can refer to the positive projection position of the bottom surface B1 of the metal mask layer 200 connected to the metal sidewall 210 on the upper surface of the substrate 100.

[0091] Specifically, the metal mask layer 200 further includes a top surface T1 and a bottom surface B1 that are in contact with the metal sidewall 210. The top surface T1 and the bottom surface B1 of the metal layer are disposed opposite each other, and the bottom surface B1 of the metal mask layer 200 is closer to the upper surface of the substrate 100 relative to the top surface T1. In some embodiments, the bottom surface B1 of the metal mask layer 200 contacts the upper surface of the substrate 100. In other embodiments, other structures are disposed between the bottom surface B1 of the metal mask layer 200 and the upper surface of the substrate 100, which are not specifically limited in this embodiment of the present invention. When the bottom surface B1 of the metal mask layer 200 contacts the upper surface of the substrate 100, the angle c between the metal sidewall 210 and the upper surface of the substrate 100 at a predetermined position is equal to the angle between the metal sidewall 210 and the bottom surface B1 of the metal mask layer 200.

[0092] In some embodiments, the angle c between the metal side wall 210 and the upper surface of the substrate 100 at a set position is less than 90 degrees, that is, the metal side wall 210 is set at an angle, the bottom area of ​​the opening 300 is smaller than the top area, and is conical, forming a mask structure. The light emitted by the light-emitting unit propagates upward and is reflected by the metal side wall 210, thereby increasing the light intensity and improving the luminous efficiency.

[0093] Figure 4 is a schematic diagram of another semiconductor structure provided by an embodiment of the present invention, with reference to Figure 4 Optionally, the semiconductor structure includes a central region F1 and an edge region F2, and the edge region F2 surrounds the central region F1; the central region F1 and the edge region F2 each include a plurality of openings 300; along a first direction, the metal sidewalls 210 on both sides of the opening 300 are respectively a first metal sidewall 211 and a second metal sidewall 212, and the first direction is the direction from the edge region F2 to the central region F1; for example, for Figure 4 The semiconductor structure shown, wherein the first direction is from left to right for the left-half conductor structure, and from right to left for the right-half semiconductor structure. At the opening 300 in the center region F1, the first metal sidewall 211 is closer to the edge region F2 relative to the second metal sidewall 212; at the opening 300 in the edge region F2, the first metal sidewall 211 is farther away from the center region F1 relative to the second metal sidewall 212; the angle between the first metal sidewall 211 and the upper surface of the substrate 100 at a predetermined position M1 is a first angle c1; the first angle c1 corresponding to the first metal sidewall 211 at the opening 300 in the center region F1 is greater than the first angle c1 corresponding to the first metal sidewall 211 at the opening 300 in the edge region F2.

[0094] As described in the above embodiment, the position M1 is set to be a position on the upper surface of the substrate 100 corresponding to the bottom surface B1 of the metal mask layer 200 that is in contact with the metal sidewall 210 .

[0095] After light-emitting units are formed in the multiple openings 300 of the metal mask layer 200 by selective epitaxy technology, the multiple light-emitting units form a light-emitting array, which includes a central area (corresponding to the central area F1 of the semiconductor structure) and an edge area surrounding the central area F1 (corresponding to the edge area F2 of the semiconductor structure). When the light-emitting array is used in the near-eye display field (such as AR and VR products), there is a light receiving area located in the light-emitting direction, and the center line of the light-receiving area coincides with or is close to the center line L1 of the central area F1 of the light-emitting array. At this time, the light emitted by each light-emitting unit of the light-emitting array needs to be directed toward the light receiving area to achieve a better display effect.

[0096] In this embodiment, the first metal sidewall 211 can be a flat surface or a curved surface. When the first metal sidewall 211 is a flat surface, the first angle c1 is the angle between the plane of the first metal sidewall 211 and the upper surface of the substrate 100 at the predetermined position M1. When the first metal sidewall 211 is a curved surface, the first angle c1 is the angle between the tangent plane of the curved surface and the upper surface of the substrate 100 at the predetermined position M1.

[0097] Figure 4 FIG shows the reflection paths of the incident light incident on the first metal sidewall 211 of the metal mask layer 200 along the same incident direction at the openings 300 in the central region F1 and the edge region F2, respectively. Figure 4 As can be seen from the reflection path, the incident angle d1 corresponding to the incident light in the edge region F2 is greater than the incident angle d1 corresponding to the incident light in the center region F1. Correspondingly, the reflection angle corresponding to the reflected light in the edge region F2 is greater than the reflection angle corresponding to the reflected light in the center region F1. In this way, the light emitted by the light-emitting units in the edge region F2 can also enter the light receiving area. In this embodiment, by setting the first angle c1 corresponding to the first metal sidewall 211 at the opening 300 in the center region F1 to be greater than the first angle c1 corresponding to the first metal sidewall 211 at the opening 300 in the edge region F2, the light reflected by the metal mask layer 200 in the center region F1 can reach the light receiving area, and the light reflected by the metal mask layer 200 in the edge region F2 can also reach the light receiving area. This ensures that the light emitted by each light-emitting unit of the light-emitting array is directed to the light receiving area, and further controls the direction of the light emitted by the light-emitting unit, so that the emitted light is focused, achieving a better display effect.

[0098] In some embodiments, the first angles c1 corresponding to the first metal sidewalls 211 at different openings 300 in the central region F1 may be equal, and the first angles c1 corresponding to the first metal sidewalls 211 at different openings 300 in the edge region F2 may be equal. In this way, the process of patterning the metal mask layer 200 will be simpler and easier to implement.

[0099] In other embodiments, the first angles c1 corresponding to the first metal sidewalls 211 at least two openings 300 in the central region F1 are not equal, and the first angles c1 corresponding to the first metal sidewalls 211 at least two openings 300 in the edge region F2 are not equal to achieve better focusing effect.

[0100] The angle between the second metal sidewall 212 and the upper surface of the substrate 100 at the set position M1 is a second angle c2. In some embodiments, the second angles c2 corresponding to the second metal sidewalls 212 at the openings 300 in the central region F1 are all equal, and the second angles c2 corresponding to the second metal sidewalls 212 at the openings 300 in the edge region F2 are all equal. Optionally, the second angles c2 corresponding to the second metal sidewalls 212 at the openings 300 in the central region F1 are equal to the second angles c2 corresponding to the second metal sidewalls 212 at the openings 300 in the edge region F2. By adjusting the first angle c1 at the openings 300 corresponding to the first metal sidewall 211, the light emitted by the light-emitting unit is directed toward the light receiving area.

[0101] Figure 5 is a schematic diagram of another semiconductor structure provided by an embodiment of the present invention, with reference to Figure 5 Optionally, at least one transition region F3 is further included between the edge region F2 and the center region F1. The transition region F3 includes multiple openings 300. At the openings 300 in the transition region F3, the first metal sidewall 211 is closer to the edge region F2 than the second metal sidewall 212. The first angle c1 corresponding to the first metal sidewall 211 at the openings 300 in the transition region F3 is between the first angle c1 corresponding to the first metal sidewall 211 at the openings 300 in the center region F1 and the first angle c1 corresponding to the first metal sidewall 211 at the openings 300 in the edge region F2. This configuration creates a structure in which the first angle c1 gradually decreases from the center region F1 to the edge region F2, further focusing the emitted light and achieving a better display effect.

[0102] The first angles c1 corresponding to the first metal sidewalls 211 at different openings 300 in the transition region F3 may be equal or unequal, which is not specifically limited in this embodiment of the present invention.

[0103] It should be noted that when at least one transition region F3 is included between the edge region F2 and the central region F1, for any transition region F3, in the transition region F3, the first angle c1 corresponding to the first metal side wall 211 at the opening 300 close to the central region F1 is greater than the first angle c1 corresponding to the first metal side wall 211 at the opening 300 away from the central region F1.

[0104] In the case where at least two transition regions F3 are included between the edge region F2 and the central region F1, for any two transition regions F3, the first angle c1 corresponding to the first metal side wall 211 at the opening 300 in the transition region F3 close to the central region F1 is greater than the first angle c1 corresponding to the first metal side wall 211 at the opening 300 in the transition region F3 away from the central region F1.

[0105] In some embodiments, the first angle c1 corresponding to the first metal sidewall 211 at each opening 300 gradually decreases from the center line L1 of the central region F1 to the side edge of the semiconductor structure. The side edge of the semiconductor structure is the edge of the edge region F2 of the semiconductor structure that is farthest from the central region F1. This further forms a structure in which the first angle c1 gradually decreases from the central region F1 to the side edge of the semiconductor structure, further focusing the emitted light and achieving a better display effect. Furthermore, this ensures that the light emitted by the light-emitting units at different openings 300 of the semiconductor structure is more evenly directed to the light receiving area, thereby improving the display effect.

[0106] Figure 6 is a schematic diagram of another semiconductor structure provided by an embodiment of the present invention, with reference to Figure 6 Optionally, the semiconductor structure includes a central region F1 and an edge region F2, and the edge region F2 surrounds the central region F1; the central region F1 and the edge region F2 each include a plurality of openings 300; along a first direction, the metal sidewalls 210 on both sides of the opening 300 are respectively a first metal sidewall 211 and a second metal sidewall 212, and the first direction is the direction from the edge region F2 to the central region F1; at the opening 300 in the central region F1, the first metal sidewall 211 is close to the edge region F2 relative to the second metal sidewall 212; at the opening 300 in the edge region F2, the first metal sidewall 211 is away from the central region F1 relative to the second metal sidewall 212; the angle between the second metal sidewall 212 and the upper surface set position M1 of the substrate 100 is a second angle c2; the second angle c2 corresponding to the second metal sidewall 212 at the opening 300 in the central region F1 is smaller than the second angle c2 corresponding to the second metal sidewall 212 at the opening 300 in the edge region F2.

[0107] In this embodiment, the second metal sidewall 212 can be a flat surface or a curved surface. When the second metal sidewall 212 is a flat surface, the second angle c2 is the angle between the plane of the second metal sidewall 212 and the upper surface of the substrate 100 at the predetermined position M1. When the second metal sidewall 212 is a curved surface, the second angle c2 is the angle between the tangent plane of the curved surface and the upper surface of the substrate 100 at the predetermined position M1.

[0108] Figure 6FIG shows the reflection paths of the incident light incident on the second metal sidewall 212 of the metal mask layer 200 along the same incident direction at the openings 300 in the central region F1 and the edge region F2, respectively. Figure 6 As can be seen from the reflection path, the incident angle d2 corresponding to the incident light in the edge region F2 is smaller than the incident angle d2 corresponding to the incident light in the center region F1. Correspondingly, the reflection angle corresponding to the reflected light in the edge region F2 is smaller than the reflection angle corresponding to the reflected light in the center region F1. This allows light emitted by the light-emitting units in the edge region F2 to also enter the light-receiving area. In this embodiment, by setting the second angle c2 corresponding to the second metal sidewall 212 at the opening 300 in the center region F1 to be smaller than the second angle c2 corresponding to the second metal sidewall 212 at the opening 300 in the edge region F2, light reflected by the metal mask layer 200 in the center region F1 can reach the light-receiving area, and light reflected by the metal mask layer 200 in the edge region F2 can also reach the light-receiving area. This ensures that light emitted by each light-emitting unit in the light-emitting array is directed toward the light-receiving area, thereby controlling the direction of light emitted by the light-emitting unit, focusing the emitted light, and achieving a better display effect.

[0109] In some embodiments, the second angles c2 corresponding to the second metal sidewalls 212 at different openings 300 in the central region F1 can be equal, and the second angles c2 corresponding to the second metal sidewalls 212 at different openings 300 in the edge region F2 can be equal. In this way, the process of patterning the metal mask layer 200 will be simpler and easier to implement.

[0110] In other embodiments, the first angles c1 corresponding to the second metal sidewalls 212 at least two openings 300 in the central region F1 are not equal, and the second angles c2 corresponding to the second metal sidewalls 212 at least two openings 300 in the edge region F2 are not equal to achieve better focusing effect.

[0111] The angle between the first metal sidewall 211 and the upper surface of the substrate 100 at the set position M1 is a first angle c1. In some embodiments, the first angles c1 corresponding to the first metal sidewalls 211 at the openings 300 in the central region F1 are all equal, and the first angles c1 corresponding to the first metal sidewalls 211 at the openings 300 in the edge region F2 are all equal. Optionally, the first angles c1 corresponding to the first metal sidewalls 211 at the openings 300 in the central region F1 are equal to the first angles c1 corresponding to the first metal sidewalls 211 at the openings 300 in the edge region F2. By adjusting the second angle c2 at the openings 300 corresponding to the second metal sidewalls 212, the light emitted by the light-emitting unit is directed toward the light receiving area.

[0112] In other embodiments, the first angle c1 corresponding to the first metal side wall 211 at the opening 300 in the central area F1 is greater than the first angle c1 corresponding to the first metal side wall 211 at the opening 300 in the edge area F2, and the second angle c2 corresponding to the second metal side wall 212 at the opening 300 in the central area F1 is smaller than the second angle c2 corresponding to the second metal side wall 212 at the opening 300 in the edge area F2, so as to further ensure that the light emitted by the light-emitting unit can reach the light receiving area.

[0113] Figure 7 is a schematic diagram of another semiconductor structure provided by an embodiment of the present invention, with reference to Figure 7 Optionally, at least one transition region F3 is further included between the edge region F2 and the center region F1. The transition region F3 includes multiple openings 300. At the openings 300 in the transition region F3, the first metal sidewall 211 is closer to the edge region F2 than the second metal sidewall 212. The second angle c2 corresponding to the second metal sidewall 212 at the openings 300 in the transition region F3 is between the second angle c2 corresponding to the second metal sidewall 212 at the openings 300 in the center region F1 and the second angle c2 corresponding to the second metal sidewall 212 at the openings 300 in the edge region F2. This configuration creates a structure in which the second angle c2 gradually increases from the center region F1 to the edge region F2, further focusing the emitted light and achieving a better display effect.

[0114] The second angles c2 corresponding to the second metal sidewalls 212 at different openings 300 in the transition region F3 may be equal or unequal, which is not specifically limited in this embodiment of the present invention.

[0115] It should be noted that when at least one transition region F3 is included between the edge region F2 and the central region F1, for any transition region F3, in the transition region F3, the second angle c2 corresponding to the second metal side wall 212 at the opening 300 close to the central region F1 is smaller than the second angle c2 corresponding to the second metal side wall 212 at the opening 300 away from the central region F1.

[0116] In the case where at least two transition regions F3 are included between the edge region F2 and the central region F1, for any two transition regions F3, the second angle c2 corresponding to the second metal side wall 212 at the opening 300 in the transition region F3 close to the central region F1 is smaller than the second angle c2 corresponding to the second metal side wall 212 at the opening 300 in the transition region F3 away from the central region F1.

[0117] In some embodiments, the second angle c2 corresponding to the second metal sidewall 212 at each opening 300 gradually increases from the centerline L1 of the central region F1 to the side of the semiconductor structure. This creates a structure in which the second angle c2 gradually increases from the central region F1 to the side of the semiconductor structure, further focusing the emitted light and achieving a better display effect. Furthermore, this ensures that light emitted by the light-emitting units at different openings 300 of the semiconductor structure is more evenly distributed toward the light-receiving area, enhancing the display effect.

[0118] In some embodiments, at the opening 300 located along the centerline of the semiconductor structure, the angle between the metal sidewall 210 and the designated position M1 on the upper surface of the substrate 100 is equal to 90 degrees. That is, the first and second metal sidewalls 211 are positioned perpendicular to the designated position M1 on the upper surface of the substrate 100. This ensures that light emitted by the light-emitting units located along the centerline is emitted vertically upward, and thus toward the central region F1 of the light-receiving area.

[0119] It should be noted that Figure 4-Figure 7 In the semiconductor structure shown, a light-emitting unit 500 is also schematically shown. When the light-emitting unit 500 is formed in the opening enclosed by the metal mask layer 200, a light-emitting array is formed.

[0120] An embodiment of the present invention further provides a light emitting array, Figure 8 This is a schematic diagram of another light emitting array provided by an embodiment of the present invention, referring to Figure 2 and Figure 8 The light-emitting array includes light-emitting units 500 arranged in an array, and an isolation layer is arranged between the light-emitting units 500; the isolation layer includes a metal mask layer 200 and a passivation layer 400, the metal mask layer 200 encloses a plurality of openings 300, and the light-emitting units 500 are located in the openings 300, and the light-emitting units 500 include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked from the upper surface of the substrate 100; the metal mask layer 200 includes a metal sidewall 210 facing the opening 300, the passivation layer 400 is arranged on the metal sidewall 210, and the sidewall of the light-emitting unit 500 is in contact with the passivation layer 400.

[0121] Specifically, the light-emitting array can be formed by forming the light-emitting unit 500 in the opening 300 of the metal mask layer 200 of the semiconductor structure of the above embodiment of the present invention. In some embodiments, after the light-emitting unit 500 is formed in the opening 300 of the metal mask layer 200, at least part of the thickness of the substrate 100 of the semiconductor structure can be removed. In other embodiments, the light-emitting array can also be formed by non-selective epitaxy, without the need to use the semiconductor structure provided by the above embodiment of the present invention, such as etching the light-emitting units arranged in an array in the epitaxial structure, forming a passivation layer on the sidewall of the light-emitting unit, and then forming a metal layer between adjacent light-emitting units or using black glue or other opaque materials instead of the metal layer, and achieving the above-mentioned beneficial effects by setting different inclination angles of the sidewalls of the light-emitting units in the central area and the edge area of ​​the light-emitting array.

[0122] The light emitting array of this embodiment has the beneficial effects of the semiconductor structure of any of the above embodiments of the present invention.

[0123] refer to Figure 4 Optionally, the light emitting array includes a central region F1 and an edge region F2, and the edge region F2 surrounds the central region F1; the central region F1 and the edge region F2 each include a plurality of openings 300; along the first direction, the metal sidewalls 210 on both sides of the opening 300 are respectively a first metal sidewall 211 and a second metal sidewall 212, and the first direction is the direction from the edge region F2 to the central region F1; at the opening 300 in the central region F1, the first metal sidewall 211 is closer to the edge region F2 relative to the second metal sidewall 212; at the opening 300 in the edge region F2, the first metal sidewall 211 is farther away from the central region F1 relative to the second metal sidewall 212; the angle between the first metal sidewall 211 and the bottom surface B1 of the metal mask layer 200 is a third angle ( Figure 4 In the illustrated embodiment, the third angle is equal to the first angle c1); the third angle corresponding to the first metal sidewall 211 at the opening 300 in the central region F1 is greater than the third angle corresponding to the first metal sidewall 211 at the opening 300 in the edge region F2. This ensures that light reflected by the metal mask layer 200 in the central region F1 reaches the light receiving area, and light reflected by the metal mask layer 200 in the edge region F2 also reaches the light receiving area. This ensures that light emitted by each light-emitting unit 500 of the light-emitting array is directed toward the light receiving area, thereby controlling the direction of light emitted by the light-emitting unit 500, focusing the emitted light and achieving a better display effect.

[0124] refer to Figure 5In some embodiments, at least one transition region F3 is included between the edge region F2 and the center region F1. The transition region F3 includes multiple openings 300. At the openings 300 in the transition region F3, the first metal sidewall 211 is closer to the edge region F2 than the second metal sidewall 212. The third angle corresponding to the first metal sidewall 211 at the openings 300 in the transition region F3 is between the third angle corresponding to the first metal sidewall 211 at the openings 300 in the center region F1 and the third angle corresponding to the first metal sidewall 211 at the openings 300 in the edge region F2. This configuration creates a structure in which the third angle gradually decreases from the center region F1 to the edge region F2, further focusing the emitted light and achieving a better display effect.

[0125] In some embodiments, the third angle corresponding to the first metal sidewall 211 at each opening 300 gradually decreases from the centerline L1 of the central region F1 to the side of the light-emitting array. This further forms a structure in which the third angle gradually decreases from the central region F1 to the side of the light-emitting array, further focusing the emitted light and achieving a better display effect. Furthermore, this ensures that the light emitted by the light-emitting units 500 at different openings 300 in the light-emitting array is more evenly directed to the light-receiving area, thereby improving the display effect.

[0126] refer to Figure 6 Optionally, the light emitting array includes a central region F1 and an edge region F2, and the edge region F2 surrounds the central region F1; the central region F1 and the edge region F2 each include a plurality of openings 300; along the first direction, the metal sidewalls 210 on both sides of the opening 300 are respectively the first metal sidewall 211 and the second metal sidewall 212, and the first direction is the direction from the edge region F2 to the central region F1; at the opening 300 in the central region F1, the first metal sidewall 211 is closer to the edge region F2 relative to the second metal sidewall 212; at the opening 300 in the edge region F2, the first metal sidewall 211 is farther away from the central region F1 relative to the second metal sidewall 212; the angle between the second metal sidewall 212 and the bottom surface B1 of the metal mask layer 200 is the fourth angle ( Figure 4 In the illustrated embodiment, the fourth angle is equal to the second angle c2); the fourth angle corresponding to the second metal sidewall 212 at the opening 300 in the central region F1 is smaller than the fourth angle corresponding to the second metal sidewall 212 at the opening 300 in the edge region F2. This ensures that light reflected by the metal mask layer 200 in the central region F1 reaches the light receiving area, and light reflected by the metal mask layer 200 in the edge region F2 also reaches the light receiving area. This ensures that light emitted by each light-emitting unit 500 of the light-emitting array is directed toward the light receiving area, and further controls the direction of light emitted by the light-emitting unit 500, focusing the emitted light and achieving a better display effect.

[0127] refer to Figure 7 Optionally, at least one transition region F3 is further included between the edge region F2 and the center region F1. The transition region F3 includes multiple openings 300. At the openings 300 in the transition region F3, the first metal sidewall 211 is closer to the edge region F2 than the second metal sidewall 212. The fourth angle corresponding to the second metal sidewall 212 at the openings 300 in the transition region F3 is between the fourth angle corresponding to the second metal sidewall 212 at the openings 300 in the center region F1 and the fourth angle corresponding to the second metal sidewall 212 at the openings 300 in the edge region F2. This configuration creates a structure in which the fourth angle gradually increases from the center region F1 to the edge region F2, further focusing the emitted light and achieving a better display effect.

[0128] In some embodiments, the fourth angle corresponding to the second metal sidewall 212 at each opening 300 gradually increases from the centerline L1 of the central region F1 to the side of the light-emitting array. This creates a structure in which the fourth angle gradually increases from the central region F1 to the side of the semiconductor structure, further focusing the emitted light and achieving a better display effect. Furthermore, this ensures that light emitted by the light-emitting units 500 at different openings 300 in the light-emitting array is more evenly distributed toward the light-receiving area, improving the display effect.

[0129] Figure 9 This is a schematic diagram of another light emitting array provided by an embodiment of the present invention, referring to Figure 9 Optionally, the light-emitting array includes a central region F1 and an edge region F2, wherein the edge region F2 surrounds the central region F1; the light-emitting array includes a bottom portion 600, wherein the bottom portion 600 includes a first surface 601 facing the light-emitting array and a second surface 602 facing away from the light-emitting array, and the first surface 601 and / or the second surface 602 are arranged at an angle from the edge region F2 to the central region F1 of the light-emitting array. In this way, the light-emitting array is arranged as a whole at an angle, so that the light emitted by the light-emitting units 500 in the edge region F2 can be concentrated toward the light-receiving area, so that the light emitted by the light-emitting units 500 in different areas of the light-emitting array is directed toward the light-receiving area, thereby improving the light focusing effect. In some embodiments, the first surface 601 and / or the second surface 602 of the bottom portion 600 are inclined planes, and in other embodiments, the first surface 601 and / or the second surface 602 of the bottom portion 600 can also be curved surfaces.

[0130] like Figure 9 As shown, when the first surface 601 of the bottom 600 is tilted and the second surface 602 is horizontally arranged, the height of the light-emitting unit 500 in the central area F1 is lower than the height of the light-emitting unit 500 in the edge area F2.

[0131] In other embodiments, the light-emitting array can also be formed by non-selective epitaxy without the need for the semiconductor structure provided by the above-mentioned embodiments of the present invention. For example, light-emitting units arranged in an array are etched in the epitaxial structure, a passivation layer is formed on the side wall of the light-emitting unit, and then a metal layer is formed between adjacent light-emitting units or black glue or other opaque materials are used to replace the metal layer. The above-mentioned beneficial effects are achieved by setting different inclination angles of the side walls of the light-emitting units in the central area and the edge area of ​​the light-emitting array.

[0132] Continue to refer Figure 9 Optionally, the bottom 600 includes a connection layer 610, and the light-emitting unit 500 is arranged on the connection layer 610; the connection layer 610 is arranged obliquely from the side of the light-emitting array to the center line L1 of the central area F1.

[0133] Illustratively, the height of the connection layer 600 in the central region F1 is lower than the height of the connection layer 600 in the edge region F2 .

[0134] The structural reliability of the light emitting array is ensured by providing the connection layer 610 as a carrier of the plurality of light emitting units 500. In some embodiments, the connection layer 610 may include at least a portion of the structure of the substrate 100 in the above-mentioned embodiments of the present invention.

[0135] In other embodiments, the connection layer 610 includes a reflective layer, and the material of the reflective layer can be metal. In this way, the light emitted from the light-emitting unit 500 toward the bottom is reflected by the connection layer 610 and then emitted, further improving the light-emitting efficiency of the light-emitting array.

[0136] In this embodiment, by tilting the connection layer 610 toward the surface of the light emitting unit 500 , the light emitting array forms a structure in which the light emitting array is tilted from the edge area F2 to the center area F1 of the light emitting array, thereby improving the light gathering effect.

[0137] Figure 10 is a schematic structural diagram of another light emitting array provided by an embodiment of the present invention. In other embodiments, such as Figure 10 As shown, the reflective layer 620 is a structure independent of the connecting layer 601. The connecting layer 610 is horizontally arranged toward the surface of the light-emitting unit 500, and the connecting layer 610 is tilted away from the surface (second surface 602) of the light-emitting unit 500. The reflective layer 620 is arranged on the surface of the connecting layer 610 away from the light-emitting unit 500. In this way, the light focusing effect can also be improved by combining the reflective layer 620 with the structure of the second surface 602 of the connecting layer 610 tilted.

[0138] The embodiment of the present invention further provides a process for preparing a semiconductor structure. Figure 11 This is a flow chart of a process for preparing a semiconductor structure provided by an embodiment of the present invention, with reference to Figure 11The preparation process of the semiconductor structure includes:

[0139] S310: Provide a substrate.

[0140] Figure 12 is a schematic diagram of the structure of the substrate, where Figure 12 Schematically shows a case where the substrate 100 includes a substrate 110 and a transition layer 120 on one side of the substrate 110. Specifically, the substrate 100 can be obtained by forming the transition layer 120 on one side of the substrate 110. In other embodiments, the substrate 100 only includes the substrate 110.

[0141] S320 , forming a metal layer on one side of the substrate.

[0142] Figure 13 This is a schematic diagram of the structure after a metal layer is formed on one side of the substrate. Figure 13 The metal layer 20 is laid as a whole layer on one side of the substrate 100 , for example, the metal layer 20 is formed as a whole layer on the side of the transition layer 120 away from the substrate.

[0143] S330, patterning the metal layer to form a plurality of openings and a metal mask layer, wherein the metal mask layer encloses the plurality of openings, and the bottoms of the openings expose the upper surface of the substrate; the metal mask layer includes metal sidewalls facing the openings.

[0144] Figure 14 This is a schematic diagram of the structure after the metal mask layer is formed. Figure 14 The metal layer 20 is patterned, for example, by etching away a portion of the metal layer 20 through an etching process to form a plurality of openings 300. The remaining metal layer 20 serves as a metal mask layer 200, which encloses the plurality of openings 300. When patterning the metal layer 20, the metal layer 20 is etched through at positions corresponding to the openings 300, so that the openings 300 expose the upper surface of the substrate.

[0145] S340 , forming a passivation layer on the metal sidewall.

[0146] Figure 15 This is a schematic diagram of the process of forming the passivation layer, refer to Figure 15 Optionally, the preparation steps of the passivation layer 400 may include, after forming the metal mask layer, forming an entire passivation layer 400 on the top surface, sidewalls and bottom of the opening of the metal mask layer; removing the passivation layer 400 material on the top surface of the metal mask layer and the bottom of the opening through a graphical process, and retaining the passivation layer 400 on the metal sidewall 210.

[0147] The fabrication process for the semiconductor structure of the embodiments of the present invention forms a metal mask layer, and during selective epitaxy, light-emitting units can be grown within the openings enclosed by the metal mask layer. The metal mask layer has excellent light reflectivity and can itself serve as a reflective layer, allowing light emitted by the light-emitting units to be reflected by the metal mask layer, thereby improving luminous efficiency and preventing light crosstalk between light-emitting units in adjacent openings. This eliminates the need for an additional reflective layer, simplifies the fabrication process, and improves production efficiency. Furthermore, the metal mask layer has excellent heat dissipation properties, preventing heat accumulation during light-emitting unit illumination, which could reduce luminous efficiency or shorten service life.

[0148] An embodiment of the present invention also provides a preparation process for a light-emitting array, which includes: forming a light-emitting unit in an opening of a semiconductor structure, the light-emitting unit including a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked from the upper surface of a substrate; wherein the semiconductor structure is the semiconductor structure of any embodiment of the present invention.

[0149] In some embodiments, after forming the light-emitting unit, the substrate is partially thinned or the substrate is peeled off.

[0150] In some embodiments, after forming the light-emitting unit, a connection layer is further formed at the bottom of the light-emitting unit, for example, the connection layer is formed after partially thinning the substrate or peeling off the substrate. Optionally, the connection layer includes a reflective layer.

[0151] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0152] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that include: substrate; a metal mask layer, wherein the metal mask layer encloses and forms a plurality of openings, wherein bottoms of the openings expose the upper surface of the substrate; The opening is used to arrange the light-emitting unit; The metal mask layer includes a metal sidewall facing the opening; A passivation layer is disposed on the metal sidewall.

2. The semiconductor structure according to claim 1, wherein: The angle between the metal sidewall and the upper surface of the substrate at a set position is less than or equal to 90 degrees; the set position is a position on the upper surface of the substrate corresponding to the bottom surface of the metal mask layer that is in contact with the metal sidewall.

3. The semiconductor structure according to claim 1, wherein: At each height position of the metal mask layer, along the horizontal direction, the thickness of the metal mask layer is greater than the thickness of the passivation layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that The semiconductor structure includes a central region and an edge region, wherein the edge region surrounds the central region; The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region; At the opening in the central region, the first metal sidewall is closer to the edge region than the second metal sidewall; at the opening in the edge region, the first metal sidewall is farther away from the central region than the second metal sidewall; The angle between the first metal side wall and the upper surface of the substrate at a set position is a first angle; The first angle corresponding to the first metal sidewall at the opening in the central region is greater than the first angle corresponding to the first metal sidewall at the opening in the edge region.

5. The semiconductor structure according to claim 4, wherein: At least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall; The first angle corresponding to the first metal sidewall at the opening in the transition region is between the first angle corresponding to the first metal sidewall at the opening in the central region and the first angle corresponding to the first metal sidewall at the opening in the edge region. The semiconductor structure according to claim 4 , wherein: From the center line of the central area to the side of the semiconductor structure, the first angle corresponding to the first metal sidewall at each opening gradually decreases.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that The semiconductor structure includes a central region and an edge region, wherein the edge region surrounds the central region; The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region; At the opening in the central region, the first metal sidewall is closer to the edge region than the second metal sidewall; at the opening in the edge region, the first metal sidewall is farther away from the central region than the second metal sidewall; The angle between the second metal side wall and the upper surface of the substrate at a set position is a second angle; The second angle corresponding to the second metal sidewall at the opening in the central region is smaller than the second angle corresponding to the second metal sidewall at the opening in the edge region.

8. The semiconductor structure according to claim 7, wherein: At least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall; The second angle corresponding to the second metal sidewall at the opening in the transition area is between the second angle corresponding to the second metal sidewall at the opening in the central area and the second angle corresponding to the second metal sidewall at the opening in the edge area.

9. The semiconductor structure according to claim 7, wherein: From the center line of the central area to the side of the semiconductor structure, the second angle corresponding to the second metal sidewall at each opening gradually increases.

10. The semiconductor structure according to any one of claims 1 to 3, characterized in that: At the opening located on the center line of the semiconductor structure, an angle between the metal sidewall and a set position on the upper surface of the substrate is equal to 90 degrees.

11. A light emitting array, characterized in that: The light emitting units are arranged in an array, and an isolation layer is provided between the light emitting units; The isolation layer includes a metal mask layer and a passivation layer, the metal mask layer encloses a plurality of openings, the light-emitting unit is located in the opening, and the light-emitting unit includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked from the upper surface of the substrate; the metal mask layer includes a metal side wall facing the opening, the passivation layer is arranged on the metal side wall, and the side wall of the light-emitting unit is in contact with the passivation layer.

12. The light emitting array according to claim 11, characterized in that: The light emitting array includes a central area and an edge area, wherein the edge area surrounds the central area; The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region; At the opening in the central region, the first metal sidewall is closer to the edge region than the second metal sidewall; at the opening in the edge region, the first metal sidewall is farther away from the central region than the second metal sidewall; An included angle between the first metal sidewall and the bottom surface of the metal mask layer is a third included angle; The third angle corresponding to the first metal sidewall at the opening in the central region is greater than the third angle corresponding to the first metal sidewall at the opening in the edge region.

13. The light emitting array according to claim 12, characterized in that: At least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall; The third angle corresponding to the first metal sidewall at the opening in the transition area is between the third angle corresponding to the first metal sidewall at the opening in the central area and the third angle corresponding to the first metal sidewall at the opening in the edge area.

14. The light emitting array according to claim 12, wherein: From the center line of the central area to the side of the light-emitting array, the third angle corresponding to the first metal sidewall at each opening gradually decreases.

15. The light emitting array according to claim 11, wherein: The light emitting array includes a central area and an edge area, wherein the edge area surrounds the central area; The central region and the edge region each include a plurality of openings; along a first direction, the metal sidewalls on both sides of the opening are respectively a first metal sidewall and a second metal sidewall, and the first direction is a direction from the edge region to the central region; At the opening in the central region, the first metal sidewall is closer to the edge region than the second metal sidewall; at the opening in the edge region, the first metal sidewall is farther away from the central region than the second metal sidewall; An included angle between the second metal sidewall and the bottom surface of the metal mask layer is a fourth included angle; The fourth angle corresponding to the second metal sidewall at the opening in the central region is smaller than the fourth angle corresponding to the second metal sidewall at the opening in the edge region.

16. The light emitting array according to claim 15, characterized in that: At least one transition region is further included between the edge region and the central region, the transition region includes a plurality of openings, and at the openings in the transition region, the first metal sidewall is closer to the edge region than the second metal sidewall; The fourth angle corresponding to the second metal sidewall at the opening in the transition area is between the fourth angle corresponding to the second metal sidewall at the opening in the central area and the fourth angle corresponding to the second metal sidewall at the opening in the edge area.

17. The light emitting array according to claim 15, characterized in that: From the center line of the central area to the side of the light-emitting array, the fourth angle corresponding to the second metal sidewall at each opening gradually increases.

18. A light emitting array, characterized in that: The light-emitting array includes a central area and an edge area, and the edge area surrounds the central area; the light-emitting array includes a bottom, and the bottom includes a first surface facing the light-emitting array and a second surface facing away from the light-emitting array, and the first surface and / or the second surface are arranged obliquely from the edge area of ​​the light-emitting array to the central area.

19. The light emitting array according to claim 18, characterized in that: The bottom of the light emitting array comprises a connection layer, and the light emitting units are arranged on the connection layer; the connection layer is arranged obliquely from the side of the light emitting array to the center line of the central area.

20. The light emitting array according to claim 19, wherein: The connection layer includes a reflective layer.

21. A process for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a metal layer on one side of the substrate; Patterning the metal layer to form a plurality of openings and a metal mask layer, wherein the metal mask layer encloses the plurality of openings, and the bottoms of the openings expose the upper surface of the substrate; the metal mask layer includes metal sidewalls facing the openings; A passivation layer is formed on the metal sidewall.

22. A process for preparing a light emitting array, characterized in that: include: forming a light-emitting unit in the opening of the semiconductor structure, wherein the light-emitting unit includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked on the upper surface of the substrate; The semiconductor structure is the semiconductor structure according to any one of claims 1 to 10.

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