Display device

Abstract

A display device is disclosed. The display device may include a display panel, a flexible circuit film attached to the display panel, and a conductive adhesive member disposed between the display panel and the flexible circuit film. The display panel may include pads spaced apart from each other in a first direction and panel cursor marks spaced apart from the pads in the first direction. The flexible circuit film may include leads overlapping the pads, respectively, on a plane. The conductive adhesive member may connect the pad and the lead, respectively. The pads may include a first pad extending in a second direction perpendicular to the first direction and a second pad extending at a first angle relative to the second direction. The panel cursor mark may include a first extension pattern extending in a direction parallel to an extension direction of the first pad and a second extension pattern extending in a direction parallel to an extension direction of the second pad.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] Flat panel display devices are used as a replacement for cathode ray tube display devices due to their light weight and thinness. Representative examples of such flat panel display devices include liquid crystal display devices and organic light emitting display devices.

[0003] A display device may include a display panel including a plurality of pixels and a flexible circuit film that transmits electrical signals to the display panel. The display panel and the flexible circuit film may be physically and electrically bonded together using a conductive adhesive. If the display panel and the flexible circuit film are bonded in a misaligned state, the reliability of the display device may be reduced. Summary of the Invention

[0004] An object of the present invention is to provide a display device with improved reliability.

[0005] However, the present invention is not limited to the above-mentioned objects, but can be expanded in various ways without departing from the scope of the concept and field of the present invention.

[0006] To achieve the aforementioned objectives of the present invention, a display device according to an exemplary embodiment of the present invention may include a display panel, a flexible circuit film attached to the display panel, and a conductive adhesive member disposed between the display panel and the flexible circuit film. The display panel may include a base substrate, a plurality of pixels, a plurality of pads, and a panel vernier mark. The base substrate includes a display area and a peripheral area outside the display area, the plurality of pixels are disposed in the display area, the plurality of pads are disposed in the peripheral area and spaced apart from each other in a first direction, and the panel vernier mark is disposed in the peripheral area and spaced apart from the plurality of pads in the first direction. The flexible circuit film may include a plurality of leads that overlap with the plurality of pads in a plane. The conductive adhesive member may connect the plurality of pads and the plurality of leads, respectively. The plurality of pads may include: a first pad extending in a second direction perpendicular to the first direction; and a second pad extending at a first angle relative to the second direction. The panel vernier mark may include: a first extension pattern extending in a direction parallel to the extension direction of the first pad; and a second extension pattern extending in a direction parallel to the extension direction of the second pad.

[0007] In one embodiment, the flexible circuit film includes a base film, and the plurality of leads are arranged on a lower surface of the base film.

[0008] In one embodiment, the second pad may be spaced apart from the first pad in the first direction. The first extension pattern may be spaced apart from the second pad in the first direction. The second extension pattern may be spaced apart from the first extension pattern in the first direction.

[0009] In one embodiment, the first pad may be a pad arranged at the center of the plurality of pads in the first direction, and the second pad may be a pad arranged at the outermost portion of the plurality of pads in the first direction.

[0010] In one embodiment, the plurality of pads may further include a third pad disposed between the first pad and the second pad and extending at a second angle with respect to the second direction that is smaller than the first angle. The panel vernier mark may further include a third extension pattern extending in a direction parallel to the extension direction of the third pad.

[0011] In one embodiment, the third extension pattern may be arranged between the first extension pattern and the second extension pattern.

[0012] In one embodiment, the panel vernier mark may further include: a first character pattern indicating an angle at which the extension direction of the second extension pattern is inclined relative to the second direction.

[0013] In one embodiment, the first character pattern may be adjacent to the second extension pattern.

[0014] In one embodiment, the panel vernier mark may further include: a fourth extending pattern extending along the first direction; and a fifth extending pattern extending along the first direction and spaced apart from the fourth extending pattern in the second direction.

[0015] In one embodiment, the panel vernier mark may further include: a second character pattern indicating the distance between the fourth extension pattern and the fifth extension pattern in the second direction.

[0016] In one embodiment, the second character pattern may be adjacent to the fifth extension pattern.

[0017] In one embodiment, the fourth extension pattern and the fifth extension pattern may be spaced apart from the first extension pattern and the second extension pattern in the first direction.

[0018] In one embodiment, the conductive adhesive member may overlap with the first extension pattern and the second extension pattern in a planar manner, and may not overlap with the fourth extension pattern and the fifth extension pattern in a planar manner.

[0019] In one embodiment, the flexible circuit film may overlap with the first extension pattern and the second extension pattern in a plane, and may not overlap with the fourth extension pattern and the fifth extension pattern in a plane.

[0020] In one embodiment, the plurality of leads may include: a first lead extending in the second direction and overlapping the first pad in a plane; and a second lead extending at an angle relative to the second direction and overlapping the second pad in a plane. The flexible circuit film may further include a film vernier mark spaced apart from the plurality of leads in the first direction and extending in a direction parallel to the extension direction of the second lead.

[0021] In one embodiment, the film vernier mark may overlap with the second extension pattern on a plane.

[0022] In one embodiment, the first extension pattern, the second extension pattern, the fourth extension pattern, and the fifth extension pattern may be formed as one body.

[0023] In one embodiment, the conductive adhesive member may not overlap with the first extension pattern, the second extension pattern, the fourth extension pattern, and the fifth extension pattern in a plane.

[0024] In one embodiment, the flexible circuit film may not overlap with the first extension pattern, the second extension pattern, the fourth extension pattern, and the fifth extension pattern on a plane.

[0025] To achieve the above-mentioned objectives of the present invention, a display device according to an exemplary embodiment of the present invention may include a display panel, a flexible circuit film attached to the display panel, and a conductive adhesive component disposed between the display panel and the flexible circuit film. The display panel may include a base substrate, a plurality of pixels, a plurality of pads, and a panel vernier mark. The base substrate includes a display area and a peripheral area outside the display area, the plurality of pixels are disposed in the display area, the plurality of pads are disposed in the peripheral area and spaced apart from each other in a first direction, and the panel vernier mark is disposed in the peripheral area and spaced apart from the plurality of pads in the first direction. The flexible circuit film may include a base film and a plurality of leads disposed on the base film and overlapping with the plurality of pads in a plane. The conductive adhesive component may connect the plurality of pads and the plurality of leads, respectively. The plurality of pads may include: a first pad extending in a second direction perpendicular to the first direction; and a second pad extending at a first angle relative to the second direction. The panel cursor mark may include: a first extension portion extending in a direction parallel to the extension direction of the first pad; a second extension portion extending in a direction parallel to the extension direction of the second pad and located in the first direction of the first extension portion; a third extension portion extending in the first direction and intersecting the first extension portion and the second extension portion; and a fourth extension portion extending in the first direction and located in the second direction of the third extension portion, and intersecting the first extension portion and the second extension portion.

[0026] According to the embodiments of the present invention, the display panel and the flexible circuit film can be precisely aligned, thereby improving the reliability of the display device.

[0027] However, the effects of the present invention are not limited to the above-mentioned effects, and can be expanded in various ways without departing from the scope of the concept and field of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a plan view showing a display device according to an embodiment of the present invention.

[0029] Figure 2 It shows Figure 1 A circuit diagram of a pixel included in a display device.

[0030] Figure 3 It shows Figure 2 A cross-sectional view of a pixel.

[0031] Figure 4 It is enlarged to show Figure 1 An example plan view of the "A" area.

[0032] Figure 5 yes Figure 4 Exploded plan view of the display device.

[0033] Figure 6 It is enlarged to show Figure 5 A plan view of the panel with Vernier markings.

[0034] Figure 7 It is enlarged to show Figure 1 A plan view of another example of the "A" area.

[0035] Figure 8 yes Figure 7 Exploded plan view of the display device.

[0036] Figure 9 It is enlarged to show Figure 8 A plan view of the panel with vernier markers.

[0037] Figure 10 is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0038] Description of Reference Numerals DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the accompanying drawings.

[0040] Figure 1 is a plan view showing a display device according to an embodiment of the present invention.

[0041] Reference Figure 1 , a display device DD according to an embodiment of the present invention may include a display panel DP, a flexible circuit film FCF, a conductive adhesive member AF, and a driving circuit DV.

[0042] The display panel DP may have a display surface defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The display panel DP may display an image in a third direction DR3 via the display surface. For example, the second direction DR2 may be perpendicular to the first direction DR1. The third direction DR3 may be substantially parallel to the normal direction of the display surface. The display surface may correspond to the upper surface (or front surface) of the display panel DP. Hereinafter, the third direction DR3 is referred to as the upper direction, and the direction opposite to the third direction DR3 is referred to as the lower direction.

[0043] Display panel DP (or Figure 3The base substrate BS may include a display area DA for displaying an image and a peripheral area PA located around the display area DA. The peripheral area PA may be located outside the display area DA. For example, the peripheral area PA may surround the display area DA in a plane.

[0044] The display panel DP may include a plurality of pixels PX arranged in the display area DA. For example, the pixels PX may be arranged in a matrix along the first direction DR1 and the second direction DR2 on a plane. This is exemplary and the present invention is not limited thereto.

[0045] Each pixel PX may include a pixel circuit and a light-emitting element. The pixel circuit may include at least one transistor and at least one capacitor. The pixel circuit may generate a drive current and provide the generated drive current to the light-emitting element. The light-emitting element may emit light based on the drive current. For example, the light-emitting element may include an organic light-emitting element, an inorganic light-emitting element, or a quantum dot light-emitting element. The image may be generated by combining the light emitted from each pixel PX.

[0046] The peripheral area PA may include a pad area located on one side of the display area DA. For example, the pad area may be located on one side of the display area DA in a direction opposite to the second direction DR2. The display panel DP may include a plurality of pads arranged in the pad area and electrically connected to the pixels PX.

[0047] A flexible circuit film (FCF) may be attached to the display panel DP. The flexible circuit film (FCF) may be attached to one side of the display panel DP. The flexible circuit film (FCF) may be attached to the display panel DP such that a first end portion overlaps the pad region. The flexible circuit film (FCF) may include a plurality of leads disposed at the first end portion.

[0048] A conductive adhesive component AF can be disposed between the display panel DP and the flexible circuit film FCF to bond the display panel DP and the flexible circuit film FCF. The conductive adhesive component AF can have both electrical conductivity and adhesive properties. Thus, the conductive adhesive component AF can physically and electrically bond the display panel DP and the flexible circuit film FCF. The conductive adhesive component AF can also connect the pads of the display panel DP and the leads of the flexible circuit film FCF, respectively. For example, the conductive adhesive component AF can include an anisotropic conductive adhesive film (ACF).

[0049] The driving circuit DV may generate an electrical signal for supplying to the display panel DP, or may also process an electrical signal received from the display panel DP. For example, the driving circuit DV may include a gate driving circuit for generating a gate signal or a data driving circuit for generating a data signal, but this is exemplary and the present invention is not limited thereto.

[0050] The driving circuit DV may be formed as an integrated circuit (IC). Figure 1 As shown, the driving circuit DV can be directly mounted on a surface of a flexible circuit film FCF using a chip-on-film (COF) method. In another embodiment, the driving circuit DV can be directly mounted on a surface of a display panel DP using a chip-on-glass (COG) method or a chip-on-plastic (COP) method.

[0051] In one embodiment, a circuit substrate (not shown) may be connected to a second end of the flexible circuit film FCF, opposite the first end. The flexible circuit film FCF may be flexible. For example, the flexible circuit film FCF may be bent so that the driving circuit DV and the circuit substrate are positioned below the display panel DP.

[0052] Figure 2 It shows Figure 1 A circuit diagram of a pixel included in a display device. Figure 3 It shows Figure 2 A cross-sectional view of a pixel.

[0053] Below, refer to Figure 2 and Figure 3 The pixels PX arranged in the display area DA of the display panel DP will be described in more detail.

[0054] Reference Figure 2 Each of the pixels PX may include the pixel circuit and the light emitting element LED. The pixel circuit may include a first transistor T1, a second transistor T2, and a storage capacitor CST.

[0055] The first transistor T1 can provide a driving current to the light-emitting element LED. A first electrode of the first transistor T1 can be connected to a first power line VDDL transmitting a first power supply voltage, and a second electrode of the first transistor T1 can be connected to a first electrode of the light-emitting element LED. A gate electrode of the first transistor T1 can be connected to a second electrode of the second transistor T2.

[0056] The second transistor T2 can provide a data signal to the gate electrode of the first transistor T1 in response to a gate signal. The first electrode of the second transistor T2 can be connected to a data line DL that transmits the data signal, and the second electrode of the second transistor T2 can be connected to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to a gate line GL that transmits the gate signal.

[0057] Figure 2 , each of the first transistor T1 and the second transistor T2 is an NMOS transistor, but this is exemplary and the present invention is not limited thereto. In another embodiment, at least one of the first transistor T1 and the second transistor T2 may be a PMOS transistor.

[0058] The storage capacitor CST may maintain a voltage between the second electrode and the gate electrode of the first transistor T1. A first electrode of the storage capacitor CST may be connected to the gate electrode of the first transistor T1, and a second electrode of the storage capacitor CST may be connected to the second electrode of the first transistor T1.

[0059] Figure 2 An embodiment in which the pixel circuit includes two transistors and one capacitor is shown, but this is exemplary and the present invention is not limited thereto. In another embodiment, the pixel circuit may include more than three transistors and / or more than two capacitors.

[0060] The light-emitting element LED can emit light based on the driving current. A first electrode of the light-emitting element LED can be connected to the second electrode of the first transistor T1, and a second electrode of the light-emitting element LED can be connected to a second power supply line VSSL that transmits a second power supply voltage. For example, the first power supply voltage can be greater than the second power supply voltage.

[0061] Reference Figure 3 In one embodiment, the display panel DP may include a base substrate BS, a buffer layer BFL, insulating layers IL1, IL2, IL3, a transistor TR, a pixel defining layer PDL, a light emitting element LED, and an encapsulation layer ENC. For example, Figure 3 The transistor TR can be Figure 2 The first transistor T1.

[0062] In one embodiment, the base substrate BS may be a transparent insulating substrate, for example, a resin substrate or a glass substrate.

[0063] A buffer layer BFL may be disposed on the base substrate BS. The buffer layer BFL can prevent impurities such as oxygen and moisture from diffusing through the base substrate BS to the upper portion of the base substrate BS. The buffer layer BFL may include inorganic insulating materials such as silicon compounds and metal oxides. For example, the buffer layer BFL may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc. These materials may be used alone or in combination. The buffer layer BFL may have a single-layer structure or a multi-layer structure including multiple insulating layers.

[0064] A transistor TR may be disposed on the buffer layer BFL and may include an active layer ACT, a gate electrode GE, a first contact electrode SE, and a second contact electrode DE.

[0065] The active layer ACT may be disposed on the buffer layer BFL. The active layer ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, or the like. For example, the oxide semiconductor may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. The active layer ACT may include a source region, a drain region, and a channel region located between the source and drain regions.

[0066] A first insulating layer IL1 may be disposed on the active layer ACT. The first insulating layer IL1 may cover the active layer ACT on the buffer layer BFL. The first insulating layer IL1 may include an inorganic insulating substance.

[0067] The gate electrode GE may be disposed on the first insulating layer IL1 , overlap the channel region of the active layer ACT, and include a conductive material such as metal, alloy, conductive metal nitride, conductive metal oxide, or a transparent conductive material. For example, the gate electrode GE may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum, an alloy containing silver, an alloy containing copper, an alloy containing molybdenum, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), indium zinc oxide (IZO), etc. These may be used alone or in combination with one another. The gate electrode GE may have a single-layer structure or a multi-layer structure including a plurality of conductive layers.

[0068] A second insulating layer IL2 may be disposed on the gate electrode GE. The second insulating layer IL2 may cover the gate electrode GE on the first insulating layer IL1. The second insulating layer IL2 may include an inorganic insulating substance.

[0069] A first contact electrode SE and a second contact electrode DE may be disposed on the second insulating layer IL2 . The first contact electrode SE and the second contact electrode DE may be connected to the source region and the drain region of the active layer ACT, respectively. The first contact electrode SE and the second contact electrode DE may include a conductive material.

[0070] A third insulating layer IL3 may be disposed on the first contact electrode SE and the second contact electrode DE. The third insulating layer IL3 may include an organic insulating material. For example, the third insulating layer IL3 may include photoresist, polyacryl-based resin, polyimide-based resin, polyamide-based resin, siloxane-based resin, acryl-based resin, epoxy-based resin, etc. These materials may be used alone or in combination.

[0071] Figure 2Although three insulating layers and two conductive layers are arranged between the active layer ACT and the light-emitting element LED, this is exemplary and the present invention is not limited thereto. For example, four or more insulating layers and three or more conductive layers may be arranged between the active layer ACT and the light-emitting element LED.

[0072] A first electrode PE of the light-emitting element LED may be disposed on the third insulating layer IL3. The first electrode PE may be an anode. The first electrode PE may include a conductive material. The first electrode PE may have a single-layer structure or a multi-layer structure including multiple conductive layers. The first electrode PE may be connected to the second contact electrode DE of the transistor TR via a contact hole formed in the third insulating layer IL3.

[0073] A pixel defining layer (PDL) may be disposed on the first electrode PE. The pixel defining layer (PDL) may cover a peripheral portion of the first electrode PE and define a pixel opening exposing a central portion of the first electrode PE. The pixel defining layer (PDL) may include an organic insulating material.

[0074] A light emitting layer EL may be disposed on the first electrode PE, may be disposed in the pixel opening of the pixel defining layer PDL, and may include at least one of an organic light emitting material and quantum dots.

[0075] In one embodiment, the organic light-emitting substance may include a low-molecular organic compound or a high-molecular organic compound. Examples of the low-molecular organic compound include copper phthalocyanine, N,N'-diphenyl benzidine, tris-(8-hydroxyquinoline)aluminum, etc. Examples of the high-molecular organic compound include poly(3,4-ethylenedioxythiophene), polyaniline, poly-phenylenevinylene, polyfluorene, etc., but this is exemplary and the present invention is not limited thereto. They can be used alone or in combination with each other.

[0076] In one embodiment, the quantum dot may include a core comprising a II-VI compound, a III-V compound, a IV-VI compound, a Group IV element, a Group IV compound, or a combination thereof. In one embodiment, the quantum dot may have a core-shell structure comprising the core and a shell surrounding the core. The shell may function as a protective layer to prevent chemical degeneration of the core while maintaining semiconductor properties, and as a charging layer to impart electrophoretic properties to the quantum dot.

[0077] The second electrode CE of the light-emitting element LED may be disposed on the light-emitting layer EL. The second electrode CE may also be disposed on the pixel-defining layer PDL. The second electrode CE may be a cathode. The second electrode CE may include a conductive material. The first electrode PE, the light-emitting layer EL, and the second electrode CE may constitute the light-emitting element LED. The light-emitting element LED may further include various functional layers (e.g., a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc.) disposed between the first electrode PE and the light-emitting layer EL, or between the light-emitting layer EL and the second electrode CE.

[0078] An encapsulation layer ENC may be disposed on the second electrode CE. The encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one embodiment, the encapsulation layer ENC may include a first inorganic encapsulation layer disposed on the second electrode CE, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. The organic encapsulation layer may cover the entire display area DA. Furthermore, although not shown in the figures, the display panel DP may further include various functional layers (e.g., a touch sensing layer, a color filter layer, a light-collecting layer, etc.) disposed on the encapsulation layer ENC.

[0079] Figure 4 It is enlarged to show Figure 1 An example plan view of the "A" area. Figure 5 yes Figure 4 Exploded plan view of the display device.

[0080] Below, refer to Figure 4 and Figure 5 The pad area of ​​the display panel DP and the flexible circuit film FCF are described in more detail.

[0081] Reference Figure 1 、 Figure 4 and Figure 5The display panel DP includes pixels PX arranged in the display area DA and pads PD, a panel alignment mark AM-P, and a panel vernier mark VM-P arranged in the peripheral area PA. The pads PD, the panel alignment mark AM-P, and the panel vernier mark VM-P may be arranged in Figure 3 on the upper surface of the base substrate BS.

[0082] The flexible circuit film FCF may include a base film and leads LD, a film alignment mark AM-F, and a film vernier mark VM-F arranged on one surface of the base film. The leads LD, the film alignment mark AM-F, and the film vernier mark VM-F may be arranged on the lower surface of the base film so as to face the pad PD, the panel alignment mark AM-P, and the panel vernier mark VM-P, respectively.

[0083] The conductive adhesive part AF may be arranged between the display panel DP and the flexible circuit film FCF. The conductive adhesive part AF may be arranged on the attachment area ADA of the display panel DP. The attachment area ADA may be defined as an area where the conductive adhesive part AF is arranged.

[0084] The pads PD may be arranged in the pad region of the peripheral area PA and may be spaced apart from each other in the first direction DR1. The pads PD may be electrically connected to the pixels PX in the display area DA through the signal lines SL. The signal lines SL may include Figure 2 The signal lines SL may be configured to provide at least one of the data lines DL, the gate lines GL, and the first power lines VDDL. Electrical signals (eg, the data signals, the gate signals, or the first power voltage, etc.) transmitted from the flexible circuit film FCF may be provided to the pixels PX in the display area DA through the signal lines SL.

[0085] In one embodiment, if Figure 4 and Figure 5 As shown, at least a portion of the pads PD spaced apart in the first direction DR1 may extend at angles of different sizes relative to the second direction DR2. Hereinafter, the acute angle between the extending direction of each pad PD and the second direction DR2 is referred to as an inclination angle.

[0086] In one embodiment, the first pad PD1 may be a pad arranged at the center in the first direction DR1 among the pads PD connected to the signal line SL. Figure 5 As shown, the pad PD may have a bilaterally symmetrical shape with respect to the first pad PD1. Hereinafter, for convenience of description, the description will be centered on the pad disposed on the left side (eg, the first direction DR1 side) with respect to the first pad PD1.

[0087] The first pad PD1 may extend in the second direction DR2. The extending direction of the first pad PD1 may be substantially parallel to the second direction DR2. The tilt angle of the first pad PD1, which is the angle between the extending direction of the first pad PD1 and the second direction DR2, may be 0 degrees.

[0088] The second pad PD2 may be spaced apart from the first pad PD1 in the first direction DR1. For example, the second pad PD2 may be the outermost pad arranged in the first direction DR1 among the pads PD connected to the signal line SL. The second pad PD2 may extend at a first angle θ1 greater than 0 degrees relative to the second direction DR2. The inclination angle of the second pad PD2, which is the angle between the extension direction of the second pad PD2 and the second direction DR2, may be the first angle θ1. The inclination angle of the second pad PD2 may be greater than the inclination angle of the first pad PD1.

[0089] The third pad PD3 may be arranged between the first pad PD1 and the second pad PD2. That is, the third pad PD3 may be spaced apart from the first pad PD1 in the first direction DR1 and may be spaced apart from the second pad PD2 in a direction opposite to the first direction DR1. The third pad PD3 may extend at a second angle θ2 that is greater than 0 degrees and less than the first angle θ1 relative to the second direction DR2. The inclination angle of the third pad PD3, which is the angle between the extension direction of the third pad PD3 and the second direction DR2, may be the second angle θ2. The inclination angle of the third pad PD3 may be greater than the inclination angle of the first pad PD1 and less than the inclination angle of the second pad PD2.

[0090] In one embodiment, the pads PD between the first pad PD1 and the second pad PD2 may have different tilt angles. For example, the tilt angle may gradually increase from the first pad PD1 to the second pad PD2. In another embodiment, at least a portion of the pads PD between the first pad PD1 and the second pad PD2 may have the same tilt angle.

[0091] The leads LD may be spaced apart from each other in the first direction DR1 , and may be arranged to overlap the pads PD one-to-one on a plane, respectively. The leads LD may be connected to the corresponding pads PD through the conductive adhesive member AF.

[0092] The leads LD may each have a shape corresponding to the corresponding pad PD. Figure 5 As shown, at least a portion of the leads LD spaced apart in the first direction DR1 may extend at angles of varying magnitude relative to the second direction DR2. Hereinafter, the acute angle between the extending direction of each lead LD and the second direction DR2 is referred to as an inclination angle.

[0093] In one embodiment, the first lead LD1 corresponding to the first pad PD1 may be a lead arranged at the center in the first direction DR1 among the leads LD connected to the pad PD. Figure 5 As shown, the lead LD may have a bilaterally symmetrical shape with respect to the first lead LD1 . Hereinafter, for ease of description, the description will be centered on the lead arranged on the left side (eg, in the first direction DR1 ) with respect to the first lead LD1 .

[0094] The first lead LD1 may extend in the second direction DR2. The extending direction of the first lead LD1 may be substantially parallel to the second direction DR2. The tilt angle of the first lead LD1, which is the angle between the extending direction of the first lead LD1 and the second direction DR2, may be 0 degrees.

[0095] The second lead LD2 corresponding to the second pad PD2 may be spaced apart from the first lead LD1 in the first direction DR1. For example, the second lead LD2 may be the outermost lead arranged in the first direction DR1 among the leads LD connected to the pad PD. The second lead LD2 may extend at a third angle θ3 that is greater than 0 degrees relative to the second direction DR2. The inclination angle of the second lead LD2, which is the angle between the extension direction of the second lead LD2 and the second direction DR2, may be the third angle θ3. The inclination angle of the second lead LD2 may be greater than the inclination angle of the first lead LD1. The third angle θ3 may be the same as the first angle θ1.

[0096] The third lead LD3 corresponding to the third pad PD3 may be arranged between the first lead LD1 and the second lead LD2. That is, the third lead LD3 may be spaced apart from the first lead LD1 in the first direction DR1 and may be spaced apart from the second lead LD2 in a direction opposite to the first direction DR1. The third lead LD3 may extend at a fourth angle θ4 that is greater than 0 degrees and less than the third angle θ3 relative to the second direction DR2. The inclination angle of the third lead LD3, which is the angle between the extension direction of the third lead LD3 and the second direction DR2, may be the fourth angle θ4. The inclination angle of the third lead LD3 may be greater than the inclination angle of the first lead LD1 and less than the inclination angle of the second lead LD2. The fourth angle θ4 may be the same as the second angle θ2.

[0097] In one embodiment, the pads PD and leads LD corresponding to each other may partially overlap on a plane. In one embodiment, each pad PD may partially overlap with the conductive adhesive member AF on a plane. For example, Figure 4 As shown, a portion of each pad PD may overlap with the conductive adhesive part AF in a plane, and the remaining portion (eg, a portion on the second direction DR2 side) may not overlap with the conductive adhesive part AF in a plane.

[0098] In one embodiment, each lead LD may partially overlap with the conductive adhesive member AF on a plane. Figure 4 As shown, each lead LD may include a first portion overlapping with the conductive adhesive part AF and a second portion not overlapping with the conductive adhesive part AF.

[0099] The first lead LD1 may include a first portion LD1a overlapping with the conductive adhesive feature AF and a second portion LD1b not overlapping with the conductive adhesive feature AF. The first portion LD1a of the first lead LD1 may overlap with the corresponding first pad PD1. The second lead LD2 may include a first portion LD2a overlapping with the conductive adhesive feature AF and a second portion LD2b not overlapping with the conductive adhesive feature AF. The first portion LD2a of the second lead LD2 may overlap with the corresponding second pad PD2. The third lead LD3 may include a first portion LD3a overlapping with the conductive adhesive feature AF and a second portion LD3b not overlapping with the conductive adhesive feature AF. The first portion LD3a of the third lead LD3 may overlap with the corresponding third pad PD3. The second portions LD1b, LD2b, and LD3b of the leads LD1, LD2, and LD3 may be located outside the conductive adhesive feature AF. That is, in a planar view, the second portions LD1b, LD2b, and LD3b of the leads LD1, LD2, and LD3 may protrude and extend from the conductive adhesive feature AF. The transmission lines TL may be connected to the second portions LD1 b , LD2 b , and LD3 b of the leads LD1 , LD2 , and LD3 .

[0100] The panel alignment mark AM-P may be arranged outside the pad PD. The film alignment mark AM-F may be arranged outside the lead LD. Figure 4 and Figure 5 As shown, the panel alignment mark AM-P can be arranged on both sides of the pad PD, and the film alignment mark AM-F can be arranged on both sides of the lead LD. The following describes the panel alignment mark AM-P and film alignment mark AM-F arranged on the left side (e.g., in the first direction DR1) of the pad PD and lead LD.

[0101] The panel alignment mark AM-P may be electrically insulated from the pixel PX and the pad PD. The panel alignment mark AM-P may be spaced apart from the pad PD in the first direction DR1. The film alignment mark AM-F may be electrically insulated from the lead LD. The film alignment mark AM-F may be spaced apart from the lead LD in the first direction DR1. In one embodiment, the panel alignment mark AM-P and the film alignment mark AM-F may overlap with the conductive adhesive member AF. That is, the panel alignment mark AM-P may be located within the attachment area ADA.

[0102] The corresponding panel alignment marks AM-P and film alignment marks AM-F can be used as a reference for aligning the display panel DP and the flexible circuit film FCF. In one embodiment, after the conductive adhesive member AF and the flexible circuit film FCF are provided on the display panel DP, the panel alignment marks AM-P and film alignment marks AM-F are used to align the display panel DP and the flexible circuit film FCF. For example, Figure 4 As shown, the display panel DP and the flexible circuit film FCF can be aligned and bonded in such a way that the panel alignment mark AM-P and the film alignment mark AM-F form an alignment pattern. Subsequently, the display panel DP and the flexible circuit film FCF can be more precisely aligned using the panel vernier mark VM-P and the film vernier mark VM-F, which will be described later.

[0103] The panel vernier mark VM-P can be arranged outside the pad PD. The film vernier mark VM-F can be arranged outside the lead LD. In one embodiment, Figure 4 and Figure 5 As shown, the panel vernier mark VM-P can be arranged on both sides of the pad PD, and the film vernier mark VM-F can be arranged on both sides of the lead LD. For example, the panel vernier marks VM-P arranged on both sides of the pad PD can have a shape that is bilaterally symmetrical with respect to the first pad PD1. The film vernier marks VM-F arranged on both sides of the lead LD can have a shape that is bilaterally symmetrical with respect to the first lead LD1. The following description focuses on the panel vernier mark VM-P and the film vernier mark VM-F arranged on the left side of the pad PD and lead LD (for example, in the first direction DR1).

[0104] In one embodiment, the panel vernier mark VM-P may include a first panel vernier mark VMA-P and a second panel vernier mark VMP-P. The first panel vernier mark VMA-P may be a reference for aligning the deflection of the display panel DP and the flexible circuit film FCF. The second panel vernier mark VMP-P may be a reference for aligning the positions of the display panel DP and the flexible circuit film FCF.

[0105] In one embodiment, if Figure 4 and Figure 5 As shown, the first panel vernier mark VMA-P and the membrane vernier mark VM-F may overlap with the conductive adhesive member AF on a plane. That is, the first panel vernier mark VMA-P may be located within the attachment area ADA.

[0106] Figure 6 It is enlarged to show Figure 5 A plan view of the panel with vernier markers.

[0107] Reference Figures 4 to 6In one embodiment, the first panel vernier mark VMA-P may include a first extension pattern LPA1, a second extension pattern LPA2, and a third extension pattern LPA3 spaced apart from each other in the first direction DR1. The first to third extension patterns LPA1 to LPA3 may be electrically insulated from the pixel PX and the pad PD. The first to third extension patterns LPA1 to LPA3 may extend at different angles relative to the second direction DR2. Hereinafter, the acute angle between the extension direction of each of the extension patterns LPA1, LPA2, and LPA3 and the second direction DR2 is referred to as an inclination angle.

[0108] The first extension pattern LPA1 may be spaced apart from the second pad PD2 in the first direction DR1. The first extension pattern LPA1 may be adjacent to the second pad PD2. The first extension pattern LPA1 may extend in a direction substantially parallel to the first pad PD1. That is, the first extension pattern LPA1 may extend in the second direction DR2. The extension direction of the first extension pattern LPA1 may be substantially parallel to the second direction DR2. The inclination angle of the first extension pattern LPA1, which is the angle between the extension direction of the first extension pattern LPA1 and the second direction DR2, may be 0 degrees.

[0109] The second extended pattern LPA2 may be spaced apart from the first extended pattern LPA1 in the first direction DR1. The second extended pattern LPA2 may extend in a direction substantially parallel to the second pad PD2. That is, the second extended pattern LPA2 may extend at a first angle θ1 relative to the second direction DR2. The inclination angle of the second extended pattern LPA2, which is the angle between the extending direction of the second extended pattern LPA2 and the second direction DR2, may be the first angle θ1. The inclination angle of the second extended pattern LPA2 may be greater than the inclination angle of the first extended pattern LPA1.

[0110] The third extension pattern LPA3 may be arranged between the first extension pattern LPA1 and the second extension pattern LPA2. That is, the third extension pattern LPA3 may be spaced apart from the first extension pattern LPA1 in the first direction DR1 and may be spaced apart from the second extension pattern LPA2 in a direction opposite to the first direction DR1. The third extension pattern LPA3 may extend in a direction substantially parallel to the third pad PD3. The third extension pattern LPA3 may extend at a second angle θ2 relative to the second direction DR2. The inclination angle of the third extension pattern LPA3, which is the angle between the extension direction of the third extension pattern LPA3 and the second direction DR2, may be the second angle θ2. The inclination angle of the third extension pattern LPA3 may be greater than the inclination angle of the first extension pattern LPA1 and less than the inclination angle of the second extension pattern LPA2.

[0111] The film vernier mark VM-F may be spaced apart from the second lead LD2 in the first direction DR1. The film vernier mark VM-F may be electrically insulated from the lead LD. The film vernier mark VM-F may extend in a direction substantially parallel to the second lead LD2. That is, the film vernier mark VM-F may extend at a third angle θ3 tilted relative to the second direction DR2. The tilt angle of the film vernier mark VM-F, which is the angle between the extension direction of the film vernier mark VM-F and the second direction DR2, may be the third angle θ3. The third angle θ3 may be the same as the first angle θ1.

[0112] In one embodiment, the film vernier mark VM-F may have a size and shape corresponding to the second extension pattern LPA2 of the first panel vernier mark VMA-P, and may be formed at a position corresponding to the second extension pattern LPA2. For example, the distance between the second pad PD2 and the second extension pattern LPA2 in the first direction DR1 may be substantially equal to the distance between the second lead LD2 and the film vernier mark VM-F in the first direction DR1. For example, Figure 4 As shown, in a case where the display panel DP and the flexible circuit film FCF are attached without error, the film vernier mark VM-F and the second extension pattern LPA2 may be completely overlapped.

[0113] The first panel vernier mark VMA-P and the film vernier mark VM-F can serve as references for aligning the skew of the display panel DP and the flexible circuit film FCF. In one embodiment, the degree of skew between the display panel DP and the flexible circuit film FCF can be accurately determined by using a magnifying glass to confirm the angle between the second extended pattern LPA2 of the first panel vernier mark VMA-P and the film vernier mark VM-F. Furthermore, the degree of skew between the display panel DP and the flexible circuit film FCF can be more accurately determined by further confirming the angles between the first and third extended patterns LPA1 and LPA3, which have different tilt angles, and the film vernier mark VM-F. Based on this, the flexible circuit film FCF can be rotated so that the second extended pattern LPA2 and the film vernier mark VM-F completely overlap, thereby precisely aligning the display panel DP and the flexible circuit film FCF. This improves the reliability of the display device DD.

[0114] In one embodiment, the first panel vernier mark VMA-P may further include a 1-1th character pattern CPA1 and a 1-2th character pattern CPA2.

[0115] The 1-1st character pattern CPA1 may be adjacent to the first extended pattern LPA1. The 1-1st character pattern CPA1 may indicate the angle at which the extension direction of the first extended pattern LPA1 is tilted relative to the second direction DR2. In other words, the 1-1st character pattern CPA1 may indicate the tilt angle of the first extended pattern LPA1. For example, the 1-1st character pattern CPA1 may indicate 0 degrees.

[0116] The first-second character pattern CPA2 may be adjacent to the second extension pattern LPA2. The first-second character pattern CPA2 may represent a first angle θ1 at which the extension direction of the second extension pattern LPA2 is tilted relative to the second direction DR2. That is, the first-second character pattern CPA2 may represent the tilt angle of the second extension pattern LPA2. Figure 6 The shape of the 1st-2nd character pattern CPA2 is shown as an example in which the first angle θ1 is 5 degrees, but this is exemplary, and the first angle θ1 may be variously deformed between 0 degrees and 90 degrees, and accordingly, the shape of the 1st-2nd character pattern CPA2 may also be variously deformed.

[0117] In one embodiment, although not shown in the drawings, the first panel vernier mark VMA-P may further include 1st-3rd character patterns adjacent to the third extension pattern LPA3. The 1st-3rd character patterns may indicate the tilt angle of the third extension pattern LPA3.

[0118] In one embodiment, if Figure 4 and Figure 5 As shown, the second panel vernier mark VMP-P may not overlap with the conductive adhesive part AF in a planar manner. That is, the second panel vernier mark VMP-P may be located outside the conductive adhesive part AF. In one embodiment, the second panel vernier mark VMP-P may not overlap with the flexible circuit film FCF in a planar manner.

[0119] In one embodiment, if Figure 6 As shown, the second panel vernier mark VMP-P may include fourth, fifth, and sixth extension patterns LPP1, LPP2, and LPP3 spaced apart from each other in the second direction DR2. The fourth to sixth extension patterns LPP1 to LPP3 may be electrically insulated from the pixels PX and the pad PD.

[0120] The fourth extended pattern LPP1 may extend along the first direction DR1. The fourth extended pattern LPP1 may be spaced apart from the second extended pattern LPA2 in the first direction DR1. The fourth extended pattern LPP1 may be adjacent to the second extended pattern LPA2. For example, the fourth extended pattern LPP1 may guide the location of a reference point displayed on the flexible circuit film FCF.

[0121] The fifth extension pattern LPP2 may extend in the first direction DR1. The fifth extension pattern LPP2 may be spaced apart from the fourth extension pattern LPP1 in the second direction DR2. In one embodiment, the length of the fifth extension pattern LPP2 in the first direction DR1 may be smaller than the length of the fourth extension pattern LPP1 in the first direction DR1.

[0122] The sixth extension pattern LPP3 may extend along the first direction DR1. The sixth extension pattern LPP3 may be spaced apart from the fourth extension pattern LPP1 in a direction opposite to the second direction DR2. In one embodiment, the length of the sixth extension pattern LPP3 in the first direction DR1 may be less than the length of the fourth extension pattern LPP1 in the first direction DR1. In one embodiment, the length of the sixth extension pattern LPP3 in the first direction DR1 may be substantially equal to the length of the fifth extension pattern LPP2 in the first direction DR1.

[0123] In one embodiment, the distance between the fourth extension pattern LPP1 and the fifth extension pattern LPP2 in the second direction DR2 may be substantially equal to the distance between the fourth extension pattern LPP1 and the sixth extension pattern LPP3 in the second direction DR2.

[0124] The second panel vernier mark VMP-P can serve as a reference for aligning the display panel DP and the flexible circuit film FCF in the second direction DR2. In one embodiment, the degree of positional error in the second direction DR2 of the display panel DP and the flexible circuit film FCF can be determined by using a magnifying glass to check the distance in the second direction DR2 between the fourth extended pattern LPP1 and the reference point of the flexible circuit film FCF. Furthermore, the degree of positional error in the second direction DR2 of the display panel DP and the flexible circuit film FCF can be more accurately determined by further checking the distance in the second direction DR2 between the fifth and sixth extended patterns LPP2 and LPP3, which are spaced a predetermined distance from the fourth extended pattern LPP1, and the reference point of the flexible circuit film FCF. Based on this, by changing the position of the flexible circuit film FCF in the second direction DR2 so that the reference point of the flexible circuit film FCF is aligned with the fourth extended pattern LPP1 (for example, so that the distance in the second direction DR between the reference point and the fourth extended pattern LPP1 is zero), the display panel DP and the flexible circuit film FCF can be precisely aligned. This improves the reliability of the display device DD.

[0125] In one embodiment, the second panel vernier mark VMP-P may further include a 2-1st character pattern CPP1 and a 2-2nd character pattern CPP2.

[0126] The 2-1st character pattern CPP1 may be adjacent to the fourth extension pattern LPP1, and the 2-2nd character pattern CPP2 may be adjacent to the fifth extension pattern LPP2. The 2-2nd character pattern CPP2 may indicate a distance in the second direction DR2 between the fourth extension pattern LPP1 and the fifth extension pattern LPP2. Figure 6 The shape of the 2-2 character pattern CPP2 is shown as an example in which the distance in the second direction DR2 between the fourth extended pattern LPP1 and the fifth extended pattern LPP2 is 5 mm. However, this is exemplary, and the distance in the second direction DR2 between the fourth extended pattern LPP1 and the fifth extended pattern LPP2 can be variously deformed. Accordingly, the shape of the 2-2 character pattern CPP2 can also be variously deformed.

[0127] In one embodiment, the pad PD, the extended patterns LPA1, LPA2, LPA3, LPP1, LPP2, LPP3, and the character patterns CPA1, CPA2, CPP1, and CPP2 may be formed in substantially the same layer. For example, the pad PD, the extended patterns LPA1, LPA2, LPA3, LPP1, LPP2, LPP3, and the character patterns CPA1, CPA2, CPP1, and CPP2 may be formed in substantially the same layer. Figure 3 The gate electrode GE is formed on the same layer as the first contact electrode SE and the second contact electrode DE. However, this is exemplary and the present invention is not limited thereto. In another embodiment, at least a portion of the pad PD, the extension patterns LPA1, LPA2, LPA3, LPP1, LPP2, LPP3, and the character patterns CPA1, CPA2, CPP1, and CPP2 may be formed on different layers.

[0128] Figure 7 It is enlarged to show Figure 1 A plan view of another example of the "A" area. Figure 8 yes Figure 7 Exploded plan view of the display device. Figure 9 It is enlarged to show Figure 8 A plan view of the panel with vernier markers.

[0129] Reference Figures 7 to 9 In one embodiment, referring to Figures 4 to 6 The first panel vernier mark VMA-P and the second panel vernier mark VMP-P are formed as one body, and the membrane vernier mark VM-F can be omitted. Hereinafter, repeated descriptions will be omitted or simplified.

[0130] In one embodiment, the display panel DP' may include a pad PD, a panel alignment mark AM-P, and a panel vernier mark VM-P' arranged in the peripheral area PA. The pad PD, the panel alignment mark AM-P, and the panel vernier mark VM-P' may be arranged in Figure 3 on the upper surface of the base substrate BS.

[0131] The flexible circuit film FCF' may include the base film and the leads LD and film alignment marks AM-F arranged on one surface of the base film. In this embodiment, Figures 4 to 6 The membrane vernier label VM-F can be omitted.

[0132] The panel vernier mark VM-P' may be spaced apart from the second pad PD2 in the first direction DR1. In one embodiment, the panel vernier mark VM-P' may not overlap with the conductive adhesive part AF in a planar manner. That is, the panel vernier mark VM-P' may be located outside the conductive adhesive part AF. In one embodiment, the panel vernier mark VM-P' may not overlap with the flexible circuit film FCF' in a planar manner.

[0133] In one embodiment, if Figure 9 As shown, the panel cursor mark VM-P' may include a panel cursor pattern VP having Figure 6 The panel vernier pattern VP may be electrically insulated from the pad PD.

[0134] The panel vernier pattern VP may include a first extension portion VP1, a second extension portion VP2, and a third extension portion VP3, each extending at different angles relative to the second direction DR2; and a fourth extension portion VP4, a fifth extension portion VP5, and a sixth extension portion VP6, each extending along the first direction DR1 and aligned along the second direction DR2. In one embodiment, the first to sixth extension portions VP1 to VP6 may be integrally formed.

[0135] The first extension portion VP1 may extend in a direction substantially parallel to the first pad PD1. That is, the first extension portion VP1 may extend in the second direction DR2. The extension direction of the first extension portion VP1 may be substantially parallel to the second direction DR2. The inclination angle of the first extension portion VP1, which is the angle between the extension direction of the first extension portion VP1 and the second direction DR2, may be 0 degrees.

[0136] The second extension portion VP2 may be located in the first direction DR1 of the first extension portion VP1. The second extension portion VP2 may extend in a direction substantially parallel to the second pad PD2. That is, the second extension portion VP2 may extend at a first angle θ1 relative to the second direction DR2. The inclination angle of the second extension portion VP2, which is the angle between the extension direction of the second extension portion VP2 and the second direction DR2, may be the first angle θ1. The inclination angle of the second extension portion VP2 may be greater than the inclination angle of the first extension portion VP1.

[0137] The third extension portion VP3 may be located between the first extension portion VP1 and the second extension portion VP2. That is, the third extension portion VP3 may be located in the first direction DR1 of the first extension portion VP1 and in a direction opposite to the first direction DR1 of the second extension portion VP2. The third extension portion VP3 may extend in a direction substantially parallel to the third pad PD3. The third extension portion VP3 may extend at a second angle θ2 relative to the second direction DR2. The inclination angle of the third extension portion VP3, which is the angle between the extension direction of the third extension portion VP3 and the second direction DR2, may be the second angle θ2. The inclination angle of the third extension portion VP3 may be greater than the inclination angle of the first extension portion VP1 and less than the inclination angle of the second extension portion VP2.

[0138] The fourth extension portion VP4 may extend in the first direction DR1 and cross the first to third extension portions VP1 to VP3 .

[0139] The fifth extension portion VP5 may extend along the first direction DR1 and may be located in the second direction DR2 of the fourth extension portion VP4. The fifth extension portion VP5 may intersect the first to third extension portions VP1 to VP3. In one embodiment, the length of the fifth extension portion VP5 in the first direction DR1 may be less than the length of the fourth extension portion VP4 in the first direction DR1.

[0140] The sixth extension portion VP6 may extend along the first direction DR1 and may be located in a direction opposite to the second direction DR2 of the fourth extension portion VP4. The sixth extension portion VP6 may intersect the first to third extension portions VP1 to VP3. In one embodiment, the length of the sixth extension portion VP6 in the first direction DR1 may be less than the length of the fourth extension portion VP4 in the first direction DR1. In one embodiment, the length of the sixth extension portion VP6 in the first direction DR1 may be substantially the same as the length of the fifth extension portion VP5 in the first direction DR1.

[0141] In one embodiment, a distance between the fourth extension portion VP4 and the fifth extension portion VP5 in the second direction DR2 may be substantially the same as a distance between the fourth extension portion VP4 and the sixth extension portion VP6 in the second direction DR2.

[0142] In one embodiment, the panel vernier mark VM-P′ may further include a first character pattern CP1 , a second character pattern CP2 , a third character pattern CP3 , and a fourth character pattern CP4 arranged adjacent to the panel vernier pattern VP.

[0143] The first character pattern CP1 may be adjacent to the first extension portion VP1. The first character pattern CP1 may indicate an angle at which the extension direction of the first extension portion VP1 is inclined relative to the second direction DR2. That is, the first character pattern CP1 may indicate the inclined angle of the first extension portion VP1.

[0144] The second character pattern CP2 may be adjacent to the second extension portion VP2. The second character pattern CP2 may indicate an angle at which the extension direction of the second extension portion VP2 is inclined relative to the second direction DR2. That is, the second character pattern CP2 may indicate the inclined angle of the second extension portion VP2.

[0145] The third character pattern CP3 may be adjacent to the fourth extension portion VP4, and the fourth character pattern CP4 may be adjacent to the fifth extension portion VP5. The fourth character pattern CP4 may indicate a distance in the second direction DR2 between the fourth extension portion VP4 and the fifth extension portion VP5.

[0146] In one embodiment, the degree of skew between the display panel DP' and the flexible circuit film FCF' can be accurately determined by using a magnifying glass to check the angle between the second extension VP2 of the panel vernier pattern VP and the second portion LD2b of the second lead LD2. The second portion LD2b of the second lead LD2 does not overlap with the conductive adhesive member AF and can be easily observed from below the display panel DP'. Furthermore, the degree of skew between the display panel DP' and the flexible circuit film FCF' can be more accurately determined by further checking the angles between the first extension VP1 and the third extension VP3 of the panel vernier pattern VP, which have different inclination angles, and the second portion LD2b of the second lead LD2. Consequently, by adjusting the angle of the flexible circuit film FCF' relative to the display panel DP' so that the second extension VP2 of the panel vernier pattern VP is parallel to the second portion LD2b of the second lead LD2, the display panel DP' and the flexible circuit film FCF' can be precisely aligned.

[0147] In one embodiment, the degree of positional error between the display panel DP' and the flexible circuit film FCF' in the second direction DR2 can be determined by using a magnifying glass to check the distance in the second direction DR2 between the fourth extension portion VP4 of the panel vernier pattern VP and a reference point of the flexible circuit film FCF'. Furthermore, the degree of positional error between the display panel DP' and the flexible circuit film FCF' in the second direction DR2 can be more accurately determined by further checking the distance in the second direction DR2 between the fifth and sixth extension portions VP5 and VP6, which are spaced a predetermined distance from the fourth extension portion VP4, and the reference point of the flexible circuit film FCF'. Consequently, by adjusting the position of the flexible circuit film FCF' in the second direction DR2 so that the reference point of the flexible circuit film FCF' and the fourth extension portion VP4 of the panel vernier pattern VP are aligned (for example, so that the distance in the second direction DR2 between the reference point and the fourth extension portion VP4 is zero), the display panel DP' and the flexible circuit film FCF' can be precisely aligned. Consequently, the reliability of the display device DD can be improved.

[0148] According to this embodiment, the panel vernier mark VM-P' can serve as a reference for aligning the skew of the display panel DP' and the flexible circuit film FCF', and can also serve as a reference for aligning the positions of the display panel DP' and the flexible circuit film FCF'. Therefore, the area occupied by the vernier mark for precisely aligning the display panel DP' and the flexible circuit film FCF' can be reduced.

[0149] Figure 10 is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0150] Reference Figure 10 In one embodiment, the electronic device 900 may include a processor 910, a memory device 920, a storage device 930, an input / output device 940, a power supply 950, and a display device 960. In this case, the display device 960 may correspond to Figure 1 The electronic device 900 may further include multiple ports capable of communicating with a video card, a sound card, a memory card, a Universal Serial Bus (USB) device, and the like. In one embodiment, the electronic device 900 may be implemented as a television. In another embodiment, the electronic device 900 may be implemented as a smartphone. However, the electronic device 900 is not limited thereto; for example, the electronic device 900 may also be implemented as a mobile phone, a video phone, a smart pad, a smartwatch, a tablet PC, a car navigation system, a computer monitor, a notebook computer, a head-mounted display (HMD), and the like.

[0151] Processor 910 can perform specific calculations or tasks. In one embodiment, processor 910 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. Processor 910 can be connected to other components via an address bus, a control bus, a data bus, etc. In one embodiment, processor 910 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0152] The memory device 920 may store data required for the operation of the electronic device 900 . For example, the memory device 920 may include a nonvolatile memory such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and the like.

[0153] The storage device 930 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device 940 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, a mouse, etc., and output devices such as a speaker, a printer, etc.

[0154] The power supply 950 can supply the power required for the operation of the electronic device 900. The display device 960 can be connected to other components via a bus or other communication links. In one embodiment, the display device 960 can also be included in the input / output device 940.

[0155] Industrial applicability The present invention can be applied to various display devices, such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for presentations or information transmission, and medical display devices.

[0156] The present invention has been described above with reference to exemplary embodiments. However, persons skilled in the art will appreciate that various modifications and variations may be made to the present invention without departing from the scope of the concept and field of the invention as set forth in the claims.

Claims

1. A display device, comprising: A display panel comprising a base substrate, a plurality of pixels, a plurality of pads, and a panel vernier mark, wherein the base substrate comprises a display area and a peripheral area outside the display area, the plurality of pixels are arranged in the display area, the plurality of pads are arranged in the peripheral area and spaced apart from each other in a first direction, and the panel vernier mark is arranged in the peripheral area and spaced apart from the plurality of pads in the first direction; a flexible circuit film attached to the display panel and comprising a plurality of leads respectively overlapping the plurality of pads on a plane; and a conductive adhesive component, arranged between the display panel and the flexible circuit film, and connecting the plurality of pads and the plurality of leads respectively; Wherein, the plurality of pads include: a first pad extending in a second direction perpendicular to the first direction; and a second pad extending at a first angle relative to the second direction; The panel cursor marks include: a first extension pattern extending in a direction parallel to an extension direction of the first pad; and The second extension pattern extends in a direction parallel to the extension direction of the second pad.

2. The display device according to claim 1, wherein The flexible circuit film includes a base film, and the plurality of leads are arranged on a lower surface of the base film.

3. The display device according to claim 1, wherein the second pad is spaced apart from the first pad in the first direction, the first extension pattern is spaced apart from the second pad in the first direction, The second extending pattern is spaced apart from the first extending pattern in the first direction.

4. The display device according to claim 3, wherein: The first pad is a pad arranged at the center in the first direction among the plurality of pads, The second pad is an outermost pad arranged in the first direction among the plurality of pads.

5. The display device according to claim 3, wherein: The plurality of pads further comprises: a third pad disposed between the first pad and the second pad and extending at a second angle with respect to the second direction that is smaller than the first angle; The panel cursor mark also includes: The third extension pattern extends in a direction parallel to the extension direction of the third pad.

6. The display device according to claim 5, wherein: The third extension pattern is arranged between the first extension pattern and the second extension pattern.

7. The display device according to claim 1, wherein: The panel cursor mark also includes: The first character pattern indicates an angle at which the extending direction of the second extending pattern is inclined relative to the second direction.

8. The display device according to claim 7, wherein: The first character pattern is adjacent to the second extension pattern.

9. The display device according to claim 1, wherein: The panel cursor mark also includes: a fourth extending pattern extending along the first direction; and a fifth extending pattern extending along the first direction and spaced apart from the fourth extending pattern in the second direction.

10. The display device according to claim 9, wherein The panel cursor mark also includes: The second character pattern indicates the distance between the fourth extension pattern and the fifth extension pattern in the second direction.

11. The display device according to claim 10, wherein: The second character pattern is adjacent to the fifth extension pattern.

12. The display device according to claim 9, wherein The fourth extension pattern and the fifth extension pattern are spaced apart from the first extension pattern and the second extension pattern in the first direction.

13. The display device according to claim 12, wherein: The conductive adhesive member overlaps with the first and second extending patterns in a two-dimensional view, and does not overlap with the fourth and fifth extending patterns in a two-dimensional view.

14. The display device according to claim 12, wherein: The flexible circuit film overlaps with the first and second extension patterns in a plane, and does not overlap with the fourth and fifth extension patterns in a plane.

15. The display device according to claim 14, wherein The plurality of leads include: a first lead extending along the second direction and overlapping the first pad in a plane; and A second lead extends at the first angle relative to the second direction and overlaps the second pad on a plane. The flexible circuit film further comprises: The film vernier mark is spaced apart from the plurality of leads in the first direction and extends in a direction parallel to an extending direction of the second leads.

16. The display device according to claim 15, wherein The film vernier mark overlaps with the second extension pattern on a plane.

17. The display device according to claim 9, wherein: The first extension pattern, the second extension pattern, the fourth extension pattern, and the fifth extension pattern are formed as one body.

18. The display device according to claim 17, wherein: The conductive adhesive member does not overlap with the first extending pattern, the second extending pattern, the fourth extending pattern, and the fifth extending pattern in a planar manner.

19. The display device according to claim 17, wherein: The flexible circuit film does not overlap with the first extension pattern, the second extension pattern, the fourth extension pattern, and the fifth extension pattern on a plane.

20. A display device comprising: A display panel comprising a base substrate, a plurality of pixels, a plurality of pads, and a panel vernier mark, wherein the base substrate comprises a display area and a peripheral area outside the display area, the plurality of pixels are arranged in the display area, the plurality of pads are arranged in the peripheral area and spaced apart from each other in a first direction, and the panel vernier mark is arranged in the peripheral area and spaced apart from the plurality of pads in the first direction; a flexible circuit film attached to the display panel and comprising a base film and a plurality of leads arranged on the base film and respectively overlapping the plurality of pads in a plane; and a conductive adhesive component, arranged between the display panel and the flexible circuit film, and connecting the plurality of pads and the plurality of leads respectively; Wherein, the plurality of pads include: a first pad extending in a second direction perpendicular to the first direction; and a second pad extending at a first angle relative to the second direction; The panel cursor marks include: a first extension portion extending in a direction parallel to an extension direction of the first pad; a second extension portion extending in a direction parallel to the extension direction of the second pad and located in the first direction of the first extension portion; a third extending portion extending along the first direction and intersecting the first extending portion and the second extending portion; and The fourth extending portion extends along the first direction and is located in the second direction of the third extending portion, and intersects the first extending portion and the second extending portion.

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